Method for determining polarity of half-bridge current and half-bridge controller

Abstract

The present disclosure relates to a method and a half-bridge controller for determining the polarity of a half-bridge current. A method and a half-bridge controller for detecting the polarity of a current through a half-bridge are provided. A switching delay of a switch of the half-bridge is determined, and the polarity of the current through the half-bridge is determined based on the switching delay.

Description

Technical Field

[0001] The present application relates to a method for determining the polarity of a current through a half-bridge, a corresponding half-bridge controller, and a method and a half-bridge controller for performing dead time compensation for a half-bridge based on the determined polarity. Background Art

[0002] Half bridges are used in many applications to selectively power a load. Applications include driving a motor using a so-called three-phase inverter, where three such half bridges are used to provide a three-phase output current. A half bridge typically includes a first switch coupled between a first potential and an output node of the half bridge and a second switch coupled between a second potential and the output node. For example, the first potential may be a positive supply voltage, and the second potential may be a negative supply voltage or ground. The first switch is typically referred to as a high-side switch, and the second switch is referred to as a low-side switch.

[0003] In operation of such a half-bridge, the first switch and the second switch are alternately closed and opened to selectively couple the output node to the first potential or the second potential.

[0004] In such a half bridge, if the first switch and the second switch are closed simultaneously, a short circuit between the first potential and the second potential will result. In order to avoid such a short circuit, a so-called dead time is inserted when both switches are open before one of the two switches is closed.

[0005] However, through these dead times, the output voltage of the half-bridge deviates from the ideal output voltage, such as when it is usually controlled by a pulse width modulation (PWM) scheme in many applications, which may introduce current ripple and increase the nonlinearity of the system using the half-bridge. The distortion of the output voltage in the case of an ideal sinusoidal voltage, for example, includes both low-frequency harmonics and switching frequency harmonics. The low-frequency harmonics may have a negative impact on the performance of some applications of the half-bridge.

[0006] Various methods have been used to compensate for the effects of introducing dead time, which is referred to herein as dead time compensation. Some of these techniques apply a compensation voltage based on the polarity of the current through the half-bridge, which indicates whether the current flows from the half-bridge to the load or from the load to the half-bridge. However, in detection circuits conventionally used to determine polarity, errors may occur when the current approaches zero because noise may cause the detection of incorrect polarity. Improving the reliability of these conventional detection circuits requires additional hardware or increased software complexity, such as for filtering algorithms. Similarly, in other cases, it may also be necessary to determine the polarity of the current through the half-bridge. Summary of the invention

[0007] A method according to claim 1 and a half-bridge controller according to claim 11 are provided. The dependent claims define further embodiments and a system comprising such a half-bridge controller.

[0008] According to one embodiment, a method for determining the polarity of a current through a half-bridge is provided, the method comprising: determining a switching delay of at least one of a high-side switch or a low-side switch of the half-bridge; and determining the polarity of the current through the half-bridge based on the switching delay.

[0009] According to another embodiment, a half-bridge controller is provided, which includes: a measurement circuit configured to determine a switching delay of at least one of a high-side switch or a low-side switch of the half-bridge; and a control circuit configured to determine the polarity of a current through the half-bridge based on the switching delay.

[0010] The above summary is intended merely to give a brief overview of some features of some embodiments and should not be construed as limiting in any way. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a flow chart illustrating a method according to an embodiment;

[0012] Figure 2 is a block diagram illustrating a system according to an embodiment;

[0013] Figure 3 is an example half bridge used to illustrate the embodiments;

[0014] Figure 4A and Figure 4B It is shown Figure 3 A signal diagram of an example operation of a half bridge;

[0015] Figure 5 is a diagram for showing the voltage and current of a half bridge;

[0016] Figure 6 A delay measurement circuit according to an embodiment is shown;

[0017] 7 to 14 (comprising Figures A and B respectively) illustrate the determination of the polarity of the current through the half-bridge in various situations;

[0018] Fig.15 is a block diagram of a delay measurement circuit that may be used in some embodiments;

[0019] Fig.16 shows the output current of the three-phase inverter;

[0020] Fig.17 is a block diagram of a circuit for phase estimation that may be used in some embodiments; and

[0021] 18A to 18D Measurement results with dead time compensation according to the techniques disclosed herein and according to a comparative example are shown. DETAILED DESCRIPTION

[0022] In the following, various embodiments will be described in detail with reference to the accompanying drawings. Although various details are shown in the drawings and described in the corresponding description, this should not be interpreted as indicating that the order of the embodiments requires all of these details. In other embodiments, some of these details may be omitted or may be replaced with alternative features or details.

[0023] Furthermore, in addition to the features or details explicitly described, other features may be provided, such as features conventionally provided in a half-bridge circuit, a controller for a half-bridge circuit, and applications of such a half-bridge circuit.

[0024] Features from different embodiments may be combined to form other embodiments. Unless otherwise explicitly stated, changes and modifications described with respect to one of the embodiments also apply to other embodiments. Unless otherwise stated, changes and modifications described with respect to one of the embodiments also apply to other embodiments, and therefore will not be described repeatedly.

[0025] Unless stated otherwise, connections or couplings shown in the figures or described herein relate to electrical connections or couplings and / or connections or couplings for transmitting signals within circuits or logical entities.

[0026] The embodiments discussed below relate to determining the polarity of a current through a half-bridge. The polarity of the current indicates whether the current flows from the half-bridge to a load coupled to the half-bridge or from the load to the half-bridge.

[0027] A half-bridge as described herein comprises a switch. The switch may comprise a control terminal and two load terminals. The state of the switch may be controlled by applying a signal to the control terminal. If the switch provides a low ohmic electrical path between its load terminals, the state of the switch is referred to as closed or on. If the switch is substantially electrically isolated between its load terminals, the switch is referred to as open or off. "Substantially electrically isolated" refers to the fact that in practical switch implementations, some parasitic leakage current may occur between the load terminals even in the open state. However, such leakage current, if it occurs, is typically several orders of magnitude lower than the current that flows when the switch is in the closed state.

[0028] The switch can be implemented using a transistor. Available transistors include field effect transistors, such as MOSFETs (metal oxide semiconductor field effect transistors), bipolar transistors, or insulated gate bipolar transistors (IGBTs). In the case of a field effect transistor, the control terminal corresponds to the gate terminal, and the load terminal corresponds to the source and drain terminals. In the case of a bipolar transistor, the control terminal corresponds to the base terminal, and the load terminal corresponds to the emitter terminal and the collector terminal. In the case of an IGBT, the control terminal corresponds to the gate terminal, and the load terminal corresponds to the collector terminal and the emitter terminal. In many implementations of a half-bridge, such a transistor-based switch also includes a freewheeling diode between the load terminals. The freewheeling diode may be inherent to the corresponding transistor design, or may be provided separately.

[0029] Figure 1 A method according to an embodiment is shown. The method may be implemented, for example, in a half-bridge controller.

[0030] At 10, Figure 1 The method comprises determining a switching delay of a switch of a half-bridge. As explained in the background section, the half-bridge comprises a first switch and a second switch, also referred to as a high-side switch and a low-side switch. The switching delay as used herein relates to the delay between a control signal for changing the state of a switch from open to closed or from closed to open and vice versa and the actual change of the state of the switch.

[0031] At 11, the method includes determining the polarity of the current through the half-bridge based on the switching delay. For example, determining the polarity may include comparing the switching delay to a threshold. Examples of suitable thresholds are discussed further below.

[0032] In some applications, it can be based on Figure 1 Dead time compensation is applied by determining the polarity at 12 in FIG.

[0033] The following will further explain Figure 1 The possible implementation details of various actions or events of the method.

[0034] Figure 2 A system according to an embodiment is shown. Figure 2 The system includes a controller 20 that controls a half bridge 21. The current flowing through the half bridge 21 provides an output current Iout to the load, or corresponds to the output current Iout received from the load. As described above, the half bridge 21 can be implemented using two switches in any conventional manner.

[0035] The controller 20 comprises a delay measurement circuit 23 configured to determine a switching delay of one or both switches of the half-bridge 21. The turn-on delay when turning on a switch, the turn-off delay when turning off a switch, or both may be determined.

[0036] The controller 20 also includes a control circuit 22. The control circuit 22 can control the switching of the switches of the half-bridge 21 by generating corresponding control signals provided to the control terminals of the switches. In addition, the control circuit 22 is configured to determine the polarity of the current Iout (i.e., the current through the half-bridge) based on the determined switching delay or multiple switching delays. In some implementations, the control circuit 22 can apply dead time compensation based on the determined polarity, for example, by modifying the control signal controlling the switch of the half-bridge 21 or by modifying the reference voltage used to control the switch. The implementation of the delay measurement circuit 23 and examples for determining polarity and dead time compensation will be further described below.

[0037] Figure 3 is a circuit diagram of a half bridge that will be used in the following description. Figure 3 The half bridge is also Figure 2 Half bridge 21 or Figure 1 An example of an implementation of a half-bridge used in the method. Figure 3 The half bridge includes a first switch QH as a high-side switch and a second switch QL as a low-side switch coupled between a first potential 30 and a second potential 31. The first potential 30 is more positive than the second potential 31. For example, the first potential 30 may correspond to the positive pole of the battery or the positive power supply voltage (e.g., VDD), and the second potential 31 may correspond to the negative pole of the battery, the negative power supply voltage or the ground. Therefore, a DC (direct current) voltage VDC is applied between the first potential 30 and the second potential 31.

[0038] The high-side switch QH is controlled by a control signal GH, and the low-side switch QL is controlled by a control signal GL.

[0039] The high side switch QH has a first freewheeling diode DH connected in parallel thereto, and the low side switch QL has a second freewheeling diode DL connected in parallel thereto. As described above, the switches QH, QL may be transistor switches, and the freewheeling diodes DH, DL may be diodes inherent to the design of the transistors, or may be provided separately.

[0040] The current Iout generated by the half-bridge when the switches QH, QL are closed and opened according to some switching schemes flows from the node between the switches QH, QL to the load 32, or from the load 32 to the node between the switches QH, QL, and the current Iout is also referred to as the output current. The polarity of the current Iout indicates whether the current Iout flows from the half-bridge to the load 32 or from the load 32 to the half-bridge. For example, the current Iout flowing to the load 32 may be referred to herein as a positive current with a positive polarity, and the current Iout flowing to the half-bridge will be referred to herein as a negative current with a negative polarity. However, it should be understood that this is merely a naming convention, and reverse naming may also be used.

[0041] The voltage across the high-side switch QH or the low-side switch QL will be referred to herein as the body voltage Vbody of the corresponding switch. In the case of a field effect transistor switch, the body voltage Vbody may correspond to the drain-source voltage Vds of the corresponding transistor.

[0042] Figure 4A and Figure 4B Shown in Figure 4A In the case of positive current Iout (Iout>0) and in Figure 4B In the case of negative current Iout (Iout<0) Figure 3 Switching of the half-bridge switches QH and QL.

[0043] It should be noted that Figure 4A and 4B It is a slightly simplified scheme because the turn-on and turn-off transients of the high-side switch QH and the low-side switch QL are not considered.

[0044] exist Figure 4A In the case of Iout>0, signals GH and GL respectively show the switching scheme for generating the desired output voltage Vout at the node between the switches. Figure 3 The ideal control signal for the high-side switch QH and the low-side switch QL. Figure 4A In the subsequent switches, the "high" control signal indicates that the corresponding switch is closed, while the "low" control signal indicates that the corresponding switch is open. In this ideal case, the high-side switch QH and the low-side switch QL are switched at the same time, for example, when the high-side switch QH is turned on, the low-side switch QL is turned off at the same time, and vice versa.

[0045] In practice, such a switching scheme carries the risk of a short circuit between the first potential 30 and the second potential 31, and therefore a dead time td is inserted. This results in a modified control signal GH1, GL1, also as Figure 4A shown.

[0046] Figure 4A Vout in shows the ideal output voltage of the ideal switching scheme using the control signals GH, GL, and Vout1 shows the output voltage in the case of dead time insertion. In this case, after the low-side switch QL is turned off by the control signal GL1, the current Iout flows through the diode DL until QH is turned on, so Vout1 remains low during the dead time td until QH is turned on (corresponding to the control signal GH1). When QH is turned off, the current Iout flows through the diode DL, and Vout1 immediately becomes low (corresponding to the second potential 31).

[0047] Due to the dead time td, Vout1 differs from the ideal output voltage Vout, and this difference is Figure 4A It is represented as error voltage.

[0048] Figure 4B It shows that when the current Iout<0 Figure 4A The same signals GH, GL and GH1, GL1, and Vout, Vout1 and Verr. In this case, when the low-side switch QL is turned off by the signal GL1, the output voltage Vout1 changes immediately. On the other hand, only after the low-side switch QL is turned off by the signal GL1, the output voltage Vout1 drops to the second potential 31, resulting in a difference between Vout1 and Vout and a corresponding error voltage, as shown in FIG. Figure 4B As shown. Figure 4A and 4B It can be seen that the error voltage Verr is different for different polarities of the current Iout. Therefore, in order to compensate for the error voltage, it is helpful to determine the polarity of the current Iout in some applications.

[0049] For further explanation, in the case of operating switches QH, QL to generate a sinusoidal output voltage as an example, the ideal output voltage Vout, the actual output voltage Vout1, the corresponding output current Iout and the error voltage Verr are Figure 5 As a load, an inductive load is taken as an example. Figure 5 The ideal output voltage Vout is shown as a sinusoidal voltage, and the distortion of the actual output voltage Vout1 generated due to the insertion of the dead time is shown. The distortion includes both low-frequency harmonics and switching frequency harmonics. As has been initially explained, this can lead to various negative effects on the performance of the system containing the half-bridge.

[0050] According to an embodiment, a dead time compensation technique is applied depending on the polarity of the current. As in conventional methods, the determination of polarity may have some disadvantages, in the embodiments discussed herein, the polarity of Iout is determined based on the measurement of the switching delay. Based on the determined polarity, conventional dead time compensation techniques can then be applied. For example, a compensation voltage having a sign opposite to that of the error voltage (the sign depends on the polarity as described above) can be applied, for example by modifying the switching scheme of the switch to provide the error voltage or by modifying the additional voltage provided accordingly.

[0051] Next, the switching delay measurement and the determination of the polarity of the current Iout based on the delay measurement will be described.

[0052] Figure 6 A delay measurement circuit according to an embodiment is shown. Figure 6 The delay measurement circuit includes a comparator 60 and a counter 61. Figure 6 The delay measurement circuit can measure Figure 3 The switching delay of each switch QH, QL.

[0053] The comparator 60 receives a body voltage Vbody at its first input and a threshold voltage Vthr at its second input. The threshold voltage may be a threshold voltage corresponding to a voltage indicating that a corresponding switch is turned on or off when the threshold voltage is crossed. In a transistor, the threshold voltage may indicate that the on-charge Qon of the transistor has been reached. Thus, in Figure 6 In FIG. 5 , the output signal of the comparator 60 is labeled Qon. It should be noted that in other embodiments, instead of the body voltage Vbody, another voltage at the corresponding switch may be used, for example, in the case of a transistor switch, a voltage between the control terminal and one of the load terminals, such as a gate-drain voltage.

[0054] When the signal Qon changes its state, this indicates that the transistor has actually been switched. The signal Qon is supplied to a first input of a counter 61 .

[0055] The respective control signal of the switch whose switching delay is to be measured (ie GH or GL) is provided to a second input of the counter 61. The counter 61 is clocked by the clock signal clock.

[0056] The counter 61 counts the time between the signal change of Qon and the edge of the control signal GH or GL, i.e., starts counting based on one signal and stops counting based on the other signal. The counting is based on the clock signal. In this way, a switching delay tdel is provided as the time difference between the actual switching of the switch (indicated by the signal Qon) and the nominal (predetermined) switching of the switch (indicated by the corresponding control signal GH or GL).

[0057] The switching delay can be measured for one or more of the following situations: the turn-on of the high-side switch QH, the turn-off of the high-side switch QH, the turn-on of the low-side switch QL, or the turn-off of the low-side switch QL, and the polarity of the current Iout can be determined based on any one or a combination of these measurements. This will be explained with reference to Figures 7 to 14, where all of these possible situations will be discussed. In each of Figures 7 to 14, the corresponding Figure A (7A, 8A, ..., 14A) shows Figure 3 A half bridge with an indication of the polarity of the output current and an indication of the current path during the dead time, and corresponding Figures B (7A, 8B, ..., 14B) respectively show the corresponding signals.

[0058] Fig. 7A and Figure 7BThe situation is shown where the output current Iout is positive as indicated by arrow 71 and the switching delay of the high side switch QH is measured. The low side switch QL is turned off and the high side switch QH is turned on, separated by a dead time td.

[0059] exist Fig. 7A and Figure 7B In the case of, after the low-side switch QL has been turned off and before the high-side switch QH is turned on (i.e., Figure 7B During the dead time td shown), the output current Iout flows from the second potential 31 to the load 32 substantially via the current path through the freewheeling diode DL, as shown by the dotted line 70. During this period, the Vbody of the high-side switch QH remains high (a high voltage drop across the transistor, corresponding to a non-conducting state). After the rising edge of GH, the high-side switch QH starts to turn on, and Vbody decreases until the threshold voltage Vthr is reached and Qon is triggered. The time delay between the rising edge of the signal GH and the falling edge of the signal Qon is the switching delay, in this case the turn-on time delay ton. In other words, ton is defined as the time of the falling edge of Qon minus the time of the rising edge of GH. The turn-on time delay ton is positive relative to the rising edge of GH, or in other words, occurs after the dead time td.

[0060] Fig. 8A and Figure 8B Again, the high-side switch QH is turned on and the low-side switch QL is turned off (separated by a dead time, such as Fig. 7A and Figure 7B ), but in this case, the current Iout<0, as shown by arrow 81. In this case, after the low-side switch QL is turned off, the output current (as generally shown by arrow 81 and more specifically as shown by current path 80) flows through diode DH. Therefore, the Vbody of the high-side switch QH decreases and becomes low before the rising edge of GH. In other words, as Figure 8B As shown, Vbody crosses the threshold Vthr before the rising edge of GH arrives, and therefore, the falling edge of Qon occurs before the rising edge of GH arrives. While the definition of the turn-on delay ton is the same as before (i.e., the time of the falling edge of Qon minus the time of the rising edge of GH), in this case, ton is negative.

[0061] Thus, for example, by using Figure 6 The circuit (in this case, tdel corresponds to ton) measures the turn-on delay of the high-side switch QH as a switching delay and by comparing the determined switching delay ton with a threshold value (e.g., zero), the polarity of the current can be determined when measuring the turn-on delay of the high-side switch. For example, if ton is greater than zero, the polarity of the current is positive, and if ton is less than zero, the polarity of the current is negative.

[0062] Next, the case where the high-side switch QH is turned off and the low-side switch QL is turned on (separated by a dead time) will be discussed, in which case the switching delay of the high-side switch QH (in this case, the turn-off delay) is measured again.

[0063] Fig.9A and Fig. 9B The case where the current Iout is positive is shown, as indicated by arrow 91 .

[0064] In this case, when the falling edge of GH arrives, indicating that the high-side switch QH should be turned off, the high-side switch QH actually starts to be turned off, and the body voltage Vbody across the high-side switch QH starts to rise and reaches the threshold value Vthr. In this case, during the dead time, the current flows through the diode DL, as shown by the dotted line 90. In this case, the turn-off delay time toff is the time essentially required for the turn-off of the high-side switch QH.

[0065] Fig. 10A and Fig. 10B 1 shows the case of the turn-off delay of the high-side switch QH when the output current is of negative polarity, as indicated by arrow 101. In this case, when the falling edge of the control signal GH arrives, while the high-side switch QH begins to turn off as shown by the dotted line 100, the current flows through the diode DH, which causes the body voltage Vbody to remain low and only rise after the dead time td has passed and the low-side switch QL begins to turn on. In this case, the measured turn-off delay toff between the rising edge of Qon and the falling edge of GH is essentially the dead time td plus the inherent device turn-on delay of the low-side switch QL, and in particular, is greater than the dead time td. Therefore, when evaluating the turn-off delay of the high-side switch, the dead time td can be used as a threshold, and if the measured turn-off delay toff is less than the dead time td, the polarity of the current is positive, and when the measured turn-off delay toff is greater than td, the polarity is negative.

[0066] Next, determination of the polarity of the current Iout based on a switching delay (a turn-on delay in this case) when the low-side switch QL is turned on will be discussed with reference to FIGS. 11 and 12 .

[0067] When the current Iout is Fig.11AWhen the arrow 111 in is positive, after the high-side switch QH is turned off, the freewheeling current flows through the diode DL, as shown by the dotted line 110. Therefore, the body voltage Vbody begins to drop and crosses the threshold, even before the rising edge of GL indicates the turn-on of the low-side switch QL. In this case, if the turn-on delay ton is defined again as the time of the falling edge of Qon minus the time of the rising edge of GL (similar to the case of Figures 7 and 8), ton is negative. In other words, in this case, the turn-on delay corresponds to td minus the time required for the high-side switch QH to turn off after the falling edge of GH.

[0068] Fig. 12A and Fig. 12B The case where Iout is negative is shown, as shown by arrow 121. In this case, during the dead time, the current flows through the diode DH, as shown by the dotted line 120. Therefore, the body voltage Vbody of the low-side switch QL remains high until the rising edge of GL turns on the low-side switch QL, after which the body voltage Vbody begins to decrease until the threshold voltage is reached. In this case, when ton is defined again as the time of the falling edge of QN minus the time of the rising edge of GL, ton is positive. Therefore, by comparing ton when the low-side switch QL is turned on with a threshold of zero, the polarity of the current Iout can be determined.

[0069] Finally, measuring the turn-off delay of the low-side switch QL and deriving the polarity of the output current from this measurement will be explained with respect to FIGS. 13 and 14 .

[0070] Fig.13A and Fig. 13B The case where the polarity of the current Iout is positive, as indicated by arrow 131, is shown. In this case, the current flows through the diode DL during the dead time, as indicated by dashed line 130. Therefore, the body voltage Vbody remains low even after the falling edge of GL, which indicates that the low-side switch QL is to be turned off, and only rises after the rising edge of GH turns on the high-side switch QH. Therefore, the turn-off delay toff, measured as the difference between the rising edge of Qon and the falling edge of GL in this case, corresponds to the dead time td plus the turn-on time of the high-side switch QH, and is greater than the delay time td.

[0071] Fig.14A and Fig. 14B The polarity of the current Iout is shown as negative. Fig.14AAs shown by arrow 141 in . Here, during the dead time as shown by dotted line 140, the current flows through diode DH. After the falling edge of GL, the body voltage Vbody across the low-side switch QL immediately starts to rise, and in this case, the device off-time toff corresponds to the inherent off-time required by the low-side switch QL. In particular, in this case, tof is less than td. Therefore, in this case, by comparing toff with td as a threshold, the polarity of the current Iout can be determined.

[0072] In summary, by measuring the turn-on delay or turn-off delay of the high-side switch QH or the low-side switch QL as a switching delay, and by comparing the corresponding delay with a threshold value (e.g., zero or dead time td), the polarity of the current Iout can be determined. In the case of Iout>0 and Iout<0, other thresholds between the corresponding switching delays other than zero or dead time td can also be used. For example, in other embodiments, the threshold value may have a value between a negative value and a value less than the actual turn-on delay time. A suitable value for the threshold value can be determined experimentally. For example, for various known test currents with known polarities, a threshold value that gives the correct determination of the polarity of all test currents can be selected. In this way, a threshold value that takes system noise into account can be determined.

[0073] It should be noted that, in terms of practical implementation, in some cases, in particular in some high voltage systems, it may be advantageous to measure the turn-on delay of the low-side switch QL, since the second potential 31 is typically a common ground in such devices and in such cases, for example, in terms of isolation between voltage domains, e.g. Figure 6 It may be easier to couple the delay measurement circuit with the low-side switch QL.

[0074] As described above, the switching delay of both the high-side switch and the low-side switch of the half-bridge can be used to determine the polarity of the current through the corresponding half-bridge. In addition, in some applications, multiple half-bridges may be provided, such as three half-bridges for a three-phase inverter driving a three-phase motor. In this case, a common circuit system including one or more multiplexers can be used as a delay measurement circuit for multiple switches. Fig.15 An example of a measurement circuit 150 that may be used in an embodiment is shown in FIG.

[0075] The measurement circuit 150 is designed for a system comprising a three-phase inverter based on three half-bridges, each half-bridge comprising a respective high-side switch ( Fig.15 The signals in HS1-HS3) and the corresponding low-side switches ( Fig.15 LS1-LS3 in the signal.

[0076] Signals from the corresponding comparators assigned to the switches HS1-HS3, LS1-LS3 (each of which compares the body voltage Vbody (e.g., the drain-source voltage Vds) with a threshold) are provided to the first multiplexer 151A. The control signals (similar to Figure 3 The signals GH, GH) are provided to the second multiplexer 151B. Using the first multiplexer 151A and the second multiplexer 151B, one of the switches is selected for delay measurement. The selected corresponding signals are provided to the circuit systems 152A, 152B respectively. Each circuit system 152A, 152B includes an edge detection circuit for detecting a rising edge, an edge detection circuit for detecting a falling edge, and an edge signal selection circuit, such as a multiplexer, for selecting a detected rising edge or a detected falling edge as an output based on the signal edgeel.

[0077] The selected detected edge is provided to the stop input and the start input of the counter 154, respectively, which essentially has the same Figure 6 The counter 154 has the same function as the counter 61. The counter 154 is clocked by the clock signal clk. The counter 154 outputs the switching delay tdel.

[0078] Furthermore, the output of circuitry 152 provided to the stop input of counter 154 is additionally provided to the set input of latch 153 which is clocked by clock signal clk. Latch 153 outputs a signal delcom indicating completion of the delay measurement.

[0079] Based on the detected edge, the counter 154 and latch 153 are also reset after each delay measurement to make the next delay measurement. Fig.15 The external reset signal marked as reset in .

[0080] For example, if the turn-on delay of the low-side switch is to be measured, the rising edge can be selected by the signal edgeel. Then, the rising edge of the corresponding signal LSx_ON (x=1-3) selected by the multiplexer 151B triggers the counter 154 to start, and the falling edge of Vds_comp_o_LSx (x=1-3) selected by the multiplexer 151A stops the counter and sets the completion signal delcom. Then, the falling edge of LSx_ON or the rising edge of Vds_comp_o_LSx resets the counter 154 and the latch 153 to prepare for the next delay measurement.

[0081] In some embodiments, the measurement circuit 150 may be a measurement circuit that is also used for other purposes, for example, for detecting whether the corresponding switches HS1-HS3, LS1-LS3 are in a "good state" by checking whether the measured switching delay is within a specified range. In some conventional devices, such monitoring of the health of the switches based on switching delays has been used. In this case, in an embodiment, the measurement circuit that has been provided for this monitoring can be additionally used to detect the polarity of the current through the half-bridge by comparing tdel with a threshold, as described above, so that almost no additional circuitry is required.

[0082] exist Fig.15 In the embodiment, multiplexers 151A, 151B are used so that only one counter 154 is provided for a plurality of switches, and therefore, the switching delay and polarity can be measured for only one switch at a time. The switching of the low-side switch and the high-side switch usually occurs at or near the zero crossing point of the corresponding current Iout of the corresponding half-bridge. Therefore, in an embodiment, the zero crossing point of the current of the different half-bridges is predicted, and the switch for measuring the switching delay is selected based on the prediction. Referring to Fig.16 and Fig.17 Describe the example.

[0083] Fig.16 Three output currents Ia, Ib and Ic are shown as typical outputs of a three-phase inverter. The operation can be divided into Fig.16 There are six stages marked as I to VI in FIG. In each stage, one of the currents passes through zero. Specifically, the relationship between the currents from the first stage to the sixth stage is:

[0084] I: Ib>Ia>Ic

[0085] II: Ib>Ic>Ia

[0086] III: Ic>Ib>Ia

[0087] IV: Ic>Ia>Ib

[0088] V: Ia>Ic>Ib

[0089] VI: Ia>Ib>Ic

[0090] In each of phases I to VI, a corresponding “intermediate current” Ia, Ib or Ic (whose magnitude is between the corresponding magnitudes of the other two currents) forms a zero crossing.

[0091] For the half-bridge that generates this "intermediate current", at each stage, the polarity can be determined based on the techniques discussed above. For the three currents Ia, Ib, and Ic, at least ideally, the relationship Ia+Ib+Ic=0 holds. At the phase angle θ=ωt, where ω is the angular frequency of the current I and t is time, the currents Ia, Ib, and Ic can be written as:

[0092] Ia=I·sin(θ)

[0093] Ib=I·sin(θ-2 / 3π)

[0094] Ic=I·sin(θ-4 / 3π)

[0095] For the six phases I to VI, the following applies to the phase angle θ:

[0096] I: 5 / 6π<θ<7 / 6π

[0097] II: 7 / 6π<θ<3 / 2

[0098] III: 3 / 2π<θ<11 / 6π

[0099] IV: 11 / 6π<θ<13 / 6π

[0100] V: 2 / 6π<θ<2 / 2π

[0101] VI: 2 / 2π<θ<5 / 6π

[0102] Based on this, we can use Fig.17 The circuit shown in FIG. 1 is used to determine the phase angle θ. The currents Ia, Ib, and Ic are subjected to a Clarke transform 170 and then to a Park transform 171. The output signal of the Park transform 171 is provided to a proportional integral (PI) controller 172 to obtain an angular velocity ω, which is then integrated by an integrator 173. The obtained phase angle θ is fed back to the Park transform 171. In this way, the phase angle θ can be determined, and in an embodiment, based on the phase angle θ, for example, by using Fig.15 The multiplexer 151A, 151B is used to select the half bridge for analysis, so that in the case of rising current, the high-side switch is selected (zero crossing in the positive direction, for example, at Fig.16 The analysis of the turn-on delay can be performed by selecting the corresponding low-side switch for the remaining stages II, IV and VI. As described above, the reverse selection can also be performed to analyze the turn-off delay.

[0103] Next, references include 18A to 18D FIG18 is used to describe some measurement results showing the effect of the techniques discussed in this article.

[0104] Measurements have been performed on a half-bridge of a three-phase inverter driving a three-phase brushless DC motor with vector control at 20 Hz, a dead time of 1 μs and a switching frequency of 20 kHz. Fig.18A and Fig.18B Figure 2 shows the measurement results without applying dead time compensation techniques. Fig.18A In FIG. 1 , curve 180 shows the output voltage, and curve 181 shows the frequency spectrum of the output voltage obtained by fast Fourier transform (FFT). It can be seen that in addition to the fundamental frequency component, there are strong fifth and seventh harmonics. Curve 183 shows the output current with visible distortion.

[0105] Fig. 18C and Fig.18D Measurement results are shown for a case where polarity detection based dead time compensation as described herein has been applied. Fig. 18C Corresponds to Fig.18A , curve 184 shows the output voltage, and curve 185 shows the spectrum obtained by fast Fourier transform. It can be seen that the fifth and seventh harmonics are suppressed compared to curve 181. This produces a signal with reduced distortion. Fig.18D The output current is shown by curve 186.

[0106] Some embodiments are defined by the following examples:

[0107] Example 1. A method for determining the polarity of a current through a half-bridge, comprising:

[0108] determining a switching delay of at least one of a high-side switch or a low-side switch of the half-bridge, and

[0109] The polarity of the current through the half-bridge is determined based on the switching delay.

[0110] Example 2. The method of Example 1, wherein the polarity of the current through the half-bridge is determined based on a comparison of the switching delay to a threshold.

[0111] Example 3. The method of Example 2, wherein the threshold is zero.

[0112] Example 4. The method of Example 2, wherein the threshold is substantially equal to a dead time of the half-bridge.

[0113] Example 5. A method according to any one of Examples 1 to 4, wherein the switching delay of at least one of the high-side switch or the low-side switch of the half-bridge is determined as: a time difference between a nominal switching time of a control signal of the high-side switch or the at least one of the low-side switches and a time when a voltage across the at least one of the high-side switch or the low-side switch crosses a predefined threshold voltage.

[0114] Example 6. The method of Example 5, wherein the nominal switching time comprises a time of a rising edge or a falling edge of the control signal.

[0115] Example 7. The method of Example 5 or 6, wherein the at least one of the high-side switch or the low-side switch is a transistor switch, and the threshold voltage is a threshold voltage of the transistor switch.

[0116] Example 8. A method according to any one of Examples 5 to 7, wherein the at least one of the high-side switch or the low-side switch is a transistor switch, and wherein the voltage across the at least one of the high-side switch or the low-side switch includes at least one of a voltage between load terminals of the transistor switch or a voltage between a control terminal and a load terminal of the transistor switch.

[0117] Example 9. The method of any one of Examples 1 to 7, wherein the switching delay comprises at least one of a turn-off delay or a turn-on delay.

[0118] Example 10. The method of any of Examples 1 to 9, wherein the current is a current through a node between the high-side switch and the low-side switch.

[0119] Example 11. The method of any one of Examples 1 to 10, further comprising selecting the half-bridge for determining the switching delay from a plurality of half-bridges based on a phase angle prediction.

[0120] Example 12. A method for dead time compensation in a half bridge, comprising:

[0121] determining the polarity of the current through the half bridge according to the method of any of Examples 1 to 11, and

[0122] The method according to any one of claims 1 to 8 determines the polarity of the current through the half-bridge, and

[0123] Example 13. A method according to Example 12, wherein applying the dead time compensation includes at least one of: modifying a reference voltage based on which the control of the half-bridge is based; or modifying a pulse width modulation mode according to which the half-bridge is controlled.

[0124] Example 14. A half-bridge controller comprising:

[0125] a measurement circuit configured to determine a switching delay of at least one of a high-side switch or a low-side switch of the half-bridge, and

[0126] A control circuit is configured to determine a polarity of a current through the half-bridge based on the switching delay.

[0127] Example 15. A half-bridge controller according to Example 14, wherein to determine the polarity of the current through the half-bridge, the control circuit is configured to compare the switching delay to a threshold value.

[0128] Example 16. The half-bridge controller of Example 15, wherein the threshold is zero.

[0129] Example 17. The half-bridge controller of Example 15, wherein the threshold is substantially equal to a dead time of the half-bridge.

[0130] Example 18. A half-bridge controller according to any one of Examples 14 to 17, wherein the measurement circuit is configured to determine the switching delay of at least one of the high-side switch or the low-side switch of the half-bridge as: a time difference between a nominal switching time of a control signal of the high-side switch or the at least one of the low-side switches and a time when a voltage across the at least one of the high-side switch or the low-side switch crosses a predefined threshold voltage.

[0131] Example 19. A half-bridge controller according to Example 18, wherein the measurement circuit includes a comparator, wherein a first input of the comparator is configured to receive the voltage across at least one of the high-side switch or the low-side switch, and a second input of the comparator is configured to receive the threshold voltage.

[0132] Example 20. A half-bridge controller according to Example 19, wherein the measurement circuit includes a counter, wherein a first input of the counter is coupled to the output of the comparator, wherein a second input of the counter is configured to receive the control signal, and wherein the counter is configured to start counting based on a first signal at one of the first input or the second input, and to stop counting based on a second signal at the other of the first input or the second input.

[0133] Example 21. A half-bridge controller according to any of Examples 18 to 20, wherein the nominal switching time includes the time of a rising edge or a falling edge of the control signal.

[0134] Example 22. A half-bridge controller according to any one of Examples 18 to 21, wherein the at least one of the high-side switch or the low-side switch is a transistor switch, and the threshold voltage is a threshold voltage of the transistor switch.

[0135] Example 23. A half-bridge controller according to any one of Examples 18 to 22, wherein the high-side switch or the at least one of the low-side switches is a transistor switch, and wherein the voltage across the at least one of the high-side switch or the low-side switch includes at least one of the voltage between the load terminals of the transistor switch or the voltage between the control terminal and the load terminal of the transistor switch.

[0136] Example 24. A half-bridge controller according to any of Examples 14 to 23, wherein the switching delay comprises at least one of a turn-off delay or a turn-on delay.

[0137] Example 25. A half-bridge controller according to any of Examples 14 to 24, wherein the current through the half-bridge is a current through a node between the high-side switch and the low-side switch.

[0138] Example 26. The half-bridge controller of any one of Examples 14 to 25, further comprising:

[0139] a prediction circuit configured to predict phase angles of the plurality of half bridges, and

[0140] A multiplexer is configured to select the half-bridge for determining the switching delay from the plurality of half-bridges based on the phase angle.

[0141] Example 27. A half-bridge controller according to any of Examples 14 to 26, wherein the control circuit is further configured to apply dead time compensation based on the polarity of the current through the half-bridge.

[0142] Example 28. A half-bridge controller according to Example 27, wherein the control circuit is configured to apply the dead time compensation by at least one of: modifying a reference voltage based on which the control of the half-bridge is based; or modifying a pulse width modulation mode according to which the half-bridge is controlled.

[0143] Example 29. A system comprising a half bridge and a half bridge controller according to any one of Examples 14 to 28.

[0144] Although specific embodiments have been shown and described herein, it will be appreciated by those of ordinary skill in the art that various alternatives and / or equivalent implementations may replace the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptation or variation of the specific embodiments discussed herein. Therefore, it is intended that the present invention is limited only by the claims and their equivalents.

Claims

1. A method for determining the polarity of a current (Iout) through a half-bridge (21), comprising: determining a switching delay (tdel, ton, toff) of at least one of a high-side switch (QH) or a low-side switch (QL) of the half-bridge (21), and Based on the comparison of the switching delay (tdel, ton, toff) with a threshold value, the polarity of the current (Iout) through the half-bridge (21) is determined.

2. The method of claim 1, wherein the switching delay (tdel, ton, toff) of at least one of the high-side switch (QH) or the low-side switch (QL) of the half-bridge (21) is determined as: a time difference between a nominal switching time of a control signal (GH, GL) of the high-side switch (QH) or the low-side switch (QL) and a time at which a voltage (Vbody) across the at least one of the high-side switch (QH) or the low-side switch (QL) crosses a predefined threshold voltage.

3. The method according to claim 2, wherein the nominal switching time comprises the time of a rising edge or a falling edge of the control signal (GH, GL).

4. The method according to claim 2 or 3, wherein the at least one of the high-side switch (QH) or the low-side switch (QL) is a transistor switch, and the threshold voltage is a threshold voltage of the transistor switch.

5. A method according to claim 2 or 3, wherein the at least one of the high-side switch (QH) or the low-side switch (QL) is a transistor switch, and wherein the voltage (Vbody) across the at least one of the high-side switch (QH) or the low-side switch (QL) includes at least one of the voltage between the load terminals of the transistor switch or the voltage between the control terminal and the load terminal of the transistor switch.

6. The method according to any one of claims 1 to 3, wherein the switching delay (tdel, ton, toff) comprises at least one of a turn-off delay (toff) or a turn-on delay (ton).

7. The method according to any one of claims 1 to 3, further comprising selecting the half-bridge (21) for determining the switching delay (tdel, ton, toff) from a plurality of half-bridges (21) based on a phase angle prediction.

8. A method for dead time (td) compensation in a half bridge (21), comprising: Determining the polarity of the current (Iout) through the half-bridge (21) according to a method according to any one of claims 1 to 7, and Dead time (td) compensation is applied based on the polarity of the current (Iout) through the half bridge (21).

9. The method of claim 8, wherein applying the dead time (td) compensation comprises at least one of: modifying a reference voltage, on which the control of the half-bridge (21) is based, or A pulse width modulation pattern is modified according to which the half bridge (21) is controlled.

10. A half-bridge controller (20), comprising: A measurement circuit (23) configured to determine a switching delay (tdel, ton, toff) of at least one of a high-side switch (QH) or a low-side switch (QL) of a half-bridge (21), and A control circuit (22) is configured to determine the polarity of a current (Iout) through the half-bridge (21) based on a comparison of the switching delay (tdel, ton, toff) with a threshold value.

11. A half-bridge controller (20) according to claim 10, wherein the measurement circuit (23) is configured to determine the switching delay (tdel, ton, toff) of at least one of the high-side switch (QH) or the low-side switch (QL) of the half-bridge (21) as: a time difference between a nominal switching time of a control signal (GH, GL) of the high-side switch (QH) or the low-side switch (QL) and a time when a voltage (Vbody) across the at least one of the high-side switch (QH) or the low-side switch (QL) crosses a predefined threshold voltage.

12. A half-bridge controller (20) according to claim 11, wherein the measurement circuit (23) includes a comparator (60), wherein a first input of the comparator (60) is configured to receive the voltage (Vbody) across at least one of the high-side switch (QH) or the low-side switch (QL), and a second input of the comparator (60) is configured to receive the threshold voltage.

13. A half-bridge controller (20) according to claim 12, wherein the measurement circuit (23) includes a counter (61; 154), wherein a first input of the counter (61; 154) is coupled to the output of the comparator (60), wherein a second input of the counter (61; 154) is configured to receive the control signal (GH, GL), and wherein the counter (61; 154) is configured to start counting based on a first signal at one of the first input or the second input, and to stop counting based on a second signal at the other of the first input or the second input.

14. A half-bridge controller (20) according to any one of claims 11 to 13, wherein the at least one of the high-side switch (QH) or the low-side switch (QL) is a transistor switch, and the threshold voltage is a threshold voltage of the transistor switch.

15. A half-bridge controller (20) according to any one of claims 11 to 13, wherein the at least one of the high-side switch (QH) or the low-side switch (QL) is a transistor switch, and wherein the voltage (Vbody) across the at least one of the high-side switch (QH) or the low-side switch (QL) comprises at least one of the voltage between the load terminals of the transistor switch or the voltage between the control terminal and the load terminal of the transistor switch.

16. The half-bridge controller according to any one of claims 10 to 13, further comprising: Prediction circuits (170-173) configured to predict phase angles for a plurality of half-bridges (21), and A multiplexer (151A, 151B) is configured to select the half-bridge (21) for determining the switching delay (tdel, ton, toff) from among the plurality of half-bridges (21) based on the phase angle.

17. A half-bridge controller (20) according to any one of claims 10 to 13, wherein the control circuit (22) is further configured to apply a dead time (td) compensation based on the polarity of the current (Iout) through the half-bridge (21).

18. A system comprising a half-bridge (21) and a half-bridge controller (20) according to any one of claims 10 to 17.

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