Method and apparatus for wafer handling and processing

Abstract

The present invention relates to methods and apparatus for wafer handling and processing. An assembly includes a device wafer received in a recess of a carrier wafer. The device wafer includes a protrusion terminating at an active surface supporting an integrated circuit, the protrusion being surrounded by a peripheral flat portion extending to the outer periphery of the device wafer. Methods of wafer thinning using the previously described carrier wafer and device wafer are also disclosed. Various embodiments of a carrier wafer having a recess and methods of manufacture are also disclosed.

Description

[0001] Priority claim

[0002] This application claims the benefit of the filing date of U.S. Patent Application No. 16 / 386,517, filed on April 17, 2019, for “Methods and Apparatus for Wafer Handling and Processing.” Technical Field

[0003] Embodiments disclosed herein relate to methods and apparatus for semiconductor wafer handling and processing. More particularly, embodiments disclosed herein relate to methods and apparatus for wafer handling that provide enhanced protection of the wafer edge during handling and processing. Background Art

[0004] Although bulk substrates in the form of semiconductor material take many forms, including layers of semiconductor material carried on substrates of other materials (e.g., glass, sapphire, another insulator), the primary form of bulk substrate employed in the microelectronics industry for fabricating microelectronic devices based on semiconductor materials has been semiconductor wafers (e.g., single crystal silicon wafers).

[0005] As the industry has progressed over time to increase the density of integrated circuits, reduce feature sizes and also increase product throughput and production, while accommodating the ever-decreasing size of devices employing integrated circuits, the lateral dimensions of semiconductor wafers have become larger, on the order of 300 mm, while devices fabricated from such wafers have become thinner, on the order of 50 μm or less. Additionally, in many cases, such as memory devices, multiple memory dies are stacked vertically, on the order of four, eight, twelve, sixteen or more dies, some or all of which (substantially all, except the topmost die) are configured to have conductive vias extending vertically therethrough for communication with adjacent dies, and are configured to have circuitry external to the die stack. Such vias, which are often referred to as "through silicon vias" or "TSVs," are spaced at relatively close spacings, and are formed during wafer processing and prior to singulating individual dies from the wafer.

[0006] Semiconductor wafers used for microelectronic device manufacturing and in particular for examples using silicon wafers are conventionally initially provided with a nominal thickness between about 600 μm and about 775 μm. The blind holes used to make TSVs are formed from the surface of the wafer received from the supplier and are filled with conductive material during one of many actions in the process of manufacturing integrated circuits in and above the active surface of the wafer to form a so-called device wafer containing a large number of in-process microelectronic devices such as memory, logic or processor dies. The semiconductor material must then be removed by, for example, back grinding and etching to expose the blind holes filled with conductive material from the back side of the device wafer to complete the TSV. Subsequently, the back side of the thinned device wafer can be passivated and contacts or terminal pads can be formed above the exposed ends of the TSVs. Optionally, a redistribution layer (RDL) can be formed above the back side to re-arrange the contact positions of the TSVs. The resulting structure after the thinning of the wafer is quite fragile due to its thinness and the incorporation of TSVs.

[0007] refer to Figures 1A to 1E , a conventional temporary bonding process flow will be described. During handling and processing, the device wafer 100 is supported and moved between locations by a carrier 102, often referred to as a "carrier wafer" or "handler", which is similar in size and shape to the device wafer and to which the device wafer is adhesively bonded. In one conventional example, a layer of thermoplastic polymer adhesive 104 is used for such bonding, and the adhesive is applied to the carrier wafer by spin coating. The thickness of the adhesive can be selected based on, for example, the surface morphology of the active surface 105 of the device wafer 100 to be bonded to the carrier wafer 102. Conventionally, the adhesive 104 is arranged to be between about 5 μm and about 150 μm in thickness. One conventional thermoplastic adhesive material for adhesive bonding is commercially available from Brewer Science, Inc. of Rolla, Missouri. HT-10.10. After application of adhesive 104, carrier wafer 102 having adhesive 104 thereon is baked to remove solvent from adhesive 104, such as solvent within applied adhesive 104 that facilitated application of adhesive 104.

[0008] Reference now Figure 1B, the device wafer 100 and the adhesive-coated carrier wafer 102 are bonded together by applying heat and pressure (i.e., normal force) between the two wafers. For example, the device wafer 100 and the adhesive-coated carrier wafer 102 may be mechanically pressed together under high temperature conditions sufficient to soften the adhesive 104 and promote bonding between the device wafer 100 and the carrier wafer 102. The temperature conditions during bonding may be selected to be close to or above the glass transition temperature (Tg) of the thermoplastic adhesive material of the adhesive 104. A portion of the softened adhesive 104 may be squeezed out around the periphery of the interface 106 between the device wafer 100 and the carrier wafer 102 during bonding. Excess adhesive around the periphery of the interface 106 is removed, for example, by dissolving the excess adhesive with a solvent.

[0009] As previously described, the back side 108 of the device wafer 100 is thinned by processes such as abrasive grinding and / or chemical mechanical polishing with or without dry etching. The thinning process can reduce the thickness of the device wafer 100 from an initial thickness to, for example, a thickness of about 50 microns or less. As described above, the thinning process can expose the ends of the conductive vias in the device wafer 100 on the back side 108 of the thinned device wafer 100 to form TSVs. The contact pads 110 ( Figure 1C Passivation and formation of the etched substrate (shown in FIG) may follow the thinning.

[0010] Reference now Figure 1D , after thinning and backside processing, the polymer adhesive 104 ( Figure 1A ) and applies a shear force in direction 112 (ie, substantially parallel to the interface 106 between the device wafer 100 and the carrier wafer 102 ( Figure 1B ) to remove the device wafer 100 from the carrier wafer 102. The heat-induced softening of the adhesive 104 enables the device wafer 100 to slide off the carrier wafer 102. The residual adhesive can be cleaned (i.e., removed) from the device wafer 100 using a solvent, and the device wafer 100 can then be mounted on the film frame support system 114.

[0011] like Figure 1E As shown in , after being mounted on a film frame support system 114, the device wafer 100 can be separated or "singulated" into individual dies 116. The individual dies can then be packaged or assembled with other dies and packaged to form a semiconductor device or integrated device.

[0012] The main causes of device wafer scrap, and especially device wafer scrap incorporating TSVs, are edge chipping and cracking. For example, device wafer edges may be susceptible to damage from wafer edge handling and contact with structures of front opening shipping boxes (FOSBs) (see, e.g., U.S. Patent Publication 2004 / 0126220) and front opening universal pod (FOUP) cassette container lids (see, e.g., International Patent Publication WO 2014 / 189739). In addition, the volume of adhesive used to bond the device wafer to the carrier wafer must be carefully managed and controlled to avoid adhesive undercutting and lack of support at the device wafer edge due to insufficient adhesive volume, or squeeze-out and contamination at the device wafer edge and adjacent surfaces due to excessive adhesive volume. Due to the latter situation, special edge cleaning techniques must be employed, increasing costs and slowing down processing throughput.

[0013] Furthermore, excess bonding material flowing from the interface between the device wafer and the carrier wafer may contaminate equipment used for back-side processing, resulting in costly downtime while the equipment is cleaned.

[0014] The inventors have recognized the foregoing problems and other problems with conventional device wafer handling and processing techniques, and developed embodiments of methods and apparatus to address the problems. Summary of the invention

[0015] In one embodiment, an assembly includes: a carrier wafer comprising a recess having a flat bottom surface surrounded by peripheral sidewalls; and a device wafer having an active surface secured to the flat bottom surface of the recess with an adhesive material, the combined thickness of the device wafer and the adhesive material not substantially exceeding the depth of the recess from the flat bottom surface to the upper extent of the peripheral sidewalls.

[0016] In another embodiment, a device chip includes: a semiconductor material body having a lateral extent; and an active surface supporting an integrated circuit, which is on one side of the semiconductor material body, the active surface extending to a peripheral side wall, the lateral extent of the peripheral side wall being smaller than the lateral extent of the semiconductor material body and extending from the active surface and perpendicular to the active surface to a peripheral flat portion, the peripheral flat portion being perpendicular to the peripheral side wall and surrounding the peripheral side wall and extending laterally outward to the periphery of the semiconductor material body.

[0017] In yet another embodiment, a method includes inserting a portion of a device wafer including an active surface for supporting an integrated circuit into a recess of a carrier wafer, the portion of the device wafer including a protrusion defined by side walls of a semiconductor material body of the device wafer and surrounded by a peripheral flat portion of the semiconductor material body extending to a lateral periphery of the device wafer, the peripheral flat portion extending laterally above the side walls of the recess of the carrier wafer; and securing the device wafer to a bottom surface of the recess of the carrier wafer through at least the active surface with an adhesive material.

[0018] In yet another embodiment, a carrier wafer for supporting a device wafer thereon includes a body having a recess sized for at least partially receiving the device wafer therein, the recess having a non-linear bottom surface. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figures 1A-1E A conventional device wafer handling process employed in backside processing of a device wafer is depicted.

[0020] Figure 2 is a side schematic cross-sectional elevation view of a portion of a device wafer bonded to a conventional carrier wafer after thinning of the device wafer;

[0021] Figure 3 is a side schematic cross-sectional elevation view of a portion of a device wafer bonded to a carrier wafer according to an embodiment of the present invention after thinning of the device wafer;

[0022] Figures 4A-4E is to process the device chip to achieve Figure 2 a side schematic cross-sectional elevational view of the method of assembly of the configuration shown;

[0023] Figure 5A is a side schematic cross-sectional elevation view of another example of a carrier wafer suitable for use in semiconductor wafer processing in an embodiment according to the present invention, and Figure 5B yes Figure 5A A side schematic cross-sectional elevation view of a variation of an embodiment of;

[0024] Figure 6 is a side schematic cross-sectional elevation view of yet another example of a carrier wafer suitable for use in semiconductor wafer processing in an embodiment according to the present invention;

[0025] Figure 7 is a side schematic cross-sectional elevation view of yet another example of a carrier wafer suitable for use in semiconductor wafer processing in an embodiment according to the present invention; and

[0026] Figures 7A to 7E Is manufacturing Figure 7 Schematic depiction of an example method of a carrier wafer. DETAILED DESCRIPTION

[0027] Methods of processing semiconductor wafers are disclosed, as well as embodiments of carrier wafers suitable for use in practicing the methods. Assemblies including a device wafer and a carrier wafer are described before and after processing according to embodiments of the invention.

[0028] The following description provides specific details such as size, shape, material composition, and orientation in order to provide a full description of embodiments of the present invention. However, a person of ordinary skill in the art will understand that embodiments of the present invention may be practiced without adopting these specific details. Embodiments of the present invention may be practiced in conjunction with conventional manufacturing techniques employed in the industry. In addition, the description provided below does not form a complete process flow for processing and disposing device wafers according to the present invention, an assembly including a device wafer and a carrier wafer, or an apparatus for processing a device wafer mounted to a carrier wafer. Only those process actions and structures necessary for understanding embodiments of the present invention are described in detail below. Additional actions to form a complete thinned device wafer, a complete thinned device wafer mounted to a carrier wafer, or a complete thinned device wafer including TSVs in association with the actions and structures described herein may be performed by conventional manufacturing processes.

[0029] The drawings presented herein are for illustrative purposes only and are not intended to be actual views of any particular material, component, structure, device or system. Changes in the shapes depicted in the drawings, for example due to manufacturing techniques and / or tolerances, should be expected. Therefore, the embodiments described herein should not be interpreted as being limited to specific shapes or regions as described, but rather include shape deviations, for example, caused by manufacturing. For example, a region described or described as box-shaped may have rough and / or nonlinear features, and a region described or described as circular may include some rough and / or linear features. In addition, the sharp angles between the illustrated surfaces may be rounded, and vice versa. Therefore, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions and do not limit the scope of the claims of the present invention. The drawings are not necessarily drawn to scale.

[0030] As used herein, the term "device wafer" means and includes a bulk substrate that includes one or more semiconductor materials and is easily thinned to achieve a smaller thickness by removing semiconductor materials from the wafer. Such substrates may be configured as conventional circular wafers, other bulk substrates, or fragments of such wafers or bulk substrates. The device wafer may include an array of semiconductor die sites, each of which includes an integrated circuit, and the die sites may be singulated into individual dies or larger wafer fragments. Prior to processing according to embodiments of the present invention, the active surface of the device wafer may be fabricated with integrated circuits, and additional dies or die stacks may be placed thereon and optionally encapsulated. It is contemplated that embodiments of the present invention are particularly suitable for implementation in conjunction with conventional circular silicon wafers, but the present invention is not limited thereto.

[0031] As used herein, the term "carrier wafer" means and includes a semiconductor substrate of glass or other suitable material that exhibits sufficient rigidity and a coefficient of thermal expansion (CTE) compatible with the device wafer to be bonded, and supports the device wafer for thinning and planarization. Although not required, it is expected that the carrier wafer will generally correspond in size and shape to that of the device wafer.

[0032] As used herein, the terms "comprising," "including," "containing," "characterized by," and their grammatical equivalents are inclusive or open terms that do not exclude additional unrecited elements or method actions, and also encompass the more restrictive terms "consisting of," and "consisting essentially of," and their grammatical equivalents.

[0033] As used herein, the term "may" with respect to materials, structures, features, or method acts indicates that such are intended for use in practicing embodiments of the invention, and such terminology is used in preference to the more restrictive term "is" so as to avoid any suggestion that other compatible materials, structures, features, and methods that may be used in combination therewith should or must be excluded.

[0034] As used herein, the terms "longitudinal," "vertical," "lateral," and "horizontal" refer to a major plane of a substrate (e.g., a substrate material, a substrate structure, a substrate configuration, etc.) in or on which one or more structures and / or features are formed, and are not necessarily defined by the Earth's gravitational field. A "lateral" or "horizontal" direction is a direction generally parallel to the major plane of a substrate, while a "longitudinal" or "vertical" direction is a direction generally perpendicular to the major plane of a substrate. A major plane of a substrate is defined by a surface of the substrate having a relatively larger area than other surfaces of the substrate.

[0035] As used herein, spatially relative terms, such as "below", "below", "lower", "bottom", "above", "above", "upper", "top", "front", "back", "left", "right", etc., can be used to simplify descriptions to describe the relationship of one element or feature to another element or feature, as illustrated in the figures. Unless otherwise specified, spatially relative terms are intended to cover different orientations of materials in addition to the orientation depicted in the drawings. For example, if the material in the drawings is inverted, the elements described as being "above" or "above" or "on" or "on top" of other elements or features will be oriented "below" or "below" or "below" or "bottom" of the other elements or features. Therefore, the term "above..." can cover both above and below orientations depending on the context in which the term is used, which will be apparent to those skilled in the art. The material can be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped), and the spatially relative descriptors used herein can be interpreted accordingly.

[0036] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0037] As used herein, the terms "configured" and "configuration" refer to the size, shape, material composition, orientation, and arrangement of one or more of at least one structure and at least one device to facilitate the operation of the at least one structure and at least one device in a predetermined manner.

[0038] As used herein, the term "substantially" with respect to a given parameter, property, or condition means and encompasses

[0039] A person of ordinary skill in the art will understand the degree to which a given parameter, property, or condition satisfies a degree of variance (e.g., within acceptable manufacturing tolerances). By way of example, depending on the particular parameter, property, or condition being substantially satisfied, the parameter, property, or condition may be at least 90.0% satisfied, at least 99.0% satisfied, or even at least 99.9% satisfied.

[0040] As used herein, "about" or "approximately" with respect to a numerical value of a particular parameter includes numerical values ​​and degrees of variation of numerical values ​​that one of ordinary skill in the art would understand to be within an acceptable tolerance for the particular parameter. For example, "about" or "approximately" with respect to a numerical value may include additional numerical values ​​that are within the 90.0% to 110.0% range of the numerical value, such as within the 95.0% to 105.0% range of the numerical value, within the 97.5% to 102.5% range of the numerical value, within the 99.0% to 101.0% range of the numerical value, within the 99.5% to 100.5% range of the numerical value, or within the 99.9% to 100.1% range of the numerical value.

[0041] As used herein, unless otherwise indicated, the terms "layer" and "film" mean and include a layer, sheet or coating of material residing on a structure, which layer or coating may be continuous or discontinuous between material portions and which may be conformal or non-conformal.

[0042] Figure 2 Depicted is a portion of a device wafer bonded to a conventional carrier wafer 202 by bonding material 204, after thinning of the device wafer to achieve a thinned device wafer 200t, with active surface 206 supporting integrated circuits bonded to carrier wafer 202 by bonding material 204, and backside 208 of device wafer 200 having been subjected to a thinning operation as previously described. Figure 2 As shown in FIG. 2 , the corners 210 of the thinned device wafer 200 t are largely exposed and susceptible to damage during handling and processing due to contact of the peripheral edge 212 with equipment.

[0043] Suitable bonding materials 204 may include low temperature waxes, hydrocarbon oligomers and polymers, modified acrylates, modified epoxies, modified silicones, and high temperature thermoplastic or thermosetting polymers. The bonding material 204 may be applied as a liquid or flowable gel, as a tape, or as a preformed film, for example, by spin coating. More specifically, the bonding material 204 may include a thermosetting or thermoplastic polymer material, preferably formulated to withstand high processing temperatures such as those used in material deposition, while not permitting relative lateral or vertical movement between the carrier wafer 202 and the device wafer 200 secured thereto. As a specific non-limiting example, the bonding material 204 may include a cured or partially cured thermoset material or a precursor for forming a thermoset material (e.g., Silicone Adhesive 401LC, available from Shin-Etsu Silicones of America, Inc., 1150 Damar Drive, Akron, OH, 44305; Adhesive BSI.T14049A, Adhesive BSI.D16052K, each available from Brewer Science, 2401 Brewer Drive, Rolla, MO, 65401; or a precursor material or a partially cured variant thereof). The thickness of the bonding material 204 may be, for example, between about 0.5 microns and about 5 microns to provide as thin a bond line as possible while maintaining sufficient adhesion of the device wafer 200 to the carrier wafer 202. As a specific non-limiting example, the thickness of the bonding material 204 may be, for example, between about 2 microns and about 3 microns (e.g., about 2.5 microns). It is desirable that the thickness of the bonding material 204 be substantially uniform across the active surface 206 of the carrier wafer 202 to which it is applied before and after the device wafer 200 is adhered thereto. In addition to the use of bonding materials, materials for so-called barrier layers that are susceptible to heating in response to laser beam irradiation and release or stripping layers that are susceptible to ashing in response to laser beam irradiation are known to those skilled in the art. Any suitable bonding material alone or in combination with release or stripping materials and barrier materials may be used in conjunction with embodiments of the present invention, none of which will rely on the details of such materials.

[0044] The technique used to peel the device wafer from the carrier wafer after processing depends largely on the composition of the bonding material and whether this can be achieved by solvent release, photolysis (e.g., ultraviolet (UV) or infrared (IR) exposure of the bonding material through the carrier wafer), thermomechanical techniques, or thermal decomposition.

[0045] Figure 3A portion of a thinned device wafer 200t is depicted bonded to a carrier wafer 300 of an embodiment of the present invention by an adhesive material 204 after thinning of the bulk of the semiconductor material of the device wafer 200 to achieve the thinned device wafer 200t. Figure 3 It is readily apparent that the carrier wafer 300 is significantly different from the bonding Figure 2 2. In particular, a recess 302 having a bottom surface 304 of the bottom layer, which may also be characterized as a bottom layer, has been formed in the major surface 306 of the carrier wafer 300 (see Figure 4A ) is formed from one side thereof, the recess 302 is surrounded by a sidewall surface 308 of a peripheral sidewall 310 between the recess 302 and an outer peripheral edge 312 of the carrier wafer 300. As depicted, the bottom surface 304 of the underlying layer can be a flat linearly extending surface. As shown, the thinned device wafer 200t resides within the recess 302 such that the device wafer edge 212, and specifically the corner 210 thereof, is substantially isolated from contact with external structures by the peripheral sidewall 310.

[0046] Figures 4A to 4E Depicted is a process flow for implementation of a carrier wafer according to an embodiment of the present invention as well as for device wafer handling and back-side processing using such a carrier wafer.

[0047] like Figure 4A , a carrier wafer precursor structure 300p of a semiconductor material (e.g., silicon) or a glass material (e.g., soda-lime glass, borosilicate glass) is provided. A recess 302 is formed from a major surface 306 (shown in phantom) of the carrier wafer precursor structure 300p to a selected depth D1 sufficient to substantially contain a bonding material and a thinned device wafer 200t within the recess 302. In other words, the height of the sidewall surface 308 of the peripheral sidewall 310 is substantially the same as the thickness of the adhesive material 204 plus the thickness of the thinned device wafer 200t, so that the upper extent 314 of the peripheral sidewall 310 and the back side 208 of the thinned device wafer 200t can be substantially coplanar at least in a horizontal plane parallel to the back side 208 of the thinned device wafer 200t, and the back side 208 of the thinned device wafer 200t can actually reside below a plane that coincides with the upper extent 314 of the peripheral sidewall 310, as described below.

[0048] The recess 302 may be formed in the carrier wafer precursor structure 300p formed, for example, from single crystal silicon, by a grinding process, optionally followed by an etching process. The grinding may be achieved by an apparatus employed in back grinding a device wafer, for example, a Taiko back grinding process may be performed by a DAG810 automatic grinder supplied by DISCO Corporation, Tokyo, Japan. An etchant (e.g., tetramethylammonium hydroxide (TMAH), TMAH and water (TMAHW), or ammonium hydroxide and water (AHW)) may be used to remove grinding damage to the underlying surface 304 and the sidewall surface 308, and to provide a smooth surface morphology to increase the mechanical strength of the carrier wafer 300. If the carrier wafer precursor structure 300p includes glass, the carrier wafer 300 having the recess 302 may be formed by molding, or may be formed by a grinding process followed by etching, similar to the process for the silicon precursor structure but using an apparatus configured for grinding glass and an etchant effective for glass materials (e.g., hydrofluoric acid (HF) in aqueous solution). Regarding the silicon or glass carrier wafer precursor structure 300p, before or instead of etching, the surface of the recess may be polished to obtain a smooth surface morphology.

[0049] like Figure 4B 3, a device wafer 200 is provided that optionally includes a TSV precursor structure (not shown) configured as a blind via formed from a side of the device wafer including an active surface 206 and containing a conductive material. The device wafer 200 can then be peripherally thinned from the active surface 206 supporting the integrated circuit toward the back side 208 by a depth D1 greater than the recess 302 using a grinding process. Figure 4A ) and a lateral distance L1 from the outer peripheral edge 212 to provide a protrusion P terminating in a laterally extending peripheral flat portion 216 that surrounds the protrusion P and extends to the outer peripheral edge 212. The protrusion P can be received in the recess 302 of the carrier wafer 300 ( Figure 4C ), wherein there is a lateral gap distance L2 between the sidewall 214 of the protrusion P and the sidewall surface 308 of the peripheral sidewall 310 of the carrier wafer 300. The lateral gap distance L2 is desirably as small as reasonably possible and is in the range of about 10 μm to about 200 μm. The sidewall 214 of the protrusion P may be optionally subjected to silicon etching to remove any surface damage or deposition of silicon or other materials such as passivation materials as needed or desired to prevent or reduce the possibility of chipping or cracking. In the case of a generally disc-shaped device wafer 200, the protrusion P may have a generally cylindrical shape, the sidewall surface 308 of the peripheral sidewall 310 may be generally circular, and the distance L2 may be from the centerline C of the device wafer. L Measure the radial distance between the two.

[0050] like Figure 4C, the device wafer 200 is inverted and the protrusion P is inserted into the recess 302 to contact the bonding material 204 on the bottom layer 304 of the recess 302, with the sidewall 214 spaced apart from the sidewall surface 308 to bond the active surface 206 to the bottom layer 304 of the recess, leaving a generally annular region between the sidewall of the protrusion P and the sidewall surface 308 of the peripheral sidewall 310. The peripheral flat portion 216 of the device wafer 200 may extend laterally above the peripheral sidewall 310. As can be seen, the bonding material 204 may be pressed laterally from between the active surface 206 and the bottom layer 304 and squeezed upward at 204e into the reservoir region R between the sidewall 214 of the protrusion P and the sidewall surface 308. Conventionally, for example, for thermoplastic and thermosetting polymer bonding materials, the assembly of the carrier wafer 300 and the device wafer 200 can be placed in a heated mechanical press, and sufficient pressure (i.e., normal force) and temperature are applied to cause the bonding material 204 to flow and fill in the surface topographic features of the active surface 206 of the device wafer to achieve close and continuous contact between the active surface 206 and the bottom layer 304 of the device wafer recess 302, and excess bonding material is squeezed into the reservoir area R.

[0051] like Figure 4D , the device wafer 200 is thinned from the back side 208, such as by back grinding, to a height that is approximately above (e.g., close to) or substantially the same as the upper extent 314 of the peripheral sidewall 310 of the carrier wafer 300. After this thinning, a silicon dry etch (i.e., reactive ion etch) process may then be used to further reduce the thickness of the now thinned device wafer 200t to a level below the height of the upper extent 314 of the peripheral sidewall 310 of the carrier wafer 300, which (where applicable to the particular device wafer) also exposes the ends of the conductors of the TSVs of the thinned device wafer 200t. The adhesive material 204 that is squeezed upward at 204e may also be etched to a desired height below the peripheral sidewall 310, or removed using a solvent, as is known in the art.

[0052] like Figure 4E As depicted in FIG. 2 , after the above-described processing, the peripheral edge 212 of the thinned device wafer 200 t resides below the upper extent 314 of the peripheral sidewall 310 of the carrier wafer 300 and is protected by the carrier wafer 300 from handling and processing.

[0053] When it is desired to remove the thinned device wafer 200t from the carrier wafer 300, any conventional peeling and removal technique as described above may be employed. In the case of thermomechanical peeling and removal, a twisting or torsional force may be applied to the thinned device wafer 200t by a carrier temporarily secured (e.g., by a temporary adhesive or vacuum) to the back side 208 of the thinned device wafer 200t after the bonding material has been sufficiently thermally softened to release the thinned device wafer 200t, because the presence of the carrier wafer peripheral sidewall 310 precludes the application of conventional linear shear forces. When the carrier wafer comprises glass and the bonding material readily releases in response to radiation, laser release may be employed, which uses ultraviolet (UV) radiation from, for example, a 250nm to 400nm wavelength UV laser. When the carrier wafer comprises silicon and the bonding material readily releases in response to radiation, laser release may be employed, which uses near infrared (NIR) radiation from, for example, a 1000nm to 1300nm wavelength NIR laser. As mentioned above with respect to adhesive materials and other barrier, release or stripping materials, embodiments of the present invention are not limited to any particular peeling and wafer release processes, and any conventional adhesive materials and peeling processes may be employed.

[0054] Reference now Figures 5A to 7E , describing other embodiments and methods of manufacturing a carrier wafer according to the present invention. It should be noted that the curvature and overall configuration of the recess of the depicted carrier wafer may be exaggerated in some instances for clarity.

[0055] Figure 5A A carrier wafer 400 is depicted in which a notch 402 is configured with a shallow arcuate concave bottom surface 404 terminating at a relatively small radius upright curved peripheral surface 410. This configuration of a generally straight-diameter "dish" shape may be formed using a grinding wheel in a sweeping motion, or the carrier wafer may be "turned" in a lathe-type motion. Figure 5B Similar to Figure 5A , except that the recess 502 of the carrier wafer 500 is configured with a very shallow, generally conical bottom surface 504, which in turn can be achieved using a different, less complex setup for the grinding process. In either case, after grinding the silicon or glass carrier substrate precursor, the surface morphology of the recess can be smoothed using an etchant and optionally a polishing mechanism.

[0056] Figure 6Depicted is a carrier wafer 600 formed into a "cup" shape having a generally concave arcuate dished bottom surface 604 with a notch 602. A surface 606 of the body of the carrier wafer 600 opposite the bottom surface 604 is similarly arcuate and dished in the same direction as the bottom surface 604 to form a generally convex surface. This shape can be achieved by initially forming the carrier wafer precursor in a planar shape, and then heating and forming into the final shape on a curved fixture. This shape can also be achieved by using a pressure fixture that applies a vacuum or suction to hold and form the carrier wafer 600 as the material of the carrier wafer precursor relaxes.

[0057] Figure 7 A carrier wafer 700 is depicted including a dished recess 702 having a generally concave bottom surface 704 that opens to a planar peripheral portion FP of a major surface of the carrier wafer 700 in which the dished recess 702 has been formed. 704. To form the carrier wafer 700, as Figures 7A to 7E As shown in the figure Fig. 7A A planar full thickness carrier wafer precursor 700P is provided as depicted in Figure 7B As depicted in FIG. 1 , the carrier wafer precursor 700P is fixed in place on the movable center fixture J, after which ... Figure 7C As depicted in FIG. 1 , the center fixture J moves upward as shown by the arrow to apply stress and force the center region C of the carrier wafer precursor 700P into a dome shape D in the elastic strain response of the wafer material. Fig.7D The linear motion shown by the arrow in FIG. 1 is parallel to the dome shape D, and the linear motion ... Fig. 7A and 7B The central fixture J is then Fig.7D As shown in FIG. 1 , the carrier wafer precursor 700P moves downward to release the stress on the carrier wafer precursor 700P. After the stress is released, the carrier wafer precursor 700P is as shown in FIG. Fig. 7E As shown, relax to form Figure 7 A carrier wafer 700 is shown.

[0058] It should be noted that the bonding material may be applied to the device wafer or the carrier wafer prior to lamination of the device wafer and the carrier wafer. Figures 5A to 7In embodiments where the corresponding notch has a nonlinear bottom surface, it should be noted that even full thickness silicon device wafers can flex several millimeters without breaking, and wafers thinned to less than 100 μm can actually curl upon themselves without breaking. Thus, for implementations of these embodiments, the curvature or other nonlinearity of the carrier wafer notch bottom can be adjusted to accommodate the bending stresses that a particular device wafer configuration can withstand without cracking or other degradation. Similarly, the back grinding process can be customized in terms of applied force and grinding wheel path to gradually adjust the normal force applied to the portion of the device wafer that has been thinned to avoid damage. Additionally, the shape of the grinding wheel can be adjusted to achieve the desired carrier wafer notch bottom configuration.

[0059] As will be appreciated by those skilled in the art, implementations of embodiments of the present invention may provide numerous advantages over prior art state of the art apparatus and methods for device wafer handling. For example, and not by way of limitation, improved die yield per wafer may result from the protected edges of the thinned wafers, the likelihood of chipping of the wafer edges due to edge handling has been reduced due to the protection of the carrier wafer, and the propensity for wafer cracking losses may be reduced due to the elimination of edge chip initiation points during device wafer peeling from the carrier wafer. Furthermore, due to the support provided by the carrier wafer and the peripheral edge protection of the carrier wafer sidewalls, handling of extremely thin wafers of about 30 μm or less may be achieved while maintaining die yield.

[0060] Additionally, and again by way of example and not limitation, implementations of embodiments of the present invention present less risk of downstream tool contamination from adhesive materials due to the encapsulation of the carrier wafer. Similarly, "squeeze out" of adhesive material from between the edge of the device wafer and the carrier is eliminated by providing a reservoir in the carrier wafer recess through the space between the edge of the device wafer and the sidewall surface of the carrier wafer sidewall. Furthermore, due to the reservoir, sufficient adhesive material can be provided between the device wafer and the carrier wafer to ensure complete coverage between the two wafers to the edge of the device wafer and beyond the edge of the device wafer, thereby eliminating any possibility of adhesive undercutting. In another advantageous aspect of implementations of embodiments of the present invention, no special edge cleaning equipment or processes are required, the carrier wafer configuration and processing is adaptable to all existing temporary carrier methods, and the carrier wafer configured in accordance with embodiments of the present invention can be reused after cleaning and recycled multiple times in device wafer processing.

[0061] In one embodiment, an assembly includes: a carrier wafer comprising a recess having a flat bottom surface surrounded by peripheral sidewalls; and a device wafer having an active surface secured to the bottom surface of the recess by an adhesive material, the combined thickness of the device wafer and the adhesive material not substantially exceeding the depth of the recess from the bottom surface to the upper extent of the peripheral sidewalls.

[0062] In another embodiment, a device chip includes: a semiconductor material body having a lateral extent; an active surface supporting an integrated circuit on one side of the body, the active surface extending to a peripheral side wall, the lateral extent of the peripheral side wall being smaller than the lateral extent of the semiconductor material body and extending from the active surface and perpendicular to the active surface to a peripheral flat portion, the peripheral flat portion being perpendicular to and surrounding the peripheral side wall and extending laterally outward to the periphery of the semiconductor material body.

[0063] In yet another embodiment, a method includes inserting a portion of a device wafer including an active surface for supporting an integrated circuit into a recess in a carrier wafer, the portion of the device wafer including a protrusion defined by side walls of a semiconductor material body of the device wafer and surrounded by a peripheral flat portion of the body extending to a lateral periphery of the device wafer, the peripheral flat portion extending laterally above the side walls of the recess in the carrier wafer, and securing the device wafer to a bottom surface of the recess in the carrier wafer through at least the active surface with an adhesive material.

[0064] In yet another embodiment, a carrier wafer for supporting a device wafer thereon includes a body having a recess sized for at least partially receiving the device wafer therein, the recess having a non-linear bottom surface.

[0065] Although certain illustrative embodiments have been described in conjunction with the drawings, those of ordinary skill in the art will recognize and appreciate that the embodiments encompassed by the present invention are not limited to those embodiments explicitly shown and described herein. Specifically, various additions, deletions, and modifications may be made to the embodiments described herein without departing from the scope of the embodiments encompassed by the present invention (such as those claimed herein, including legal equivalents). In addition, features of one disclosed embodiment may be combined with features of another disclosed embodiment and still be encompassed within the scope of the present invention.

Claims

1. An assembly comprising: a generally circular carrier wafer including a recess having a planar bottom surface surrounded by peripheral sidewalls; as well as A generally circular device wafer including an array of unsingulated semiconductor die sites and having an active surface secured to the planar bottom surface of the recess with an adhesive material, the combined thickness of the generally circular device wafer and the adhesive material not exceeding substantially the depth of the recess from the planar bottom surface to the upper extent of the peripheral sidewall.

2. The assembly of claim 1 wherein the combined thickness of the generally circular device wafer and the bonding material is less than the depth of the recess from the planar bottom surface to the upper extent of the peripheral sidewall.

3. The assembly of claim 1 wherein the generally circular carrier wafer comprises silicon or glass.

4. The assembly of claim 1, wherein the substantially circular device wafer has a thickness of 50 μm or less.

5. The assembly of claim 1, wherein the bonding material comprises a high temperature thermosetting polymer, a high temperature thermoplastic polymer, a low temperature wax, a hydrocarbon oligomer, a hydrocarbon polymer, a modified acrylate, a modified epoxy, or a modified silicone.

6. The assembly of claim 1 further comprising a generally annular region between an outer periphery of the generally circular device wafer and a surface of the peripheral sidewall of the generally circular carrier wafer.

7. A device wafer comprising: a generally circular body of semiconductor material having a lateral extent; as well as An array of unsingulated semiconductor die sites having an active surface supporting an integrated circuit on one side of the generally circular body of semiconductor material, the active surface extending to a peripheral sidewall having a lateral extent less than the lateral extent of the generally circular body of semiconductor material and extending from the active surface and perpendicular to the active surface to an annular peripheral flat portion perpendicular to and surrounding the peripheral sidewall and extending laterally outward to the periphery of the generally circular body of semiconductor material.

8. A device chip according to claim 7, wherein the peripheral sidewall of the device chip is sized and configured to be received in a recess of a carrier chip, wherein a lateral gap between the peripheral sidewall of the device chip and the peripheral sidewall of the carrier chip defines the recess, and the annular peripheral flat portion of the device chip extends laterally above the peripheral sidewall of the carrier chip.

9. The device wafer of claim 7 further comprising a TSV precursor structure comprising a conductive material within a blind hole extending from the active surface into the generally circular body of semiconductor material and terminating within the generally circular body of semiconductor material.

10. A method for forming an assembly, comprising: inserting a portion of a device wafer including an active surface supporting an integrated circuit into a recess in a carrier wafer, the portion of the device wafer including a protrusion defined by sidewalls of a body of semiconductor material of the device wafer and surrounded by a peripheral planar portion of the body of semiconductor material extending to a lateral periphery of the device wafer, the peripheral planar portion extending laterally above the sidewalls of the recess in the carrier wafer; as well as The device wafer is secured to a bottom surface of the recess of the carrier wafer through at least the active surface with an adhesive material.

11. The method of claim 10, further comprising using a bonding material comprising a high temperature thermosetting polymer, a high temperature thermoplastic polymer, a low temperature wax, a hydrocarbon oligomer, a hydrocarbon polymer, a modified acrylate, a modified epoxy resin or a modified silicone.

12. The method of claim 10, wherein the device wafer is generally circular and the protrusions are formed into a generally cylindrical shape.

13. The method of claim 10, further comprising removing material from the device wafer from its backside surface toward the active surface to lower the level of the backside surface to at least close to the level of the upper extent of the sidewalls of the recess of the carrier wafer.

14. The method of claim 13, wherein removing material from the device wafer from a backside surface thereof toward the active surface comprises back grinding the backside surface.

15. The method of claim 13, further comprising removing additional material from the backside surface of the device wafer to lower the level of the backside surface below an upper extent of the sidewalls of the recess of the carrier wafer. 16 . The method of claim 15 , wherein removing additional material from the backside surface comprises at least one of etching the backside surface and polishing the backside surface. 17 . The method of claim 15 , wherein removing additional material from the backside surface comprises exposing ends of conductive material of TSV precursor structures.

18. The method of claim 15, further comprising reducing adhesion of the bonding material between the active surface of the device wafer and the bottom surface of the recess of the carrier wafer, followed by separating the device wafer from the carrier wafer.

19. A carrier wafer for supporting a device wafer thereon, the carrier wafer comprising: A body having a recess sized for at least partially receiving the device wafer therein, the recess having a non-linear bottom surface, the device wafer including an array of unsingulated semiconductor die sites.

20. The carrier wafer of claim 19 wherein the recess has an arcuate dished bottom surface.

21. The carrier wafer of claim 20 wherein the arcuate dished bottom surface is surrounded by an upstanding peripheral sidewall surface having a small radius of curvature.

22. The carrier wafer of claim 20 wherein the arcuate dished bottom surface terminates at a peripheral flat portion.

23. The carrier wafer of claim 19 wherein the non-linear bottom surface comprises a shallow, generally conical bottom surface.

24. The carrier wafer of claim 19 wherein a surface of the body opposite the recess is planar.

25. A carrier wafer according to claim 19, wherein the nonlinear bottom surface of the recess is generally concave and arcuate and dished, and the surface of the body opposite the recess is generally convex in the same direction as the nonlinear bottom surface and is similarly arcuate and dished.

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