Method for operating an H-bridge circuit and corresponding driver device

Abstract

Embodiments of the present disclosure generally relate to methods of operating an H-bridge circuit and corresponding driver devices. The H-bridge circuit includes a supply voltage node, a first pair of transistors, and a second pair of transistors. The first transistor in each pair of transistors has a current path through the first transistor, which current paths are respectively included in current flow lines between the supply node and the first output node and between the supply node and the second output node. The second transistor in each pair of transistors has a current path through the second transistor, which current paths are respectively coupled to the third output node and the fourth output node. The first output node and the third output node are isolated from each other, and the second output node and the fourth output node are isolated from each other. The H-bridge circuit can be operated in one of a first mode, a second mode, and a third mode.

Description

[0001] Priority Claim

[0002] This application claims priority to Italian Patent Application No. 102019000006078, filed on April 18, 2019, the content of which is incorporated herein by reference in its entirety to the maximum extent permitted by law. Technical Field

[0003] This description relates to driving an H-bridge circuit.

[0004] One or more embodiments can be applied to driving components, for example, for consumer electronics, industrial control, and DC motor control. Background Art

[0005] Various control circuits can be employed to drive a bidirectional DC motor.

[0006] For example, a motor can be driven via four MOSFET transistors configured in an H-bridge, which is capable of switching the polarity of the signal applied to the load.

[0007] To provide a driver capable of operating in a manner independent of the load type, an H-bridge driver can embed separate multiple intellectual properties (IPs) for each different application mode. In electronic design, a semiconductor intellectual property core, IP core, or IP block is a term in the art that refers to a reusable unit designed for the layout of the logic, cells, or integrated circuit (commonly referred to as a "chip") of one party's intellectual property.

[0008] One solution as described above involves replicating the internal circuitry. This exhibits obvious drawbacks in terms of die size (increased area) and packaging (additional number of pins), resulting in undesirable additional costs.

[0009] Therefore, in the case of standard products (SPs) that are expected to be small and inexpensive to be attractive and competitive in the market, embedding multiple IPs is a difficult option to conceive.

[0010] Therefore, there is a need in the art to provide such an improved solution. Summary of the Invention

[0011] One or more embodiments can relate to a corresponding H-bridge circuit driver device.

[0012] A method of operating an H-bridge circuit in multiple modes can be an example of such a method.

[0013] One or more embodiments can include a flexible and adaptable architecture to address multiple different applications.

[0014] One or more embodiments may include associated diagnostic structures that operate under all different conditions.

[0015] One or more embodiments may provide independent driving of an external MOSFET transistor (e.g., in a so-called “four-mode”).

[0016] One or more embodiments may facilitate operation using a single-stage charge pump topology, reducing costs and optimizing price. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] One or more embodiments will now be described by way of non-limiting example only, with reference to the accompanying drawings, in which:

[0018] Figure 1 and Figure 2 are examples of H-bridge circuits;

[0019] Figures 3 to 5 are exemplary diagrams of one or more embodiments of a method for driving an H-bridge circuit;

[0020] Figure 6 and Figure 7 are exemplary diagrams of one or more embodiments of an application of a method for driving an H-bridge circuit; and

[0021] Figure 8 is Figure 7 a schematic diagram of a part of. DETAILED DESCRIPTION

[0022] In the following description, one or more specific details are illustrated, aiming to provide an in-depth understanding of examples of embodiments of this description. Embodiments may be obtained without one or more specific details, or in the case of other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so as not to obscure certain aspects of the embodiments.

[0023] References made in the framework of this specification to “an embodiment” or “one embodiment” are intended to indicate that at least one embodiment includes the specific configuration, structure, or characteristic described in relation to that embodiment. Thus, phrases such as “in an embodiment” or “in one embodiment” that may occur at one or more points in this specification do not necessarily refer to one and the same embodiment.

[0024] Furthermore, in one or more embodiments, specific configurations, structures, or characteristics may be combined in any suitable manner.

[0025] References used herein are provided for convenience only and thus do not limit the scope of protection or the scope of embodiments.

[0026] The accompanying drawings are in simplified form and not to exact scale. For simplicity, directional (up / down, etc.) or motility (forward / backward, etc.) terms may be used relative to the drawings. The term "coupled" and like terms do not necessarily denote direct and immediate connection, but also include connection through intermediate elements or devices.

[0027] As Figure 1 and Figure 2 illustrated, the H-bridge circuit 10 may include a power node VDD configured to be coupled to a power supply voltage, which is, for example, a direct current (DC) source providing the voltage VDD such as a battery or a charge pump, and the source terminal of the low-side device is connected to ground GND, and a first pair of "left-branch" transistors QH1, QL1 (e.g., MOSFET transistor devices) of the bridge and a second pair of "right-branch" transistors QH2, QL2 (e.g., MOSFET transistor devices) of the bridge. In other words, the H-bridge circuit 10 may employ a pair of "high-side" MOSFET transistor devices QH1, QH2 and a pair of "low-side" MOSFET transistor devices QL1, QL2. The H-bridge 10 may be discussed as having a "left" branch and a "right" branch, each branch having a high-side transistor QH1, QH2 and a low-side transistor QL1, QL2, respectively.

[0028] In one or more embodiments, a pair of output terminals E1, E2 between the current paths through the left-side transistors QH1, QL1 and the right-side transistors QH2, QL2 may be configured to be connected to a load Z, such as a bidirectional motor load Z.

[0029] A control circuit D may be provided, which is configured to operate the transistors (e.g., turn on / off) of the high-side QH1, QH2 devices and the low-side QL1, QL2 devices such that the transistors QH1, QH2, QL1, QL2 may be modeled as switches to drive current through the motor Z, e.g., in a direction through its windings to cause the rotor of the motor Z to rotate in a clockwise or counterclockwise direction. For simplicity, the electrical connections of the control circuit D are represented by arrows pointing to the H-bridge circuit 10.

[0030] If an application involves driving more than one load, a "half-bridge" may be used, e.g., similar to a class-AB amplifier solution, with two transistors QH1, QL1 employed on one branch of the H-bridge 10.

[0031] For example, as Figure 2 illustrated, the half-bridge may be controlled via respective controllers Da, Db to drive two motor loads Za, Zb, where the H-bridge 10 may be regarded as including two parallel half-bridges 10a, 10b.

[0032] Existing H-bridge driver solutions do not provide complete flexibility because they may be able to drive only motor-type loads, such as using H-bridge or half-bridge topologies.

[0033] In some cases, when considering driving loads Z, Za, Zb with topologies other than those provided by H-bridges operating in a traditional manner, an integrated circuit (IC) driver can facilitate driving a half-bridge independently in a so-called "dual mode".

[0034] In some cases, the same IC device may not be able to drive different applications in which external transistors QH1, QL1, QH2, QL2 can be configured in any selected manner, such as configured as high-side or low-side. For example, the driver may not be able to operate independently of the type of load.

[0035] Figure 3 A diagram showing an H-bridge circuit driver device 100, which may include control logic circuit portions 101, 102, such as a first portion 101 for driving a first pair of transistors QH1, QL1 in the "left" branch 10a of the H-bridge circuit 10, and a second portion 102 for driving a second pair of transistors QH2, QL2 in the "right" branch 10b of the H-bridge circuit 10.

[0036] Hereinafter, for simplicity, components in the first portion 101 are mainly discussed. For the second circuit portion 102, similar elements may be indicated with similar reference numerals for corresponding components on the corresponding "right" branch 102 of the H-bridge driver circuit 10.

[0037] In one or more embodiments, as Figure 3 illustrated, the H-bridge circuit 10 may include a power node configured to be coupled to a power supply voltage VDD and a first pair of "left-branch" transistors QH1, QL1 and a second pair of "right-branch" transistors QH2, QL2, each pair of transistors including a first transistor QH1, QH2 and a second transistor QL1, QL2.

[0038] In one or more embodiments, the first transistors QH1, QH2 in the two pairs of transistors QH1, QL1 and QH2, QL2 have current paths through the first transistors QH1, QH2, with current flowing in respective current flow lines between the power node VDD and a first output node EH1 and between the power node VDD and a second output node EH2.

[0039] In one or more embodiments, the second transistors QL1, QL2 in the "left" pair of transistors QH1, QL1 and the "right" pair of transistors QH2, QL2 respectively have current paths through the current paths, and the current paths are respectively coupled to a third output node EL1 and a fourth output node EL2.

[0040] In one or more embodiments (see Figure 5 ), the first output node EH1 and the third output node EL1 may be isolated from each other, and the second output node EH2 and the fourth output node EL2 may be isolated from each other.

[0041] As Figure 3 illustrated in, the logic control circuit system portions 101, 102 in the H-bridge driver circuit 100 may include:

[0042] - A first pair of transistor drive pins GH1, GL1 and a second pair of transistor drive pins GH2, GL2, which are configured to be coupled to the respective control terminals of the first pair of transistors QH1, QL1 and the second pair of transistors QH2, QL2 in the H-bridge circuit 10;

[0043] - A first output node pin SH1 and a second output node pin SH2 and a third output node pin DL1 and a fourth output node pin DL2, which are configured to be coupled to the first output node EH1 and the second output node EH2 and the third output node EL1 and the fourth output node EL2 respectively;

[0044] - At least one power node pin VS;

[0045] - Logic control circuit systems 101, 102, which are coupled to the first pair of transistor drive pins GH1, GL1 and the second pair of transistor drive pins GH2, GL2, the first output node pin SH1, the second output node pin SH2, the third output node pin DL1 and the fourth output node pin DL2, and at least one power node pin VS.

[0046] In one or more embodiments, the logic control circuit systems 101, 102 may be configured to operate the H-bridge circuit 10 in a selected one of a plurality of modes, the plurality of modes including a first mode, a second mode and a third mode.

[0047] In one or more embodiments, the H-bridge driver 100 may include:

[0048] - A set of paired differential amplifiers 11, 12; 31, 32; 61, 62; 71, 72. For example, two pairs of differential amplifiers are used for drain-source monitoring (e.g., amplifiers 11, 12 and 61, 62) and / or open-load monitoring (e.g., amplifiers 31, 32 and 71, 72);

[0049] - A set of paired pull-up resistors, for example, two pairs of resistors RH1, RH2; RL1, RL2, for off-state diagnosis;

[0050] - A pair of comparators 41, 42, which are configured to facilitate open-load monitoring independently of the first pair of transistors QH1, QL1 in the left branch of the H-bridge 10 and the second pair of transistors QH2, QL2 in the right branch of the H-bridge 10, respectively;

[0051] - A set of switch pairs 21, 22; 51, 52; 81, 82, which can be operated via signals provided to the corresponding control logic parts 101, 102 in the driver device 100 as described below.

[0052] In one or more embodiments, the resistors in the resistor groups RH1, RL1 can have the same value. For example, RH1 = RL1 = 20 kOhm (1 kOhm = 1 kilo-Ohm = 10 3 Ohm).

[0053] Figure 4 is an exemplary diagram of a possible use of the H-bridge driver circuit 100 to drive a load between output terminals (e.g., a bidirectional motor Z1 for window lifting in a vehicle).

[0054] In the example considered:

[0055] - The first pair of switches 81, 82 can be in a first state, for example, open, so as to couple the second pins DL1, DL2 to the power supply node VS;

[0056] - The second pair of switches 51, 52 can be in a second state, for example, closed, so as to couple the first pin SH1 to the second pin DL1 (and pin SH1 to pin DL2).

[0057] In one or more embodiments, as discussed below, the bridge can be driven in a half-bridge mode (dual mode) for two separate motors in a manner known per se, for example, by setting the dual-mode bit DM = 1 in a dedicated logic circuit block control or status register.

[0058] Figure 5 is an exemplary diagram of a possible use of the driver circuit parts 101, 102 of the driver circuit 100 to supply current to two loads (e.g., two heater impedances Z1, Z2 for a seat module in a vehicle).

[0059] In the example considered:

[0060] - The first pair of switches 81, 82 can be in a second state, such as "closed", to couple the differential stage 41 to the power supply node VS, and

[0061] - The second pair of switches 51, 52 can be in a first state, such as, "open", to decouple the first load node DL1 from the second load node SH1 (and to decouple node DL2 from node SH2).

[0062] As Figure 5 illustrated:

[0063] - The first output node - to - node load Z10 can be coupled between the first pin SH1 and ground GND or between the first pin SH1 and the second pin DL1,

[0064] - The second output node - to - node load Z20 can be coupled between the third pin SH2 and ground GND or between the third pin SH2 and the fourth pin DL2,

[0065] Thus, in one or more embodiments, the high - side transistor can drive a heating application (while the low - side transistor can ground the heater or leave it "floating").

[0066] In one or more embodiments as Figure 7 illustrated, it is possible to operate all up to four transistors QH1, QL1, QH2, QL2 as "high - side" drivers to make the IP more flexible.

[0067] In this particular case, for a full diagnosis, it may be necessary to include a pair of additional operational amplifiers (referred to simply as op - amps) for lower device drain - source monitoring. In fact, due to this configuration, the operational amplifiers (referred to simply as op - amps) 71 and 72 cannot perform both open - load diagnosis and drain - source diagnosis (see, for example Figure 8 ).

[0068] In one or more embodiments, for example, in a cost / size - optimized solution, such as for an application - specific standard product (ASSP) using a low - power single - stage charge pump CP, a solution is provided to handle the CP current capability.

[0069] In one or more embodiments, the third transistor QL1 and the fourth transistor QL2 can also be driven as "high - side" transistors, alternating sequentially (not simultaneously) with the other two transistors QH1, QH2.

[0070] As discussed below, this arrangement can advantageously facilitate avoiding modifications in the charge - pump CP fan - out while facilitating a flexible adoption of a "four - high - side" H - bridge arrangement.

[0071] In one or more embodiments, the driver circuit may include respective control logic blocks 101, 102.

[0072] In one or more embodiments of driver 100, another pair of switches CP_good1, CP_good2 may selectively couple charge pump CP to the first transistor in a respective pair of transistors, such as "high-side" transistors QH1, QH2, or the second transistor in a respective pair of transistors, such as "low-side" transistors QL1, QL2.

[0073] In one or more embodiments, the respective control logic portions 101, 102 in driver 100 may operate cooperatively to provide such pairings that can operate only transistors QH1, QH2 or QL1, QL2 simultaneously to supply current to a load group.

[0074] Hereinafter, the drain terminals of the low-side transistors are respectively indicated as auxiliary load nodes SL1 and SL2 and may be "floating" rather than coupled to ground GND.

[0075] In the example considered, for example:

[0076] - Only when switches CP_GOOD_1, CP_GOOD_2 are in a first state, for example, only when switches CP_GOOD_1, CP_GOOD_2 are "closed", can low-side transistors QL1, QL2 be operated to supply current to loads coupled to the drain terminal nodes SL1, SL2;

[0077] - Only when switches CP_GOOD_1, CP_GOOD_2 are in a second state, for example, only when CP_GOOD_1 and CP_GOOD_2 are "open", can high-side transistors QH1, QH2 be operated to supply current to loads coupled to the third node DL1 and the fourth node DL2.

[0078] In one or more embodiments, switches CP_GOOD_1 and CP_GOOD_2 may be operated via respective signals "CP_GOOD".

[0079] In one or more embodiments, due to the solution discussed herein, the CP fan-out can be maintained while facilitating driving up to four transistors to supply current to a load.

[0080] Figure 7 It is an example diagram of using driver circuit D to supply current to four loads, for example, blower motor Z40, defroster Z30, a pair of heater impedances Z10, Z20. Such an arrangement of loads Z10, Z20, Z30, Z40 can be advantageously used, for example, in a body control module for automotive applications.

[0081] Since signals are sent on corresponding wires and their values can be stored in dedicated registers C_reg, S_reg coupled to the control logic sections 101, 102, the control logic sections 101, 102 can control pairs of switches 21, 22; 51, 52; 81, 82 in the driver 100.

[0082] For example:

[0083] - The control register C_reg can store binary data that includes information on how to change the states (e.g., open / closed) of the switches in switch pairs 21, 22; 81, 82; 51, 52; CP_GOOD_1, CP_GOOD_2 of the driver 100;

[0084] - The status register S_reg can store binary data that includes information on the current states (e.g., open / closed) of the switches in switch pairs 21, 22; 81, 82; 51, 52; CP_GOOD_1, CP_GOOD_2 of the driver 100.

[0085] In one or more embodiments, the microcontroller MP can host a software code portion to provide data to such registers, for example, via SPI communication, and can provide the binary data therein to the driver control logic sections 101, 102.

[0086] In one or more embodiments, the control register C_reg and the status register S_reg can have a given number of bits, for example, 24 bits. The values of such bits can be assigned to have determined binary values depending on the switch states for activation. For example, if the 22nd bit has a value of "0", the switch is activated as "open".

[0087] Hereinafter, the table summarizes which bits (represented by references such as QM, QMDIR) can be provided or added to the control register C_reg to activate the first mode, second mode, or third mode, such as the "four - mode", or, for example, configure direct drive for existing pins DIRH and PWMH. Other bits can also be added for independent drain - source monitoring of transistors.

[0088] For example, when the 20th bit indicated as QM in the control register has a first value, the H - bridge driver can be operated to drive four loads using two charge pumps. For example, the default value of bit QM can be "0", and when set to the value "1", this bit can enable driving four loads.

[0089] Table I below shows an example of the values of the most significant bits (MSB) in the control register for setting a mode of the H - bridge driver.

[0090] Table I

[0091]

[0092]

[0093] In one or more embodiments, bit 19 indicated as QMDIR_2 in control register C_reg and bits indicated as QMDIR_1, QMDIR_0 can be configured to select a drive configuration. Specifically, in one or more embodiments, the settings of the bits indicated as QMDIR_2, QMDIR_1, and QMDIR_0 can help select which of a pair of input pins DIRH, PWMH can actually be used (e.g., directly) to drive any of the transistors in transistor groups QH1, QH2, QL1, or QL2. For example, as indicated in the following table:

[0094] In one or more embodiments, the operating mode in, for example, the last row of Table II can be set as the default operating mode.

[0095] The following Table II is an example of possible selections of input pins for driving any of the transistors in transistor groups QH1, QH2, QL1, or QL2.

[0096] Table II

[0097]

[0098] Note that these configurations can be valid if bit QM has a first value, e.g., QM = "1". In other cases, the pins follow "single" or "dual" mode behavior according to the selected operating mode.

[0099] In one or more embodiments, the bit indicated as QMPLUS can facilitate operating all MOSFETs in H-bridge 10 as high-side transistors. For example, when QM has a first value, e.g., QM = "0", the third operating mode is disabled, while if QM has a second value, e.g., QM = "1", the third operating mode is enabled.

[0100] In addition, as previously mentioned, status register S_reg can also be updated to facilitate control by control logic sections 101, 102. For example, the coupling of two bits CP_GOOD_1, CP_GOOD_2 is used to mark that the gate voltages in high-side transistors GH1, GH2 are high enough and charge pump CP is ready to also provide the required gate voltages to low-side transistors GL1, GL2.

[0101] Table III below shows the values of the status register bits, in particular a summary of the least significant bit (LSB) values of the status register (SR).

[0102] Table III

[0103]

[0104] As Figure 8 illustrated in Figure 7 and representing a part of Figure 7 the "four high-side" arrangement, specifically the left part, one or more embodiments may include a dedicated operational amplifier 91 coupled between the drain and source of (e.g., transistor QL1 on the left side) to facilitate drain-source monitoring, e.g., detecting a possible short-circuit condition to ground GND. Specifically, such an operational amplifier 91 can be used to detect such a condition during the on-state of transistor QL1.

[0105] A method according to one or more embodiments may include:

[0106] a) Providing an H-bridge circuit that includes a power node configured to be coupled to a power supply voltage (e.g., VDD) and a first pair of transistors (e.g., QH1, QL1) and a second pair of transistors (e.g., QH2, QL2), each pair of transistors including a first transistor (e.g., QH1, QH2) and a second transistor (e.g., QL1, QL2), wherein:

[0107] - The first transistors in the two pairs of transistors may have current paths through the first transistors, the current paths being respectively included in corresponding current flow lines between the power node and a first output node (e.g., EH1) and between the power node and a second output node (e.g., EH2), and

[0108] - The second transistors in the two pairs of transistors may have current paths through the second transistors, the current paths being respectively coupled to a third output node (e.g., EL1) and a fourth output node (e.g., EL2), the first output node being isolated from the third output node, and the second output node being isolated from the fourth output node,

[0109] b) Operating the H-bridge circuit in a selected one of a plurality of modes, the plurality of modes including a first mode, a second mode, and a third mode, wherein:

[0110] - i) In the first mode:

[0111] - Shorting the first output node to the third output node to provide a first output terminal (EH1, EL1), and shorting the second output node to the fourth output node to provide a second output terminal,

[0112] - The second transistor of the two pairs of transistors is arranged to have current paths through the current paths, and the current paths are respectively coupled between the first output terminal and ground (e.g., GND) and between the second output terminal and ground (e.g., GND).

[0113] - An inter-output-terminal electrical load (e.g., Z1) can be coupled between the first output terminal (e.g., EH1, EL1) and the second output terminal (e.g., EL1, EL2), and the inter-output-terminal electrical load is configured to be traversed by currents flowing through the inter-output-terminal electrical load in opposite directions respectively due to the conduction of the first transistor (e.g., QH1) in the first pair of transistors, the second transistor (e.g., QL2) in the second pair of transistors, the first transistor (e.g., QH2) in the second pair of transistors, and the second transistor (e.g., QL1) in the first pair of transistors.

[0114] - ii) In the second mode:

[0115] - The second transistors (e.g., QL1, QL2) of the two pairs of transistors are arranged to have current paths through the second transistors, and the current paths are respectively coupled between the third output node and ground and between the fourth output node and ground.

[0116] - A first inter-output-node electrical load (e.g., Z10) and a second inter-output-node electrical load (e.g., Z20) can be respectively coupled between the first output node (e.g., EH1) and the third output node (e.g., EL2) and between the second output node (e.g., EH2) and the fourth output node (e.g., EL2), and the first inter-output-node electrical load and the second inter-output-node electrical load are configured to be powered respectively due to the conduction of the first and second transistors in the first pair of transistors and the conduction of the first and second transistors in the second pair of transistors.

[0117] - iii) In the third mode:

[0118] - The third output node and the fourth output node can be coupled to respective power supply voltages (e.g., VS).

[0119] - The second transistors of the two pairs of transistors are arranged to have current paths through the second transistors, and the current paths can be coupled to respective ground reference loads (e.g., Z10, Z20) of a reference ground (e.g., GND) opposite to the third output node (e.g., EL1) and the fourth output node (e.g., EL2), and the respective ground reference loads (e.g., Z20) are configured to be powered due to the conduction of the second transistor in the first pair of transistors and the second transistor in the second pair of transistors.

[0120] - The first output node load (e.g., Z30) may be coupled to the first output node (e.g., EH1), where the first output load is configured to be powered due to the conduction of the first transistor in the first pair of transistors.

[0121] - The second output node load (e.g., Z40) may be coupled to the second output node, where the second output node load (e.g., Z40) is configured to be powered due to the conduction of the first transistor in the second pair of transistors.

[0122] In one or more embodiments, the method may include:

[0123] - Providing first pair of transistor drive pins (e.g., GH1, GL1) and second pair of transistor drive pins (e.g., GH2, GL2), which are configured to be coupled to the respective control terminals of the first pair of transistors and the second pair of transistors in the H-bridge circuit;

[0124] - Providing a charge pump circuit (e.g., CP), which is configured to be coupled to the first pair of transistor drive pins and the second pair of transistor drive pins to supply charge to the first pair of transistor drive pins and the second pair of transistor drive pins.

[0125] In one or more embodiments, in the third mode, the method may include any one of the following:

[0126] - Coupling the charge pump circuit (e.g., CP) to the transistor drive pins (e.g., GH1, GH2) configured to be coupled to the control terminals of the first transistors in the first pair of transistors and the second pair of transistors, and keeping the charge pump circuit decoupled from the transistor drive pins configured to be coupled to the control terminals of the second transistors in the first pair of transistors and the second pair of transistors, and

[0127] - Keeping the charge pump circuit decoupled from the transistor drive pins configured to be coupled to the control terminals of the first transistors in the first pair of transistors and the second pair of transistors, and coupling the charge pump circuit to the transistor drive pins configured to be coupled to the control terminals of the second transistors in the first pair of transistors and the second pair of transistors.

[0128] One or more embodiments may include an H-bridge circuit driver device configured to drive an H-bridge circuit using the method of any of the foregoing claims. The H-bridge circuit includes a power node configured to be coupled to a power supply voltage (e.g., VDD), and a first pair of transistors (e.g., QH1, QL1) and a second pair of transistors (e.g., QH2, QL2). Each pair of transistors includes a first transistor (e.g., QH1, QH2) and a second transistor (e.g., QL1, QL2). The first transistors in the two pairs of transistors (e.g., QH1, QL1; QH2, QL2) have current paths through the first transistors, and the current paths are respectively included in corresponding current flow lines between the power node (e.g., VDD) and a first output node (e.g., EH1) and between the power node (e.g., VDD) and a second output node (e.g., EH2). The second transistors in the two pairs of transistors have current paths through the second transistors, and the current paths are respectively coupled to a third output node (e.g., EL1) and a fourth output node (e.g., EL2). The first output node and the third output node are isolated from each other, and the second output node and the fourth output node are isolated from each other.

[0129] In one or more embodiments, the driver device may include:

[0130] - A first pair of transistor drive pins (e.g., GH1, GL1) and a second pair of transistor drive pins (e.g., GH2, GL2) configured to be coupled to respective control terminals of the first pair of transistors (e.g., QH1, QL1) and the second pair of transistors (e.g., QH2, QL2) in the H-bridge circuit;

[0131] - A first output node pin (e.g., SH1), a second output node pin (e.g., SH2), a third output node pin (e.g., DL1), and a fourth output node pin (e.g., DL2) configured to be coupled to the first output node, the second output node, the third output node, and the fourth output node, respectively;

[0132] - At least one power node pin (e.g., VS);

[0133] - A logic control circuitry (e.g., 101, 102) coupled to the first pair of transistor drive pins, the second pair of transistor drive pins, the first output node pin, the second output node pin, the third output node pin, the fourth output node pin, and at least one power node pin (e.g., VS). The logic control circuit (101, 102) is configured to:

[0134] - i) In the first mode:

[0135] - Short the first output node pin to the third output node pin, and short the second output node pin (e.g., SH2) to the fourth output node pin (e.g., DL2).

[0136] - Activate the transistor drive pins (e.g., GH1, GL2) for the first transistor in the first pair of transistors and the second transistor in the second pair of transistors, and the drive pins (e.g., GH2, GL2) for the first transistor in the second pair of transistors and the second transistor in the first pair of transistors, respectively, to turn on the transistors, where the electrical load (e.g., Z1) between the output terminals is traversed by the current flowing through the electrical load between the output terminals.

[0137] - ii) In the second mode:

[0138] - Activate the transistor drive pins (e.g., GH1, GL1) for the first transistor and the second transistor in the first pair of transistors, and the transistor drive pins for the first transistor and the second transistor in the second pair of transistors, respectively, to turn on the transistors, where the electrical load (e.g., Z10) between the first output nodes and the electrical load (e.g., Z20) between the second output nodes are powered.

[0139] - iii) In the third mode:

[0140] - Couple the third output node pin and the fourth output node pin to the respective supply voltage (e.g., VS).

[0141] - Activate the transistor drive pins (e.g., GL1, GL2) for the second transistor in the first pair of transistors and the second transistor in the second pair of transistors to turn on the transistors, where the respective ground reference load (e.g., Z20) is powered.

[0142] - Activate the transistor drive pin (e.g., GH1) for the first transistor in the first pair of transistors to turn on the transistor, where the first output load (e.g., Z30) is powered.

[0143] - Activate the transistor drive pin (e.g., GH2) for the first transistor in the second pair of transistors to turn on the transistor, where the second output load (e.g., Z40) is powered.

[0144] In one or more embodiments, the H-bridge circuit driver device may include a charge pump circuit (e.g., CP) configured to be coupled to the first pair of transistor drive pins and the second pair of transistor drive pins to supply charge to the first pair of transistor drive pins and the second pair of transistor drive pins.

[0145] In one or more embodiments, in the third mode, the H-bridge circuit may include any of the following:

[0146] - Coupling a charge pump circuit to a transistor drive pin configured to be coupled to a control terminal of a first transistor of a first pair of transistors and a second pair of transistors, and keeping the charge pump circuit decoupled from a transistor drive pin configured to be coupled to a control terminal of a second transistor of the first pair of transistors and the second pair of transistors, and

[0147] - Keeping the charge pump circuit decoupled from a transistor drive pin configured to be coupled to a control terminal of a first transistor of a first pair of transistors and a second pair of transistors, and coupling the charge pump circuit to a transistor drive pin configured to be coupled to a control terminal of a second transistor of the first pair of transistors and the second pair of transistors.

[0148] One or more embodiments of the system may include:

[0149] - One or more embodiments of an H-bridge circuit driver device, and

[0150] - A memory (e.g., MP), including a register bank (e.g., S_reg, C_reg), where:

[0151] a) At least one register (e.g., C_reg) in the register bank (e.g., S_reg, C_reg) may be configured to provide a signal to the logic control circuitry (e.g., 101, 102) in the H-bridge circuit driver device to operate the H-bridge circuit in a selected one of a plurality of modes, the plurality of modes including a first mode, a second mode, and a third mode, and

[0152] b) At least another register in the register bank (e.g., S_reg) may be configured to store a binary value indicating a selected one of a plurality of modes, the plurality of modes including a first mode, a second mode, and a third mode for operating the H-bridge circuit driver.

[0153] It will also be understood that the various individual implementation options illustrated throughout the accompanying drawings with this specification are not necessarily intended to be employed in the same combinations as illustrated in the drawings. Thus, one or more embodiments may employ these options individually and / or in different combinations relative to the combinations illustrated in the drawings (additionally, non-mandatory).

[0154] The claims are an integral part of the technical guidance provided herein with reference to the embodiments.

[0155] Without prejudice to the basic principles, details and embodiments may be varied even significantly with respect to what has been described only by way of example, without departing from the scope of protection. The scope of protection is defined by the appended claims.

Claims

1. A method for driving an H-bridge circuit, wherein, The H-bridge circuit includes: a power node configured to be coupled to a power supply voltage, and a first pair of transistors and a second pair of transistors, each pair of transistors including a first transistor and a second transistor, wherein: the first transistors in the two pairs of transistors have current paths through the first transistors, the current paths being respectively included in corresponding current flow lines between the power node and a first output node and between the power node and a second output node, and the second transistors in the two pairs of transistors have current paths through the second transistors, the current paths being respectively coupled to a third output node and a fourth output node, the first output node and the third output node being isolated from each other, and the second output node and the fourth output node being isolated from each other, The method includes: selecting to operate the H-bridge circuit in one of a plurality of modes, the plurality of modes including a first mode, a second mode, and a third mode, wherein: i) Operating in the first mode includes: shorting the first output node to the third output node to provide a first output terminal, and shorting the second output node to the fourth output node to provide a second output terminal, arranging the second transistors in the two pairs of transistors, wherein the current paths through the second transistors are respectively coupled between the first output terminal and ground and between the second output terminal and ground, and wherein, due to the first transistor in the first pair of transistors, the second transistor in the second pair of transistors, the first transistor in the second pair of transistors, and the second transistor in the first pair of transistors being turned on respectively, an inter-output-terminal electrical load coupled between the first output terminal and the second output terminal is traversed by currents flowing in opposite directions through the inter-output-terminal electrical load; ii) Operating in the second mode includes: arranging the second transistors in the two pairs of transistors, wherein the current paths through the second transistors are respectively coupled between the third output node and ground and between the fourth output node and ground, wherein, an electrical load between the first output nodes and an electrical load between the second output nodes are respectively coupled between the first output node and the third output node and between the second output node and the fourth output node, and the electrical load between the first output nodes and the electrical load between the second output nodes are configured to be powered respectively due to the first transistor and the second transistor in the first pair of transistors being turned on and the first transistor and the second transistor in the second pair of transistors being turned on; iii) Operating in the third mode includes: coupling the third output node and the fourth output node to respective power supply voltages, The second transistor disposed in the two pairs of transistors, wherein a current path through the second transistor is coupled to a respective ground reference load that is opposite to the third output node and the fourth output node and is coupled to a ground reference, and wherein the respective ground reference load is configured to be powered due to conduction of the second transistor in the first pair of transistors and the second transistor in the second pair of transistors, and Couple the first output node load to the first output node, wherein the first output node load is configured to be powered due to conduction of the first transistor in the first pair of transistors; and Couple the second output node load to the second output node, wherein the second output node load is configured to be powered due to conduction of the first transistor in the second pair of transistors.

2. The method according to claim 1, further comprising: Couple a first pair of transistor drive pins to respective control terminals of the first pair of transistors; Couple a second pair of transistor drive pins to respective control terminals of the second pair of transistors; And Couple a charge pump circuit to the first pair of transistor drive pins and the second pair of transistor drive pins to supply charge to the first pair of transistor drive pins and the second pair of transistor drive pins.

3. The method according to claim 2, wherein operating in the third mode further comprises coupling the charge pump circuit to the transistor drive pin configured to be coupled to the control terminal of the first transistor of the first pair of transistors and the second pair of transistors, and keeping the charge pump circuit decoupled from the transistor drive pin configured to be coupled to the control terminal of the second transistor of the first pair of transistors and the second pair of transistors.

4. The method according to claim 2, wherein operating in the third mode further comprises keeping the charge pump circuit decoupled from the transistor drive pin configured to be coupled to the control terminal of the first transistor of the first pair of transistors and the second pair of transistors, and coupling the charge pump circuit to the transistor drive pin configured to be coupled to the control terminal of the second transistor of the first pair of transistors and the second pair of transistors.

5. An H-bridge circuit driver device configured to drive an H-bridge circuit, the H-bridge circuit including a power node configured to be coupled to a power supply voltage and a first pair of transistors and a second pair of transistors, each pair of transistors including a first transistor and a second transistor, wherein the first transistors in the two pairs of transistors have current paths through the first transistors, the current paths being respectively included in corresponding current flow lines between the power node and a first output node and between the power node and a second output node, and the second transistors in the two pairs of transistors have current paths through the second transistors, the current paths being respectively coupled to a third output node and a fourth output node, the first output node and the third output node being isolated from each other, and the second output node and the fourth output node being isolated from each other, the H-bridge circuit driver device comprising: A first pair of transistor drive pins, configured to be coupled to respective control terminals of the first pair of transistors in the H-bridge circuit; A second pair of transistor drive pins, configured to be coupled to respective control terminals of the second pair of transistors in the H-bridge circuit; A first output node pin, a second output node pin, a third output node pin, and a fourth output node pin, configured to be coupled to the first output node, the second output node, the third output node, and the fourth output node, respectively; At least one power node pin; A logic control circuitry, coupled to the first pair of transistor drive pins and the second pair of transistor drive pins, the first output node pin, the second output node pin, the third output node pin, the fourth output node pin, and the at least one power node pin: i) wherein, in a first operating mode, the logic control circuitry is configured to: Short the first output node pin to the third output node pin and short the second output node pin to the fourth output node pin, and Respectively activate the transistor drive pins for the first transistor in the first pair of transistors and the second transistor in the second pair of transistors, and the drive pins for the first transistor in the second pair of transistors and the second transistor in the second pair of transistors to turn on the transistors, wherein an electrical load between the output terminals is traversed by a current flowing through the electrical load between the output terminals; ii) wherein, in a second operating mode, the logic control circuitry is configured to: Activate the transistor drive pins for the first transistor and the second transistor in the first pair of transistors, and the transistor drive pins for the first transistor and the second transistor in the second pair of transistors, so that the transistors are turned on, wherein the electrical load between the first output nodes and the electrical load between the second output nodes are powered; iii) wherein, the logic control circuit system is configured in a third operation mode to: Couple the third output node pin and the fourth output node pin to the respective power supply voltages, Activate the transistor drive pins for the second transistor in the first pair of transistors and the second transistor in the second pair of transistors, so that the transistors are turned on, wherein the respective ground reference loads are powered; and Activate the transistor drive pin for the first transistor in the first pair of transistors, so that the transistor is turned on, wherein the first output load is powered; and Activate the transistor drive pin for the first transistor in the second pair of transistors, so that the transistor is turned on, wherein the second output load is powered.

6. The H-bridge circuit driver device according to claim 5, further comprising a charge pump circuit configured to be coupled to the first pair of transistor drive pins and the second pair of transistor drive pins to provide charge to the first pair of transistor drive pins and the second pair of transistor drive pins.

7. The H-bridge circuit driver device according to claim 6, wherein in the third operating mode, the logic control circuitry is further configured to couple the charge pump circuit to the transistor drive pin configured to be coupled to the control terminal of the first transistor in the first pair of transistors and the second pair of transistors, and to keep the charge pump circuit decoupled from the transistor drive pin configured to be coupled to the control terminal of the second transistor in the first pair of transistors and the second pair of transistors.

8. The H-bridge circuit driver device according to claim 6, wherein in the third operation mode, the logic control circuit system is further configured to keep the charge pump circuit decoupled from the transistor drive pin configured to be coupled to the control terminal of the first transistor among the first pair of transistors and the second pair of transistors, and couple the charge pump circuit to the transistor drive pin configured to be coupled to the control terminal of the second transistor among the first pair of transistors and the second pair of transistors.

9. The H-bridge circuit driver device according to claim 5, further comprising: A memory, comprising a register bank, wherein: a) At least one register in the register bank is configured to provide a signal to the logic control circuit system in the H-bridge circuit driver device to operate the H-bridge circuit in one of the operation modes selected from the first operation mode, the second operation mode, and the third operation mode, and b) At least another register in the register bank is configured to store a binary value indicating one of the operation modes selected from the first operation mode, the second operation mode, and the third operation mode.

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