Open Pin Detection for Analog-to-Digital Converters

Abstract

Embodiments of the present invention generally relate to methods for open pin detection of analog-to-digital converters. A method includes: applying a current to an input pin of an integrated circuit; and converting an analog signal at the input pin into a digital stream using a sigma-delta modulator; converting the digital stream into a first digital output signal, the first digital output signal being proportional to the analog signal within a first input range between a first analog signal value and a second analog signal value, wherein the first input range corresponds to a predetermined range of the analog signal, the predetermined range being less than a full-scale input range of the analog signal; converting the digital stream into a second output signal; comparing the second output signal to a first threshold, the first threshold corresponding to a third analog signal value at the input pin outside the first input range; and providing an indication of an open circuit condition at the input pin when the second output signal crosses the first threshold.

Description

Technical Field

[0001] Embodiments of the present invention relate generally to analog-to-digital converter (ADC) circuits, and more particularly to systems and methods for detecting open pin conditions in analog-to-digital converter circuits. Background Art

[0002] AC motors, such as three-phase motors, are becoming increasingly popular in applications such as automotive, industrial, and HVAC (heating, ventilation, and air conditioning). By replacing the mechanical commutator used in conventional motors with an electronic device, reliability can be increased, durability can be improved, and the form factor can be reduced. As an example, additional advantages of AC motors include better speed-torque characteristics, faster dynamic response, and a larger speed range. Typically, an AC motor (e.g., a three-phase motor) has a controller that generates a pulse width modulation (PWM) signal that is used to generate drive signals for power switches coupled to different phases of the motor. These PWM signals can determine the average voltage and average current supplied to the motor coils, thereby controlling the motor speed and torque.

[0003] For closed-loop control of an AC motor, the state of the motor can be provided to a controller of the motor system, for example, via a feedback path. For example, the phase currents of a three-phase motor are measured and the measurements are sent to the controller, which generates a PWM control signal based on the measured values ​​of the phase currents. In motor control applications, an analog-to-digital converter (ADC) is typically used to convert an analog signal (e.g., the phase current in each phase of a three-phase motor) into digital data. Summary of the invention

[0004] According to an embodiment, a method includes: applying a current to an input pin of an integrated circuit; converting an analog signal at the input pin into a digital stream using a sigma-delta modulator; converting the digital stream into a first digital output signal using a decimation filter, wherein the first digital output signal is proportional to the analog signal at the input pin within a first input range between a first analog signal value and a second analog signal value, wherein the first input range corresponds to a predetermined range of the analog signal, which is less than a full-scale input range of the analog signal; converting the digital stream into a second output signal; comparing the second output signal with a first threshold, wherein the first threshold corresponds to a third analog signal value of the analog signal at the input pin outside the first input range; and providing an indication of an open circuit condition at the input pin when the second output signal crosses the first threshold.

[0005] According to an embodiment, an integrated circuit includes a pin bias circuit configured to provide current to an input pin of the integrated circuit; and a sigma-delta modulator having an input coupled to the input pin; a decimation filter coupled to the output of the sigma-delta modulator and configured to provide a first digital output signal proportional to an analog signal at the input pin within a first input range between a first analog signal value and a second analog signal value, wherein the first input range corresponds to a predetermined range of the analog signal, which is less than the full-scale input range of the analog signal; and an open pin detection circuit coupled to the output of the sigma-delta modulator, the open pin detection circuit configured to convert the output of the sigma-delta modulator to a second output signal; compare the second output signal with a first threshold, wherein the first threshold corresponds to a third analog signal value of the analog signal at the input pin outside the first input range; and provide an indication of an open circuit condition at the input pin when the second output signal crosses the first threshold.

[0006] According to an embodiment, an analog-to-digital converter circuit includes a first input terminal and a second input terminal; a sigma-delta modulator coupled to the first input terminal and the second input terminal and configured to convert a voltage between the first input terminal and the second input terminal into a one-bit data stream; a pull-up circuit configured to be coupled between a power supply node and the first input terminal and the second input terminal, and to pull a first voltage at the first input terminal to a first voltage value above a predetermined voltage threshold when the first input terminal is kept open, or to pull a second voltage at the second input terminal to a first voltage value when the second input terminal is kept open, wherein the predetermined voltage threshold is less than a full-scale input voltage of the sigma-delta modulator by a predetermined percentage; a first low-pass filter coupled to the output of the sigma-delta modulator and configured to convert the one-bit data stream into a first multi-bit data stream at the output of the analog-to-digital converter circuit; and an open pin detection circuit coupled to the output of the sigma-delta modulator and configured to use the one-bit data stream to detect that the voltage between the first input terminal and the second input terminal is above the predetermined voltage threshold. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Details of one or more embodiments of the present invention are set forth in the accompanying drawings and the following description. Other features, objects, and advantages of the present invention will become apparent from the description and drawings, and from the claims. In the drawings, unless otherwise indicated, the same or similar reference numerals in different drawings generally refer to the same components, which are generally not re-described for the sake of brevity. For a more complete understanding of the present invention, reference is now made to the following description in conjunction with the accompanying drawings, in which:

[0008] Figure 1 illustrates a schematic diagram of a three-phase motor system according to an embodiment;

[0009] Figure 2 illustrates a schematic diagram of a three-phase motor system according to another embodiment;

[0010] Figure 3 illustrates a block diagram of an analog-to-digital converter (ADC) circuit with an open pin detection circuit according to an embodiment;

[0011] Figure 4 illustrates a block diagram of a sigma-delta ADC circuit according to an embodiment;

[0012] Figure 5 The diagram shows a Figure 3 Block diagram of a decimation filter for an open pin detection circuit;

[0013] Figure 6 The relationship between the signal-to-noise-distortion ratio (SDNR) of the ADC output and the input signal range is illustrated according to some embodiments.

[0014] Figure 7 illustrates the relationship between the output and analog input of an ADC circuit according to an embodiment;

[0015] Figure 8 illustrates a block diagram of an analog-to-digital converter (ADC) circuit with an open pin detection circuit according to another embodiment;

[0016] Fig. 9 illustrates a block diagram of an analog-to-digital converter (ADC) circuit with an open pin detection circuit according to yet another embodiment; and

[0017] Fig.10 A flow chart of a method of operating an ADC circuit according to some embodiments is illustrated. DETAILED DESCRIPTION

[0018] The manufacture and use of the currently preferred embodiments are discussed in detail below. However, it should be appreciated that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific environments. The specific embodiments discussed only illustrate specific ways to manufacture and use the present invention and do not limit the scope of the present invention.

[0019] The present invention is described with respect to exemplary embodiments in a specific context, namely, detection of an open pin condition of an analog-to-digital converter (ADC) circuit. In some embodiments, the ADC circuit includes a sigma-delta ADC circuit and an open pin detection circuit. An input port of the ADC circuit is connected to a pull-up circuit in addition to being connected to an analog input signal. A sigma-delta modulator of the sigma-delta ADC circuit converts the input analog signal into a one-bit data stream, which is then converted to multi-bit data by a decimation filter of the sigma-delta ADC circuit. The open pin detection circuit forms an estimate of the value (e.g., voltage value) of the input analog signal using the one-bit data stream and compares the estimate to a predetermined threshold. In the illustrated embodiment, the value of the analog input signal is within a predetermined range that is less than the full-scale input range of the ADC circuit. When an open pin condition exists at the input port (e.g., the analog input signal is disconnected from the input port), the pull-up circuit pulls up the voltage at the input port of the ADC circuit to a voltage value outside the predetermined range. The open pin detection circuit detects the open pin condition by detecting that the estimate of the analog signal crosses a predetermined threshold.

[0020] refer to Figure 1 The motor system 100 includes an AC motor 101 (eg, a three-phase motor) connected to a power source V via three half bridges. sup (shown as capacitor C s The voltage across the two ends is V sup Each of the three half-bridges includes a high-side switch (eg, T ha , T hb or T hc ) and the low-side switch (for example, T la , T Lb or T lc ), where the high-side switch is coupled to the power supply V sup The first half-bridge includes a high-side switch T coupled in series. ha With the low-side switch T la In the first half-bridge, the high-side switch T ha The gate is coupled to the gate driver GD ha The output of the high-side switch T ha The drain terminal is coupled to the power supply V sup , while the high-side switch T ha The source terminal is coupled to the low-side switch T la The drain terminal of the low-side switch T la The gate is coupled to the gate driver GD la The output of the low-side switch T la The source is connected via a shunt resistor Ra Coupled to a lower potential terminal (eg, electrical ground). High-side switch T ha The source terminal of a The low side switch T la The drain terminal of the node P a Also called phase node P a The topology of the second and third half bridges is similar to that of the first half bridge, so it will not be repeated in this article. Figure 1 As shown, the three phases of the AC motor 101 are coupled to the phase node P via three conductive paths (eg, wires) 110, 120, and 130, respectively. a , P b and P c .

[0021] The AC motor 101 may be any type of multi-phase (e.g., more than three phases) motor, and a three-phase motor is only an example. The AC motor 101 may be a synchronous motor, an induction motor, a switched reluctance motor, etc. The disclosed embodiments use a three-phase motor as an example, wherein it should be understood that other types of AC motors may also be used and are within the scope of the present disclosure.

[0022] like Figure 1 As shown, the shunt resistor R a The shunt voltage V a , shunt resistor R b The shunt voltage V b , and the shunt resistor R c The shunt voltage V c The ADC module 140 is sent to the ADC module 140 and converted into a digital value. The ADC module 140 may include one or more suitable analog-to-digital converters. For example, the ADC module 140 may have three sigma-delta ADCs, wherein each of the three sigma-delta ADCs converts the input analog signal (e.g., the shunt voltage V a , V b and V c ) to a digital value. The output of ADC module 140 represents the input analog signal (e.g., V a , V b and V c ) are sent to the PWM module 150 via data path 143. In some embodiments, data path 143 is a multi-bit data path. The PWM module 150 generates PWM pulses (also referred to as PWM control signals (e.g., PWM ha , PWM lb , PWM hb , PWMlb , PWM hc and PWM lc )) to control the operation of the AC motor 101, these PWM pulses control the high-side switch (e.g., T ha , T hb and T hc ) and low-side switches (such as T la , T lb and T lc ) operation, and the high-side switch and the low-side switch control the voltage and / or current supplied to the AC motor 101. The PWM pulses generated by the PWM module 150 can be driven by a gate driver (e.g., GD ha , GD la , GD hb , GD lb , GD hc , GD lc ) buffer, and the output of the gate driver is used to drive the high-side switch and the low-side switch. As an example, the PWM module 150 can be or include a microprocessor, a microcontroller, an application-specific integrated circuit (ASIC) for motor control. In some embodiments, the PWM module 150 monitors the shunt voltage V supplied by the ADC module 140, for example. a , V b and V c The measured values ​​are used to monitor the state of the AC motor 101, and PWM pulses are generated to control the operation of the AC motor 101.

[0023] exist Figure 1 In the example, the high-side switch T ha , T hb and T hc And the low-side switch T la , T lb and T lc The power switches 100 are shown as metal oxide semiconductor field effect transistors (MOSFETs). Other suitable power switches, such as insulated gate bipolar transistors (IGBTs), may also be used. The motor system 100 with three half bridges is only an example, and other topologies for multi-phase motor systems may also be used.

[0024] The open pin detection principle in the signal acquisition system (e.g., analog-to-digital conversion system) disclosed herein can be applied to applications other than motor control applications, such as a stand-alone ADC system or an ADC system used in applications other than motor control applications. In addition, in an embodiment of the present disclosure, three analog input signals (e.g., three shunt voltages) are converted to digital values ​​in parallel, and those skilled in the art should appreciate that the signal acquisition system and method disclosed herein can be used for any number of analog input signals, for example, less than or more than three analog input signals. In addition, for a three-phase motor system (e.g., motor system 100), since the third phase current can be calculated, for example, using Kirchhoff's law, only the phase currents from two of the half-bridges can be measured.

[0025] Still reference Figure 1 , each phase current is measured by converting the corresponding shunt voltage into a digital value when the corresponding low-side switch is activated (e.g., turned on) and the phase current flows through the shunt resistor. For example, to measure the phase current I a , when the low-side switch T la Activate (eg, transistor T la When the shunt resistor R a The shunt voltage V a .exist Figure 1 In the example, the shunt resistor R a , R b and R c The shunt resistor is located in the low-side current path (e.g., between the low-side switch and a reference voltage level (such as electrical ground)), so when the low-side switch is activated, the phase current flows through the shunt resistor. The skilled person will appreciate that the shunt resistor can be located in the high-side current path (e.g., between the high-side switch and the power supply V sup In this case, when the high-side switch is activated (e.g., turned on), the phase current can be measured. Figure 2 As shown in the motor system 100A, the shunt resistor is located at the phase node P a , P b , P c and the AC motor 101 in the conductive paths 110 / 120 / 130 .

[0026] As described above, for closed-loop control of the AC motor 101, the PWM module 150 may use the shunt voltage V provided by the ADC module 140 a , V b and V creal-time data. However, if the analog input at the input port of the ADC module 140 is disconnected (also referred to as an open pin condition or an open circuit condition), for example due to an incorrect connection between the ADC module 140 and the shunt resistor, the ADC module 140 no longer reflects the shunt voltage, and the PWM module 150 may generate an incorrect control signal for the AC motor 101. If the open pin condition is not detected quickly and the error mitigation procedure (e.g., an emergency shutdown procedure) is not initiated quickly, the motor system may be damaged. Therefore, it is advantageous that the ADC circuit is able to detect the open pin condition in real time while the ADC circuit is operating, so that damage to the motor system can be avoided and repair work to implement the open pin condition can be performed in a timely manner. Another advantage of having the ability to perform open pin detection in real time is as follows: there is no need to stop normal operation of the motor system 100, so that a test mode can be entered to check for an open pin condition.

[0027] Figure 3 FIG. 2 is a block diagram of an analog-to-digital converter (ADC) circuit 200 with an open pin detection circuit according to an embodiment. It should be noted that in order to illustrate the connection between the ADC circuit 200 and the external circuit, Figure 3 Also illustrated are external components 600 (e.g., shunt resistors, boards, sensors, etc.) and bond wires 611 that couple the external components 600 to the ADC circuit 200, neither of which is part of the ADC circuit 200. In some embodiments, the ADC circuit 200 is used to measure a shunt voltage across a shunt resistor in the motor system 100 or 100A. For example, Figure 1 (or Figure 2 ) may include three instances of the ADC circuit 200, wherein each instance of the ADC circuit 200 is used to measure a corresponding shunt voltage.

[0028] like Figure 3 As shown, the ADC circuit 200 includes an input port 207, a sigma-delta ADC circuit 400, an open pin detection circuit 300, and a pull-up circuit 500. Figure 3 In the example of FIG. 1 , the input port 207 is a differential input port having input terminals 207A and 207B connected to an external component 600, for example, connected to Figure 1 or Figure 2 The two terminals of the shunt resistor in Figure 3 A differential input port is illustrated in FIG. 1 , but those skilled in the art should readily appreciate that the principles of the present disclosure can be applied to a single-ended input port.

[0029] In some embodiments, the value of the analog input signal at the input port 207 (e.g., the shunt voltage value) is within a predetermined range that is less than the maximum input range (also referred to as full-scale range, full-scale input range, or full-scale input voltage range) of the sigma-delta ADC circuit 400. For example, the sigma-delta ADC circuit 400 is capable of accepting analog voltage signals within a maximum input range between -10V and 10V, but the analog voltage supplied to the input port 207 may be within a predetermined range between, for example, -5V and 5V or -7V and 7V. Figure 6 As shown, this smaller predetermined range is selected to avoid the signal quality of the ADC output from degrading near full scale.

[0030] Temporary reference Figure 6 , which illustrates the relationship between the signal-to-noise-distortion ratio (SNDR) of the output of a typical ADC circuit and the input analog signal amplitude according to some embodiments. Figure 6 In FIG. 1 , the x-axis illustrates the amplitude of the input analog signal (e.g., the absolute value of the amplitude), and the y-axis illustrates the SNDR. The unit of the input analog signal amplitude is decibel relative to full scale (dBFS), which is a normalized value showing the ratio (in dB) between the amplitude of the input analog signal and the maximum input amplitude (e.g., full-scale input voltage). Figure 6 An input amplitude of up to A is shown, where A may be, for example, -6dBFS or -3dBFS, and the SNDR increases as the amplitude of the input analog signal increases. However, the SNDR decreases dramatically as the input amplitude approaches the full-scale input level (0dBFS). To this end, the amplitude of the input analog signal for the ADC circuit is typically controlled within a predetermined range, where the maximum amplitude of the predetermined range is several dB (e.g., 3dB or 6dB) below the full-scale input level. In the motor system 100 or 100A, the shunt voltage sent to the ADC module 140 may be controlled within a predetermined range that is less than the full-scale input range of the ADC module 140, which may be achieved by limiting the current flowing through the shunt resistor or by specifying the resistance of the shunt resistor so that during normal operation of the system, the voltage across the shunt resistor is within the predetermined range of the ADC.

[0031] Figure 7 An ADC circuit (eg, Figure 3 The relationship between the digital output of the sigma-delta ADC circuit 400 and the value of the analog input signal. Figure 7In FIG. 1 , the x-axis illustrates the voltage of the analog input signal, and the y-axis illustrates the output of the ADC circuit. The output of the ADC circuit can have a multi-bit value. For example, for an ADC circuit with a 16-bit resolution, the output can be represented in a hexadecimal format of 0x0000-0xFFFF, where each of the outputs corresponds to the analog input signal value. Each of the digital outputs (e.g., 0x0000) can be referred to as an output code of the ADC circuit, and all possible codes form a code space of the ADC circuit. As an example, the ADC circuit can have other resolutions, such as 8-bit resolution or 32-bit resolution.

[0032] exist Figure 7 In the example of , the hardware of the ADC circuit is configured to have a full-scale analog input range between -Vb volts and Vb volts. However, in order to avoid the signal dropping near full scale (see reference above Figure 6 As discussed above, the analog input of the ADC circuit is controlled to be within a (smaller) predetermined range between -Va volts and Va volts, where Va and Vb are positive values ​​and Vb>Va. For example, Va may be 3dB or 6dB smaller than Vb. In other words, Va may be smaller than Vb by a predetermined percentage. Due to the smaller input analog signal range (e.g., between -Va volts and Va volts), the output code of the ADC circuit may be between code C1 and code C2, and may not cover the entire code space without additional processing (e.g., scaling). In some embodiments, a gain adjustment module (such as a VDD) of the ADC circuit may be configured to adjust the output code of the ADC circuit to a predetermined value. Figure 4 The gain adjustment module 430 of the sigma-delta ADC circuit 400 (discussed below) in the ADC circuit scales (eg, multiplies or shifts) the output code of the ADC circuit so that the final output code (eg, Figure 4 ) covers the entire code space. For example, due to the scaling of the gain adjustment module 430, the upper boundary of the predetermined input range (e.g., Va) generates the output code of C2' (e.g., the maximum output code corresponding to the input analog signal value Vb), and the lower boundary of the predetermined input range (e.g., -Va) generates the output code of C1' (e.g., the minimum output code corresponding to the input analog signal value -Vb). In other embodiments, the gain adjustment module of the ADC circuit scales the output code of the ADC circuit, but the scaled output code still does not cover the entire code space between code C1' and code C2'.

[0033] Reference again Figure 3In addition to being connected to the input port 411 of the sigma-delta ADC circuit 400, the input port 207 of the ADC circuit 200 is also connected to the pull-up circuit 500. The pull-up circuit 500 (which may also be referred to as a pin bias circuit) includes a current source 203 and may optionally include a resistor 205 (shown in dashed lines). Figure 3 In the example of FIG. 1 , each of the input terminals 207A / 207B is coupled to a power supply V via a current source 203 and a resistor 205. supply (e.g., about 14V). In some embodiments, as described with respect to Figure 8 As shown in the pull-up circuit 500' in FIG. 1 , the resistor 205 is omitted from the pull-up circuit, wherein each of the input terminals 207A / 207B is coupled to the power supply V via the current source 203. supply In yet another embodiment, as with respect to Fig. 9 As shown in the pull-up circuit 500 in FIG. 1 , the current source 203 is omitted in the pull-up circuit, wherein each of the input terminals 207A / 207B is coupled to the power supply V via a resistor 205 (also referred to as a pull-up resistor). supply .

[0034] The current source 203 can provide a current greater than the current flowing through the shunt resistor R a , R b and R c For example, the current source 203 can provide a current of about 250 μA. In contrast, the current flowing through the shunt resistor R a , R b and R c The current may be about 150A. In the illustrated embodiment, the resistance of the shunt resistor may be relatively small, such as about 1 mΩ, and therefore, the shunt voltage across the shunt resistor is within a few volts. In embodiments where the pull-up circuit 500 includes the current source 203 and the resistor 205, the resistor 205 may have a relatively small resistance, for example, about 1Ω. In embodiments where the pull-up circuit 500 includes only the resistor 205 (see Fig. 9 ), the resistor 205 may have a resistance of, for example, approximately 56 kΩ.

[0035] During normal operation of the ADC circuit 200, the input port 207 is connected to the external component 600 (e.g., a shunt resistor), and the analog signal (e.g., a shunt voltage) at the input port 207 is sent to the input terminals 411A / 411B of the sigma-delta ADC circuit 400 and converted into digital data. Figure 3 As shown by the current I1 in FIG. 1 , the current from the current source 203 flows from the input port 207 to the external component 600. It should be noted that for the sake of clarity, Figure 3, the currents (e.g., I1 and I2) from only one branch of the pull-up circuit 500 are illustrated, where it should be understood that the same or similar current flow occurs in the other branch of the pull-up circuit 500. Since the current provided by the current source 203 is small (e.g., about 250 μA) compared to the current flowing through the shunt resistor (e.g., about 150 A), the effect of the current I1 on the operation of the external component 600 is negligible. In an embodiment where a pull-down circuit is used instead of the pull-up circuit 500, the directions of the currents I1 and I2 can be the same as Figure 3 The direction shown is opposite.

[0036] When an open pin condition occurs, for example, when the bond wire 611 is damaged or an external component is disconnected, current from the current source 203 flows to the sigma-delta ADC circuit 400, as shown by the current I2. Now, the voltage at the input terminal (e.g., 207B) is pulled up to the same voltage as the power supply voltage V by the pull-up circuit 500. supply The same or close voltage (e.g., 14V) is used. Therefore, when an open pin condition occurs, the magnitude of the voltage difference between input terminals 207A and 207B can be close to the power supply voltage V supply , such as about 13 V, which is higher than the normal voltage difference of, for example, a few volts.

[0037] As discussed above, when an open pin condition occurs at the input terminal of the ADC circuit 200, the pull-up circuit 500 pulls up the voltage at the input terminal to a power supply voltage level, which is higher than the normal voltage at the input terminal when not in the open pin condition. As a result, the sigma-delta ADC circuit 400 generates a digital output outside the normal range. The open pin detection circuit 300 monitors the digital output from the sigma-delta modulator 410 and detects the open pin condition by detecting that the digital output is outside the normal range. The details of this detection are discussed below.

[0038] The analog signal (e.g., shunt voltage) at the input port 207 is sent to the input terminals 411A / 411B of the sigma-delta ADC circuit 400. The sigma-delta modulator 410 of the sigma-delta ADC circuit 400 converts the analog signal into a data stream, which in some embodiments is a one-bit data stream. Alternatively, the data stream can be a multi-bit data stream. The data stream (e.g., a one-bit data stream) from the sigma-delta modulator 410 is then converted into multi-bit data by the extraction module 428 of the sigma-delta ADC circuit 400. The open pin detection circuit 300 uses the one-bit data stream to form an estimate of the value of the input analog signal (e.g., shunt voltage value) and compares the estimate with a predetermined threshold.

[0039] Go to Figure 7In the illustrated embodiment, the value of the analog input signal (e.g., the shunt voltage value) during normal conditions (e.g., no open pin condition) is within a predetermined range between -Va and Va, where Va can be referred to as a predetermined voltage threshold. When an open pin condition exists at the input terminal of the input port 207, the pull-up circuit 500 pulls up the voltage at the input terminal to a high voltage value V supply (e.g., equal to or close to Vb). Since the analog input signal at the other input terminal of the input port 207 is small (e.g., less than 1V due to the small shunt resistor and the limited shunt current), the voltage difference between the input terminals 207A and 207B is -Vc or Vc, depending on which terminal of the input port 207 has an open pin condition, where Vc is a value close to Vb (e.g., Va<Vc≤Vb). For a normal condition, this large voltage difference (e.g., -Vc or Vc) is outside a predetermined range (e.g., between -Va and Va) and causes the sigma-delta modulator 410 to generate an output (e.g., a one-bit data stream) that is different from the output corresponding to the normal analog input range (e.g., between -Va and Va). For example, the output of the sigma-delta modulator 410 may include a large number of consecutive ones or consecutive zeros.

[0040] The open pin detection circuit 300 forms an estimate of the input analog signal (e.g., shunt voltage) using a decimation filter 310 that converts a one-bit data stream (at a lower data rate) from a sigma-delta modulator 410 into a multi-bit data stream. The output of the decimation filter 310 is then compared to a predetermined threshold using a comparator 320 to detect that the analog input signal has a value outside a predetermined range of normal conditions, which indicates an open pin condition. It should be noted that the predetermined threshold may include a first threshold corresponding to a first analog signal value above an upper boundary of the predetermined range, and may include a second threshold corresponding to a second analog signal value below a lower boundary of the predetermined range. For the example discussed above, the predetermined range of the input analog signal for a normal condition is between -Va and Va, and therefore, the first threshold may correspond to an analog input signal value between Va and Vc, and the second threshold may correspond to an analog input signal value between -Vc and -Va. In other words, if the output of the decimation filter 310 indicates that the input analog signal crosses (e.g., increases above) a first threshold or the input analog signal crosses (e.g., decreases below) a second threshold, an open pin condition is detected. Thus, the open pin detection circuit 300 operates in parallel (e.g., simultaneously) with the sigma-delta ADC circuit 400 without affecting the normal operation of the sigma-delta ADC circuit.

[0041] The comparator 320 of the open pin detection circuit 300 can be any suitable digital comparator for comparing the output of the extraction filter 310 with a predetermined threshold. After discussing the sigma-delta ADC circuit 400, the details of the extraction filter 310 are discussed below. In some embodiments, the ADC circuit 200 is integrated into an integrated circuit (IC) device (e.g., an IC device formed on a single semiconductor substrate such as a silicon substrate), in which case the IC device can detect an open pin condition without using external components. In some embodiments, the open pin detection circuit 300 is implemented using analog components. For example, an analog low-pass filter can be used as the extraction filter 310, which is used to convert a one-bit data stream into an analog output signal (e.g., an analog voltage value), and the comparator 320 can be an analog comparator.

[0042] Reference now Figure 4 , which illustrates a block diagram of a sigma-delta ADC circuit 400 according to an embodiment. Figure 4 As shown, the sigma-delta ADC circuit 400 includes a sigma-delta modulator 410, a decimation filter 420, a gain adjustment module 430, and an optional configuration module 440. The decimation filter 420 and the gain adjustment module 430 correspond to Figure 2 The sigma-delta modulator 410 is configured to generate a decimation module 428 at a sampling frequency f s The analog input signal at the input port 411 is sampled and converted to a one-bit digital stream (eg, a digital data sequence with 1-bit resolution) at the output 415. The sampling rate f s Typically much higher (e.g., at least an order of magnitude higher) than the Nyquist sampling frequency of the analog input signal. For example, for a three-phase motor system with a phase frequency of about 20 KHz, the sampling frequency f of the sigma-delta modulator is s The sampling frequency may be about 20 MHz. In some embodiments, the large sampling frequency allows the use of a simple low pass filter in the decimation filter 420 and provides a higher bit resolution at the output of the decimation filter 420. The sigma-delta modulator 410 may be a continuous time sigma-delta modulator or a discrete time sigma-delta modulator. Sigma-delta modulators are known in the art and will not be described in detail herein.

[0043] Still reference Figure 4, the decimation filter 420 includes two functional modules: a low pass filter (LPF) 423 and a down sampler 425 (also referred to as a decimator 425). For hardware implementation, although the LPF 423 and the down sampler 425 can also be implemented in different circuit modules or hardware modules, the LPF 423 and the down sampler 425 can be implemented in the same circuit module or hardware module. The digital cutoff frequency of the LPF 423 is π / D, where π is the frequency corresponding to the sampling frequency f s Half the normalized digital frequency (in radians / second), D is the decimation factor of the decimator 425. The LPF 423 may be constructed using any suitable filter, such as an infinite impulse response (IIR) filter, a finite impulse response (FIR) filter, a SINC filter, a comb filter, a cascaded integrator comb (CIC) filter, etc. The LPF 423 reduces or removes frequency components of its input signal (e.g., a one-bit digital stream) that are higher than the digital frequency π / D, and prevents aliasing in the decimation process when the output of the LPF 423 is downsampled by the downsampler 425 (also referred to as decimation).

[0044] Downsampler 425 reduces the sampling frequency of the digital signal by a factor D (also referred to as decimation factor D, decimation rate D, and downsampling factor D). Decimation filter 420 may include multiple processing stages ( Figure 4 4 (not shown), where each stage has an LPF and a decimator. In addition to removing the frequency components (higher than the digital frequency π / D) of the digital stream at the output 415 of the sigma-delta modulator 410, the LPF 423 also has the function of "averaging" its input signal, thereby converting a single-bit digital stream into a multi-bit digital value. The multi-bit digital value from the LPF 423 is decimate by a factor of D through the decimator 425, and then the n-bit digital value is sent out at the data path 417 of the decimation filter 420.

[0045] Figure 4 A gain adjustment module 430 coupled to the output of the decimation filter 420 is shown. In some embodiments, the gain adjustment module 430 includes a multiplier that multiplies the output of the decimation filter 420 by a scaling factor. In other embodiments, the gain adjustment module 430 includes a divider unit that is used to output a normalized data format. Through the multiplier or divider, the gain adjustment scales the output of the decimation filter 420 by the scaling factor. In some embodiments, the gain adjustment module 430 is integrated into the same hardware module as the decimation filter 420. For example, the decimation filter 420 can have a built-in gain factor that implements the functionality of the gain adjustment module 430.

[0046] In some embodiments, optional configuration module 440 sets the configuration of decimation filter 420 and the scaling factor of gain adjustment module 430. External interface 450 allows configuration module 440 to be controlled by a controller (e.g., Figure 1 4. In some embodiments, the configuration module 440 is omitted and the configuration of the decimator filter 420 and the gain adjustment module 430 is hardwired. In other embodiments, the configuration parameters of the decimator filter 420 and the gain adjustment module 430 are stored in a memory (e.g., a non-volatile memory) and loaded into the configuration registers of the sigma-delta ADC circuit 400 during power-up or reset of the hardware.

[0047] Figure 5 The diagram shows a Figure 3 1 is a block diagram of a decimation filter 310 of an open pin detection circuit 300. Figure 4 4. Similar to the decimation filter 420 of , the decimation filter 310 includes an LPF 313 and a downsampler 315, wherein the downsampler 315 may be optional. In some embodiments, the LPF 313 and the downsampler 315 are the same as or similar to the LPF 423 and the downsampler 425, respectively, and thus are not described in detail. It should be noted that since the function of the decimation filter 310 is to form an estimate of the input analog signal (rather than to obtain a high-resolution digital output), the decimation filter 310 may have a structure that may be simpler than that of the decimation filter 420. For example, Figure 4 Compared to LPF 423 of decimation filter 310, LPF 313 of decimation filter 310 may have a lower filter order, fewer filter taps, and / or fewer filter stages in the filter design. As a result, the number of bits (also referred to as bit resolution) of output 317 of decimation filter 310 may be lower than the number of bits of decimation filter 420. Therefore, the same analog input signal value at input port 207 of ADC circuit 200 may correspond to different output codes (e.g., with different resolutions) at the outputs of decimation filters 420 and 310. In some embodiments, decimation filter 310 has a unity gain, which is less than the gain of decimation module 428.

[0048] Figure 8 FIG. 2 is a block diagram of an analog-to-digital converter (ADC) circuit 200A having an open pin detection circuit according to an embodiment. Figure 3 The ADC circuit 200 is similar to the ADC circuit 200, but the counter 310A is used to replace the decimation filter 310 in the open pin detection circuit 300. In addition, Figure 8 The pull-up circuit 500 has no Figure 3 The resistor 205 in.

[0049] exist Figure 8In an embodiment of the present invention, the open pin detection circuit 300 forms an estimate of the input analog signal (e.g., the shunt voltage) using a counter 310A that is configured to count the number of consecutive zeros and / or consecutive ones in a one-bit data stream from the sigma-delta modulator 410. For example, a small input analog signal may produce a long string of zeros in the one-bit data stream at the output of the sigma-delta modulator 410, while a large input analog signal may produce a long string of ones in the one-bit data stream. By counting the number of consecutive zeros and / or the number of consecutive ones in the one-bit data stream, the output of the counter 310A forms an estimate of the input analog signal, which is compared to a predetermined threshold by the comparator 320 to detect an open pin condition. For example, the predetermined threshold may be 60, which means that if the counter 310A detects (e.g., counts) sixty consecutive ones or consecutive zeros in the one-bit stream, the comparator 320 may output a logic 1 to indicate that an open pin condition has been detected. In the illustrated embodiment, the predetermined threshold (e.g., 60) is determined by, for example, the design and threshold voltage of the sigma-delta modulator 410, and is independent of the design (e.g., length, order, gain) of the decimation module 428. In an alternative embodiment, the total number of ones and / or zeros (which may not be consecutive) occurring within a predetermined time period is counted, and an open pin condition is detected if more than the predetermined number of ones and / or zeros are present in the measured time period.

[0050] Fig. 9 FIG. 2 is a block diagram of an analog-to-digital converter (ADC) circuit 200B having an open pin detection circuit according to yet another embodiment. Figure 8 The ADC circuit 200A is similar to the ADC circuit 200A, but the pull-up circuit 500 has a pull-up resistor 205. It should be noted that in different embodiments, the pull-up circuits 500, 500' and 500" can be used interchangeably. For example, the pull-up circuit 500' or the pull-up circuit 500" can be used instead of Figure 3 These and other variations are fully intended to be included within the scope of the present disclosure.

[0051] Fig.10 1000 is a flow chart illustrating a method of operating an ADC circuit according to some embodiments. It should be understood that Fig.10 The illustrated embodiment methods are examples of many possible embodiment methods. Those skilled in the art will recognize many variations, alternatives, and modifications. For example, the following may be added, removed, replaced, rearranged, and repeated. Fig.10 The steps shown.

[0052] refer to Fig.10, at step 1010, a current is applied to an input pin of an integrated circuit. For example, the current can be applied to the input pin via a pull-up circuit (e.g., 500, 500', or 500"). At step 1020, an analog signal at the input pin is converted into a digital stream using a sigma-delta modulator (e.g., 410). At step 1030, a decimation filter (e.g., 420) is used to convert the digital stream into a first digital output signal, wherein the first digital output signal is proportional to the analog signal at the input pin within a first input range between a first analog signal value and a second analog signal value, wherein the first analog signal value corresponds to a predetermined range of the analog signal, the predetermined range being less than a full-scale input range of the analog signal. For example, at Figure 7 The predetermined range of the analog signal can be between -V a With V b The full-scale input range can be between -V b With V b At step 1040, the digital stream is converted into a second output signal, for example, by the open pin detection circuit 300. At step 1050, the second output signal is compared with a first threshold, wherein the first threshold corresponds to a third analog signal value at the output pin outside the first input range. For example, Figure 7 The third threshold can be between V a and V b Between or -V b and -V a At step 1060, when the second output signal crosses the first threshold, an indication of an open circuit condition at the input pin is provided.

[0053] Advantages of embodiments of the present invention include real-time detection of an open pin condition in an ADC circuit. The disclosed open pin detection circuit 300 operates in parallel with the sigma-delta ADC circuit 400 without affecting the operation of the sigma-delta ADC circuit. For example, the code range and dynamic range of the sigma-delta ADC circuit 400 are not affected by the open pin detection circuit 300. In the illustrated embodiment, the open pin condition is detected in real time, and there is no need to stop the sigma-delta ADC circuit 400 to enter a test mode to check for normal operation of the open pin condition. The ADC circuit capable of open pin detection can be integrated into an integrated circuit (IC), in which case the open pin condition can be detected using the IC without the need for external components.

[0054] Example embodiments of the invention are summarized herein. Other embodiments are also contemplated based on the overall specification and claims submitted herein.

[0055] Example 1. In an embodiment, a method includes: applying a current to an input pin of an integrated circuit; converting an analog signal at the input pin into a digital stream using a sigma-delta modulator; converting the digital stream into a first digital output signal using a decimation filter, wherein the first digital output signal is proportional to the analog signal at the input pin within a first input range between a first analog signal value and a second analog signal value, wherein the first input range corresponds to a predetermined range of the analog signal, which is less than a full-scale input range of the analog signal; converting the digital stream into a second output signal; comparing the second output signal with a first threshold, wherein the first threshold corresponds to a third analog signal value of the analog signal at the input pin outside the first input range; and providing an indication of an open circuit condition at the input pin when the second output signal crosses the first threshold.

[0056] Example 2. The method of Example 1, wherein the input pins include a first input pin and a second input pin; applying current to the input pins includes: applying a first current to the first input pin and applying a second current to the second input pin; and the sigma-delta modulator includes a differential input coupled to the first input pin and the second input pin.

[0057] Example 3. The method of Example 2 also includes: comparing the second output signal with a second threshold, wherein the second threshold corresponds to a fourth analog signal value of the analog signal at the input pin outside the first input range; and when the second output signal crosses the second threshold, providing an indication of an open circuit condition at the input pin, wherein the third analog signal value is greater than the second analog signal value, the fourth analog signal value is less than the first analog signal value, and the second analog signal value is greater than the first analog signal value.

[0058] Example 4. The method of Example 1, wherein applying the current to the input pin of the integrated circuit comprises: using a pull-up resistor or a pull-down resistor.

[0059] Example 5. The method of Example 1, wherein applying current to an input pin of the integrated circuit comprises: using a current source.

[0060] Example 6. The method of Example 1, wherein the digital stream comprises a one-bit data stream.

[0061] Example 7. The method of Example 6, wherein converting the digital stream to the second output signal comprises: converting the digital stream to the second output signal using a counter.

[0062] Example 8. The method of Example 6, wherein converting the digital stream to the second output signal comprises: converting the digital stream to the second output signal using an analog low pass filter.

[0063] Example 9. The method of Example 1, wherein the first analog signal value corresponds to a minimum output code of the first digital output signal, and the second analog signal value corresponds to a maximum output code of the first digital output signal.

[0064] Example 10. In an embodiment, an integrated circuit includes a pin bias circuit configured to provide current to an input pin of the integrated circuit; a sigma-delta modulator having an input coupled to the input pin; a decimation filter coupled to the output of the sigma-delta modulator and configured to provide a first digital output signal proportional to an analog signal at the input pin within a first input range between a first analog signal value and a second analog signal value, wherein the first input range corresponds to a predetermined range of the analog signal, which is less than the full-scale input range of the analog signal; and an open pin detection circuit coupled to the output of the sigma-delta modulator, the open pin detection circuit configured to: convert the output of the sigma-delta modulator to a second output signal; compare the second output signal to a first threshold, wherein the first threshold corresponds to a third analog signal value of the analog signal at the input pin outside the first input range; and provide an indication of an open circuit condition at the input pin when the second output signal crosses the first threshold.

[0065] Example 11. An integrated circuit of Example 10, wherein the input pins of the integrated circuit include a first input pin and a second input pin, wherein the pin bias circuit is configured to apply a first current to the first input pin and a second current to the second input pin, wherein the sigma-delta modulator includes a differential input coupled to the first input pin and the second input pin.

[0066] Example 12. An integrated circuit of Example 10, wherein the open pin detection circuit is further configured to: compare the second output signal with a second threshold, wherein the second threshold corresponds to a fourth analog signal value of the analog signal at the input pin outside the first input range; and provide an indication of an open circuit condition at the input pin when the second output signal crosses the second threshold, wherein the third analog signal value is greater than the second analog signal value, the fourth analog signal value is less than the first analog signal value, and wherein the first analog signal value is less than the second analog signal value.

[0067] Example 13. The integrated circuit of Example 10, wherein the pin bias circuit comprises a pull-up resistor or a pull-down resistor configured to be coupled between a power supply and an input pin of the integrated circuit.

[0068] Example 14. The integrated circuit of Example 10, wherein the pin bias circuit comprises a current source configured to be coupled between a power supply and an input pin of the integrated circuit.

[0069] Example 15. The integrated circuit of Example 10, wherein the sigma-delta modulator is configured to convert an analog signal at an input pin of the integrated circuit into a one-bit data stream.

[0070] Example 16. The integrated circuit of Example 15, wherein the open pin detection circuit comprises a counter configured to count a number of consecutive ones or consecutive zeros in a one-bit data stream.

[0071] Example 17. The integrated circuit of Example 15, wherein the open pin detection circuit comprises an analog low pass filter configured to convert a one bit data stream into an analog output signal.

[0072] Example 18. In an embodiment, an analog-to-digital converter circuit includes a first input terminal and a second input terminal; a sigma-delta modulator coupled to the first input terminal and the second input terminal and configured to convert a voltage between the first input terminal and the second input terminal into a one-bit data stream; a pull-up circuit configured to be coupled between a power supply node and the first input terminal and the second input terminal, and to pull a first voltage at the first input terminal to a first voltage value above a predetermined voltage threshold when the first input terminal is held open, or to pull a second voltage at the second input terminal to a first voltage value when the second input terminal is held open, wherein the predetermined voltage threshold is less than a full-scale input of the sigma-delta modulator by a predetermined percentage; a first low-pass filter coupled to the output of the sigma-delta modulator and configured to convert the one-bit data stream into a first multi-bit data stream at the output of the analog-to-digital converter circuit; and an open pin detection circuit coupled to the output of the sigma-delta modulator and configured to use the one-bit data stream to detect that the voltage between the first input terminal and the second input terminal is above a predetermined voltage threshold.

[0073] Example 19. The analog-to-digital converter circuit of Example 18, wherein the open pin detection circuit includes a counter configured to count the number of consecutive zeros or consecutive ones in a one-bit data stream; and a comparator configured to compare the number of consecutive zeros or consecutive ones with a predetermined threshold.

[0074] Example 20. The analog-to-digital converter circuit of Example 18, wherein the open pin detection circuit includes a second low-pass filter coupled to the output of the sigma-delta modulator and configured to convert a one-bit data stream into a second multi-bit data stream, wherein a gain of the second low-pass filter is less than a gain of the first low-pass filter, and a bit width of the second multi-bit data stream is less than a bit width of the first multi-bit data stream; and a comparator configured to compare the value of the second multi-bit data stream with a predetermined threshold.

[0075] Example 21. The analog-to-digital converter circuit of Example 18, wherein the first input terminal, the second input terminal, the sigma-delta modulator, the pull-up circuit, the first low-pass filter, and the open pin detection circuit are integrated into the same integrated circuit device.

[0076] Although the present invention has been shown and described primarily in conjunction with specific exemplary embodiments, it will be appreciated by those skilled in the art that various changes may be made to its structure and details without departing from the essence and scope of the present invention as defined by the following claims. Therefore, the scope of the present invention is determined by the appended claims and is intended to be used for all changes that fall within the meaning and scope of the claims and equivalents covered by the claims.

Claims

1. A method comprising: applying current to the input pin of the integrated circuit; converting the analog signal at the input pin into a digital stream using a sigma-delta modulator; converting the digital stream to a first digital output signal using a decimation filter, wherein the first digital output signal is proportional to an analog signal at the input pin within a first input range between a first analog signal value and a second analog signal value, wherein the first input range corresponds to a predetermined range of the analog signal, the predetermined range being less than a full-scale input range of the analog signal; converting the digital stream into a second output signal; comparing the second output signal to a first threshold, wherein the first threshold corresponds to a third analog signal value of the analog signal at the input pin that is outside of the first input range; as well as When the second output signal crosses the first threshold, an indication of an open circuit condition at the input pin is provided.

2. The method according to claim 1, wherein: The input pins include a first input pin and a second input pin; Applying the current to the input pin includes: applying a first current to the first input pin, and applying a second current to the second input pin; as well as The sigma-delta modulator includes a differential input coupled to the first input pin and the second input pin.

3. The method according to claim 2, further comprising: comparing the second output signal to a second threshold, wherein the second threshold corresponds to a fourth analog signal value of the analog signal at the input pin outside of the first input range; as well as An indication of the open circuit condition at the input pin is provided when the second output signal crosses the second threshold, wherein the third analog signal value is greater than the second analog signal value, the fourth analog signal value is less than the first analog signal value, and the second analog signal value is greater than the first analog signal value.

4. The method of claim 1 , wherein applying the current to the input pin of the integrated circuit comprises: Use either a pull-up resistor or a pull-down resistor.

5. The method of claim 1 , wherein applying the current to the input pin of the integrated circuit comprises: Use a current source. The method of claim 1 , wherein the digital stream comprises a one-bit data stream.

7. The method of claim 6, wherein converting the digital stream into the second output signal comprises: The digital stream is converted into the second output signal using a counter.

8. The method of claim 6, wherein converting the digital stream into the second output signal comprises: The digital stream is converted into the second output signal using an analog low pass filter.

9. The method of claim 1, wherein the first analog signal value corresponds to a minimum output code of the first digital output signal, and the second analog signal value corresponds to a maximum output code of the first digital output signal.

10. An integrated circuit comprising: a pin bias circuit configured to provide current to an input pin of the integrated circuit; a sigma-delta modulator having an input coupled to the input pin; a decimation filter coupled to an output of the sigma-delta modulator and configured to provide a first digital output signal proportional to an analog signal at the input pin within a first input range between a first analog signal value and a second analog signal value, wherein the first input range corresponds to a predetermined range of the analog signal, the predetermined range being less than a full-scale input range of the analog signal; and an open pin detection circuit coupled to the output of the sigma-delta modulator, the open pin detection circuit being configured to: converting the output of the sigma-delta modulator into a second output signal; comparing the second output signal to a first threshold, wherein the first threshold corresponds to a third analog signal value of the analog signal at the input pin outside of the first input range; as well as When the second output signal crosses the first threshold, an indication of an open circuit condition at the input pin is provided.

11. The integrated circuit of claim 10, wherein the input pins of the integrated circuit include a first input pin and a second input pin, wherein the pin bias circuit is configured to apply a first current to the first input pin and a second current to the second input pin, wherein the sigma-delta modulator includes a differential input coupled to the first input pin and the second input pin.

12. The integrated circuit of claim 10, wherein the open pin detection circuit is further configured to: comparing the second output signal to a second threshold, wherein the second threshold corresponds to a fourth analog signal value of the analog signal at the input pin outside of the first input range; and The indication of the open circuit condition at the input pin is provided when the second output signal crosses the second threshold, wherein the third analog signal value is greater than the second analog signal value, the fourth analog signal value is less than the first analog signal value, and wherein the first analog signal value is less than the second analog signal value.

13. The integrated circuit of claim 10, wherein the pin bias circuit comprises a pull-up resistor or a pull-down resistor configured to be coupled between a power supply and the input pin of the integrated circuit.

14. The integrated circuit of claim 10, wherein the pin bias circuit comprises a current source configured to be coupled between a power supply and the input pin of the integrated circuit.

15. The integrated circuit of claim 10, wherein the sigma-delta modulator is configured to convert the analog signal at the input pin of the integrated circuit into a one-bit data stream. 16 . The integrated circuit of claim 15 , wherein the open pin detection circuit comprises a counter configured to count the number of consecutive ones or consecutive zeros in the one-bit data stream.

17. The integrated circuit of claim 15, wherein the open pin detection circuit comprises an analog low pass filter configured to convert the one-bit data stream into an analog output signal.

18. An analog-to-digital converter circuit, comprising: a first input terminal and a second input terminal; a sigma-delta modulator coupled to the first input terminal and the second input terminal and configured to convert a voltage between the first input terminal and the second input terminal into a one-bit data stream; a pull-up circuit configured to be coupled between a power supply node and the first input terminal and the second input terminal and to pull a first voltage at the first input terminal to a first voltage value above a predetermined voltage threshold when the first input terminal is held open, or to pull a second voltage at the second input terminal to the first voltage value when the second input terminal is held open, wherein the predetermined voltage threshold is less than a full-scale input voltage of the sigma-delta modulator by a predetermined percentage; a first low pass filter coupled to the output of the sigma-delta modulator and configured to convert the one-bit data stream to a first multi-bit data stream at the output of the analog-to-digital converter circuit; as well as An open pin detection circuit is coupled to the output of the sigma-delta modulator and is configured to use the one-bit data stream to detect that the voltage between the first input terminal and the second input terminal is above the predetermined voltage threshold.

19. The analog-to-digital converter circuit of claim 18, wherein the open pin detection circuit comprises: a counter configured to count the number of consecutive zeros or consecutive ones in the one-bit data stream; as well as A comparator is configured to compare the number of consecutive zeros or consecutive ones with a predetermined threshold.

20. The analog-to-digital converter circuit of claim 18, wherein the open pin detection circuit comprises: a second low pass filter coupled to the output of the sigma-delta modulator and configured to convert the one-bit data stream into a second multi-bit data stream, wherein a gain of the second low pass filter is less than a gain of the first low pass filter and a bit width of the second multi-bit data stream is less than a bit width of the first multi-bit data stream; as well as A comparator is configured to compare the value of the second multi-bit data stream with a predetermined threshold value.

21. The analog-to-digital converter circuit of claim 18, wherein the first input terminal, the second input terminal, the sigma-delta modulator, the pull-up circuit, the first low-pass filter, and the open pin detection circuit are integrated into a same integrated circuit device.

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