A power-off retention circuit without separate core power domain

Abstract

The present invention discloses a power-off holding circuit without a separate core power domain, comprising: a holding control signal generating circuit, a holding circuit, and a level conversion circuit for converting an input signal IN of a core voltage VDD level into an output signal OUTP and an output signal OUTN of an input-output voltage VDDIO level, wherein the holding control signal generating circuit comprises: first to fifth NMOS tubes, first to fifth PMOS tubes and a resistor, and the holding circuit comprises: sixth to ninth PMOS tubes and sixth to ninth NMOS tubes. The design is simplified, layout and wiring are convenient, and the layout area is saved.

Description

Technical Field

[0001] The invention relates to a power-off holding circuit. Background Art

[0002] In DDR (Double Data Rate Synchronous Dynamic Random Access Memory) power-off mode, the core module power is turned off to achieve low power consumption. In this mode, the signal state before power-off needs to be maintained so that the signal before power-off can be quickly read when exiting the power-off mode. Usually a separate core power domain is required to maintain the core signal state. Summary of the invention

[0003] The object of the present invention is to provide a power-off holding circuit which does not require a separate core power domain, thereby simplifying the design, facilitating layout and wiring, and saving layout area.

[0004] The technical solution to achieve the above purpose is:

[0005] A power-off holding circuit without a separate core power domain comprises: a holding control signal generating circuit, a holding circuit, and a level conversion circuit for converting an input signal IN of a core voltage VDD level into an output signal OUTP and an output signal OUTN of an input-output voltage VDDIO level, wherein:

[0006] The holding control signal generating circuit includes: first to fifth NMOS transistors, first to fifth PMOS transistors and a resistor,

[0007] The source of each of the first to fifth PMOS transistors is connected to the input-output voltage VDDIO; the source of each of the first to fifth NMOS transistors is connected to the ground VSS;

[0008] The drain of the first PMOS tube is connected to the drain of the first NMOS tube; the drain of the second PMOS tube is connected to the drain of the second NMOS tube; the drain of the third PMOS tube is connected to the drain of the third NMOS tube; the drain of the fourth PMOS tube is connected to the drain of the fourth NMOS tube; the drain of the fifth PMOS tube is connected to the drain of the fifth NMOS tube;

[0009] The gate of the first PMOS tube is connected to the drain of the third PMOS tube; the gate of the second PMOS tube is connected to the gate of the second NMOS tube; the gate of the third PMOS tube is connected to the drain of the first PMOS tube; the gate of the fourth PMOS tube is connected to the drain of the third PMOS tube; the gate of the fifth PMOS tube is connected to the drain of the fourth PMOS tube;

[0010] The gate of the first NMOS tube is connected to the core voltage VDD through the resistor; the gate of the first NMOS tube is connected to the gate of the second PMOS tube; the gate of the third NMOS tube is connected to the drain of the second NMOS tube; the gate of the fourth NMOS tube is connected to the drain of the third PMOS tube; the gate of the fifth NMOS tube is connected to the drain of the fourth PMOS tube;

[0011] The connected end of the drain of the fourth PMOS tube and the drain of the fourth NMOS tube outputs a hold control signal; the connected end of the drain of the fifth PMOS tube and the drain of the fifth NMOS tube outputs a holdb control signal;

[0012] The holding circuit includes: sixth to ninth PMOS tubes and sixth to ninth NMOS tubes;

[0013] The source electrodes of the sixth PMOS transistor and the seventh PMOS transistor are respectively connected to the input-output voltage VDDIO;

[0014] The source electrodes of the sixth NMOS tube and the seventh NMOS tube are respectively grounded to VSS;

[0015] The drain of the sixth PMOS tube is connected to the source of the eighth PMOS tube, the drain of the eighth PMOS tube is connected to the drain of the eighth NMOS tube; the source of the eighth NMOS tube is connected to the drain of the sixth NMOS tube;

[0016] The drain of the seventh PMOS tube is connected to the source of the ninth PMOS tube, the drain of the ninth PMOS tube is connected to the drain of the ninth NMOS tube; the source of the ninth NMOS tube is connected to the drain of the seventh NMOS tube;

[0017] The connecting end of the gate of the sixth PMOS tube and the gate of the sixth NMOS tube is connected to the output signal OUTP; the connecting end of the drain of the ninth PMOS tube and the drain of the ninth NMOS tube is connected to the output signal OUTP;

[0018] The connecting end of the gate of the seventh PMOS tube and the gate of the seventh NMOS tube is connected to the output signal OUTN; the connecting end of the drain of the eighth PMOS tube and the drain of the eighth NMOS tube is connected to the output signal OUTN;

[0019] The connecting end of the gate of the eighth PMOS tube and the gate of the ninth PMOS tube is connected to the holdb control signal;

[0020] The connecting end of the gate of the eighth NMOS tube and the gate of the ninth NMOS tube is connected to the hold control signal.

[0021] Preferably, the level conversion circuit transmits the hold control signal and the holdb control signal to the holding circuit.

[0022] The beneficial effect of the present invention is that the present invention utilizes the power-off and power-on of the core power supply (VDD) to generate a hold / holdb control signal in the input and output high power domain (VDDIO) to achieve that when the core power supply is powered off, the signal is locked and maintained in the state before the power-off. No separate core power domain is required, which simplifies the design, facilitates layout and wiring, and saves the layout area. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a circuit diagram of a power-off holding circuit of the present invention;

[0024] Figure 2 It is a schematic diagram of input and output waveforms of the power-off holding circuit of the present invention. DETAILED DESCRIPTION

[0025] The present invention will be further described below in conjunction with the accompanying drawings.

[0026] See also Figure 1 The power-off holding circuit of the present invention without the need for a separate core power domain comprises: a holding control signal generating circuit, a holding circuit and a level conversion circuit.

[0027] The holding control signal generating circuit includes: first to fifth NMOS transistors NM1 - NM5 , first to fifth PMOS transistors PM1 - PM5 , and a resistor R1 .

[0028] The sources of the first to fifth PMOS transistors PM1 - PM5 are respectively connected to the input-output voltage VDDIO; the sources of the first to fifth NMOS transistors NM1 - NM5 are respectively connected to the ground VSS.

[0029] The drain of the first PMOS tube PM1 is connected to the drain of the first NMOS tube NM1; the drain of the second PMOS tube PM2 is connected to the drain of the second NMOS tube NM2; the drain of the third PMOS tube PM3 is connected to the drain of the third NMOS tube NM3; the drain of the fourth PMOS tube PM4 is connected to the drain of the fourth NMOS tube NM4; the drain of the fifth PMOS tube PM5 is connected to the drain of the fifth NMOS tube NM5.

[0030] The gate of the first PMOS transistor PM1 is connected to the drain of the third PMOS transistor PM3; the gate of the second PMOS transistor PM2 is connected to the gate of the second NMOS transistor NM2; the gate of the third PMOS transistor PM3 is connected to the drain of the first PMOS transistor PM1; the gate of the fourth PMOS transistor PM4 is connected to the drain of the third PMOS transistor PM3; the gate of the fifth PMOS transistor PM5 is connected to the drain of the fourth PMOS transistor PM4;

[0031] The gate of the first NMOS tube NM1 is connected to the core voltage VDD through the resistor R1; the gate of the first NMOS tube NM1 is connected to the gate of the second PMOS tube PM2; the gate of the third NMOS tube NM3 is connected to the drain of the second NMOS tube NM2; the gate of the fourth NMOS tube NM4 is connected to the drain of the third PMOS tube PM3; the gate of the fifth NMOS tube NM5 is connected to the drain of the fourth PMOS tube PM4;

[0032] The drain of the fourth PMOS tube PM4 and the drain of the fourth NMOS tube NM4 are connected to each other to output the hold control signal; the drain of the fifth PMOS tube PM5 and the drain of the fifth NMOS tube NM5 are connected to each other to output the holdb control signal. The core voltage VDD is powered off (from 1 to 0), the gates of the second NMOS tube NM2 and the second PMOS tube PM2 are changed from 1 to 0, so that the second NMOS tube NM2 is turned off, the second PMOS tube PM2 is turned on, the gate of the third NMOS tube NM3 is pulled up to the input-output voltage VDDIO, and the third NMOS tube NM3 is turned on. The first NMOS tube NM1 is turned off during the process of the core voltage VDD changing from 1 to 0, and the gate of the third PMOS tube PM3 is pulled up through the first PMOS tube PM1, so that the third PMOS tube PM3 is turned off. The drain end of the third PMOS tube PM3 is pulled down to VSS (0 potential) by the opened third NMOS tube NM3, and the hold control signal is pulled to a high potential through the inverter fourth PMOS tube PM4 / fourth NMOS tube NM4, such as Figure 2 shown.

[0033] The level conversion circuit converts the input signal IN of the core voltage VDD level into the output signal OUTP and the output signal OUTN of the input-output voltage VDDIO level. When the core voltage VDD is powered off (from 1 to 0), the input signal IN is in a high-impedance (Hi-Z) state. At this time, the output signal OUTP / OUTN needs to pass through the holding circuit to maintain the state before power failure. The level conversion circuit transmits the hold control signal and the holdb control signal to the holding circuit.

[0034] The holding circuit includes: sixth to ninth PMOS transistors PM1 - PM5 and sixth to ninth NMOS transistors NM6 - NM9 .

[0035] The source electrodes of the sixth PMOS transistor PM6 and the seventh PMOS transistor PM7 are connected to the input-output voltage VDDIO; the source electrodes of the sixth NMOS transistor NM6 and the seventh NMOS transistor NM7 are connected to the ground VSS;

[0036] The drain of the sixth PMOS transistor PM6 is connected to the source of the eighth PMOS transistor PM8, the drain of the eighth PMOS transistor PM8 is connected to the drain of the eighth NMOS transistor NM8; the source of the eighth NMOS transistor NM8 is connected to the drain of the sixth NMOS transistor NM6;

[0037] The drain of the seventh PMOS transistor PM7 is connected to the source of the ninth PMOS transistor PM9, and the drain of the ninth PMOS transistor PM9 is connected to the drain of the ninth NMOS transistor NM9; the source of the ninth NMOS transistor NM9 is connected to the drain of the seventh NMOS transistor NM7;

[0038] The gate of the sixth PMOS transistor PM6 and the gate of the sixth NMOS transistor NM6 are connected to the output signal OUTP; the drain of the ninth PMOS transistor PM9 and the drain of the ninth NMOS transistor NM9 are connected to the output signal OUTP;

[0039] The gate of the seventh PMOS transistor PM7 and the gate of the seventh NMOS transistor NM7 are connected to the output signal OUTN; the drain of the eighth PMOS transistor PM8 and the drain of the eighth NMOS transistor NM8 are connected to the output signal OUTN;

[0040] The connecting end of the gate of the eighth PMOS transistor PM8 and the gate of the ninth PMOS transistor PM9 is connected to the holdb control signal; the connecting end of the gate of the eighth NMOS transistor NM8 and the gate of the ninth NMOS transistor NM9 is connected to the hold control signal.

[0041] The core voltage VDD is powered off (from 1 to 0), the hold / holdb control signals are 1 / 0 respectively, the eighth NMOS tube NM8, the ninth NMOS tube NM9, the eighth PMOS tube PM8, and the ninth PMOS tube PM9 are turned on, the sixth to ninth PMOS tubes PM1-PM5 and the sixth to ninth NMOS tubes NM6-NM9 are latch circuits composed of two inverters, and the output signal OUTP / OUTN latches the state before power off.

[0042] The above embodiments are only used to illustrate the present invention, rather than to limit the present invention. Those skilled in the relevant technical field may make various changes or modifications without departing from the spirit and scope of the present invention. Therefore, all equivalent technical solutions should also belong to the scope of the present invention and should be defined by the claims.

Claims

1. A power-off retention circuit without a separate core power domain, characterized in that: include: A holding control signal generating circuit, a holding circuit, and a level conversion circuit for converting an input signal IN of a core voltage VDD level into an output signal OUTP and an output signal OUTN of an input-output voltage VDDIO level, wherein: The holding control signal generating circuit includes: first to fifth NMOS transistors, first to fifth PMOS transistors and a resistor, The source of each of the first to fifth PMOS transistors is connected to the input-output voltage VDDIO; the source of each of the first to fifth NMOS transistors is connected to the ground VSS; The drain of the first PMOS tube is connected to the drain of the first NMOS tube; the drain of the second PMOS tube is connected to the drain of the second NMOS tube; the drain of the third PMOS tube is connected to the drain of the third NMOS tube; the drain of the fourth PMOS tube is connected to the drain of the fourth NMOS tube; the drain of the fifth PMOS tube is connected to the drain of the fifth NMOS tube; The gate of the first PMOS tube is connected to the drain of the third PMOS tube; the gate of the second PMOS tube is connected to the gate of the second NMOS tube; the gate of the third PMOS tube is connected to the drain of the first PMOS tube; the gate of the fourth PMOS tube is connected to the drain of the third PMOS tube; the gate of the fifth PMOS tube is connected to the drain of the fourth PMOS tube; The gate of the first NMOS tube is connected to the core voltage VDD through the resistor; the gate of the first NMOS tube is connected to the gate of the second PMOS tube; the gate of the third NMOS tube is connected to the drain of the second NMOS tube; the gate of the fourth NMOS tube is connected to the drain of the third PMOS tube; the gate of the fifth NMOS tube is connected to the drain of the fourth PMOS tube; The connected end of the drain of the fourth PMOS tube and the drain of the fourth NMOS tube outputs a hold control signal; the connected end of the drain of the fifth PMOS tube and the drain of the fifth NMOS tube outputs a holdb control signal; The holding circuit includes: sixth to ninth PMOS tubes and sixth to ninth NMOS tubes; The source electrodes of the sixth PMOS transistor and the seventh PMOS transistor are respectively connected to the input-output voltage VDDIO; The source electrodes of the sixth NMOS tube and the seventh NMOS tube are respectively grounded to VSS; The drain of the sixth PMOS tube is connected to the source of the eighth PMOS tube, the drain of the eighth PMOS tube is connected to the drain of the eighth NMOS tube; the source of the eighth NMOS tube is connected to the drain of the sixth NMOS tube; The drain of the seventh PMOS tube is connected to the source of the ninth PMOS tube, the drain of the ninth PMOS tube is connected to the drain of the ninth NMOS tube; the source of the ninth NMOS tube is connected to the drain of the seventh NMOS tube; The connecting end of the gate of the sixth PMOS tube and the gate of the sixth NMOS tube is connected to the output signal OUTP; the connecting end of the drain of the ninth PMOS tube and the drain of the ninth NMOS tube is connected to the output signal OUTP; The connecting end of the gate of the seventh PMOS tube and the gate of the seventh NMOS tube is connected to the output signal OUTN; the connecting end of the drain of the eighth PMOS tube and the drain of the eighth NMOS tube is connected to the output signal OUTN; The connecting end of the gate of the eighth PMOS tube and the gate of the ninth PMOS tube is connected to the holdb control signal; The connecting end of the gate of the eighth NMOS tube and the gate of the ninth NMOS tube is connected to the hold control signal.

2. The power-off holding circuit without a separate core power domain according to claim 1, characterized in that: The level conversion circuit transmits the hold control signal and the holdb control signal to the holding circuit.

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