Semiconductor module and method of manufacturing the same

Abstract

A method for manufacturing a power semiconductor module device (100) comprises mixing inorganic fillers (81) with a casting material (5), thereby preparing a mixture comprising a first concentration of inorganic fillers (81), wherein the inorganic fillers (81) have a density (p cc ) higher than a density (p f ) of the casting material (5). The method further comprises filling the mixture comprising inorganic fillers (81) and casting material (5) into an enclosure (7), wherein a semiconductor substrate (10) is arranged within the enclosure (7), and wherein at least one semiconductor body (20) is arranged on a top surface of the semiconductor substrate (10); performing a sedimentation step during which the inorganic fillers (81) sediment onto the semiconductor substrate (10) and the at least one semiconductor body (20), thereby forming a first layer (800) comprising a portion of the casting material (5) and the inorganic fillers (81) and a second layer (801) comprising a remaining portion of the casting material (5) but no inorganic fillers (81); and hardening the casting material (5).

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor module and a manufacturing method thereof. BACKGROUND

[0002] Power semiconductor module devices often comprise at least one semiconductor substrate arranged in a housing. A semiconductor device comprising a plurality of controllable semiconductor elements, e.g. two IGBTs in a half-bridge configuration, is arranged on each of the at least one substrate. Each substrate typically comprises a substrate layer, e.g. a ceramic layer, a first metallization layer deposited on a first side of the substrate layer and a second metallization layer deposited on a second side of the substrate layer. The controllable semiconductor elements are mounted on the first metallization layer, for example. The second metallization layer can optionally be attached to a base plate. The controllable semiconductor elements are typically mounted on the semiconductor substrate by soldering or sintering techniques.

[0003] Wires or electrical connections are used to connect different semiconductor devices of a power semiconductor module device. Such wires and electrical connections can comprise metallic and / or semiconductor materials. The housing of a power semiconductor module device is generally permeable to gases to some extent. For example, some gases, e.g. sulfur containing gases, can react with the metallic components inside the housing. This causes a chemical deterioration of these components, which can lead to a failure of individual components and eventually to a failure of the entire semiconductor device.

[0004] Therefore, the components inside the housing are typically protected from corrosion by encapsulating the components. Different materials are known to be suitable for protecting the components inside the housing from corrosion. However, such materials can have a different coefficient of thermal expansion (CTE) than the substrate and the elements mounted on the substrate. Furthermore, encapsulation materials for reducing the CTE mismatch can cause high stresses inside the housing.

[0005] There is a need for a power semiconductor module, wherein the semiconductor components are protected from corrosion and wherein the CTE mismatch between different components and internal stresses are reduced, thereby prolonging the overall lifetime of the power semiconductor module device. SUMMARY

[0006] A method for manufacturing a power semiconductor module device comprises mixing an inorganic filler with a casting material, thereby preparing a mixture comprising a first concentration of the inorganic filler, wherein the inorganic filler has a density higher than the density of the casting material. The method further comprises filling the mixture comprising the inorganic filler and the casting material into an enclosure, wherein a semiconductor substrate is arranged within the enclosure, and wherein at least one semiconductor body is arranged on a top surface of the semiconductor substrate; performing a sedimentation step during which the inorganic filler sediments downwards onto the semiconductor substrate and the at least one semiconductor body, thereby forming a first layer comprising a portion of the casting material and the inorganic filler and a second layer comprising a remaining portion of the casting material but no inorganic filler; and hardening the casting material.

[0007] A semiconductor module device comprises a semiconductor substrate arranged within an enclosure; at least one semiconductor body arranged on a top surface of the semiconductor substrate; a first layer arranged on the top surface of the semiconductor substrate, wherein the first layer comprises an inorganic filler being impermeable to corrosive gases and a casting material filling any spaces present in the inorganic filler, and wherein the inorganic filler has a density higher than the density of the casting material; and a second layer arranged on the first layer, wherein the second layer comprises the casting material without the inorganic filler.

[0008] The application can be better understood with reference to the following drawings and description. The components in the drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the application. Furthermore, in the drawings, like reference numerals designate corresponding parts throughout the different views. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a cross-sectional view of a power semiconductor module device.

[0010] Figure 2 is a cross-sectional view of another power semiconductor module device.

[0011] includes Figures 3A to 3D Figure 3 of includes steps of a method for manufacturing a power semiconductor module device according to one example.

[0012] Figure 4 exemplarily shows the resulting forces occurring at the interface between different elements and the encapsulation material. DETAILED DESCRIPTION

[0013] The following detailed description will be referenced to the accompanying drawings. The drawings illustrate specific examples in which the invention can be practiced. It should be understood that, unless otherwise specified, features and principles described with respect to various examples can be combined with each other. The designation of certain elements as “first element,” “second element,” “third element,” etc., in the specification and claims should not be construed as an enumeration. Rather, such designation is merely for referring to different “elements.” That is, for example, the presence of a “third element” does not require the presence of “first element” and “second element.” The wires or electrical connections described herein may be a single conductive element or may include at least two individual conductive elements connected in series and / or parallel. The wires and electrical connections may include metallic and / or semiconductor materials and may be permanently conductive (i.e., non-switchable). The semiconductor body described herein may be constructed of (doped) semiconductor material and may be a semiconductor chip or may be included in a semiconductor chip. The semiconductor body has electrical connection pads and includes at least one semiconductor element with electrodes.

[0014] refer to Figure 1 The diagram schematically illustrates a cross-sectional view of a power semiconductor module device 100. The power semiconductor module device 100 includes a housing 7 and a semiconductor substrate 10. The semiconductor substrate 10 includes a dielectric insulating layer 11, a (structured) first metallization layer 111 attached to the dielectric insulating layer 11, and a (structured) second metallization layer 112 attached to the dielectric insulating layer 11. The dielectric insulating layer 11 is disposed between the first metallization layer 111 and the second metallization layer 112.

[0015] Each of the first metallization layer 111 and the second metallization layer 112 can be composed of or can include one of the following materials: copper; a copper alloy; aluminum; an aluminum alloy; any other metal or alloy that remains in a solid state during operation of the power semiconductor module device. The semiconductor substrate 10 can be a ceramic substrate, i.e. a substrate in which the dielectric insulating layer 11 is ceramic, e.g. a thin ceramic layer. The ceramic can be composed of or can include one of the following materials: aluminum oxide; aluminum nitride; zirconium oxide; silicon nitride; boron nitride; or any other dielectric ceramic. For example, the dielectric insulating layer 11 can be composed of or can include one of the following materials: AI2O3, AIN, SiC, BeO or Si3N4. For example, the substrate 10 can be, e.g., a direct copper bonding (DCB) substrate, a direct aluminum bonding (DAB) substrate or an active metal brazing (AMB) substrate. Further, the substrate 10 can be an insulated metal substrate (IMS). For example, an insulated metal substrate generally includes a dielectric insulating layer 11 containing a (filling) material such as an epoxy resin or a polyimide. For example, the material of the dielectric insulating layer 11 can be filled with ceramic particles. Such particles can include, e.g., Si2O, AI2O3, AIN or BrN and can have a diameter between approximately 1 pm and approximately 50 pm. The substrate 10 can also be a conventional printed circuit board (PCB) having a non-ceramic dielectric insulating layer 11. For example, the non-ceramic dielectric insulating layer 11 can be composed of or can include a cured resin.

[0016] The semiconductor substrate 10 is arranged in the housing 7. In the example shown in Figure 1 the semiconductor substrate 10 forms a bottom surface of the housing 7, while the housing 7 itself exclusively includes a sidewall and a lid. However, this is merely an example. It is also possible that the housing 7 further includes a bottom surface and that the semiconductor substrate 10 is arranged inside the housing 7. According to another example, the semiconductor substrate can be mounted on a base plate (not shown). In some power semiconductor module devices 100, more than one semiconductor substrate 10 is arranged on a single base plate. For example, the base plate can form a bottom surface of the housing 7.

[0017] One or more semiconductor bodies 20 can be arranged on the semiconductor substrate 10. Each of the semiconductor bodies 20 arranged on the semiconductor substrate 10 can include a diode, an IGBT (insulated gate bipolar transistor), a MOSFET (metal oxide semiconductor field effect transistor), a JFET (junction field effect transistor), a HEMT (high electron mobility transistor) or any other suitable semiconductor element.

[0018] One or more semiconductor bodies 20 can form a semiconductor device on the semiconductor substrate 10. In Figure 1 two semiconductor bodies 20 are merely exemplarily shown.Figure 1 The second metallization layer 112 of the semiconductor substrate 10 is a continuous layer. Figure 1 In the example shown, the first metallization layer 111 is a structured layer. A "structured layer" means that the first metallization layer 111 is not a continuous layer, but rather includes recesses between different segments of that layer. Figure 1 The recess is schematically illustrated. In this example, the first metallization layer 111 comprises three distinct segments. However, this is merely an example. Any other number of segments are possible. Different semiconductor bodies 20 can be mounted on the same or different segments of the first metallization layer 111. The different segments of the first metallization layer may not have any electrical connections, or they may be electrically connected to one or more other segments using, for example, bonding leads 3. For example, to illustrate a few examples, the electrical connections 3 may also include connecting plates or conductor rails. One or more semiconductor bodies 20 may be electrically and mechanically connected to the semiconductor substrate 10 via a conductive connection layer 30. Such a conductive connection layer may be a solder layer, a conductive adhesive layer, or a sintered metal powder (e.g., sintered silver powder) layer.

[0019] According to other examples, the second metallization layer 112 may also be a structured layer. The second metallization layer 112 may also be omitted. For example, the first metallization layer 111 may also be a continuous layer.

[0020] Figure 1 The power semiconductor module device 100 shown also includes a terminal element 4. The terminal element 4 is electrically connected to the first metallization layer 111 and provides an electrical connection between the interior and exterior of the housing 7. The terminal element 4 can be electrically connected to the first metallization layer 111 with its first end, while a second end 41 of the terminal element 4 extends from the housing 7. Electrical contact with the terminal element 4 can be made externally at the second end 41. However, Figure 1 The terminal element 4 shown is merely an example. The terminal element 4 can be implemented in any other manner and can be arranged anywhere within the housing 7. For example, one or more terminal elements 4 can be arranged close to or adjacent to the sidewall of the housing 7. The terminal element 4 can also extend through the sidewall of the housing 7 instead of through the cover. Any other suitable implementation is possible.

[0021] Semiconductor bodies 20 may include chip pad metallization (not specifically shown), such as source, drain, anode, cathode, or gate metallization. Chip pad metallization generally provides contact surfaces for electrically connecting the semiconductor bodies 20. For example, chip pad metallization may electrically contact the interconnect layer 30, terminal element 4, or electrical connection portion 3. For example, chip pad metallization may be made of, or may include, metals such as aluminum, copper, gold, or silver. For example, electrical connection portion 3 and terminal element 4 may also be made of, or may include, metals such as copper, aluminum, gold, or silver.

[0022] Components within the housing 7 of the power semiconductor module device 100 mentioned above, as well as other components, may corrode upon contact with corrosive gases. For example, corrosive gases may include sulfur or sulfur-containing compounds, such as hydrogen sulfide (H₂S). Corrosive gases in the surrounding area of ​​the power semiconductor module device 100 can penetrate into the interior of the housing 7. The housing 7 used for the power semiconductor module device 100 is typically not fully protected against intruding gases. Furthermore, corrosive gases can enter the housing 7, for example, when it is open or before it is closed. Inside the housing 7, corrosive gases can, for example, combine with moisture present inside the housing 7 to form acids or solutions. The corrosive gases or the resulting solutions can cause corrosion of some or all of the different components. During the corrosion process, the metallic components of the components can be oxidized into their respective sulfides. The formation of sulfides can alter the electrical properties of the components, or lead to the formation of new conductive connections or short circuits within the power semiconductor module device 100.

[0023] Furthermore, when exposed to corrosive gases and further subjected to an electric field and possible moisture, the power semiconductor module device 100 exhibits mobile metal ions (e.g., Cu, Ag, etc.) in its metallic components and structures, as well as anions (e.g., S, etc.) present in the corrosive gases. 2- Dendrite structures can form. Dendrites are a unique type of tree-like crystal structure. Dendrite growth in metal layers can have significant consequences relative to material properties and is generally undesirable.

[0024] Examples of corrosive gases include hydrogen sulfide (H₂S), carbonyl sulfide (OCS), or gaseous sulfur (S₂). In some applications, power semiconductor module devices may be exposed to corrosive gases such as Cl₂. - SO x or NO x Generally speaking, sulfur may also enter the interior of the outer casing 7 as a solid material or a liquid component.

[0025] Components and structures comprising one or more metals may be particularly susceptible to corrosion, such as copper (e.g., first metallization layer 111, electrical connection 3, terminal element 4, connection layer 30, chip pad metallization), silver (e.g., first metallization layer 111, electrical connection 3, terminal element 4, connection layer 30, chip pad metallization), or lead (e.g., connection layer 30 including lead-containing solder). Other metals (e.g., aluminum) may have a thin oxide layer covering their surface area, which provides at least some degree of protection against corrosive gases.

[0026] A conventional power semiconductor module device 100 generally also includes a casting compound 5. For example, the casting compound 5 may be made of or may include silicone gel, or it may be a rigid molding compound. The casting compound 5 may at least partially fill the interior of the housing 7, thereby covering components and electrical connections disposed on the semiconductor substrate 10. Terminal elements 4 may be partially embedded in the casting compound 5. However, at least their second end 41 is not covered by the casting compound 5 and extends through the housing 7 from the casting compound 5 to the outside of the housing 7. The casting compound 5 is configured to protect components and electrical connections inside the power semiconductor module 100 (especially inside the housing 7) from certain environmental conditions and mechanical damage. The casting compound 5 also provides electrical isolation for components inside the housing 7. However, corrosive gases can typically penetrate the casting compound 5. Therefore, the casting compound 5 typically cannot protect components and electrical connections from corrosive gases.

[0027] The casting compound 5 can form a protective layer on the semiconductor substrate 10 in the vertical direction y. The vertical direction y is a direction substantially perpendicular to the top surface of the semiconductor substrate 10. The top surface of the semiconductor substrate 10 is the surface on which the semiconductor body 20 is mounted or can be mounted. The first protective layer 5 at least partially covers any components disposed on the top surface of the semiconductor substrate 10 and any exposed surfaces of the semiconductor substrate 10.

[0028] To better protect the metal components of the power semiconductor module device 100 from corrosive gases, the casting compound 5 may also include a filler 81. Specifically, the filler 81 may be mixed into the casting compound 5. However, the filler 81 may not be uniformly distributed within the casting compound 5. Instead, the semiconductor device may include a first layer 800 formed of a mixture of the filler 81 and the casting compound 5, and a second layer 801 comprising only the casting compound 5 but without the filler 81. The second layer 801 may be disposed above the first layer 800. That is, the first layer 800 may be disposed between the second layer 801 and the semiconductor substrate 10 on which the semiconductor body 20 is mounted.

[0029] This isFigure 2 The example is shown below. The filler 81 can be configured to chemically react with corrosive gases, or particularly with sulfur or sulfur-containing compounds of corrosive gases. Corrosive gases can also be captured, adsorbed, or absorbed by the filler 81. By chemically reacting with corrosive gases, the filler 81 prevents harmful substances from reaching the (metallic) components inside the housing 7, thereby protecting the components from corrosion. For example, the filler 81 can be a powder of a second material distributed throughout the first material of the casting compound 5. The second material can include any material that reacts with corrosive gases and can, for example, form metal sulfides upon exposure to corrosive gases. The filler 81 can be distributed substantially uniformly throughout the first layer 800. The first material of the casting compound 5 can include or be composed of a non-reactive crosslinkable or non-crosslinkable polymer, such as a silicone gel or silicone rubber. Other casting materials, such as epoxy resin, are also possible, for example.

[0030] For example, filler 81 can be an inorganic filler. Inorganic fillers can include non-solubilized inorganic materials such as silica, fused silica, crystalline silica, precipitated silica, alumina, beryllium, boron nitride, aluminum nitride, silicon nitride, silicon carbide, boron carbide, titanium carbide, magnesium oxide, zinc oxide, or glass fiber. For example, filler 81 can be provided in particulate form, with the particles having a diameter between approximately 1 μm and 400 μm or between approximately 4 μm and 20 μm. All particles can have the same diameter. However, not all particles in filler 81 need to have the same diameter. It is also possible to use fillers comprising particles of different sizes. For example, binary systems (e.g., particles with two different diameters) or ternary systems (particles with three different diameters) are also possible. In this way, the packing density of filler 81 can be increased. In the mixture comprising casting compound 5 and filler 81, i.e., in the first layer 800, for example, the amount of filler 81 may be between approximately 20 vol% and 90 vol%, or between approximately 60 vol% and 80 vol%. Generally, the first layer 800 may include a relatively high amount of filler 81. The particles of filler 81 may have a relatively high density ρ. f For example, at approximately 0.9 g / cm³ 3 and 5.0g / cm 3 Between. On the other hand, the casting compound 5 can have a lower density ρ than the filler 81. f density ρ cc According to one example, the density ρ of casting compound 5 cc It can be at approximately 0.2 g / cm³. 3 and 0.9g / cm3 Between. According to one example, if the density ρ of filler 81... f It is 0.9 g / cm³ 3 Then the density ρ of casting compound 5 cc <0.9g / cm 3 or even <0.5g / cm 3 For example, the aspect ratio of each individual particle in filler 81 can be between 1 and 100.

[0031] If the inorganic filler 81 includes a conductive material such as a metallic material, then the concentration of the inorganic filler 81 in the first layer 800 is such that the first layer 800 as a whole remains electrically insulating.

[0032] The first layer 800 may have a first thickness d1 in the vertical direction y. The first layer 800 at least partially covers any components disposed on the top surface of the semiconductor substrate 10 and any exposed surfaces of the semiconductor substrate 10. For example, the first thickness d1 may be between 1 mm and 10 mm, or between 2 mm and 6 mm.

[0033] The second layer 801 is disposed on top of the first layer 800. In this context, "on top of the first layer 800" means that the second layer 801 is disposed adjacent to the first layer 800 in the vertical direction y, such that the first layer 800 is disposed between the second layer 801 and the semiconductor substrate 10. For example, the second layer 801 may include a casting material, such as a non-reactive soft crosslinked or non-crosslinked polymer. For example, a non-reactive polymer may include silicone gel or silicone rubber. Other casting materials such as epoxy resin are also possible. The material of the second layer 801 may be the same as the first material of the first layer 800. The second layer 801 may have a second thickness d2 in the vertical direction y. The second thickness d2 may be the same as the first thickness d1, or the second thickness d2 may be greater than or less than the first thickness d1. For example, the second thickness d2 may be between 1 mm and 10 mm, or between 2 mm and 6 mm.

[0034] like Figure 2 As shown in the example, the bottom of the housing 7 of the power semiconductor module device 100 can be filled only with a first layer 800 comprising both a first material and a filler 81. The thickness d1 of the first layer 800 is significantly smaller than that of the housing 7. Figure 1 The height of the unfilled casting compound 5 in the apparatus shown is... Figure 1 In the apparatus shown, the main part of the outer shell 7 is filled with casting compound 5. Figure 1The relatively large thickness of a single layer of the casting compound 5 in a power semiconductor module device can cause flexure of the power semiconductor module device 100, particularly flexure of the semiconductor substrate 10 and / or the substrate (if applicable), especially when the casting compound 5 includes a so-called hard encapsulant. The hard encapsulant has a hardness greater than a certain threshold hardness. For example, the hardness of the material can be determined by a Shore hardness tester and can be indicated by one of several Shore hardness tester scales (e.g., Shore Type A, Shore Type D, etc.). Figure 2 The relatively thin first layer 800 of the power semiconductor module device generally causes only minor or no flexural deformation of the power semiconductor module device 100.

[0035] This is Figure 4 As shown in the example, Figure 4 The diagram schematically illustrates the forces that may occur on the surfaces of different components in a semiconductor module device. These forces include those found in casting compounds 5, which are made of hard resin materials (see [reference]). Figure 1 The corresponding forces on the surfaces of different components of the semiconductor module device Figure 4 The force is shown as 100% in each case, with the values ​​shown for reference. Using a soft resin instead of a hard resin can significantly reduce the forces that occur. For example, when using a soft resin instead of a hard resin, the force occurring on the surface of the second metallization layer 112 (Cu, bottom) can be reduced by more than 30% to about 65%. When using a soft resin instead of a hard resin, the force occurring on the surface of the IMS substrate (IMS) can be reduced by more than 40% to about 58%. When using a soft resin instead of a hard resin, the force occurring on the surface of the first metallization layer 111 (Cu, top) can be reduced by more than 30% to about 68%. When using a soft resin instead of a hard resin, the force occurring on the surface of the solder layer 30 (solder) can be reduced by about 60% to about 40%. When using a soft resin instead of a hard resin, the force occurring on the surface of the semiconductor body 20 (chip) can be reduced by more than 50% to about 47%. When using a soft resin instead of a hard resin, the force occurring on the surface of the first layer 800 (soft resin with filler) can be reduced by more than 30% to about 63%.

[0036] It can be seen that by using a soft encapsulation material and forming a first layer 800 including both the soft encapsulation and the filler 81, and a second layer 801 including only the soft encapsulation but without the filler 81, stress within the semiconductor module can be reduced, and the reliability of the entire system can be enhanced. Furthermore, the mismatch in the coefficient of thermal expansion (CTE) between different components of the semiconductor module can be reduced by adding the filler 81 to the casting compound 5 in the first layer 800. For example, the CTE of the first layer 800... 800The coefficient of thermal expansion (CTE) of the semiconductor substrate 10 and at least one semiconductor body 20 can be compared. 10 CTE 20 Similarly, this makes (for example) CTE 800 =CTE 10 ±5ppm / K, and CTE 800 =CTE 20 ±5ppm / K. This method can reduce undesirable flexing in semiconductor modules. Undesirable flexing can generally occur when different forces are applied at different interfaces within a semiconductor module. For example, the semiconductor substrate 10 and / or the substrate of the semiconductor module may bend to some extent, causing the semiconductor substrate 10 and / or the substrate to no longer be flat, but possibly to have concave or convex curvature in the vertical direction y. This can further cause undesirable tension on connections formed within the semiconductor substrate, such as conductive connection layers 30 used to mount the semiconductor body 20 onto the semiconductor substrate 10. Localized thermal stress can cause degradation of the casting compound 5.

[0037] In an ideal semiconductor module, the balance of forces dominates. That is, F1 + F2 + F3 + ... + F i = 0, where F is the force and i is the component number in the semiconductor module. Furthermore, in an ideal semiconductor module, torque balance dominates. That is, M1 + M2 + M3 + ... + M i =M ext Where M is torque and I is the component number in the semiconductor module.

[0038] The strain continuity between adjacent layers within a semiconductor module can be calculated as follows: Or, more generally speaking, Where F is force, α is CTE, E is modulus, and d is the thickness of the layer in the vertical direction y. For example, different layers of the semiconductor module may be a first metallization layer 111, a second metallization layer 112, a dielectric insulating layer 11, a conductive interconnect layer 30, or a casting compound 5.

[0039] The bend generated by the semiconductor module can generally be adjusted by adjusting the amount of filler 81 in the first layer 801. For example, a larger bend can occur when the amount of filler 81 in the first layer 801 is reduced, and a smaller bend can occur when the amount of filler 81 in the first layer 801 is increased.

[0040] Figure 2 An example of a power semiconductor module device 100 after the formation of the first layer 800 and the second layer 801 is shown. This will now be illustrated by including... Figures 3A to 3D Figure 3 explains the use of manufacturing Figure 2Methods for power semiconductor module devices.

[0041] Figure 3B A power semiconductor module device 100 is shown prior to the formation of the first layer 800 and the second layer 801. The power semiconductor module device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 may correspond to the above description relative to... Figure 1 and Figure 2 The semiconductor substrate 10 has already been described. As described above, one or more semiconductor bodies 20 may be disposed on the semiconductor substrate 10. The power semiconductor module device 100 may also include terminal elements 4, as described above. The housing 7 of the power semiconductor module device 100 substantially corresponds to the above description relative to... Figure 1 and Figure 2 The housing 7 has already been described. However, the cover may be added to the housing 7 at a later stage, such as after the formation of the first layer 800 and the second layer 801. Figure 3B The housing 7 of the device shown may also include a bottom. Alternatively, a semiconductor substrate 10 may be disposed on a substrate (not shown), thereby forming the bottom of the housing 7 from the substrate. Figure 3A As schematically shown, the inorganic filler 81 can be premixed with the casting compound 5. For example, the particles of filler 81 can be uniformly distributed within the casting compound 5. For example, the material of the casting compound 5 can be a liquid or a viscous substance.

[0042] Then, the mixture including casting compound 5 and filler 81 can be filled into the semiconductor module, such as... Figure 3B As shown schematically in the diagram. Figure 3C The diagram schematically illustrates a semiconductor module device 100 after the mixture has been filled into the housing 7. It can be seen that at this point, the filler 81 is still uniformly distributed within the casting compound 5. However, due to the density ρ of the filler 81... f The density ρ of the casting compound 5 is greater than that of the casting compound 5. cc Therefore, the filler 81 is deposited downwards onto the surface of the semiconductor substrate 10 and the semiconductor body 20 and any other components mounted on the semiconductor substrate 10. For example... Figure 3DAs schematically shown, a dense first layer 800 is formed in this way by the descending filler 81. As described above, the filler 81 may comprise particles. For example, the particles may have a generally rounded or elliptical shape. However, any other form of particle is also possible. After downward sedimentation, the particles of the filler 81 may stack on top of each other. However, spaces or gaps remain between the different particles of the filler 81. Part of the casting compound 5 fills these spaces or gaps. Thus, the first layer 800 is a relatively dense layer formed by causing the filler 81 to descend within the casting compound 5. The concentration of the filler within the first layer 800 is significantly higher than the concentration of the filler 81 in the premixed mixture filled into the casing 7.

[0043] The remaining portion of the casting compound forms a second layer 801 disposed on the first layer 800. Since the filler 81 falls onto the semiconductor substrate 10, no filler 81 remains in the second layer 801. The thickness d1 of the first layer 800 and the thickness d2 of the second layer 801 depend on the amount of casting compound 5 and filler 81 used to form the premixed mixture (see reference). Figure 3A ).

[0044] The deposition of filler 81 can be accelerated by heating the semiconductor module device 10 during the deposition step. Heating reduces the density of the casting compound 5, thereby liquefying the material of the casting compound (reducing the viscosity of the casting compound 5). Therefore, filler 81 can deposit faster at higher temperatures than at lower temperatures. For example, the temperature during the deposition step can be between 30°C and 150°C.

[0045] The precipitation of filler 81 can be performed in a vacuum. For example, a vacuum of 1 mbar to 200 mbar can be created. In addition to heating the semiconductor module device or as an alternative, it is also possible to accelerate the precipitation of filler 81 by reducing the vacuum level during the precipitation step. The temperature and vacuum level can depend on the material used to cast compound 5.

[0046] Once filler 81 has completely settled, a curing or hardening step (not specifically shown) can be performed. During the curing or hardening of casting compound 5, casting compound 5 crosslinks with inorganic filler 81. This significantly reduces the mobility of inorganic filler 81. By substantially filling all remaining spaces and gaps between the particles of inorganic filler 81 and by crosslinking casting compound 5 with inorganic filler, any gas becomes difficult, if not impossible, to diffuse through the first layer 800.

[0047] For example, curing or hardening the casting compound 5 may include heating the casting compound 5 and causing all or most of the liquid in the casting compound 5 to evaporate. For example, instead of curing the casting compound 5 or after curing the casting compound 5, the casting compound 5 may be cooled to below its glass transition temperature. For example, the casting compound 5 may be cooled to room temperature, which is often much lower than the glass transition temperature of the material used as the casting compound 5.

[0048] The particles of the inorganic filler 81 are generally stacked on top of each other in a random manner. Therefore, if there were any discrepancies, the gas could not diffuse in a straight line through the first layer 800. Generally, the gas cannot penetrate the inorganic filler 81, but only through the casting compound 5 surrounding the filler 81. Therefore, the gas must diffuse around the inorganic filler 81, resulting in a relatively long diffusion path. This makes it even more difficult for the gas to diffuse through the first layer 800. Generally, due to the relatively high amount of inorganic filler 81 in the first layer 800, there is almost no space for the gas to diffuse through the first layer 800. This makes it virtually impossible for corrosive gases to diffuse through the first layer 800.

[0049] from Figure 2 As can be seen, and as described above, the concentration of filler 81 in the first layer 800 adjacent to the semiconductor substrate 10 and the semiconductor body 20 mounted thereon is very high. On the other hand, the second layer 801 does not contain any filler 81. In this way, with... Figure 1 Compared to other devices, the elastic modulus of the filler material can be increased, and the CTE of the first layer 800 can be reduced compared to a layer containing only casting compound 5. In this way, the CTE of the first layer 800 can be adjusted to match the CTE of the semiconductor substrate 10 and the semiconductor body 20. The CTE can be adjusted by changing the concentration of the filler 81 within the casting compound 5. The resulting semiconductor module device 100 is stable at high temperatures (e.g., above 200°C).

Claims

1. A method for manufacturing a power semiconductor module device (100), comprising: The inorganic filler (81) is mixed with the casting material (5) to prepare a mixture comprising an inorganic filler (81) of a first concentration, wherein the inorganic filler (81) has a density (ρ) higher than that of the casting material (5). cc The density (ρ) f ); The mixture comprising the inorganic filler (81) and the casting material (5) is filled into the housing (7), wherein a semiconductor substrate (10) is disposed within the housing (7), and wherein at least one semiconductor body (20) is disposed on the top surface of the semiconductor substrate (10). A deposition step is performed, during which the inorganic filler (81) is deposited downwards onto the semiconductor substrate (10) and the at least one semiconductor body (20), thereby forming a first layer (800) comprising a portion of the casting material (5) and the inorganic filler (81) and a second layer (801) comprising the remaining portion of the casting material (5) but without the inorganic filler (81); and Harden the casting material (5), During the precipitation step, the power semiconductor module device (100) is heated, thereby liquefying the casting material (5). In the first layer (800), the casting material (5) fills all remaining spaces and gaps between the particles of the inorganic filler (81) and crosslinks the casting material (5) with the inorganic filler (81). The inorganic filler (81) comprises particles having two or more different diameters to increase the packing density of the inorganic filler (81).

2. The method according to claim 1, wherein, The inorganic filler (81) has a concentration of 0.9 g / cm³. 3 and 5.0g / cm 3 Density between (ρ) f ), and wherein the casting material (5) has a concentration of 0.2 g / cm³. 3 and 0.9g / cm 3 Density between (ρ) cc ).

3. The method according to claim 1 or 2, wherein, The amount of the inorganic filler (81) in the first layer (800) is between 20 vol% and 90 vol%, or between 60 vol% and 80 vol%.

4. The method according to claim 1 or 2, wherein, The casting material (5) includes non-reactive crosslinkable or non-crosslinkable polymers.

5. The method according to claim 4, wherein, The polymer includes silicone gel, silicone rubber, or epoxy resin.

6. The method according to claim 1 or 2, wherein, The inorganic filler (81) includes at least one of silicon dioxide, fused silicon dioxide, crystalline silicon dioxide, precipitated silicon dioxide, aluminum oxide, beryllium, boron nitride, aluminum nitride, silicon nitride, silicon carbide, boron carbide, titanium carbide, magnesium oxide, zinc oxide, or glass fiber.

7. The method according to claim 1 or 2, wherein, The inorganic filler (81) comprises particles having a diameter between 1 μm and 400 μm or between 4 μm and 20 μm.

8. The method according to claim 1 or 2, wherein, The first layer (800) is disposed between the second layer (801) and the semiconductor substrate (10).

9. The method according to claim 1 or 2, wherein, The first layer (800) has a coefficient of thermal expansion (CTE) relative to the semiconductor substrate (10) and the at least one semiconductor body (20). 10 CTE 20 Similar coefficient of thermal expansion CTE 800 This makes CTE 800 =CTE 10 ±5ppm / K, and CTE 800 =CTE 20 ±5ppm / K.

10. The method according to claim 1 or 2, wherein, The first layer (800) has a first thickness (d1) in a vertical direction (y) perpendicular to the top surface of the semiconductor substrate (10); The second layer (801) has a second thickness (d2) in the vertical direction (y); and The second thickness (d2) is the same as the first thickness (d1), or the second thickness (d2) is less than or greater than the first thickness (d1).

11. The method according to claim 1 or 2, further comprising the following operations: The precipitation step is performed in a vacuum.

12. A power semiconductor module device (100), comprising: A semiconductor substrate (10) is disposed within a housing (7); At least one semiconductor body (20) is disposed on the top surface of the semiconductor substrate (10); A first layer (800) is disposed on the top surface of the semiconductor substrate (10), wherein the first layer (800) comprises an inorganic filler (81) impermeable to corrosive gases and a casting material (5) filling any spaces present in the inorganic filler (81), wherein the inorganic filler (81) has a higher density (ρ) than the casting material (5). cc The density (ρ) f ), and wherein the inorganic filler (81) is configured to chemically react with the corrosive gas; and A second layer (801) is disposed on top of the first layer (800), wherein the second layer (801) includes the casting material (5) but without the inorganic filler (81), and In the first layer (800), the casting material (5) fills all remaining spaces and gaps between the particles of the inorganic filler (81) and the casting material (5) is cross-linked with the inorganic filler (81), and the inorganic filler (81) comprises particles having two or more different diameters to increase the bulk density of the inorganic filler (81).

13. The power semiconductor module device (100) according to claim 12, wherein, The inorganic filler (81) has a concentration of 0.9 g / cm³. 3 and 5.0g / cm 3 Density between (ρ) f ), and wherein the casting material (5) has a concentration of 0.2 g / cm³. 3 and 0.9g / cm 3 Density between (ρ) cc ).

14. The power semiconductor module device (100) according to claim 12 or 13, wherein, The amount of the inorganic filler (81) in the first layer (800) is between 20 vol% and 90 vol%, or between 60 vol% and 80 vol%.

15. The power semiconductor module device (100) according to claim 12 or 13, wherein, The inorganic filler (81) comprises particles having a diameter between 1 μm and 400 μm or between 4 μm and 20 μm.

Images