Chips, circuit boards, circuit board assemblies and electronic devices

Abstract

The present disclosure relates to chips, circuit boards, circuit board assemblies, and electronic devices. The substrate of the chip is divided into a central area and an edge area, and a plurality of pads are divided into a first pad arranged in the edge area of the substrate and a second pad arranged in the central area of the substrate, so that the straight edge of the first pad can share the stress from the peripheral edge of the substrate. The above-mentioned structural setting strengthens the ability of each pad located in different areas of the substrate to resist stress, increases the structural strength of the pad itself and the welding strength between the pad and the solder ball, prevents the pad and the solder ball from breaking due to impact, falling, etc. during testing and use, and improves the service life of the chip, circuit board, circuit board assembly, and electronic equipment.

Description

Technical Field

[0001] The present disclosure relates to the field of electronic technology, and in particular to chips, circuit boards, circuit board assemblies, and electronic devices. Background Art

[0002] In related technologies, electronic devices such as mobile phones usually contain chips for realizing various functions. The electronic components and control circuits on the chips are packaged through solder pads and solder balls soldered to the solder pads.

[0003] However, as the market demands for chip functionality and the overall thinness of electronic devices increase, the chip packaging circuits within a unit size become more and more complex, and the chip pad size and pad spacing are gradually reduced to accommodate the packaging circuits. This leads to a decrease in the structural strength of the pad itself and the welding strength between the pad and the solder ball. This can easily cause solder joint breakage and damage to electronic devices during testing and use. Summary of the Invention

[0004] The present disclosure provides a chip, a circuit board, a circuit board assembly, and an electronic device to increase the soldering reliability between a solder pad and a solder ball, thereby prolonging the service life of the chip, the circuit board assembly, and the electronic device.

[0005] According to a first aspect of the present disclosure, a chip is provided, comprising a substrate and a plurality of pads disposed on the substrate, each of the pads being soldered with a solder ball;

[0006] The plurality of pads include a first pad and a second pad; the substrate includes a central area and an edge area surrounding the central area, the first pad is arranged in the edge area, and the second pad is arranged in the central area;

[0007] The first pad includes a polygonal soldering area and an arched soldering area connected to the polygonal soldering area, and the polygonal soldering area is arranged between the arched soldering area and the edge of the substrate.

[0008] Optionally, the edge region includes a straight edge sub-region and a corner edge sub-region connecting two adjacent straight edge sub-regions, and the straight edge sub-region and the corner edge sub-region are respectively provided with the first pad.

[0009] Optionally, a plurality of first pad arrays are arranged in the corner edge sub-region, and an array direction of the first pads arranged in the corner edge sub-region includes a first horizontal direction and a first vertical direction.

[0010] Optionally, the number of rows of the first solder pads in the first vertical direction is greater than or equal to two.

[0011] Optionally, the corner edge sub-region includes two adjacent substrate edges and an angle formed by the two substrate edges, and the first vertical direction is parallel to a midline of the angle.

[0012] Optionally, the first pad disposed in the corner edge sub-region includes a first straight side and a second straight side, the first straight side is parallel to the first horizontal direction, and the second straight side is parallel to the first vertical direction.

[0013] Optionally, a plurality of first pad arrays are arranged in the straight edge sub-region, and an array direction of the first pads arranged in the straight edge sub-region includes a second horizontal direction and a second vertical direction;

[0014] The first pad disposed in the straight edge sub-region includes a third straight side and a fourth straight side, the third straight side is parallel to the second horizontal direction, and the fourth straight side is parallel to the second vertical direction.

[0015] Optionally, the second pad includes a circular pad area.

[0016] Optionally, the areas of the first pad and the second pad are equal.

[0017] According to a second aspect of the present disclosure, a circuit board assembly is provided, the circuit board assembly comprising a mainboard and the chip, wherein the chip is assembled on the mainboard;

[0018] The mainboard is provided with a third solder pad and a fourth solder pad, the third solder pad is conductively connected to the first solder pad in a one-to-one correspondence, and the corresponding first solder pad and the third solder pad have the same structure; the fourth solder pad is conductively connected to the second solder pad in a one-to-one correspondence, and the corresponding second solder pad and the fourth solder pad have the same structure.

[0019] Optionally, the circuit board assembly further includes a filling adhesive layer, which is arranged between the mainboard and the chip; the filling adhesive layer is respectively bonded to the first solder pad and the third solder pad, and the filling adhesive layer is respectively bonded to the second solder pad and the fourth solder pad.

[0020] According to a third aspect of the present disclosure, an electronic device is provided, comprising:

[0021] the chip;

[0022] Or, the circuit board assembly.

[0023] According to a fourth aspect of the present disclosure, a chip is provided, comprising a chip substrate and a plurality of pads disposed on the chip substrate;

[0024] The plurality of pads include a first pad and a second pad; the chip substrate includes a central area and an edge area surrounding the central area, the first pad is arranged in the edge area, and the second pad is arranged in the central area;

[0025] The first pad includes at least one straight edge adjacent to an edge of the chip substrate.

[0026] Optionally, at least one straight edge is parallel to the edge of the chip substrate.

[0027] Optionally, the straight edges parallel to the same edge of the chip substrate are collinear.

[0028] Optionally, the first pad and the second pad have the same area.

[0029] Optionally, the edge area includes a straight edge sub-area and a corner edge sub-area connecting two adjacent straight edge sub-areas, at least one of the first pad arrays is arranged in the corner edge sub-area, and at least one straight edge of the first pad arranged in the corner edge sub-area is at a 45° angle to the edge of the chip substrate.

[0030] Optionally, the edge region includes a peripheral region close to the edge of the chip substrate, and a transition region respectively connected to the peripheral region and the central region.

[0031] Optionally, the first pad includes a rectangular welding area and an arcuate welding area connected to the rectangular welding area;

[0032] And / or, the first pad includes a polygonal pad;

[0033] And / or, the first pad includes a pentagonal welding area and an arcuate welding area connected to the pentagonal welding area;

[0034] And / or, the first pad includes a triangular soldering area and an arcuate soldering area connected to the triangular soldering area.

[0035] Optionally, the second soldering pad includes a circular soldering area and / or a polygonal soldering area.

[0036] According to a fifth aspect of the present disclosure, a circuit board is provided, comprising a circuit board substrate and a plurality of pads arranged on the circuit board substrate;

[0037] The plurality of pads include a fifth pad and a sixth pad; the circuit board substrate includes a central area and an edge area surrounding the central area, the fifth pad is arranged in the edge area, and the sixth pad is arranged in the central area;

[0038] The fifth pad includes at least one straight edge adjacent to an edge of the circuit board substrate.

[0039] Optionally, at least one straight edge is parallel to an edge of the circuit board substrate.

[0040] Optionally, the straight edges parallel to the same edge of the circuit board substrate are collinear.

[0041] Optionally, the fifth pad and the sixth pad have the same area.

[0042] Optionally, the edge area includes a straight edge sub-area and a corner edge sub-area connecting two adjacent straight edge sub-areas, at least one of the fifth solder pad arrays is arranged in the corner edge sub-area, and at least one straight edge of the fifth solder pad arranged in the corner edge sub-area is at a 45° angle to the edge of the circuit board substrate.

[0043] Optionally, the edge region includes a peripheral region close to an edge of the circuit board substrate, and transition regions respectively connected to the peripheral region and the central region.

[0044] Optionally, the fifth pad includes a rectangular welding area and an arcuate welding area connected to the rectangular welding area;

[0045] And / or, the fifth pad includes a polygonal pad;

[0046] And / or, the fifth pad includes a pentagonal welding area and a bow-shaped welding area connected to the pentagonal welding area;

[0047] And / or, the fifth pad includes a triangular soldering area and an arcuate soldering area connected to the triangular soldering area.

[0048] Optionally, the sixth soldering pad includes a circular soldering area and / or a polygonal soldering area.

[0049] According to a sixth aspect of the present disclosure, an electronic device is provided, comprising: the chip and the circuit board.

[0050] The technical solutions provided by the embodiments of the present disclosure may have the following beneficial effects:

[0051] The present invention divides the chip substrate into a central region and an edge region, and divides the multiple solder pads into a first solder pad located in the edge region of the substrate and a second solder pad located in the central region of the substrate, so that the straight edges of the first solder pads can distribute the stress from the peripheral edges of the substrate. This structural arrangement strengthens the stress resistance of each solder pad located in different regions of the substrate, increases the structural strength of the solder pads themselves and the bonding strength between the solder pads and solder balls, prevents the solder pads and solder balls from breaking due to impact, falling, etc. during testing and use, and increases the service life of the chip, circuit board, circuit board assembly, and electronic equipment.

[0052] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0054] Figure 1 This is one of the schematic top view structural diagrams of a chip before soldering solder balls in an exemplary embodiment of the present disclosure;

[0055] Figure 2 This is a schematic diagram of the cross-sectional structure of a chip after soldering of solder balls in an exemplary embodiment of the present disclosure;

[0056] Figure 3 This is the second schematic diagram of a top view of a chip before soldering solder balls in an exemplary embodiment of the present disclosure;

[0057] Figure 4 is a schematic diagram of a partially enlarged structure of a corner edge sub-region in an exemplary embodiment of the present disclosure;

[0058] Figure 5 is a schematic diagram of a partially enlarged structure of a straight edge sub-region in an exemplary embodiment of the present disclosure;

[0059] Figure 6 This is the third schematic diagram of a top view of a chip before soldering solder balls in an exemplary embodiment of the present disclosure;

[0060] Figure 7 is a schematic cross-sectional structural diagram of a circuit board assembly in another exemplary embodiment of the present disclosure;

[0061] Figure 8 is a schematic cross-sectional structural diagram of an electronic device in an exemplary embodiment of the present disclosure;

[0062] Figure 9 This is the fourth schematic diagram of a top view of a chip before soldering solder balls in an exemplary embodiment of the present disclosure;

[0063] Figure 10 This is the fifth schematic diagram of a top view of a chip before soldering solder balls in an exemplary embodiment of the present disclosure;

[0064] Figure 11 This is the sixth schematic diagram of a top view of a chip before soldering solder balls in an exemplary embodiment of the present disclosure;

[0065] Figure 12 This is the seventh schematic diagram of a top view of a chip before soldering solder balls in an exemplary embodiment of the present disclosure;

[0066] Figure 13 This is the eighth schematic diagram of a top view of a chip before soldering solder balls in an exemplary embodiment of the present disclosure;

[0067] Figure 14 This is one of the schematic top view structural diagrams of a circuit board before soldering solder balls in an exemplary embodiment of the present disclosure;

[0068] Figure 15 This is the second schematic diagram of a top view of a circuit board before soldering solder balls in an exemplary embodiment of the present disclosure;

[0069] Figure 16 This is the third schematic diagram of a top view of a circuit board before soldering solder balls in an exemplary embodiment of the present disclosure;

[0070] Figure 17 This is a fourth schematic diagram of a top view of a circuit board before soldering solder balls in an exemplary embodiment of the present disclosure;

[0071] Figure 18 This is the fifth schematic diagram of a top view of a circuit board before soldering solder balls in an exemplary embodiment of the present disclosure;

[0072] Figure 19 FIG2 is a schematic cross-sectional structural diagram of an electronic device in another exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0073] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present disclosure. Rather, they are merely examples of apparatuses and methods consistent with certain aspects of the present disclosure, as detailed in the appended claims.

[0074] In related technologies, electronic devices such as mobile phones usually contain chips for realizing various functions. The electronic components and control circuits on the chips are packaged through solder pads and solder balls soldered to the solder pads.

[0075] However, as the market demands for chip functionality and the overall thinness of electronic devices increase, the chip packaging circuits within a unit size become more and more complex, and the chip pad size and pad spacing are gradually reduced to accommodate the packaging circuits. This leads to a decrease in the structural strength of the pad itself and the welding strength between the pad and the solder ball. This can easily cause solder joint breakage and damage to electronic devices during testing and use.

[0076] Figure 1 This is one of the schematic top view structural diagrams of a chip before soldering solder balls in an exemplary embodiment of the present disclosure; Figure 2 FIG. 1 is a schematic diagram of the cross-sectional structure of a chip after soldering solder balls in an exemplary embodiment of the present disclosure. Figure 1 、 Figure 2 As shown, the chip 1 includes a substrate 11 and a plurality of pads 12 disposed on the substrate 11, each of which has a solder ball 13 soldered thereto. The plurality of pads 12 include a first pad 121 and a second pad 122. The substrate 11 includes a central region 112 and an edge region 111 surrounding the central region 112. The first pad 121 is disposed in the edge region 111, and the second pad 122 is disposed in the central region 112. The first pad 121 includes a polygonal solder area 1211 and an arched solder area 1212 connected to the polygonal solder area 1211. The polygonal solder area 1211 is disposed between the arched solder area 1212 and the edge of the substrate 11.

[0077] In the above embodiment, the intersection line x of the polygonal welding area 1211 and the arcuate welding area 1212 is Figure 1 The middle dashed line indicates that the points on the intersection line x and the polygonal area formed by the intersection line x and each straight edge form a polygonal soldering area 1211. The polygonal soldering area 1211 is arranged between the arch soldering area 1212 and the edge of the substrate 11. This can mean that the first soldering pad 121 is located near any edge of the substrate 11, and the distance from any point on the polygonal soldering area 1211 of the first soldering pad 121 to the edge of the substrate 11 is less than the distance from any point on the arch soldering area 1212 of the same first soldering pad 121 to the edge of the substrate 11. For example Figure 1 As shown, multiple first pads 121 are provided near an edge 113 of the substrate 11 , and the distance d1 from any point on the polygonal soldering area 1211 of the first pad 121 to the edge 113 is smaller than the distance d2 from any point on the arched soldering area 1212 of the same first pad 121 to the edge 113 .

[0078] The multiple pads 12 on the chip 1 are divided into a first pad 121 disposed in the edge region 111 of the substrate 11 and a second pad 122 disposed in the central region 112 of the substrate 11. The polygonal solder area 1211 of the first pad 121 is disposed between the arcuate solder area 1212 and the edge of the substrate 11, so that the straight edges of the polygonal solder area 1211 can distribute stress from the outer edge of the substrate 11, while the curved edges of the arcuate solder area 1212 can decompose stress from within the substrate 11. This structural arrangement enhances the stress resistance of the pads 12 located in different regions of the substrate 11, increases the structural strength of the pads 12 themselves, and enhances the bonding strength between the pads 12 and the solder balls 13. This prevents the pads 12 and solder balls 13 from breaking due to stress concentration in the edge region 111 during testing and use, such as impact or dropping. This allows the chip 1 to achieve better test results even with increasing numbers of impact tests, thereby extending the service life of the chip 1, the circuit board assembly 2, and the electronic device 3.

[0079] According to the Griffith fracture criterion: the necessary condition for brittle fracture to occur under static conditions is that the energy released in the fracture zone is equal to the energy required to form the crack area. That is, if the energy generated by the external applied strain force is to produce cracks, the ability of the external strain force to produce must be greater than the energy required to form the crack area. When the crack area is approximated by a rectangle, it is found that: when the crack depth is the same, the longer the crack, the larger the crack area; the wider the width of the crack surface, the shorter the crack length, and the smaller the crack area when the crack depth is the same. That is, increasing the width of the surface where cracks may occur can effectively decompose the stress acting on the surface. The various straight edges of the polygonal solder area 1211 of the first solder pad 121 of the present disclosure extend the width of the surface where cracks may occur, thereby sharing the stress from the outer edge of the substrate 11, increasing the structural strength of the solder pad 12 itself and the welding strength between the solder pad 12 and the solder ball 13.

[0080] The side of the first solder pad 121 facing the central area 112 faces the stress generated on the first solder pad 121 by other solder pads 12 and the inside of the substrate 11 from all directions. The arc-shaped edge of the bow-shaped solder area 1212 can decompose the stress from the inside of the substrate 11 and relieve the stress from all directions, thereby having a better stress buffering effect.

[0081] In the above embodiment, the pad 12 can be a copper sheet provided on the substrate 11, and the pad 12 is electrically connected to the control circuit or electronic components of the chip 1. The polygonal solder area 1211 of the first pad 121 can be a polygonal solder area 1211 including multiple straight edges, such as a quadrilateral solder area, a pentagonal solder area, or a hexagonal solder area, and the bow-shaped solder area 1212 of the first pad 121 can be an arc formed by an arc line and any side of the polygonal solder area 1211. The first pad 121 can be formed by a combination of a polygonal solder area 1211 and a bow-shaped solder area 1212, or the first pad 121 can also include multiple polygonal solder areas 1211 and multiple bow-shaped solder areas 1212, and the present disclosure is not limited to this.

[0082] The second solder pad 122 can be a circular solder area, an elliptical solder area, or other solder area surrounded by arc lines, or the second solder pad 122 can be an irregularly shaped solder area surrounded by one or more curves, so as to achieve buffering of the internal stress of the chip 1 through one or more arc structures at the edge of the second solder pad 122.

[0083] It should be noted that the angle between the edges of adjacent substrates 11 is a right angle or other angles, and the substrate 11 can be a rectangular, polygonal, irregular shape or other structure, and the present disclosure does not limit this.

[0084] The following example illustrates the arrangement of the first and second pads 121 and 122 by taking the substrate 11 as a rectangle, the second pad 122 forming a circular pad, and the first pad 121 including a rectangular pad and an arched pad 1212 matching one side of the rectangular pad as an example.

[0085] In some embodiments, the edge region 111 of the substrate 11 may include a straight edge sub-region 1112 and a corner edge sub-region 1111 connecting two adjacent straight edge sub-regions 1112, and each of the straight edge sub-regions 1112 and the corner edge sub-region 1111 is provided with a first solder pad 121. By dividing the edge region 111 of the substrate 11 into the straight edge sub-region 1112 and the corner edge sub-region 1111, stress levels at different locations on the edge of the substrate 11 are differentiated. Providing the first solder pad 121 in each of the straight edge sub-region 1112 and the corner edge sub-region 1111 enables the first solder pad 121 provided in the straight edge sub-region 1112 and the corner edge sub-region 1111 to achieve a stress buffering effect that matches its location.

[0086] In one embodiment, if Figure 3As shown, the first pads 121 disposed in the straight edge sub-region 1112 and the corner edge sub-region 1111 are irregularly distributed, but the rectangular pads 121 are still disposed between the edge of the substrate 11 and the arched pads 1212. The arrangement of the first pads 121 in the straight edge sub-region 1112 and the corner edge sub-region 1111 is not limited, which can increase the utilization of the substrate 11 space by the first pads 121 and enhance the flexibility of the arrangement of the first pads 121. The rectangular pads disposed between the edge of the substrate 11 and the arched pads 1212 can use their straight sides facing the edge of the substrate 11 to distribute stress from the outer edge of the substrate 11. The curved sides of the arched pads 1212 facing the center region 112 of the substrate 11 can decompose stress from within the substrate 11, thereby enhancing the stress resistance of each pad 12 located in different regions of the substrate 11.

[0087] For example, the circular soldering areas of the second soldering pads 122 are irregularly distributed in the central region 112 of the substrate 11, and the first soldering pads 121 are irregularly distributed in the straight edge sub-region 1112 and the corner edge sub-region 1111. The sides of the rectangular soldering areas of the first soldering pads 121 located in the straight edge sub-region 1112 can be parallel or perpendicular to the edge of the substrate 11, and the curved sides of the arched soldering areas 1212 can mate with the first sides 1211a of the rectangular soldering areas parallel to the edge of the substrate 11. The two sets of opposite sides of the rectangular soldering areas of the first soldering pads 121 located in the corner edge sub-region 1111 can form 45° angles with the two corresponding edges of the substrate 11, respectively, and the curved sides of the arched soldering areas 1212 can mate with the second sides 1211b of the rectangular soldering areas facing the central region 112. Alternatively, the two pairs of opposite sides of the rectangular soldering area of the first solder pad 121 disposed in the corner edge sub-region 1111 can also be inclined at other angles relative to the two corresponding edges of the substrate 11, and can be arranged according to the direction in which stress may be generated along the edge of the substrate 11, and this disclosure is not limited to this. This structural arrangement can enhance the buffering effect of the first solder pad 121 against stress in various directions, and strengthen the ability of each solder pad 12 located in different areas of the substrate 11 to resist stress.

[0088] In another embodiment, Figure 4As shown, the dot-dash arrow n represents the first horizontal direction, and the dot-dash arrow m represents the first vertical direction. A plurality of first pads 121 are arrayed in the corner edge sub-region 1111, and the array direction of the first pads 121 arranged in the corner edge sub-region 1111 includes the first horizontal direction n and the first vertical direction m. The sides of the rectangular soldering area of the first pads 121 can be parallel to or perpendicular to the first vertical direction m. By arraying the first pads 121 in the corner edge sub-region 1111, the buffering capacity of the first pads 121 against stress is increased, so that each first pad 121 arrayed in the corner edge sub-region 1111 can buffer the edge stress with maximum efficiency against the stress from the corner edge sub-region 1111 of the substrate 11. The stress direction from the corner edge sub-region 1111 of the substrate 11 can be the same as the first vertical direction m, or be at a preset angle to the first vertical direction m.

[0089] Furthermore, the number of rows of the first solder pads 121 in the first vertical direction m can be greater than or equal to two rows, so as to achieve a buffering effect on edge stress by expanding the array area of the first solder pads 121, thereby avoiding the problem of the edge stress range being too large and exceeding the coverage area of the first solder pads 121.

[0090] Furthermore, the corner edge sub-region 1111 includes two adjacent edges of the substrate 11 and the angle formed by the two edges of the substrate 11. The first vertical direction m is parallel to the midline of the angle, and the first lateral direction n can be perpendicular to the first vertical direction m. By defining the direction of the first vertical direction m as the midline direction of the angle, the sides of the rectangular solder area of the first solder pad 121 provided in the corner edge sub-region 1111 can be parallel or perpendicular to the first vertical direction m, so that the first solder pad 121 can buffer edge stress with maximum efficiency.

[0091] In other embodiments, the first vertical direction m may also form other angles with the midline of the aforementioned angle so as to achieve the best buffering effect of the first pad 121 on edge stress, and the present disclosure is not limited thereto.

[0092] In yet another embodiment, Figure 5As shown, the dot-dash arrow r represents the second horizontal direction, and the dot-dash arrow o represents the second vertical direction. A plurality of first solder pads 121 are arrayed in the straight edge sub-area 1112, and the array direction of the first solder pads 121 arranged in the straight edge sub-area 1112 includes the second horizontal direction r and the second vertical direction o. The sides of the rectangular soldering area of the first solder pads 121 can be parallel to or perpendicular to the second vertical direction o. By arraying the first solder pads 121 in the straight edge sub-area 1112, the buffering capacity of the first solder pads 121 against stress is increased, so that each first solder pad 121 arrayed in the straight edge sub-area 1112 can buffer the edge stress with maximum efficiency against the stress from the edge of the substrate 11. The stress direction from the straight edge sub-area 1112 of the substrate 11 can be the same as the second vertical direction o, or form a preset angle with the second vertical direction o.

[0093] Furthermore, the second vertical direction o may be perpendicular to the edge of the substrate 11 in the straight edge sub-region 1112, and the second lateral direction r may be perpendicular to the second vertical direction o. The number of rows of the first pads 121 in the second vertical direction o may be greater than or equal to one row, so as to achieve a buffering effect on edge stress through the array area of the first pads 121.

[0094] In yet another embodiment, Figure 6 As shown, a plurality of first solder pads 121 are arranged in an array in a corner edge sub-region 1111. The array direction of the first solder pads 121 arranged in the corner edge sub-region 1111 includes a first horizontal direction n and a first vertical direction m. A plurality of first solder pads 121 are arranged in an array in a straight edge sub-region 1112. The array direction of the first solder pads 121 arranged in the straight edge sub-region 1112 includes a second horizontal direction r and a second vertical direction o. The corner edge sub-region 1111 includes two adjacent edges of the substrate 11 and an angle formed by the two edges of the substrate 11. The first vertical direction m is parallel to the midline of the angle. The second vertical direction o can be perpendicular to the edge of the substrate 11 in the straight edge sub-region 1112. The first horizontal direction n can be perpendicular to the first vertical direction m, and the second horizontal direction r can be perpendicular to the second vertical direction o. The sides of the rectangular soldering area of the first solder pad 121 disposed in the corner edge sub-region 1111 can be parallel or perpendicular to the first vertical direction m, and the sides of the rectangular soldering area of the first solder pad 121 disposed in the straight edge sub-region 1112 can be parallel or perpendicular to the second vertical direction o, so that the first solder pad 121 can buffer edge stress with maximum efficiency. The stress direction from the corner edge sub-region 1111 of the substrate 11 can be the same as the first vertical direction m, or form a preset angle with the first vertical direction m, and the stress direction from the straight edge sub-region 1112 of the substrate 11 can be the same as the second vertical direction o, or form a preset angle with the second vertical direction o.

[0095] It should be noted that the first lateral direction n and the first vertical direction m can be perpendicular to each other, or they can be inclined at a predetermined angle based on parameters such as the shape of the substrate 11 or the stress direction, and this disclosure is not limited to this. Similarly, the second lateral direction r and the second vertical direction o can be perpendicular to each other, or they can be inclined at a predetermined angle based on parameters such as the shape of the substrate 11 or the stress direction, and this disclosure is not limited to this either.

[0096] In some embodiments, a plurality of first solder pads 121 are arrayed in a corner edge sub-region 1111, and the array direction of the first solder pads 121 arranged in the corner edge sub-region 1111 includes a first lateral direction n and a first vertical direction m. The first solder pads 121 arranged in the corner edge sub-region 1111 include a first straight edge 1213 and a second straight edge 1214, wherein the first straight edge 1213 is parallel to the first lateral direction n, and the second straight edge 1214 is parallel to the first vertical direction m. That is, in the corner edge sub-region 1111, based on the first lateral direction n and the first vertical direction m of the array of the first solder pads 121, the first straight edge 1213 is parallel to the first lateral direction n, and the second straight edge 1214 is parallel to the first vertical direction m, so that each first solder pad 121 can obtain a straight edge for buffering stress in the array direction, thereby improving the stress buffering effect and structural strength of the first solder pads 121 arranged in the array.

[0097] Furthermore, the first pads 121 arranged in the array form a row in the first horizontal direction n, and the first straight edges 1213 of the first pads 121 in the same row can be on the same straight line, so that the first straight edges 1213 of the first pads 121 in the row have the same stress buffering effect. The first pads 121 arranged in the array form a column in the first vertical direction m, and the second straight edges 1214 in the same column can be on the same straight line, so that the second straight edges 1214 of the first pads 121 in the column have the same stress buffering effect.

[0098] In another embodiment, a plurality of first solder pads 121 are arranged in an array in a linear edge sub-region 1112. The array direction of the first solder pads 121 arranged in the linear edge sub-region 1112 includes a second lateral direction r and a second vertical direction o. The first solder pads 121 arranged in the linear edge sub-region 1112 include a third linear edge 1215 and a fourth linear edge 1216. The third linear edge 1215 is parallel to the second lateral direction r, and the fourth linear edge 1216 is parallel to the second vertical direction o. That is, in the linear edge sub-region 1112, based on the second lateral direction r and the second vertical direction o of the array of the first solder pads 121, the third linear edge 1215 is parallel to the second lateral direction r, and the fourth linear edge 1216 is parallel to the second vertical direction o. This allows each first solder pad 121 to have a linear edge in the array direction that buffers stress, thereby enhancing the stress buffering effect and structural strength of the arrayed first solder pads 121.

[0099] Furthermore, the first pads 121 arranged in the array form rows in the second horizontal direction r, and the third linear edges 1215 of the first pads 121 in the same row are aligned on the same straight line, so that the third linear edges 1215 of the first pads 121 in the row have the same stress buffering effect. The first pads 121 arranged in the array form columns in the second vertical direction o, and the fourth linear edges 1216 of the first pads 121 in the same column are aligned on the same straight line, so that the fourth linear edges 1216 of the first pads 121 in the column have the same stress buffering effect.

[0100] Furthermore, the second pad 122 can be a circular pad, an elliptical pad, or other pads surrounded by arcuate lines. Alternatively, the second pad 122 can be an irregularly shaped pad surrounded by one or more curved lines, so as to buffer the internal stress of the chip 1 through one or more curved structures along the edge of the second pad 122. For example, taking the second pad 122 as a circular pad with a diameter of 0.23 mm, multiple second pads 122 can be distributed in an array in the central region 112 of the substrate 11. Alternatively, the multiple second pads 122 can be irregularly distributed in the central region 112 of the substrate 11 based on the structure of the substrate 11 and the arrangement of the electronic components.

[0101] In the above embodiment, the areas of the first soldering pad 121 and the second soldering pad 122 are equal to ensure the same amount of soldering on the solder ball 13, thereby avoiding interference and influence on the soldering process caused by structural and shape improvements of the first soldering pad 121 and / or the second soldering pad 122.

[0102] It should be noted that the spacing between two adjacent pads 12 may be 0.35 mm, 0.4 mm, 0.5 mm, 0.8 mm, etc., wherein the spacing between two adjacent pads 12 may refer to the distance between the centers of the two adjacent pads 12 .

[0103] The present disclosure further proposes a circuit board assembly 2, such as Figure 7 As shown, the circuit board assembly 2 includes a mainboard 21 and the chip 1 described above, and the chip 1 is assembled on the mainboard 21. The mainboard 21 is provided with a third solder pad 22 and a fourth solder pad 23. The third solder pad 22 is electrically connected to the first solder pad 121 in a one-to-one correspondence, and the corresponding first solder pad 121 and the third solder pad 22 have the same structure. The fourth solder pad 23 is electrically connected to the second solder pad 122 in a one-to-one correspondence, and the corresponding second solder pad 122 and the fourth solder pad 23 have the same structure.

[0104] The multiple pads 12 on the chip 1 are divided into a first pad 121 disposed in the edge region 111 of the substrate 11 and a second pad 122 disposed in the central region 112 of the substrate 11. The polygonal solder area 1211 of the first pad 121 is disposed between the arcuate solder area 1212 and the edge of the substrate 11, so that the straight edges of the polygonal solder area 1211 can share the stress from the outer edge of the substrate 11, while the arcuate edges of the arcuate solder area 1212 can cooperate with the circular solder area of the second pad 122 to decompose the stress from within the substrate 11. This structural arrangement enhances the stress resistance of the pads 12 located in different regions of the substrate 11, increases the structural strength of the pads 12 themselves, and the welding strength between the pads 12 and the solder balls 13, preventing the pads 12 and solder balls 13 from breaking due to impact, falling, etc. during testing and use, thereby extending the service life of the chip 1 and the circuit board assembly 2.

[0105] Furthermore, the circuit board assembly 2 also includes a filling glue layer 24, which is arranged between the mainboard 21 and the chip 1; the filling glue layer 24 is respectively bonded to the first solder pad 121 and the third solder pad 22, and the filling glue layer 24 is respectively bonded to the second solder pad 122 and the fourth solder pad 23.

[0106] The present disclosure further proposes an electronic device 3, which includes: the above chip 1 or the above circuit board assembly 2. Figure 8 As shown, taking the electronic device 3 including the above-mentioned circuit board assembly 2 as an example, the circuit board assembly 2 includes a mainboard 21 and the above-mentioned chip 1 , and the chip 1 is assembled on the mainboard 21 .

[0107] The multiple pads 12 on the chip 1 are divided into a first pad 121 disposed in the edge region 111 of the substrate 11 and a second pad 122 disposed in the central region 112 of the substrate 11. The polygonal solder area 1211 of the first pad 121 is disposed between the arcuate solder area 1212 and the edge of the substrate 11, so that the straight edges of the polygonal solder area 1211 can share the stress from the outer edge of the substrate 11, while the arcuate edges of the arcuate solder area 1212 can cooperate with the circular solder area of the second pad 122 to decompose the stress from within the substrate 11. The above-mentioned structural arrangement strengthens the stress resistance of the pads 12 located in different regions of the substrate 11, increases the structural strength of the pads 12 themselves, and the welding strength between the pads 12 and the solder balls 13, prevents the pads 12 and the solder balls 13 from breaking due to impact, falling, etc. during testing and use, and improves the service life of the chip 1, the circuit board assembly 2, and the electronic device 3. In addition, the increased strength of the pads 12 of the chip 1 and the circuit board assembly 2 and the increased welding strength between the pads 12 and the solder balls 13 help to reduce the size of the pads 12 on the chip 1 and the spacing between the pads 12, thereby reducing the size of the chip 1 and improving the overall lightness of the electronic device 3.

[0108] It should be noted that the electronic device 3 may be a mobile phone, a tablet computer, a vehicle-mounted terminal or a medical terminal, etc., and the present disclosure does not limit this.

[0109] The present disclosure further proposes a chip, wherein the chip 4 includes a chip substrate 41 and a plurality of pads 42 arranged on the chip substrate 41. Figures 9-12 As shown, the plurality of pads 42 include a first pad 421 and a second pad 422. The chip substrate 41 includes a central region 411 and an edge region 412 surrounding the central region 411. The first pad 421 is disposed in the edge region 412, and the second pad 422 is disposed in the central region 411. The first pad 421 includes at least one straight edge adjacent to the chip substrate edge 413.

[0110] In the above embodiment, the straight edges of the first solder pads 421 can distribute stress from the outer edges of the chip substrate 41. This structural arrangement strengthens the stress resistance of the individual solder pads 42 located in different areas of the chip substrate 41, thereby increasing the structural strength of the solder pads 42 themselves. Each solder pad 42 can be soldered to a solder ball, so this structural arrangement can also strengthen the bond strength between the solder pads 42 and the solder ball, preventing the solder pads 42 and solder balls from breaking due to impact, dropping, etc. during testing and use, thereby increasing the service life of the chip 4.

[0111] In some embodiments, at least one straight edge is parallel to the chip substrate edge 413, thereby improving the stress resistance of the first pad 421 through the straight edges parallel to the chip substrate edge 413. Furthermore, the straight edges parallel to the same chip substrate edge 413 are collinear. These collinear straight edges share the stress from the chip substrate edge 413, thereby improving the strength of the pad 42 when the chip 4 is impacted or knocked, and improving the bonding strength between the pad 42 and the solder ball.

[0112] In some embodiments, the first solder pad 421 and the second solder pad 422 have the same area. This ensures that the same amount of solder balls are soldered to the solder pad 42, preventing interference and impact on the soldering process caused by structural or shape improvements to the first solder pad 421 and / or the second solder pad 422, and improving soldering stability. For example, this structural arrangement can reduce problems such as instability caused by empty solder joints or uneven soldering.

[0113] In some embodiments, the first pad 421 includes a rectangular soldering area 4211 and an arcuate soldering area connected to the rectangular soldering area 4211. The arcuate soldering area may be a semicircular soldering area or other arcuate shapes other than a semicircular shape, and the present disclosure does not limit this. Figure 9As shown, the first solder pad 421 includes a rectangular solder area 4211 and a semicircular solder area 4212 connected to the rectangular solder area 4211. The third side 4211a of the rectangular solder area 4211 is butted against the edge formed by the diameter of the semicircular solder area 4212, forming a semicircular and semi-square solder area shape. The third side 4211a of the rectangular solder area 4211 and the fourth side 4211b opposite the third side 4211a are parallel to one chip substrate edge 413 of the chip 4, and the fourth side 4211b is adjacent to the chip substrate edge 413 to share the stress acting on the chip substrate edge 413 on that side. The stress can be perpendicular to the chip substrate edge 413 on that side, or it can be at a predetermined angle to the chip substrate edge 413 on that side. The rectangular soldering area 4211 may further include a fifth side 4211c and a sixth side 4211d perpendicular to the third side 4211a. The fifth side 4211c and the sixth side 4211d are parallel to the other chip substrate edge 413 of the chip 4 to share the stress acting on the chip substrate edge 413 on that side. The stress may be perpendicular to the chip substrate edge 413 on that side or may be inclined at a predetermined angle to the chip substrate edge 413 on that side.

[0114] The semicircular and semi-square first pads 421 can be arranged around the edge region 412 of the chip substrate 41. That is, one or more rows of semicircular and semi-square first pads 421 are provided in the edge region 412 adjacent to each chip substrate edge 413 of the chip 4 to share the stress from the edge and enhance the strength of the system from all sides of the chip substrate 41. In addition, the structure of the first pads 421 in this embodiment is uniform, thereby facilitating processing and arrangement.

[0115] In another embodiment, Figure 10 As shown, the first pad 421 includes a rectangular pad 4211 and a semicircular pad 4212 connected to the rectangular pad 4211. The third side 4211a of the rectangular pad 4211 mates with the side formed by the diameter of the semicircular pad 4212, forming a pad shape that is semicircular and semisquare. The first pad 421 also includes a triangular pad 4213 and an arched pad 4214 connected to the triangular pad 4213. One side of the triangular pad 4213 mates with the chord of the arched pad 4214 to form a fan-shaped pad shape. The edge region 412 includes a straight edge sub-region 4121 and a corner edge sub-region 4122 connecting two adjacent straight edge sub-regions 4121.

[0116] The semicircular, semi-square first soldering area is disposed in the linear edge sub-region. A third side 4211a of the rectangular soldering area 4211 of the semicircular, semi-square first soldering area and a fourth side 4211b opposite the third side 4211a are parallel to one chip substrate edge 413 of the chip 4. The fourth side 4211b is adjacent to the chip substrate edge 413 to share the stress acting on that chip substrate edge 413. The stress can be perpendicular to the chip substrate edge 413 or at a predetermined angle to the chip substrate edge 413. The rectangular soldering area 4211 further includes a fifth side 4211c and a sixth side 4211d perpendicular to the third side 4211a. The fifth side 4211c and the sixth side 4211d are parallel to the other chip substrate edge 413 of the chip 4 to share the stress acting on that chip substrate edge 413. The stress may be perpendicular to the chip substrate edge 413 or may be at a preset inclination angle to the chip substrate edge 413 .

[0117] The fan-shaped first soldering area is disposed in the corner edge sub-region 4122. The triangular soldering area 4213 may be a right-angled triangular soldering area 4213. The two right-angled sides of the right-angled triangular soldering area 4213 are respectively parallel to the two adjacent chip substrate edges 413 to share the stress acting on the corner edge sub-region 4122. The stress may be perpendicular to either of the two adjacent chip substrate edges 413 or may be inclined at a predetermined angle to either of the two adjacent chip substrate edges 413.

[0118] In some embodiments, edge region 412 includes a straight edge sub-region 4121 and a corner edge sub-region 4122 connecting two adjacent straight edge sub-regions 4121. At least one first solder pad 421 is arranged in an array in straight edge sub-region 4121, with at least one straight edge of the first solder pad 421 arranged in straight edge sub-region 4121 being parallel to chip substrate edge 413. At least one first solder pad 421 is arranged in an array in corner edge sub-region 4122, with at least one straight edge of the first solder pad 421 arranged in corner edge sub-region 4122 forming a 45° angle with chip substrate edge 413. The straight edges parallel to chip substrate edge 413 can share stress perpendicular to chip substrate edge 413, while the straight edges forming a 45° angle with chip substrate edge 413 can share stress in corner edge sub-region 4122. This improves the strength of solder pad 42 against impacts and knocks, as well as the bond strength between solder pad 42 and solder balls.

[0119] In one embodiment, the first solder pad 421 includes a rectangular solder area 4211 and a semicircular solder area 4212 connected to the rectangular solder area 4211. The third side 4211a of the rectangular solder area 4211 is aligned with the side formed by the diameter of the semicircular solder area 4212, forming a semicircular and semi-square solder area shape. The first solder pad 421 also includes a pentagonal solder area 4215 and an arched solder area 4216 connected to the pentagonal solder area 4215. The seventh side 4215a of the pentagonal solder area 4215 is aligned with the chord of the arched solder area 4216. Two sides of the pentagonal solder area 4215 are respectively at a 45° angle to the adjacent chip substrate edge 413, and the other two sides of the pentagonal solder area 4215 can be respectively parallel to the adjacent chip substrate edge 413.

[0120] In some embodiments, as Figure 11 As shown, the first pads 421 including the pentagonal soldering areas 4215 can be distributed in the corner edge sub-region 4122. The angled edges of the pentagonal soldering areas 4215 can buffer stress in various directions acting on the corner edge sub-region 4122, achieving a good stress distribution effect and helping to enhance the overall strength of the first pads 421. The first pads 421 including the pentagonal soldering areas 4215 can be arranged in a row at a 45° angle to the adjacent chip substrate edge 413. A row can include two, three, or more first pads 421. Semi-circular and semi-square first soldering areas can be distributed in the straight edge sub-region 4121. The straight edges of the rectangular soldering areas 4211 can buffer stress acting on the straight edge sub-region 4121.

[0121] In other embodiments, the edge region 412 may include a peripheral region 4123 close to the chip substrate edge 413, and a transition region 4124 connected to the peripheral region 4123 and the central region 411. Figure 12 As shown, taking the corner edge sub-region 4122 of the edge region 412 as an example, the corner edge sub-region 4122 includes a peripheral region 4123 close to the chip substrate edge 413, and a transition region 4124 connected to the peripheral region 4123 and the central region 411 respectively. The first solder pads 421 including the pentagonal solder area 4215 and the semicircular and semi-square first solder pads 421 can be distributed in the peripheral region 4123 and the transition region 4124 of the corner edge sub-region 4122. The first solder pads 421 can be arranged in two, three or more rows along a direction at a 45° angle to the adjacent chip substrate edge 413, and each row can include two, three or more first solder pads 421. Figure 12As shown, the first pads 421 are arranged in three rows along a 45° angle with the adjacent chip substrate edge 413. The first pads 421 including pentagonal pads 4215 can be located at both ends of each row, and the semicircular and semi-square first pads 421 can be located in the middle of each row. This arrangement of the straight edges of the first pads 421 enhances the stress buffering effect on the corner edge sub-region. The semicircular and semi-square first pads 421 can be distributed in the straight edge sub-region 4121 to buffer the stress acting on the straight edge sub-region 4121 through the straight edges of the rectangular pads 4211.

[0122] In some other embodiments, the first pad 421 includes a polygonal pad. Figure 13 As shown, the first pad 421 includes a rectangular soldering area 4217, a straight side of which is parallel to a chip substrate edge 413 of the chip 4 to share the stress acting on the chip substrate edge 413. The stress can be perpendicular to the chip substrate edge 413 or at a predetermined angle to the chip substrate edge 413.

[0123] The rectangular pads 4217 can be arranged around the edge region 412 of the chip substrate 41. That is, one or more rows of rectangular pads 4217 are provided in the edge region 412 adjacent to each chip substrate edge 413 of the chip 4 to share the stress from the edge and enhance the strength of the system from all sides of the chip substrate 41. In addition, the first pads 421 in this embodiment have the same structure, thus facilitating processing and arrangement.

[0124] In the above embodiment, the second pad 422 can be a circular pad, an elliptical pad, or other pads surrounded by arcuate lines. Alternatively, the second pad 422 can be an irregularly shaped pad surrounded by one or more curved lines, so that the internal stress of the chip 4 is buffered by one or more curved structures along the edge of the second pad 422. For example, taking the second pad 422 as a circular pad with a diameter of 0.23 mm, multiple second pads 422 can be distributed in an array in the central region 411 of the chip substrate 41. Alternatively, the multiple second pads 422 can be irregularly distributed in the central region 411 of the chip substrate 41 based on the structure of the chip substrate 41 and the arrangement of the electronic components.

[0125] In other embodiments, the second pad 422 may also be a polygonal pad. For example, the second pad 422 may be Figure 13 Alternatively, the second pad 422 is a pad formed by a polygonal pad and a circular pad, or the second pad 422 is a pad formed by a polygonal pad and an arc line, which is not limited in the present disclosure.

[0126] It should be noted that the spacing between two adjacent pads 42 may be 0.35 mm, 0.4 mm, 0.5 mm, 0.8 mm, etc., wherein the spacing between two adjacent pads 42 may refer to the distance between the centers of the two adjacent pads 42 .

[0127] The present disclosure further provides a circuit board 5, comprising a circuit board substrate 51 and a plurality of solder pads 52 disposed on the circuit board substrate 51. The plurality of solder pads 52 include a fifth solder pad 521 and a sixth solder pad 522. The circuit board substrate 51 includes a central region 511 and an edge region 512 surrounding the central region 511. The fifth solder pad 521 is disposed in the edge region 512, and the sixth solder pad 522 is disposed in the central region 511. The fifth solder pad 521 includes at least one straight edge adjacent to the circuit board substrate edge 513.

[0128] In the above embodiment, the straight edges of the fifth solder pads 521 can distribute stress from the outer edges of the circuit board substrate 51. This structural arrangement enhances the stress resistance of the individual solder pads 52 located in different areas of the circuit board substrate 51, increasing the structural strength of the solder pads 52 themselves. Each solder pad 52 can be soldered with a solder ball, so this structural arrangement also strengthens the bond strength between the solder pads 52 and the solder ball, preventing breakage of the solder pads 52 and solder balls due to impact, dropping, etc. during testing and use, thereby extending the service life of the circuit board 5.

[0129] In some embodiments, at least one straight edge is parallel to the circuit board substrate edge 513, thereby enhancing the stress resistance of the fifth solder pad 521 through the straight edge parallel to the circuit board substrate edge 513. Furthermore, the straight edges parallel to the circuit board substrate edge 513 are collinear. These collinear straight edges share the stress from the circuit board substrate edge 513, thereby enhancing the strength of the solder pad 52 when the circuit board 5 is impacted or knocked, and enhancing the soldering strength between the solder pad 52 and the solder ball.

[0130] In some embodiments, the fifth solder pad 521 and the sixth solder pad 522 have the same area. This ensures that the same amount of solder balls are soldered to the solder pads 52, preventing interference and impact on the soldering process caused by structural or shape improvements to the fifth solder pad 521 and / or the sixth solder pad 522, and improving soldering stability. For example, this structural arrangement can reduce problems such as unstable soldering caused by empty soldering or uneven soldering.

[0131] In one embodiment, the fifth pad 521 includes a rectangular soldering area 5211 and an arcuate soldering area connected to the rectangular soldering area 5211. The arcuate soldering area may be a semicircular soldering area or other arcuate shapes other than a semicircular shape, and the present disclosure does not limit this. Figure 14As shown, the fifth solder pad 521 includes a rectangular solder area 5211 and a semicircular solder area 5212 connected to the rectangular solder area 5211. The third side 5211a of the rectangular solder area 5211 is aligned with the side formed by the diameter of the semicircular solder area 5212, forming a semicircular and semi-square solder area shape. The third side 5211a of the rectangular solder area 5211 and the fourth side 5211b opposite the third side 5211a are parallel to one of the chip's circuit board substrate edges 513, and the fourth side 5211b is adjacent to the circuit board substrate edge 513 to share the stress acting on the circuit board substrate edge 513 on that side. The stress can be perpendicular to the circuit board substrate edge 513 on that side, or it can be at a predetermined angle to the circuit board substrate edge 513 on that side. The rectangular soldering area 5211 may further include a fifth side 5211c and a sixth side 5211d perpendicular to the third side 5211a. The fifth side 5211c and the sixth side 5211d are parallel to the other circuit board substrate edge 513 of the chip to share the stress acting on the other circuit board substrate edge 513. The stress may be perpendicular to the other circuit board substrate edge 513 or may be inclined at a predetermined angle to the other circuit board substrate edge 513.

[0132] The semicircular and semi-square fifth solder pads 521 can be arranged around the edge region 512 of the chip circuit board substrate 51. That is, one or more rows of semicircular and semi-square fifth solder pads 521 are provided in the edge region 512 adjacent to each edge 513 of the chip circuit board substrate. This distributes stress from these edges and enhances the system strength from all sides of the circuit board substrate 51. Furthermore, the structure of the fifth solder pads 521 in this embodiment is uniform, thus facilitating processing and layout.

[0133] In another embodiment, Figure 15 As shown, the fifth pad 521 includes a rectangular pad 5211 and a semicircular pad 5212 connected to the rectangular pad 5211. The third side 5211a of the rectangular pad 5211 abuts against the edge formed by the diameter of the semicircular pad 5212, forming a semicircular, semi-square pad shape. The fifth pad 521 also includes a triangular pad 5213 and an arched pad 5214 connected to the triangular pad 5213. One side of the triangular pad 5213 abuts against the chord of the arched pad 5214, forming a fan-shaped pad shape. The edge region 512 includes a straight edge sub-region 5121 and a corner edge sub-region 5122 connecting two adjacent straight edge sub-regions 5121.

[0134] The semicircular, semi-square first soldering area is located in the linear edge sub-region. The third side 5211a of the rectangular soldering area 5211 of the semicircular, semi-square first soldering area and the fourth side 5211b opposite the third side 5211a are parallel to one of the chip's circuit board substrate edges 513. The fourth side 5211b is adjacent to the circuit board substrate edge 513 to share the stress acting on that side of the circuit board substrate edge 513. The stress can be perpendicular to the circuit board substrate edge 513 or at a predetermined angle to the circuit board substrate edge 513. The rectangular soldering area 5211 further includes a fifth side 5211c and a sixth side 5211d perpendicular to the third side 5211a. The fifth side 5211c and the sixth side 5211d are parallel to the other circuit board substrate edge 513 of the chip to share the stress acting on that side of the circuit board substrate edge 513. The stress may be perpendicular to the side circuit board substrate edge 513 , or may be at a preset inclination angle to the side circuit board substrate edge 513 .

[0135] The fan-shaped first soldering area is disposed in the corner edge sub-region 5122. The triangular soldering area 5213 may be a right-angled triangular soldering area 5213. The two right-angled sides of the right-angled triangular soldering area 5213 are respectively parallel to the two adjacent circuit board substrate edges 513 to share the stress acting on the corner edge sub-region 5122. The stress may be perpendicular to either of the two adjacent circuit board substrate edges 513 or may be inclined at a predetermined angle to either of the two adjacent circuit board substrate edges 513.

[0136] In some embodiments, the edge region 512 includes a straight edge sub-region 5121 and a corner edge sub-region 5122 connecting two adjacent straight edge sub-regions 5121. At least one fifth solder pad 521 is arranged in an array in the straight edge sub-region 5121, with at least one straight edge of the fifth solder pad 521 arranged in the straight edge sub-region 5121 being parallel to the circuit board substrate edge 513. At least one fifth solder pad 521 is arranged in an array in the corner edge sub-region 5122, with at least one straight edge of the fifth solder pad 521 arranged in the corner edge sub-region 5122 forming a 45° angle with the circuit board substrate edge 513. The straight edges parallel to the circuit board substrate edge 513 can share stress perpendicular to the circuit board substrate edge 513, while the straight edges forming a 45° angle with the circuit board substrate edge 513 can share stress in the corner edge sub-region 5122. This improves the strength of the solder pad 52 against impacts and knocks, as well as the solder joint strength between the solder pad 52 and the solder ball.

[0137] In one embodiment, the fifth solder pad 521 includes a rectangular solder area 5211 and a semicircular solder area 5212 connected to the rectangular solder area 5211. The third side 5211a of the rectangular solder area 5211 is aligned with the side formed by the diameter of the semicircular solder area 5212, forming a semicircular and semi-square solder area shape. The fifth solder pad 521 also includes a pentagonal solder area 5215 and an arched solder area 5216 connected to the pentagonal solder area 5215. The seventh side 5215a of the pentagonal solder area 5215 is aligned with the chord of the arched solder area 5216. Two sides of the pentagonal solder area 5215 are respectively at a 45° angle to the adjacent circuit board substrate edge 513, and the other two sides of the pentagonal solder area 5215 can be respectively parallel to the adjacent circuit board substrate edge 513.

[0138] In some embodiments, as Figure 16 As shown, the fifth pads 521 including the pentagonal soldering areas 5215 can be distributed in the corner edge sub-region 5122. The angled edges of the pentagonal soldering areas 5215 can buffer stress in various directions acting on the corner edge sub-region 5122, achieving a good stress distribution effect and helping to enhance the overall strength of the fifth pads 521. The fifth pads 521 including the pentagonal soldering areas 5215 can be arranged in a row at a 45° angle to the adjacent circuit board substrate edge 513. A row can include two, three, or more fifth pads 521. The semi-circular and semi-square first soldering areas can be distributed in the straight edge sub-region 5121. The straight edges of the rectangular soldering areas 5211 can buffer stress acting on the straight edge sub-region 5121.

[0139] In other embodiments, the edge region 512 may include a peripheral region 5123 close to the edge 513 of the circuit board substrate, and a transition region 5124 connected to the peripheral region 5123 and the central region 511. Figure 12 As shown, taking the corner edge sub-region 5122 of the edge region 512 as an example, the corner edge sub-region 5122 includes a peripheral region 5123 close to the edge 513 of the circuit board substrate, and a transition region 5124 connected to the peripheral region 5123 and the central region 511. Figure 17As shown, the aforementioned fifth solder pads 521 including pentagonal solder areas 5215 and semicircular / square fifth solder pads 521 can be distributed in the peripheral area 5123 and transition area 5124 of the corner edge sub-region 5122. The fifth solder pads 521 can be arranged in two, three, or more rows along a 45° angle with the adjacent circuit board substrate edge 513, with each row containing two, three, or more fifth solder pads 521. The fifth solder pads 521 including pentagonal solder areas 5215 can be located at both ends of each row, while the semicircular / square fifth solder pads 521 can be located in the middle of each row. This arrangement of the straight edges of the fifth solder pads 521 enhances the stress buffering effect on the corner edge sub-region. The semicircular / square fifth solder pads 521 can be distributed in the straight edge sub-region 5121, so that the straight edges of the rectangular solder areas 5211 can buffer the stress acting on the straight edge sub-region 5121.

[0140] In some other embodiments, the fifth pad 521 includes a polygonal pad. Figure 18 As shown, the fifth solder pad 521 includes a rectangular solder area 5217, a straight side of which is parallel to a circuit board substrate edge 513 of the circuit board 4 to share the stress acting on the circuit board substrate edge 513 on that side. The stress can be perpendicular to the circuit board substrate edge 513 on that side, or it can be inclined at a predetermined angle to the circuit board substrate edge 513 on that side.

[0141] The rectangular soldering areas 5217 can be arranged around the edge region 512 of the circuit board substrate 51. That is, one or more rows of rectangular soldering areas 5217 are provided in the edge region 512 adjacent to each edge 513 of the circuit board 5 to distribute stress from the edge and enhance the strength of the system from all sides of the circuit board substrate 51. Furthermore, the fifth soldering pads 521 in this embodiment have the same structure, thus facilitating processing and layout.

[0142] In the above embodiment, the sixth solder pad 522 can be a circular solder area, an elliptical solder area, or other solder area surrounded by arcuate lines. Alternatively, the sixth solder pad 522 can be an irregularly shaped solder area surrounded by one or more curved lines, so as to buffer the internal stress of the chip through one or more curved structures at the edge of the sixth solder pad 522. Taking the sixth solder pad 522 as a circular solder area with a diameter of 0.23 mm as an example, multiple sixth solder pads 522 can be distributed in an array in the central area 511 of the circuit board substrate 51. Alternatively, the multiple sixth solder pads 522 can be irregularly distributed in the central area 511 of the circuit board substrate 51 based on the structure of the circuit board substrate 51 and the arrangement of the electronic components.

[0143] In other embodiments, the sixth pad 522 may also be a polygonal pad. For example, the sixth pad may be Figure 18Alternatively, the sixth pad 522 is a pad formed by a polygonal pad and a circular pad, or the sixth pad 522 is a pad formed by a polygonal pad and an arc line, which is not limited in the present disclosure.

[0144] It should be noted that the spacing between two adjacent pads 52 may be 0.35 mm, 0.4 mm, 0.5 mm, 0.8 mm, etc., wherein the spacing between two adjacent pads 52 may refer to the distance between the centers of the two adjacent pads 52 .

[0145] The present disclosure further proposes an electronic device 6, such as Figure 19 As shown, the electronic device 6 includes: the aforementioned chip 4 and the aforementioned circuit board 5, wherein the chip 4 is assembled on the circuit board 5. The circuit board 5 is provided with a fifth pad 521 and a sixth pad 522. The fifth pad 521 is electrically connected to the first pad 421 in a one-to-one correspondence, and the sixth pad 522 is electrically connected to the second pad 422 in a one-to-one correspondence.

[0146] The chip substrate 41 of the chip 4 is divided into a central region 411 and an edge region 412, and the plurality of pads 42 are divided into a first pad 421 disposed in the edge region 412 of the chip 4 substrate and a second pad 422 disposed in the central region 411 of the chip 4 substrate, so that the straight edges of the first pads 421 can distribute stress from the peripheral edges of the chip substrate 41. Similarly, the circuit board substrate 51 of the circuit board 5 can also be divided into a central region 511 and an edge region 512, and the plurality of pads 52 are divided into a fifth pad 521 disposed in the edge region 512 of the circuit board substrate 51 and a sixth pad 522 disposed in the central region 511 of the circuit board substrate 51, so that the straight edges of the fifth pads 521 can distribute stress from the peripheral edges of the circuit board substrate 51. The above-described structural arrangement strengthens the stress resistance of the individual pads 42, 52 located in different areas of the substrates of chip 4 and circuit board 5, increases the structural strength of the pads 42, 52 themselves, and the bonding strength between the pads 42, 52 and the solder balls. This prevents the pads and solder balls from breaking due to impact, dropping, and the like during testing and use, thereby extending the service life of chip 4, circuit board 5, and the electronic device. Furthermore, the increased pad strength of chip 4 and circuit board 5, as well as the bonding strength between the pads and the solder balls, helps reduce the size and spacing of the pads on chip 4 and circuit board 5, thereby reducing the size of chip 4 and improving the overall thinness of electronic device 6.

[0147] It should be noted that the electronic device 6 may be a mobile phone, a tablet computer, a vehicle-mounted terminal or a medical terminal, etc., and the present disclosure does not limit this.

[0148] Those skilled in the art will readily recognize other embodiments of the present disclosure after considering the specification and practicing the technical solutions disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the following claims.

[0149] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes can be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A chip, characterized in that: The chip includes a substrate and a plurality of pads arranged on the substrate, each of the pads being soldered with a solder ball; The plurality of pads include a first pad and a second pad; the substrate includes a central area and an edge area surrounding the central area, the first pad is arranged in the edge area, and the second pad is arranged in the central area; The first pad includes a polygonal pad and an arched pad connected to the polygonal pad, wherein the polygonal pad is disposed between the arched pad and the edge of the substrate; the edge region includes a straight edge sub-region and a corner edge sub-region connecting two adjacent straight edge sub-regions; the first pad located within the straight edge sub-region includes a rectangular pad and an arched pad connected to the rectangular pad; the first pad located within the corner edge sub-region includes: A pentagonal welding area and an arcuate welding area connected to the pentagonal welding area; Or, a triangular welding area and an arcuate welding area connected to the triangular welding area.

2. The chip according to claim 1, characterized in that A plurality of first pad arrays are arranged in the corner edge sub-region, and an array direction of the first pads arranged in the corner edge sub-region includes a first horizontal direction and a first vertical direction.

3. The chip according to claim 2, characterized in that The number of rows of the first solder pads in the first vertical direction is greater than or equal to two.

4. The chip according to claim 2, characterized in that The corner edge sub-region includes two adjacent substrate edges and an angle formed by the two substrate edges, and the first vertical direction is parallel to a midline of the angle.

5. The chip according to claim 2, characterized in that The first pad disposed in the corner edge sub-region includes a first straight side and a second straight side, the first straight side is parallel to the first horizontal direction, and the second straight side is parallel to the first vertical direction.

6. The chip according to claim 1, characterized in that A plurality of first pad arrays are arranged in the straight edge sub-region, and the array directions of the first pads arranged in the straight edge sub-region include a second horizontal direction and a second vertical direction; The first pad disposed in the straight edge sub-region includes a third straight side and a fourth straight side, the third straight side is parallel to the second horizontal direction, and the fourth straight side is parallel to the second vertical direction.

7. The chip according to claim 1, characterized in that The second pad includes a circular pad area.

8. The chip according to claim 1, characterized in that The first pad and the second pad have the same area.

9. A circuit board assembly, characterized in that: comprising a mainboard and the chip according to any one of claims 1 to 8, wherein the chip is assembled on the mainboard; The mainboard is provided with a third solder pad and a fourth solder pad, the third solder pad is conductively connected to the first solder pad in a one-to-one correspondence, and the corresponding first solder pad and the third solder pad have the same structure; the fourth solder pad is conductively connected to the second solder pad in a one-to-one correspondence, and the corresponding second solder pad and the fourth solder pad have the same structure.

10. The circuit board assembly according to claim 9, wherein: It also includes a filling glue layer, which is arranged between the mainboard and the chip; the filling glue layer is respectively bonded to the first solder pad and the third solder pad, and the filling glue layer is respectively bonded to the second solder pad and the fourth solder pad.

11. An electronic device, characterized in that: include: The chip according to any one of claims 1 to 8; Or, the circuit board assembly as claimed in claim 9 or claim 10.

12. A chip, characterized in that: The chip includes a chip substrate and a plurality of pads arranged on the chip substrate; The plurality of pads include a first pad and a second pad; the chip substrate includes a central area and an edge area surrounding the central area, the first pad is arranged in the edge area, and the second pad is arranged in the central area; The first pad includes at least one straight edge adjacent to the edge of the chip substrate; the edge region includes a straight edge sub-region and a corner edge sub-region connecting two adjacent straight edge sub-regions; the first pad located in the straight edge sub-region includes a rectangular solder area and an arched solder area connected to the rectangular solder area; the first pad located in the corner edge sub-region includes: A pentagonal welding area and an arcuate welding area connected to the pentagonal welding area; Or, a triangular welding area and an arcuate welding area connected to the triangular welding area.

13. The chip according to claim 12, characterized in that At least one straight edge is parallel to the chip substrate edge.

14. The chip according to claim 13, characterized in that The straight edges parallel to the same edge of the chip substrate are collinear.

15. The chip according to claim 12, characterized in that The first pad and the second pad have the same area.

16. The chip according to claim 12, characterized in that At least one of the first pad arrays is disposed in the corner edge sub-region, and at least one straight edge of the first pad disposed in the corner edge sub-region forms an angle of 45° with the edge of the chip substrate.

17. The chip according to claim 12, characterized in that The edge region includes a peripheral region close to the edge of the chip substrate and transition regions respectively connected to the peripheral region and the central region.

18. The chip according to claim 12, characterized in that The second pad includes a circular pad area and / or a polygonal pad area.

19. A circuit board, characterized in that: The circuit board includes a circuit board substrate and a plurality of pads arranged on the circuit board substrate; The plurality of pads include a fifth pad and a sixth pad; the circuit board substrate includes a central area and an edge area surrounding the central area, the fifth pad is arranged in the edge area, and the sixth pad is arranged in the central area; The fifth pad includes at least one straight edge adjacent to the edge of the circuit board substrate; the edge region includes a straight edge sub-region and a corner edge sub-region connecting two adjacent straight edge sub-regions; the fifth pad located within the straight edge sub-region includes a rectangular soldering area and an arched soldering area connected to the rectangular soldering area; The fifth pad located in the corner edge sub-region includes: A pentagonal welding area and an arcuate welding area connected to the pentagonal welding area; Or, a triangular welding area and an arcuate welding area connected to the triangular welding area.

20. The circuit board according to claim 19, wherein: At least one straight edge is parallel to the edge of the circuit board substrate.

21. The circuit board according to claim 20, wherein: The straight edges parallel to the same edge of the circuit board substrate are collinear.

22. The circuit board according to claim 19, wherein: The fifth pad and the sixth pad have the same area.

23. The circuit board according to claim 19, wherein: At least one of the fifth pad arrays is disposed in the corner edge sub-region, and at least one straight edge of the fifth pad disposed in the corner edge sub-region forms an angle of 45° with the edge of the circuit board substrate.

24. The circuit board according to claim 19, wherein The edge region includes a peripheral region close to the edge of the circuit board substrate and transition regions respectively connected to the peripheral region and the central region.

25. The circuit board according to claim 19, wherein The sixth pad includes a circular pad and / or a polygonal pad.

26. An electronic device, characterized in that: include: The chip according to any one of claims 12 to 18; Or, a circuit board as described in any one of claims 19-25.

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