A method for fabricating high-voltage VDMOS by using silicon-silicon bonding process

Abstract

The application relates to a method for manufacturing a high-voltage VDMOS by adopting a silicon-silicon bonding process, which comprises the following steps: preparing a support substrate and a bonding substrate; carrying out silicon-silicon bonding on the support substrate and the bonding substrate, and carrying out high-temperature annealing solidification; carrying out etching treatment on the edge chamfering of the support substrate and the bonding substrate after bonding; thinning the bonding substrate to a required thickness; and polishing the bonding substrate. The method for manufacturing a high-voltage VDMOS by adopting the silicon-silicon bonding process of the application uses the silicon-silicon bonding technology, uses conventional CZ silicon substrate materials with different resistivities to bond with each other to prepare a silicon-silicon bonded wafer, replaces a current thick-film epitaxial wafer, obtains a high-quality silicon substrate wafer satisfying customer requirements, improves production efficiency and reduces production cost, and the transition region of the obtained high-voltage VDMOS device is obviously narrowed, and the consistency of product parameters is better.

Description

Technical Field

[0001] This invention relates to the field of semiconductor chip manufacturing technology, and in particular to a method for fabricating high-voltage VDMOS using silicon-silicon bonding technology. Background Technology

[0002] Conventional semiconductor manufacturing uses various processes to form semiconductor devices on a substrate. This substrate can be a small, thin, circular wafer of a semiconducting material such as silicon. The semiconductor device formed on the substrate can be a discrete device or an integrated circuit. For example, a semiconductor device can consist of a single discrete power transistor, or it can consist of many transistors electrically coupled together to form an integrated circuit, or other electronic components such as resistors and capacitors. After the semiconductor device is formed, the wafer is tested and diced to separate the individual dies within the wafer.

[0003] High-voltage VDMOS is gradually evolving towards higher voltage withstand and lower power consumption, currently achieved through thick epitaxy. However, for high-resistivity epitaxy, when the epitaxial thickness reaches 100µm, the fabrication process becomes lengthy, exceeding 2.5 hours per furnace, resulting in low production efficiency, high fabrication costs, and problems such as numerous defects, poor resistivity consistency, severe self-doping, and a wide transition region. These issues negatively impact product performance and increase costs. Summary of the Invention

[0004] To address the aforementioned technical problems, this application is proposed. Embodiments of this application provide a method for fabricating high-voltage VDMOS using silicon-silicon bonding technology. By replacing epitaxial growth with silicon-silicon bonding, product performance is effectively improved and costs are reduced.

[0005] According to one aspect of this application, a method for fabricating a high-voltage VDMOS using a silicon-silicon bonding process is provided, comprising: preparing a support substrate and a bonding substrate; bonding the support substrate and the bonding substrate to silicon-silicon bonding and performing high-temperature annealing and curing, wherein the bonding substrate is located on the support substrate; etching the chamfered edges of the bonded support substrate and the bonding substrate; thinning the bonding substrate to a required thickness; polishing the bonding substrate; fabricating a device P+ layer, an active region, a polysilicon gate, and a device N+ layer on the bonding substrate; creating contact holes on the device N+ layer using an etching process; fabricating a front metal layer covering the contact holes, the device N+ layer, and the polysilicon gate; and fabricating a back metal layer.

[0006] Furthermore, when bonding the support substrate and the bonding substrate, a uniform oxide layer is formed on the surface of the support substrate and the bonding substrate as a medium layer through a cleaning process.

[0007] Furthermore, the thickness of the medium layer is less than 5 angstroms.

[0008] Furthermore, the resistivity of the bonding substrate is >15 ohm·cm.

[0009] Furthermore, the resistivity of the supporting substrate is 0.008~0.06 ohm·cm.

[0010] Furthermore, the high-temperature annealing and curing is carried out at 900~1200℃ for 20~50 minutes.

[0011] Furthermore, the bonding substrate has a thickness of 50~250µm and a thickness uniformity of 2µm.

[0012] Furthermore, the polysilicon gate has a thickness of 6000~10000 angstroms and a resistivity of 6~15 ohm / sqr.

[0013] Furthermore, the front metal layer is made of aluminum and has a thickness of 3~5µm.

[0014] Furthermore, the back metal layer is made of TiNiAg with a total thickness of 8000~15000 angstroms.

[0015] Compared with the prior art, the method for fabricating high-voltage VDMOS using silicon-silicon bonding process according to the embodiments of this application uses silicon-silicon bonding technology to bond conventional CZ silicon substrate materials with different resistivities to each other to prepare silicon-silicon bonded wafers, replacing the current thick film epitaxial wafers. This results in high-quality silicon substrate wafers that meet customer requirements, improves production efficiency and reduces production costs. The transition region of the obtained high-voltage VDMOS device is significantly narrower, and the consistency of product parameters is better. Attached Figure Description

[0016] The above and other objects, features, and advantages of this application will become more apparent from the more detailed description of the embodiments of this application in conjunction with the accompanying drawings. The drawings are provided to further illustrate the embodiments of this application and form part of the specification. They are used together with the embodiments of this application to explain this application and do not constitute a limitation thereof. In the drawings, the same reference numerals generally represent the same components or steps.

[0017] Figure 1 This is a structural diagram of the high-voltage VDMOS of the present invention;

[0018] Figure 2 This is a flowchart of the high-voltage VDMOS fabrication process of the present invention;

[0019] Figure 3 This is a performance diagram of a high-voltage VDMOS fabricated using conventional epitaxial technology;

[0020] Figure 4This is a performance diagram of a high-voltage VDMOS fabricated using the silicon-silicon bonding process described in this application. Detailed Implementation

[0021] Hereinafter, exemplary embodiments of this application will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this application, and not all embodiments of this application. It should be understood that this application is not limited to the exemplary embodiments described herein.

[0022] Application Overview

[0023] The typical process flow for high-voltage VDMOS products is as follows: substrate preparation – epitaxial growth on the substrate. The thickness of the epitaxial layer is usually between 50 and 250 μm, depending on the voltage requirement. For high-voltage VDMOS products, the thickness and resistivity of the epitaxial layer are directly related to the breakdown voltage. This results in a long fabrication time when the epitaxial thickness reaches 100 μm, with a single-furnace process time exceeding 2.5 hours, leading to low production efficiency, high fabrication costs, and problems such as more defects, poor resistivity consistency, severe self-doping, and a wide transition region. These issues affect product performance and increase costs.

[0024] To address the aforementioned technical problems, this application proposes using silicon-silicon bonding instead of epitaxial growth. Compared to epitaxy, silicon-silicon bonding provides a steeper transition region. High-voltage VDMOS devices require a steep transition region because its width affects the actual epitaxial thickness. An excessively wide transition region can lead to significant deviations between actual and design parameters. Furthermore, due to self-doping effects in epitaxy, the transition region at the epitaxial edges is wider, resulting in poorer on-wafer consistency and decreased device performance and yield. In this respect, silicon-silicon bonding offers a clear advantage over epitaxy.

[0025] After introducing the basic principles of this application, various non-limiting embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0026] Exemplary methods

[0027] A method for fabricating high-voltage VDMOS using silicon-silicon bonding technology, such as Figure 1 and Figure 2 As shown, it includes:

[0028] S10. Prepare the support substrate and bonding substrate. The resistivity of the support substrate is 0.008~0.06 ohm·cm, and the bonding substrate is 50~250um. The thickness uniformity requirement is 2um, and the resistivity is >15 ohm·cm. The substrate resistivity will affect the breakdown voltage of the device, so the resistivity setting in this area is very important and cannot be too low.

[0029] S20. The supporting substrate and the bonding substrate are silicon-silicon bonded and then subjected to high-temperature annealing and curing. During the bonding process, a uniform oxide layer is formed on the surfaces of the supporting substrate and the bonding substrate as a medium layer through a cleaning process. The thickness of the medium layer is less than 5 angstroms. The function of the medium oxide layer is to adsorb a large number of OH groups using the unsaturated dangling bonds exposed on its surface. - The group saturates its bonds, and then adsorbs water molecules. When the two silicon wafers are bonded face to face at room temperature, the van der Waals forces between the water molecules adsorbed on the surface tightly bind the two silicon wafers together. Then, it is annealed and cured at 900~1200℃ for 20~50 minutes.

[0030] S30. The chamfered edges of the bonding support substrate and the bonding substrate after bonding are etched.

[0031] S40. Thin the bonding substrate to the required thickness;

[0032] S50. Polish the bonding substrate. Due to the use of grinding and polishing process, an epitaxial layer of any thickness can be obtained, and there are fewer surface defects, which can improve the device yield.

[0033] The fabrication of the S60 device includes the P+ layer, active region, polysilicon gate, and N+ layer. These structures are existing technologies, and those skilled in the art can fabricate them in various ways, which will not be elaborated upon here. The polysilicon gate has a thickness of 6000~10000 angstroms and a resistivity of 6~15 ohms / sqr. The thickness and resistivity of the polysilicon gate have a significant impact on the frequency of the high-voltage VDMOS. The resistivity is the saturation resistivity, and the thickness is generally guaranteed to be above 6000 angstroms but not exceeding 10000 angstroms. Excessive thickness will cause large variations in the surface of the product, affecting subsequent etching processes.

[0034] S70. Contact holes are created through an etching process;

[0035] S80. Fabricate the front metal layer. The front metal layer is made of aluminum and has a thickness of 3~5um.

[0036] S90. Fabricate the back metal layer. The back metal layer is made of TiNiAg with a total thickness of 8000~15000 angstroms.

[0037] The thickness of the metal layer has a significant impact on product cost. If the metal layer is too thin, it will not be able to withstand the pressure of subsequent packaging wire bonding; if it is too thick, it will increase costs and will not significantly improve product performance. Therefore, the setting of the thickness parameter is also the key to manufacturing high-voltage VDMOS.

[0038] Performance comparison of high-voltage VDMOS fabricated using the silicon-silicon bonding process of this application with high-voltage VDMOS fabricated using conventional epitaxial processes under the same conditions: Figure 3-4 As shown in the figure, it can be clearly seen that the transition region of the high voltage VDMOS device narrows from 11um to 5um. For high voltage VDMOS products, the narrowing of the transition region means that (1) the product design voltage is closer to the actual process voltage and the design error is smaller; (2) on the same wafer, the difference in product parameters between the wafer center and the edge will be smaller, that is, the on-chip consistency is better.

[0039] It should also be noted that in the method of this application, the components or steps can be disassembled and / or recombined. These disassemblies and / or recombinations should be considered equivalent solutions of this application. The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects without departing from the scope of this application. Therefore, this application is not intended to be limited to the aspects shown herein, but rather to be carried out within the widest scope consistent with the principles and novel features disclosed herein.

[0040] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this application to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

Claims

1. A method for fabricating high-voltage VDMOS using silicon-silicon bonding technology, characterized in that, include: Prepare the support substrate and bonding substrate; The supporting substrate and the bonding substrate are bonded together with silicon and then annealed and cured at high temperature, with the bonding substrate located on the supporting substrate. The edges of the bonding support substrate and the bonding substrate are etched. The bonding substrate is thinned to the required thickness; The bonding substrate is polished; A device P+ layer, an active region, a polysilicon gate, and a device N+ layer are fabricated on the bonding substrate. Contact holes are formed on the N+ layer of the device by etching. A front metal layer is fabricated, which covers the contact hole, the device N+ layer, and the polysilicon gate. Create the back metal layer; The resistivity of the supporting substrate is 0.008~0.06 ohm·cm, the resistivity of the bonding substrate is >15 ohm·cm, the bonding substrate is 50~250 μm, and the thickness uniformity is 2 μm. When the supporting substrate and the bonding substrate are bonded, a uniform oxide layer is formed on the surface of the supporting substrate and the bonding substrate as a medium layer through a cleaning process. The thickness of the medium layer is less than 5 angstroms. Then, high-temperature annealing and curing are carried out at 900~1200℃ for 20~50 minutes. The polysilicon gate has a thickness of 6000~10000 angstroms and a resistivity of 6~15 ohm / sqr.

2. The method for fabricating high-voltage VDMOS using silicon-silicon bonding process according to claim 1, characterized in that, The front metal layer is made of aluminum and has a thickness of 3~5um.

3. The method for fabricating high-voltage VDMOS using silicon-silicon bonding process according to claim 1, characterized in that, The back metal layer is made of TiNiAg with a total thickness of 8000~15000 angstroms.

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