For high pressure annealing of metal-containing materials

Abstract

The present disclosure provides a method for performing an annealing process on a metal-containing layer in a TFT display application, a semiconductor, or a memory application. In one example, a method for forming a metal-containing layer on a substrate includes the following steps: supplying an oxygen-containing gas mixture to a substrate in a process chamber, the substrate including the metal-containing layer disposed on an optically transparent substrate; maintaining the oxygen-containing gas mixture in the process chamber at a process pressure between about 2 bar and about 50 bar; and thermally annealing the metal-containing layer in the presence of the oxygen-containing gas mixture.

Description

Technical Field

[0001]

[0014] Embodiments of the present invention generally relate to methods for forming metal-containing layers in film stacks that can be utilized in TFT device structures, semiconductor, or memory applications. Background Art

[0002] Display devices have been widely used in a wide range of electronic applications, such as televisions, monitors, mobile phones, MP3 players, e-book readers, and personal digital assistants (PDAs). Display devices are generally designed to produce a desired image by applying an electric field to liquid crystals. The liquid crystals fill the gap between two substrates and have an anisotropic dielectric constant that controls the strength of the dielectric field. By adjusting the amount of light transmitted through the substrates, the intensity, quality, and power consumption of the light and image can be efficiently controlled.

[0003] Various display devices, such as active matrix liquid crystal displays (AMLCDs) or active matrix organic light emitting diodes (AMOLEDs), can be used as light sources for display devices utilizing touch screen panels. When manufacturing TFT devices, electronic devices having high electron mobility, low leakage current, and high breakdown voltage allow more pixel area to be used for light transmission and circuit system integration, thereby resulting in brighter display, higher overall electrical efficiency, faster response time, and higher resolution display. Low film quality material layers formed in the device, such as metal electrode layers with impurities, generally result in poor device electrical performance and short device life. Therefore, in order to provide a device structure with low film leakage, a stable and reliable method for forming a film layer in a TFT device and integrating the film layer with the TFT device becomes crucial, and a high breakdown voltage is required for manufacturing an electronic device with a lower threshold voltage shift and improving the overall performance of the electronic device.

[0004] Therefore, there is a need for improved materials for use in fabricating TFT devices that result in improved device electrical performance and device stability. Summary of the Invention

[0005] The present disclosure provides a method for performing an annealing process on a metal-containing layer in TFT display applications, semiconductors, or resistive random access memory (ReRAM). In one example, a method for forming a metal-containing layer on a substrate includes the following steps: supplying an oxygen-containing gas mixture to a substrate in a process chamber, the substrate including the metal-containing layer disposed on an optically transparent substrate; maintaining the oxygen-containing gas mixture in the process chamber at a process pressure between 2 bar and 50 bar; and thermally annealing the metal-containing layer in the presence of the oxygen-containing gas mixture.

[0006] In another example, a method for densifying a metal-containing layer disposed on a substrate includes the steps of: heat treating the metal-containing layer disposed on an optically transparent substrate at a pressure greater than 2 bar; and maintaining the substrate temperature at less than 500 degrees Celsius during heat treating the dielectric layer.

[0007] In yet another example, a method for densifying a metal-containing layer disposed on a substrate includes the steps of forming the metal-containing layer on the substrate; implanting a dopant into the metal-containing layer; and heat treating the metal-containing layer on the substrate at a pressure greater than 2 bar while maintaining a substrate temperature of less than 500 degrees Celsius. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The foregoing features of the invention, as well as a more particular description of the invention briefly summarized above, may be understood in detail by reference to its embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the drawings illustrate only typical embodiments of the invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.

[0009] Figure 1 is a simplified front cross-sectional view of a process chamber having a cassette disposed therein according to some embodiments;

[0010] Figure 2 It is a cluster system that can Figure 1 The processing chamber is merged into the cluster system;

[0011] Figure 3 is a cross-sectional view of an example of a thin film transistor device structure; and

[0012] Figure 4 is a cross-sectional view of another example of a thin film transistor device structure.

[0013] Figure 5 depicts a flow chart of an annealing process performed in a metalliferous material according to some embodiments;

[0014] Figures 6A-6D Describing an embodiment of the present invention Figure 5 One embodiment of a sequence for thermally annealing a metal-containing material.

[0015] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements common to the figures (such as annealing at atmospheric pressure for similar annealing conditions). It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

[0016] It is to be noted, however, that the appended drawings illustrate only exemplary embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments. DETAILED DESCRIPTION

[0017] Embodiments of the present disclosure generally provide a TFT device structure and a method for performing a thermal annealing process on the active layer of the source, drain, interface, and contact regions in the TFT device structure to enhance the electrical performance of the display device. Other applications (including semiconductor or memory device manufacturing processes) may also utilize the embodiments described herein. The thermal annealing process can densify the metal electrodes, source / drain and / or contact regions, and / or active layer film properties of the film layer on the substrate. In one example, a thermal treatment process is performed to provide thermal energy to a metal-containing layer, such as a metal-containing layer (e.g., an active layer) or a metal electrode layer (e.g., a metal gate electrode, source-drain and / or contact region or electrode layer, or other suitable metal structure) formed in a TFT device. The thermal annealing process can densify or minimize oxygen deficiency in the active layer film structure to provide good quality, interface management, and thermal stability to the device structure. The thermal annealing process can also increase the crystallinity of the metal-containing material, thereby improving the electrical performance of the metal-containing layer. Therefore, the film properties required for metal electrodes and active layers of source / drain and / or contact regions in display devices can effectively enhance the electrical performance of transistor and diode devices.

[0018] Figure 1 1 is a simplified front cross-sectional view of a single substrate processing chamber 100 for high pressure annealing of a single substrate. The single substrate processing chamber 100 has a body 110 having an outer surface 112 and an inner surface 113 enclosing an inner volume 115. Figure 1 In some embodiments, the body 110 has an annular cross-section, however, in other embodiments, the cross-section of the body 110 can be rectangular or any closed shape. The outer surface 112 of the body 110 can be made of corrosion resistant steel (CRS) such as, but not limited to, stainless steel. One or more heat shields 125 are provided on the inner surface 113 of the body 110, which prevent heat from being lost from the single substrate processing chamber 100 to the external environment. The inner surface 113 of the body 110 and the heat shield 125 can be made of a nickel-based steel alloy that exhibits a high degree of corrosion resistance, such as, but not limited to, and

[0019] A substrate support 130 is disposed within the interior volume 115. The substrate support 130 includes a stem 134 and a substrate support member 132 held by the stem 134. The stem 134 extends through a passage 122 formed through the chamber body 110. A rod 139, connected to an actuator 138, extends through a second passage 123 formed through the chamber body 110. The rod 139 is coupled to a plate 135 having a hole 136 that accommodates the stem 134 of the substrate support 130. Lift pins 137 are connected to the substrate support member 132. The actuator 138 actuates the rod 139, causing the plate 135 to move up and down to connect and disconnect with the lift pins 137. As the lift pins 137 are raised or lowered, the substrate support member 132 is raised or lowered within the interior volume 115 of the chamber 100. The substrate support member 132 includes a resistive heating element 131 embedded in its center. The power supply 133 is configured to supply power to the resistive heating element 131. The operation of the power supply 133 and the actuator 138 is controlled by a controller 180.

[0020] The single substrate processing chamber 100 has an opening 111 in the main body 110 through which one or more substrates 120 can be loaded and unloaded into and from a substrate support 130 disposed in an interior volume 115. The opening 111 forms a tunnel 121 in the main body 110. A slit valve 128 is configured to sealably close the tunnel 121, such that access to the opening 111 and the interior volume 115 is limited only when the slit valve 128 is open. A high-pressure seal 127 is used to seal the slit valve 128 to the main body 110 to seal the interior volume 115 for processing. The high-pressure seal 127 can be made of a polymer, such as a fluoropolymer, such as, but not limited to, perfluoroelastomer and polytetrafluoroethylene (PTFE). The high-pressure seal 127 can further include a spring member to bias the seal to improve sealing performance. A cooling channel 124 is provided on the tunnel 121 near the high pressure seal 127 to maintain the high pressure seal 127 below its maximum safe operating temperature during processing. A coolant (such as, but not limited to, an inert, dielectric, and high performance heat transfer fluid) from a cooling fluid source 126 can be circulated within the cooling channel 124. The flow rate of the coolant from the cooling fluid source 126 is controlled by the controller 180 using feedback received from the temperature sensor 116 or a flow sensor (not shown). An annular thermal choke 129 is formed around the tunnel 221 to prevent heat from the interior volume 115 from flowing through the opening 111 when the slit valve 128 is open.

[0021] The single substrate processing chamber 100 has a port 117 through the body 110 that is fluidly connected to a fluid circuit 190 that connects the gas panel 150, the condenser 160, and the port 117. The fluid circuit 190 has a gas conduit 192, a source conduit 157, an inlet isolation valve 155, an exhaust conduit 163, and an outlet isolation valve 165. A number of heaters 196, 158, 152, 154, 164, 166 interface with various portions of the fluid circuit 190. A number of temperature sensors 151, 153, 119, 167, and 169 are also positioned at various portions of the fluid circuit 190 to take temperature measurements and send information to the controller 180. Controller 180 uses the temperature measurement information to control operation of heaters 152 , 154 , 158 , 196 , 164 , and 166 so that the temperature of fluid circuit 190 is maintained above the freezing point of the process fluid disposed in fluid circuit 190 and interior volume 115 .

[0022] The gas panel 150 is configured to provide a process fluid at a pressure within the interior volume 115. The pressure of the process fluid introduced into the interior volume 115 is monitored by a pressure sensor 114 coupled to the main body 110. The condenser 160 is fluidly coupled to a cooling fluid source (not shown) and is configured to condense the gaseous process fluid exiting the interior volume 115 through the gas conduit 192. The condensed process fluid is then removed by a pump 176. One or more heaters 140 are disposed on the main body 110 and are configured to heat the interior volume 115 within the single substrate processing chamber 100. The heaters 140, 152, 154, 158, 196, 164, and 166 maintain the process fluid within the fluid circuit 190 in a gas phase while the outlet isolation valve 165 to the condenser 160 is open to prevent condensation within the fluid circuit.

[0023] The controller 180 controls the operation of the single substrate processing chamber 100. The controller 180 controls the operation of the gas panel 150, the condenser 160, the pump 170, the inlet isolation valve 155, the outlet isolation valve 165, and the power supplies 133 and 145. The controller 180 is also communicatively connected to the temperature sensor 116, the pressure sensor 114, the actuator 138, the cooling fluid source 126, and the temperature readout devices 156 and 162.

[0024] The processing fluid may include an oxygen-containing gas and / or a nitrogen-containing gas, and / or a chalcogenide or tellurium (such as S, Se, Te) gas or vapor, such as oxygen, dry steam, water, hydrogen peroxide, ammonia, S vapor, Se vapor, H2S, H2Se, etc. The processing fluid may react with the metal material on the substrate to form a metal nitride, a metal oxide, a metal oxychalcogenide, or a metal chalcogenide. Instead of or in addition to the oxygen-containing gas and / or nitrogen-containing gas, the processing fluid may include a silicon-containing gas. Examples of silicon-containing gases include organosilicon, tetraalkyl orthosilicate gas, and disiloxane. Organosilicon gas includes a gas of an organic compound having at least one carbon-silicon bond. Tetraalkyl orthosilicate gas includes a gas composed of a silicon-containing compound attached to SiO4 4- More specifically, the one or more gases may be (dimethylsilyl)(trimethylsilyl)methane ((Me)3SiCH2SiH(Me)2), hexamethyldisilane ((Me)3SiSi(Me)3), trimethylsilane ((Me)3SiH), trimethylsilyl chloride ((Me)3SiCl), tetramethylsilane ((Me)4Si), tetraethoxysilane ((EtO)4Si), tetramethoxysilane ((MeO)4Si), tetrakis(trimethylsilyl)silane ((Me3Si)4Si), (dimethylamino) )dimethylsilane ((Me2N)SiHMe2), dimethyldiethoxysilane ((EtO)2Si(Me)2), dimethyldimethoxysilane ((MeO)2Si(Me)2), methyltrimethoxysilane ((MeO)3Si(Me)), dimethoxytetramethyldisiloxane (((Me)2Si(OMe))2O), tris(dimethylamino)silane ((Me2N)3SiH), bis(dimethylamino)methylsilane ((Me2N)2CH3SiH), disiloxane ((SiH3)2O), and combinations thereof.

[0025] During processing of the substrate 120, the environment of the high-pressure region 115 is maintained at a temperature and pressure that maintains the processing fluid in the high-pressure region in the gas phase. Such pressure and temperature are selected based on the composition of the processing fluid. In the case of vapor, the temperature and pressure are maintained under conditions that maintain the vapor in a dry vapor state. In one example, the high-pressure region 115 is pressurized to a pressure greater than atmospheric pressure, for example, greater than about 2 bar. In another example, the high-pressure region 115 is pressurized to a pressure of from about 10 to about 50 bar (for example, from about 20 to about 50 bar). In another example, the high-pressure region 115 is pressurized to a pressure of up to about 100 bar. During processing, the high-pressure region 115 is also maintained at a high temperature, for example, a temperature exceeding 225 degrees Celsius (limited by the thermal budget of the substrate 155 provided on the cassette 150), for example, between about 300 degrees Celsius and about 500 degrees Celsius.

[0026] Figure 2 is a schematic top plan view of an exemplary processing system 200 including a processing chamber (such as a Figure 1 In one embodiment, the processing system 200 may be a process system available from Applied Materials, Inc. located in Santa Clara, California. or Integrated Processing Systems. It is contemplated that other processing systems, including those from other manufacturers, may be adapted to benefit from the present disclosure.

[0027] The system 200 includes a vacuum-tight processing platform 204, a factory interface 202, and a system controller 244. The platform 204 includes a plurality of processing chambers 100, 212, 232, 228, 220 (such as Figure 1 ), and at least one load lock chamber 222 coupled to the vacuum substrate transfer chamber 236. Figure 2 Two load lock chambers 222 are shown in FIG. The factory interface 202 is coupled to the transfer chamber 236 through the load lock chambers 222 .

[0028] In one embodiment, the factory interface 202 includes at least one docking station 208 and at least one factory interface robot 214 to facilitate the transfer of substrates. The docking station 208 is configured to receive one or more front opening unified pods (FOUPs). Figure 2In the embodiment of FIG. 2 , two FOUPs 206A-B are shown. A factory interface robot 214 having a blade 216 disposed on one end of the robot 214 is configured to transfer substrates from the factory interface 202 through the load lock chamber 222 to the processing platform 204 for processing. Optionally, one or more metrology stations 518 can be connected to the terminal 226 of the factory interface 202 to facilitate measuring substrates from the FOUPs 206A-B.

[0029] Each of the load lock chambers 222 has a first port coupled to the factory interface 202 and a second port coupled to the transfer chamber 236. The load lock chambers 222 are coupled to a pressure control system (not shown) that evacuates and vents the load lock chambers 222 to facilitate transferring substrates between the vacuum environment of the transfer chamber 236 and the substantially ambient (e.g., atmospheric) environment of the factory interface 202.

[0030] The transfer chamber 236 has a vacuum robot 230 disposed therein. The vacuum robot 230 has a blade 234 that can transfer the substrate 224 between the load lock chamber 222, the metrology system 210, and the processing chambers 212, 232, 228, and 220.

[0031] In one embodiment of the system 200, the system 200 may include one or more process chambers 100, 212, 232, 228, 220, which may be annealing chambers (e.g., high pressure annealing chambers, RTP chambers, laser annealing chambers), deposition chambers, etching chambers, cleaning chambers, curing chambers, or other similar types of semiconductor processing chambers. In some embodiments of the system 200, the system 200 may include one or more of at least one of the process chambers 100, 212, 232, 228, 220, a transfer chamber 236, a factory interface 202, and / or a load lock chamber 222.

[0032] A system controller 244 is coupled to the processing system 200. The system controller 244 (which may include or be included within the computing device 201) controls the operation of the processing system 200 using direct control of the processing chambers 100, 212, 232, 228, 220 of the system 200. Alternatively, the system controller 244 may control computers (or controllers) associated with the processing chambers 100, 212, 232, 228, and the system 200. In operation, the system controller 244 also allows for data collection and feedback from the various chambers to optimize the performance of the system 200.

[0033] Much like the computing device 201 described above, the system controller 244 generally includes a central processing unit (CPU) 238, memory 240, and support circuits 242. The CPU 238 can be one of any general-purpose computer processors that can be used in an industrial environment. The support circuits 242 are conventionally coupled to the CPU 238 and may include cache memory, clock circuits, input / output subsystems, power supplies, and the like. Software programs transform the CPU 238 into a special-purpose computer (controller) 244. The software programs may also be stored and / or executed by a second controller (not shown) located remotely from the system 200.

[0034] Figure 3 Depicts an example of a TFT device 350 that includes a metal-containing layer that may undergo a thermal annealing process in a high pressure annealing chamber, such as Figure 1 The high pressure annealing process 100 depicted in FIG. 1 may incorporate the high pressure annealing chamber into Figure 2 In the system 200 depicted in FIG. , the thin film transistor device structure 350 is a bottom gate TFT structure disposed on the substrate 301. Note that the substrate 301 may have different combinations of films, structures, or layers previously formed thereon to facilitate forming different device structures or different film stacks on the substrate 301. In one example, the substrate 301 may have the device structure 350 formed thereon, such as Figure 3 Alternatively, the substrate 301 may have another device structure 450 disposed thereon, such as Figure 4 The device structure will be further described below. The substrate 301 can be any of a glass substrate, a plastic substrate, a polymer substrate, a metal substrate, a single substrate, a roll-to-roll substrate, or other suitable transparent substrate for forming thin film transistors thereon.

[0035] A gate electrode layer 302 is formed and patterned on the substrate 301, followed by a gate insulating layer 304. In one embodiment, the gate electrode layer 302 can be made of any suitable metal material, such as aluminum (Al), tungsten (W), chromium (Cr), tantalum (Ta), molybdenum (Mo), copper (Cu), or a combination thereof. Suitable materials for the gate insulating layer 304 include silicon oxide (SiO2), silicon oxynitride (SiON), silicon nitride (SiN), and the like. Note that Figure 3 The thin film transistor device structure 350 depicted in FIG. 3 is a bottom-gate device structure in which the gate electrode layer 302 is formed on the bottom of the device structure 350 .

[0036] The active layer 306 is formed on the gate insulating layer 304. The material for the active layer 306 can be selected from transparent metal oxide materials having high electron mobility and suitable for low-temperature manufacturing, which allows flexible substrate materials (such as plastic materials) to be processed at low temperatures without damaging the substrate. Suitable examples of materials that can be used for the active layer 306 include a-IGZO (amorphous indium gallium zinc oxide), InGaZnON, ZnO, ZnON, ZnSnO, CdSnO, GaSnO, TiSnO, CuBO2, CuAlO2, CuGaO2, SrCuO, LaCuOS, GaN, InGaN, AlGaN, or InGaAlN, etc.

[0037] After forming the active layer 306, a barrier layer 308 may be formed on the active layer 306. The barrier layer 308 may be formed of a metal-containing material to provide good interfacial adhesion and good barrier properties (e.g., diffusion barrier) to a metal electrode layer 310 (e.g., for a source-drain electrode) subsequently formed thereon. The barrier layer 308 may be patterned to form a desired pattern on the active layer 306 to facilitate the transfer of features to a film layer disposed on the substrate 301 during a subsequent etching process. Although Figure 3 The barrier layer 308 depicted in FIG is patterned into a desired pattern, but it is noted that the barrier layer 308 can take any form, including an entire continuous blank film or any distinct features in the device structure 350, as desired, as long as the barrier layer 308 can effectively provide barrier / diffusion barrier properties to prevent elements from the active layer 306 from diffusing into the metal electrode layer 310 and vice versa. In one embodiment, the barrier layer 308 can be a single layer of a metal-containing dielectric layer (such as Ta2O5 or TiO2 or any suitable metal-containing dielectric layer, as desired), as shown. Figure 3 In another embodiment, the barrier layer 308 can be in the form of a composite film as desired.

[0038] After a metal electrode layer 310 (such as a source-drain metal electrode layer) is disposed over the barrier layer 308, an etching process is then performed to form a channel 320 in the metal electrode layer 310. Following etching, an insulating material layer 314 (such as a passivation layer) is then formed over the metal electrode layer 310 to complete the process of forming the thin film transistor device structure 350.

[0039] In one embodiment, examples of materials that can be used as the metal electrode layer 310 include copper (Cu), gold, silver (Ag), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), tantalum (Ta), alloys thereof, and combinations thereof. Suitable materials that can be used as the insulating material layer 314 include silicon oxide (SiO2), silicon oxynitride (SiON), or silicon nitride (SiN), and the like.

[0040] Figure 4 Depicts an example of a top-gate low temperature polysilicon (LTPS) TFT device structure 450 that may be formed on substrate 301 instead of Figure 3 3. The bottom-gate device structure 350 depicted in FIG. LTPS TFT device 450 is a MOS device constructed with an active layer 452 including a source region 409a, a channel region 408, and a drain region 409b (e.g., also referred to as a metal contact region or source-drain metal contact) formed on an optically transparent substrate 301, with or without an optional insulating layer 404 disposed thereon. In one example, the active layer including the source region 409a, the channel region 408, and the drain region 409b can be fabricated from a transparent metal-containing layer (such as a metal oxide material) that has high electron mobility and is suitable for low-temperature fabrication, which allows flexible substrate materials (such as plastic materials) to be processed at low temperatures without damaging the substrate. Suitable examples of such materials that can be used for the source region 409a, the channel region 408, and the drain region 409b include a-IGZO (amorphous indium gallium zinc oxide), doped IGZO, InGaZnON, ZnO, ZnON, ZnSnO, CdSnO, GaSnO, TiSnO, CuBO2, CuAlO2, CuGaO2, SrCuO, LaCuOS, GaN, InGaN, AlGaN, or InGaAlN, etc.

[0041] A gate insulating layer 406 is then deposited on top of the deposited polysilicon layer to isolate a barrier layer 411 and a metal electrode layer 414 (such as a gate electrode) disposed on the gate insulating layer from the channel region 408, the source region 409a, and the drain region 409b. The barrier layer 411 can be formed from a metal-containing material to provide good interfacial adhesion and good barrier properties (such as diffusion barrier) to the metal electrode layer 414 (e.g., gate electrode) subsequently formed on the barrier layer. The barrier layer 411 can be patterned to form a desired pattern on the gate insulating layer 406 to facilitate the transfer of features to a film layer disposed on the substrate 102 during a subsequent etching process. The barrier layer 411 can effectively provide barrier / diffusion barrier properties to prevent elements from the gate insulating layer 406 from diffusing into the metal electrode layer 414, and vice versa. In one embodiment, the barrier layer 411 may be a single layer of a metal-containing dielectric layer made of a metal dielectric layer such as Ta2O5 or TiO2 or any suitable metal dielectric layer as required, as shown in FIG. Figure 4 In another embodiment, the barrier layer 411 may be in the form of a composite film as desired.

[0042] A gate electrode layer 414 is formed on top of the gate insulating layer 406 with a barrier layer 411 interposed therebetween. The gate insulating layer 406 is also often referred to as a gate oxide layer because it is typically made of a silicon dioxide (SiO2) layer. An insulating material layer 412 (such as an interlayer insulator) and device connectors (not shown) are then fabricated through the insulating material layer 412 to allow control of the TFT device.

[0043] After the insulating material layer 412 is formed, source-drain metal electrode layers 410a, 410b are then deposited, formed, and patterned in the insulating material layer 412. After the source-drain metal electrode layers 410a, 410b are patterned, a passivation layer 418 is then formed over the source-drain metal electrode layers 410a, 410b.

[0044] Figure 5 Describe the metal-containing layers (such as Figure 3-4 The active layers 306, 452, or respectively in Figure 3-4 Flowchart of an example of a thermal annealing process 500 performed on the metal electrodes 302, 310, 410a, 410b, 414 in FIG.

[0045] The method 500 comprises providing a substrate (such as Figure 3 and 4 The process begins at operation 502. The substrate 301 may be an optically transparent substrate. The substrate 301 may include a material layer 601 disposed thereon, such as Figure 6AAs shown in . Material layer 601 can be a single layer or multiple layers that can be used to form a TFT device structure. Alternatively, material layer 601 can be a structure that can include multiple materials that can be used to form a TFT device structure.

[0046] The substrate 301 further includes a metal-containing layer 602 formed on the material layer 601, such as Figure 6B In the example where the material layer 601 is not present, the metal-containing layer 602 can be formed directly on the substrate 301. In some examples, the metal-containing layer 602 can be used as Figure 3 or the active layer 306, 452 in 4, or Figure 3-4 The metal electrodes 302, 310, 410a, 410b, 414 in FIG. In one example, the metal-containing layer 602 is a metal oxide layer selected from the group consisting of a-IGZO (amorphous indium gallium zinc oxide), doped IGZO, InGaZnON, ZnO, ZnON, ZnSnO, CdSnO, GaSnO, TiSnO, CuBO2, CuAlO2, CuGaO2, SrCuO, LaCuOS, GaN, InGaN, AlGaN, or InGaAlN, and the like. In one example, the metal-containing layer 602 is IGZO or a doped IGZO layer. Alternatively, the metal-containing layer 602 can be a metal layer such as copper (Cu), gold, silver (Ag), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), tantalum (Ta), alloys thereof, or the like.

[0047] At operation 504, an optional ion doping / implantation process is performed to implant ions into the metal-containing layer 602 to form a doped metal-containing layer 610, such as Figure 6C . In an example where the ion implantation process is eliminated, the thermal annealing process at operation 506 (described in more detail below) can be performed directly on the metal-containing layer 602. The ion doping / implantation process is performed to dope, coat, treat, implant, insert, or modify certain film / surface properties at certain locations of the metal-containing layer 602, wherein dopants are formed in the metal-containing layer to form a doped metal-containing layer 610. The ion doping / implantation process utilizes incident ions to modify the film / surface properties on the metal-containing layer 602, wherein dopants are doped into the metal-containing layer to form the doped metal-containing layer 610. The ion doping / implantation process can be performed in any suitable ion implantation / doping process tool. Ions including atoms of a desired type can be doped into the metal-containing layer 602 at a desired concentration. Ions doped into the metal-containing layer 602 may modify the film / surface properties of the metal-containing layer 602 , which may affect, improve, or alter the lattice structure, crystallinity, bonding structure, or film density of the metal-containing layer 602 , thereby forming a doped metal-containing layer 610 .

[0048] In embodiments where the metal-containing layer 602 comprises InGaZnO, the ions doped into the metal-containing layer 602 may include indium (In) or molybdenum (Mo), gallium (Ga), zinc (Zn), and the like. It is believed that the In or Mo dopants doped into the metal-containing layer 602 (e.g., InGaZnO) can modify the electrical properties of the InGaZnO material, such as high mobility, crystallinity (e.g., from an amorphous structure, a C-axis oriented crystalline structure (CAAC), a polycrystalline structure, or even a single crystal structure), thereby providing a doped metal-containing layer 610 with desirable film properties. For example, the higher degree of crystallinity provided by the In or Mo dopants in the InGaZnO material is believed to increase the electron mobility of the film property, thereby enhancing the electrical performance of a TFT device structure or semiconductor device when the doped metal-containing layer 610 is utilized in the TFT device structure or semiconductor device.

[0049] Furthermore, it is also believed that the ratio of gallium (Ga) and zinc oxide (ZnO) included in the InGaZnO material can also affect the resulting lattice structure of the doped metal-containing layer 610. It is believed that the ratio of the Ga element included in the InGaZnO material can increase the film transparency and the overall film band gap. The ratio of the Zn or ZnO element included in the InGaZnO material can increase the mobility and reduce the thermal annealing temperature requirement for enhancing crystallinity. Therefore, by selecting an appropriate dose of In dopant doped into the InGaZnO material, the desired InGaZnO material crystal can be obtained. Furthermore, the desired InGaZnO material crystal can also help reduce the temperature requirement in the subsequent thermal annealing process at operation 506, thereby providing a processing advantage in TFT device applications because the substrate 301 is generally an optically transparent material with a relatively low thermal cycling budget.

[0050] In one embodiment, the generated In dopant in the InGaZnO material may have a density of about 5E15 ions / cm2 formed in the doped metal-containing layer 610. 2 to about 9E15 ions / cm 2 between (such as about 8.5E15 ions / cm 2 Furthermore, the ratio of the In or Mo element in the InGaZnO material in terms of atomic weight can be increased from about 10%-13% to about 14%-16% (an increase between about 15% and about 30%).

[0051] Several processing parameters can be controlled during the ion doping / implantation process. The ion doping / implantation process can be performed by the following steps: the ion doping gas mixture and the power energy of the required amount are supplied to the ion doping / implantation tool to dope the ions from the ion doping gas mixture into the substrate 301. The ion doping gas mixture can be supplied to the ion doping / implantation tool at a flow rate between about 10 sccm and about 1000 sccm. Suitable elements for gaseous supply in the ion doping operation used during the implantation period include indium vapor and molybdenum vapor. RF power (such as capacitive or inductive RF power), DC power, electromagnetic energy, ion beam, or magnetron sputtering can be supplied to the ion doping / implantation process to assist in dissociating the ion doping gas mixture during the treatment period. The ions produced by the dissociation energy can be accelerated toward the substrate by applying a DC or RF electrical bias to the gas inlet above the substrate support or to both the substrate support and the gas inlet. In some embodiments, the high-energy ions containing the gas can be plasma. Ions may be implanted into the metal-containing layer 602 using an energy between about 20 keV and about 80 keV, such as between about 35 keV and about 55 keV, for example about 45 keV. The substrate temperature may be controlled between about 5 degrees Celsius and about 50 degrees Celsius, such as about 15 degrees Celsius.

[0052] At operation 506, a high pressure annealing process is performed. Annealing processes performed at high process pressures (such as greater than 2 bar but less than 50 bar) can assist in densifying and repairing vacancies in the doped metal-containing layer 610, thereby forming an annealed metal-containing layer 603 having desired film properties, such as Figure 6D In some examples, the high process pressure can be as high as 100 bar. In embodiments where the ion doping / implantation process at operation 504 is not performed, the ion doping / implantation process can be performed directly on the substrate from Figure 6B A high pressure annealing process is performed on the metal-containing layer 602 to form an annealed metal-containing layer 603, such as Figure 6D As shown in . Figure 1 The annealing process is performed in a processing chamber 100 (as depicted in FIG. 1 ) or other suitable processing chamber, including those that process one substrate at a time.

[0053] The high pressure annealing process performed at operation 506 maintains the process pressure at the high pressure region in a gas phase (e.g., a dry gas phase in which there are substantially no droplets). The process pressure and temperature are controlled to densify the film structure so as to repair film defects, thereby driving out impurities and increasing film density. In one example, the high pressure region 115 is pressurized to a pressure greater than atmospheric pressure, for example, greater than about 2 bar. In another example, the high pressure region 115 is pressurized to a pressure from about 5 bar to about 100 bar, such as from about 5 bar to about 50 bar, such as about 35 bar. Because high pressure can efficiently assist in densifying the film structure, a relatively low process temperature (such as less than 500 degrees Celsius) reduces the possibility of thermal cycling damaging the substrate 301.

[0054] During processing, the high pressure region 115 is maintained at a relatively low temperature, for example, less than 500 degrees Celsius, such as between about 150 degrees Celsius and about 350 degrees Celsius, by the heater 122 disposed within the outer chamber 110. Thus, a low substrate thermal budget can be achieved by utilizing a high pressure annealing process and a low temperature regime.

[0055] It is believed that the high pressure treatment can provide a driving force to drive off dangling bonds in the metal-containing layer 602 or the doped metal-containing layer 610, thereby repairing, reacting, and saturating the dangling bonds in the metal-containing layer 602 during the annealing process. In one example, an oxygen-containing gas (such as O3 gas, O2 gas, air, H2O, H2O2, N2O, NO2, CO2, CO, and dry steam), or a chalcogenide vapor (including sulfur (S) vapor and selenium (Se) vapor), or tellurium vapor, or other suitable gas can be supplied during the annealing process. In one specific example, the oxygen-containing gas includes steam, such as dry steam and / or air. Oxygen from the oxygen-containing gas can be driven into the metal-containing layer 602 during the annealing process, thereby changing the bonding structure therein and removing atomic vacancies, thereby densifying and strengthening the lattice structure of the metal-containing layer 602 and increasing the crystallinity of the metal-containing layer. In some examples, an inert gas or carrier gas (such as Ar, N2, He, Kr and the like) may be supplied with the oxygen-containing gas. In one embodiment, the oxygen-containing gas supplied in the oxygen-containing gas mixture is dry vapor supplied at a pressure greater than 2 bar.

[0056] In an exemplary embodiment, the process pressure is adjusted to a pressure greater than 2 bar, such as between 5 bar and 100 bar, such as between 20 bar and about 80 bar, for example, between about 25 bar and 75 bar, such as about 35 bar. The process temperature can be controlled to be greater than 150 degrees Celsius but less than 500 degrees Celsius, such as between about 150 degrees Celsius and about 380 degrees Celsius, such as between about 180 degrees Celsius and about 400 degrees Celsius. In one example, a chalcogenide vapor (such as sulfur (S) vapor, selenium (Se) vapor) can be supplied during an annealing process for a metal oxychalcogenide element (such as InGaZnO including S or Se).

[0057] After the high-pressure annealing process, the metal-containing layer 602 or the doped metal-containing layer 610 has a densified film structure compared to the metal-containing layer 602 or the doped metal-containing layer 610 annealed by a conventional annealing process at a pressure of approximately 1 atmosphere. This provides a relatively robust film structure with an amorphous morphology, which provides a higher film density, high film mobility, low carrier concentration, and low film resistivity, wherein both annealing processes are at the same annealing temperature. In one example, the mobility of the high-pressure annealed metal-containing layer 603 (formed from the doped metal-containing layer 610) with indium dopant increases by between about 5 times and about 20 times, the resistivity increases by about 10 times, and the carrier concentration decreases by about 100 times, compared to the conventional annealing process at 1 atmosphere and the same annealing temperature.

[0058] In one example, the high pressure annealed metal-containing layer 603 (formed from the metal-containing layer 602) without indium dopants has a mobility increased by between about 1.5 times and about 5 times, a resistivity increased by about 20 percent to about 99 percent, and a carrier concentration decreased by about 100 times, compared to a conventional annealing process at 1 atmosphere pressure and the same annealing temperature.

[0059] Thus, methods for thermally annealing a metal-containing layer are provided. The metal-containing layer can be thermally treated / annealed by a high pressure annealing process having a high process pressure (e.g., greater than 2 bar but less than 50 bar). By utilizing such a high pressure annealing process, the process temperature can be maintained at less than 500 degrees Celsius, thereby reducing the thermal budget contributed to the substrate on which the metal-containing layer is formed, thereby providing good film quality with desired crystallinity and structural integrity management.

[0060] While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope of the invention is determined by the claims that follow.

Claims

1. A method for forming a metal-containing layer on a substrate, the method comprising the following steps: supplying an oxygen-containing gas mixture onto a substrate in a processing chamber, the substrate comprising a metal-containing layer disposed on an optically transparent substrate; maintaining the oxygen-containing gas mixture in the process chamber at a process pressure between 2 bar and 50 bar; and thermally annealing the metal-containing layer in the presence of the oxygen-containing gas mixture, wherein: The metal-containing layer is selected from the group consisting of GaN, InGaN, AlGaN and InGaAlN, or the metal-containing layer is a metal oxide layer selected from the group consisting of a-IGZO (amorphous indium gallium zinc oxide), doped IGZO, InGaZnON, ZnO, ZnON, ZnSnO, CdSnO, GaSnO, TiSnO, CuBO2, CuAlO2, CuGaO2, SrCuO and LaCuOS, The metal-containing layer is an electrode of a TFT device structure, The method further comprises implanting a dopant into the metal-containing layer before supplying the oxygen-containing gas mixture, and The dopant implanted into the metal-containing layer includes indium or molybdenum, and increases crystallinity of the metal-containing layer.

2. The method of claim 1 , wherein the step of supplying the oxygen-containing gas mixture further comprises the following steps: Maintain the substrate temperature at less than 400 degrees Celsius.

3. The method of claim 1, wherein the oxygen-containing gas mixture comprises at least one oxygen-containing gas selected from the group consisting of: O3 gas, O2 gas, H2O, H2O2, N2O, NO2, CO2, CO, air, and dry steam.

4. The method of claim 3, wherein the oxygen-containing gas mixture comprises dry steam or air. The method of claim 1 , wherein the metal oxide layer is InGaZnON. The method of claim 1 , wherein the metal-containing layer has a higher mobility after the thermal annealing step.

7. The method of claim 1, wherein the metal-containing layer has a higher film density after the thermal annealing step.

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