A power-on reset circuit and optimization method

Abstract

The present invention discloses a power-on reset circuit and an optimization method, comprising a startup circuit, a PTAT current generating circuit, a voltage detection circuit and a delay circuit, wherein the startup circuit comprises a MOS tube MP1, a MOS tube MP2, a MOS tube MP3 and a MOS tube MP4, wherein the gate of the MOS tube MP3 is connected to ground, the source of the MOS tube MP3 and the MOS tube MP4 are connected to a power supply voltage VH, the drain of the MOS tube MP3 and the MOS tube MP4 are connected, the MOS tube MP1 is connected to the source of the MOS tube MP2, and the drain of the MOS tube MP1 is connected to ground. The power-on reset circuit and the optimization method realize low power supply voltage, low power consumption, voltage threshold hysteresis and adjustable delay, and can be generally used as a module circuit or a dedicated reset ASIC in an integrated circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of reset circuits for integrated circuit chips, and in particular to a power-on reset circuit and an optimization method thereof. Background Art

[0002] Before the logic of an integrated circuit chip can work normally, it usually needs to enter a certain working state first, and reset is the most common method to ensure that the chip can enter this state. Reset generally includes external reset and power-on reset. External reset refers to "notifying" the internal logic of the chip by generating a valid reset signal through a specific pin. In addition to adding a pin, external reset also requires system cooperation, which limits its application. Stable power-on reset has undoubtedly become the first choice for different application requirements. Even with an external reset circuit, it is also compatible with power-on reset to increase the flexibility of system wiring.

[0003] For traditional power-on reset circuits, if the power-on time is fast, RC delay comparison is usually used to implement it. This circuit usually requires larger resistors or capacitors and a larger circuit area. If the power-on time is slow, a reference voltage is generated by a BGR circuit to compare with the power supply, and this circuit is usually limited to the operating voltage, settling time and output stability of the BGR circuit. Summary of the invention

[0004] The purpose of the present invention is to provide a power-on reset circuit and optimization method to achieve low power supply voltage, low power consumption, voltage threshold hysteresis, and adjustable delay. It can be widely used in integrated circuits as a module circuit or a dedicated reset ASIC to solve the problems raised in the above background technology.

[0005] To achieve the above-mentioned object, the present invention provides the following technical solutions: a power-on reset circuit, comprising a startup circuit, a PTAT current generating circuit, a voltage detecting circuit, and a delay circuit, wherein the startup circuit comprises a MOS tube MP1, a MOS tube MP2, a MOS tube MP3, and a MOS tube MP4, wherein the gate of the MOS tube MP3 is connected to ground, the sources of the MOS tube MP3 and the MOS tube MP4 are connected to a power supply voltage VH, the drain of the MOS tube MP3 is connected to the drain of the MOS tube MP4, the MOS tube MP1 is connected to the source of the MOS tube MP2, and the drain of the MOS tube MP1 is connected to ground;

[0006] The PTAT current generating circuit comprises a MOS transistor MP5, a MOS transistor MP6, a MOS transistor MN1, a MOS transistor MN2 and a MOS transistor MN8, wherein the source electrodes of the MOS transistors MP5 and MP6 are connected to a power supply voltage VH, the gate electrodes of the MOS transistors MP5 and MP6 are connected, the drain electrode of the MOS transistor MN1 is connected to the drain electrode of the MOS transistor MP5, the source electrodes of the MOS transistors MN1 and MN2 are connected to ground, the drain electrode of the MOS transistor MN2 is connected to a resistor R1, a resistor R2 and a resistor R3 in series, and then to the drain electrode of the MOS transistor MP6, the gate electrode of the MOS transistor MN2 is connected to a circuit interface of the resistor R1, the resistor R2 and the resistor R3 in series, the gate circuit interface of the MOS transistors MP5 and MP6 is connected to a gate circuit interface of the MOS transistor MP4, the drain electrode of the MOS transistor MN8 is connected to a circuit interface of the resistor R3, the source electrode of the MOS transistor MN8 is connected to a drain circuit interface of the MOS transistor MN2, and the gate electrode of the MOS transistor MN8 is connected to a Schmitt trigger circuit;

[0007] The voltage detection circuit comprises a MOS transistor MP7, a MOS transistor MP8, a MOS transistor MN3, a MOS transistor MN4, a MOS transistor MN5, an inverter INV1 and an inverter INV2, wherein the source electrodes of the MOS transistor MP7 and the MOS transistor MP8 are connected to a power supply voltage VH, the drain electrode of the MOS transistor MP7 is connected to a resistor R4, the resistor R4 is connected to the gate electrode and the drain electrode of the MOS transistor MN4, the source electrode of the MOS transistor MN4 is connected to the gate electrode and the drain electrode of the MOS transistor MN3, the source electrodes of the MOS transistor MN3 and the MOS transistor MN5 are connected to ground, the MOS transistor MN3 is connected to the gate electrode of the MOS transistor MN5, the drain electrode of the MOS transistor MN5 is connected to the drain electrode of the MOS transistor MP8, and the circuit interface connecting the MOS transistor MN5 and the MOS transistor MP8 is connected to the inverter INV1 and the inverter INV2 connected in series;

[0008] The delay circuit comprises a MOS transistor MP9, a MOS transistor MP10, a MOS transistor MN6, a MOS transistor MN7, a MOS transistor MP11 and a Schmitt trigger circuit, wherein the source of the MOS transistor MP9 is connected to the power supply voltage VH, the drain of the MOS transistor MP9 is connected to the source of the MOS transistor MP10, the MOS transistor MP10 is connected to the gate of the MOS transistor MN6, the drain of the MOS transistor MP10 is connected to the drain of the MOS transistor MN6, the source of the MOS transistor MN6 is connected to the ground, and the source and drain of the MOS transistor MN7 are connected to the ground;

[0009] The POR signal of the Schmitt trigger circuit is connected to the gate of the MOS tube MP11 through an inverter, wherein the drain circuit interface of the MOS tube MP3 and the MOS tube MP4 is connected to the source circuit interface of the MOS tube MP1 and the MOS tube MP2, and the MOS tube MP4 is connected to the gate of the MOS tube MP9; the gate of the MOS tube MP1 is connected to the gate circuit interface of the MOS tube MN2, the gate of the MOS tube MP2 is connected to the drain circuit interface of the MOS tube MP6, and the drain of the MOS tube MP2 is connected to the drain circuit interface of the MOS tube MN2; the gate circuit interface of the MOS tube MP5 and the MOS tube MP6 is connected to the gate circuit interface of the MOS tube MP4; the gate of the MOS tube MP7 and the MOS tube MP8 is connected to the gate circuit interface of the MOS tube MP4; the series-connected inverters INV1 and INV2 are connected to the gate circuit interface of the MOS tube MP10 and the MOS tube MN6.

[0010] The present invention provides another technical solution: a method for optimizing a power-on reset circuit, comprising the following steps:

[0011] S1: Before the reset signal is pulled high, Vy=Vx+I1*(R2+R1+R3) in the PTAT current generating circuit, Vih1=K*I1, and after the reset signal is pulled high, Vy=Vx+I2*(R2+ R1), Vih2=K*I2; Since K*I2>K*I1, Vih2>Vih1, the conditions for external interference to generate a reset signal are improved to protect the normal reset signal operation; Among them, Vy is the gate voltage of transistor MP2, that is, the detection voltage of the startup circuit, Vx is the gate voltage of transistor NM1, I1 is the bias current generated by the PTAT current generating circuit, that is, the current between the drain and source of transistor MP6, I1=(Vgs_NM2-Vgs_NM1) / (R1+R3), where Vgs_N M2 is the voltage between the gate and source of transistor NM2, Vgs_NM1 is the voltage between the gate and source of transistor NM1, Vih1 is the detection threshold voltage, K is the equivalent detection resistor, when the power supply voltage exceeds this threshold voltage, the reset signal state starts to flip from low level to high level; after the reset is pulled high, since the R3 resistor is bypassed, the bias current generated by the PTAT current generating circuit changes, I2=(Vgs_NM2-Vgs_NM1) / R1, Vih2 is the detection threshold voltage after the reset is pulled high;

[0012] S2: After the reset signal is pulled high, it is connected to the MOS tube MP11 in the delay circuit through the inverter INV1 and the inverter INV2 in the voltage detection circuit. When the POR signal of the Schmitt trigger circuit is at a low level, it will not bring additional power consumption. After the reset is released, it can produce a pull-up effect to better protect the POR signal from interference;

[0013] S3: The signal output to the delay circuit through the inverter INV1 and the inverter INV2 is pulled up through the MOS tube MP9, and the source and drain currents of the MOS tube MP9 can be controlled by controlling the number of the MOS tubes MP9, thereby controlling the speed of charging the capacitor, and further controlling the signal pull-up time, thereby achieving the purpose of controlling the low level effective time of the POR signal of the circuit.

[0014] Compared with the prior art, the present invention has the following beneficial effects:

[0015] The present invention proposes a power-on reset circuit and an optimization method. The startup circuit is realized by a differential circuit, thereby ensuring the stability of the startup circuit. The PTAT current generation circuit is independent of temperature under a certain temperature condition, and the MOS tube is designed in a sub-threshold region to reduce the circuit voltage and power consumption. The voltage detection circuit compares the KI point with the input thresholds of the series inverter INV1 and the inverter INV2 to generate the required logic signal, and the reset time can be adjusted by a delay circuit. Finally, the Schmitt trigger circuit ensures that the output signal has no burrs. Therefore, the circuit realizes low power supply voltage, low power consumption, voltage threshold hysteresis, and adjustable delay, and can be generally used in integrated circuits as a module circuit or a dedicated reset ASIC. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic diagram of the power-on reset circuit structure of the present invention;

[0017] Figure 2 A power-on reset threshold hysteresis circuit diagram of the present invention;

[0018] Figure 3 A power-on reset anti-interference circuit diagram of the present invention;

[0019] Figure 4 This is a power-on reset delay adjustment circuit diagram of the present invention.

[0020] In the figure: 1. Start-up circuit; 2. PTAT current generating circuit; 3. Voltage detection circuit; 4. Delay circuit. DETAILED DESCRIPTION

[0021] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Example

[0022] See also Figure 1A power-on reset circuit includes a startup circuit 1, a PTAT current generating circuit 2, a voltage detection circuit 3 and a delay circuit 4. The startup circuit 1 includes a MOS tube MP1, a MOS tube MP2, a MOS tube MP3 and a MOS tube MP4, wherein the gate of the MOS tube MP3 is connected to ground, the sources of the MOS tube MP3 and the MOS tube MP4 are connected to a power supply voltage VH, the MOS tube MP3 is connected to the drain of the MOS tube MP4, the MOS tube MP1 is connected to the source of the MOS tube MP2, the drain of the MOS tube MP1 is connected to ground, the drain circuit interface of the MOS tube MP3 and the MOS tube MP4 is connected to the source circuit interface of the MOS tube MP1 and the MOS tube MP2, the MOS tube MP4 is connected to the gate of the MOS tube MP9, the gate of the MOS tube MP1 is connected to the gate circuit interface of the MOS tube MN2, the gate of the MOS tube MP2 is connected to the drain circuit interface of the MOS tube MP6, and the drain of the MOS tube MP2 is connected to the source circuit interface of the MOS tube MN2.

[0023] The PTAT current generating circuit 2 comprises a MOS transistor MP5, a MOS transistor MP6, a MOS transistor MN1 and a MOS transistor MN2, wherein the source electrodes of the MOS transistor MP5 and the MOS transistor MP6 are connected to a power supply voltage VH, the gate electrode of the MOS transistor MP5 and the MOS transistor MP6 are connected, the drain electrode of the MOS transistor MN1 is connected to the drain electrode of the MOS transistor MP5, the source electrodes of the MOS transistor MN1 and the MOS transistor MN2 are connected to ground, the source electrode of the MOS transistor MN2 is connected to a resistor R1 and a resistor R2 in series, and then to a drain electrode of the MOS transistor MP6, the gate electrode of the MOS transistor MN2 is connected to a circuit interface of the resistor R1 and the resistor R2 in series, and the gate circuit interface of the MOS transistor MP5 and the MOS transistor MP6 is connected to a gate circuit interface of the MOS transistor MP4 and the MOS transistor MP9.

[0024] The voltage detection circuit 3 includes MOS transistor MP7, MOS transistor MP8, MOS transistor MN3, MOS transistor MN4, MOS transistor MN5, inverter INV1 and inverter INV2. Among them, the sources of MOS transistors MP7 and MP8 are connected to the power supply voltage VH. The drain of MOS transistor MP7 is connected to resistor R4. Resistor R4 is connected to the gate and drain of MOS transistor MN4. The source of MOS transistor MN4 is connected to the gate and drain of MOS transistor MN3. The sources of MOS transistors MN3 and MN5 are connected to ground. The gates of MOS transistors MN3 and MN5 are connected to each other. The drain of MOS transistor MN5 is connected to the drain of MOS transistor MP8. The circuit interface where MOS transistor MN5 is connected to MOS transistor MP8 is connected to the series-connected inverters INV1 and INV2. The gates of MOS transistors MP7 and MP8 are connected to the gate circuit interface of MOS transistors MP4 and MP9. The series-connected inverters INV1 and INV2 are connected to the gate circuit interface of MOS transistors MP10 and MN6.

[0025] The delay circuit 4 includes MOS transistor MP9, MOS transistor MP10, MOS transistor MN6 and MOS transistor MN7. Among them, the source of MOS transistor MP9 is connected to the power supply voltage VH. The drain of MOS transistor MP9 is connected to the source of MOS transistor MP10. The gates of MOS transistors MP10 and MN6 are connected to each other. The drain of MOS transistor MP10 is connected to the drain of MOS transistor MN6. The source of MOS transistor MN6 is connected to ground. The source and drain of MOS transistor MN7 are connected to ground.

[0026] Circuit principle: During the rising process of the power supply voltage, the gate of MOS transistor MP3 is grounded. When the power supply voltage reaches the threshold voltage Vthmp3 of MOS transistor MP3, MOS transistor MP3 conducts. If both MOS transistors MN1 and MN2 are operating in the cut-off region, then Vx = Vy < Vthmn1; if at least one of MOS transistors MN1 or MN2 is not operating in the cut-off region, then Vy ≈ Vy ≈ VNth, I ≈ 0, and MN1 or MN2 is operating in the sub-threshold region. In both of the above cases, when VH ≥ Vthmp2 + Vdsmp3 + Vy, MP2 starts to conduct, and MOS transistors MN1 and MN2 start to operate, completing the voltage startup. Therefore, when the power supply voltage satisfies VH ≥ Vthmp2 + Vthmn2, that is, the sum of the threshold voltage values of one PMOS and NMOS, the circuit can operate.

[0027] For the MOS tube MN2, Vdsmn2 = Vgsmn2 - I*R1, so the tube will always work in the subthreshold region, and Vy=I*R2+Vgsmn2; as the gate voltage Vz of the MOS tube MN1 increases, the MOS tube MN1 is turned on, so that the gate voltages of the MOS tubes MP4, MP5 and MP6 are reduced, but the power supply will quickly increase the gate voltages of the MOS tubes MP4, MP5 and MP6 through the MOS tube MP5, so the gate voltages of the MOS tubes MP4, MP5, MP6, MP7, MP8 and MP9 will quickly continue to rise with the power supply after a short drop, and the current I will continue to increase until it is stable; compared with the commonly used circuit tubes working in the saturation region, the MOS tube MN2 works in the subthreshold region to reduce the circuit current, thereby saving power consumption.

[0028] As the gate voltage of the MOS tube MP7 gradually increases, the gate voltages of the MOS tube MN3 and the MOS tube MN5 will also gradually increase. Due to the effect of the resistor R4, the drain of the MOS tube MN5 is pulled down while ensuring that the Vsense voltage is not pulled too low, thereby ensuring that the current passing through the resistor R4 does not lose too much power consumption, thereby making the level through the inverter INV1 pulled from high to low. The rising and falling edges of the signal are steeper after passing through the two-stage inverters; and the delay circuit 4 part can control the low level time point by controlling the pull-up strength to ensure the system reset time. The final Schmitt trigger adopts a traditional circuit, which can be used to filter the jitter or interference of the generated reset signal.

[0029] In order to better demonstrate the optimization process of the power-on reset circuit, the present invention proposes an optimization method for the power-on reset circuit, comprising the following steps:

[0030] S1: Before the reset signal is pulled high, Vy=Vx+I1*(R2+R1+R3) in the PTAT current generating circuit 2, Vih1=K*I1, and after the reset signal is pulled high, Vy=Vx+I2*(R2+ R1), Vih2=K*I2; Since K*I2>K*I1, Vih2>Vih1, the reset signal generation condition of external interference is improved to protect the normal reset signal operation; Among them, Vy is the gate voltage of transistor MP2, that is, the detection voltage of the startup circuit 1, Vx is the gate voltage of transistor NM1, I1 is the bias current generated by the PTAT current generating circuit 2, that is, the current between the drain and source of transistor MP6, I1=(Vgs_NM2-Vgs_NM1) / (R1+R3), where Vgs_ NM2 is the voltage between the gate and source of transistor NM2, Vgs_NM1 is the voltage between the gate and source of transistor NM1, Vih1 is the detection threshold voltage, K is the equivalent detection resistor, and when the power supply voltage exceeds this threshold voltage, the reset signal state starts to flip from a low level to a high level; after the reset is pulled high, since the R3 resistor is bypassed, the bias current generated by the PTAT current generating circuit 2 changes, I2=(Vgs_NM2-Vgs_NM1) / R1, Vih2 is the detection threshold voltage after the reset is pulled high;

[0031] S2: After the reset signal is pulled high, it is connected to the MOS tube MP11 in the delay circuit 4 through the inverter INV1 and the inverter INV2 in the voltage detection circuit 3. When the POR signal of the Schmitt trigger circuit is at a low level, it will not bring additional power consumption. After the reset is released, it can produce a pull-up effect to better protect the POR signal from interference;

[0032] S3: The signal output to the delay circuit 4 through the inverter INV1 and the inverter INV2 is pulled up through the MOS tube MP9, and the source and drain currents of the MOS tube MP9 can be controlled by controlling the number of the MOS tubes MP9, thereby controlling the speed of charging the capacitor, and further controlling the signal pull-up time, so as to achieve the purpose of controlling the low level effective time of the POR signal of the circuit. Example

[0033] See also Figure 2A power-on reset circuit includes a startup circuit 1, a PTAT current generating circuit 2, a voltage detection circuit 3 and a delay circuit 4. The startup circuit 1 includes a MOS tube MP1, a MOS tube MP2, a MOS tube MP3 and a MOS tube MP4, wherein the gate of the MOS tube MP3 is connected to ground, the sources of the MOS tube MP3 and the MOS tube MP4 are connected to a power supply voltage VH, the MOS tube MP3 is connected to the drain of the MOS tube MP4, the MOS tube MP1 is connected to the source of the MOS tube MP2, the drain of the MOS tube MP1 is connected to ground, the drain circuit interface of the MOS tube MP3 and the MOS tube MP4 is connected to the source circuit interface of the MOS tube MP1 and the MOS tube MP2, the MOS tube MP4 is connected to the gate of the MOS tube MP9, the gate of the MOS tube MP1 is connected to the gate circuit interface of the MOS tube MN2, the gate of the MOS tube MP2 is connected to the drain circuit interface of the MOS tube MP6, and the drain of the MOS tube MP2 is connected to the source circuit interface of the MOS tube MN2.

[0034] The PTAT current generating circuit 2 comprises a MOS transistor MP5, a MOS transistor MP6, a MOS transistor MN1, a MOS transistor MN2 and a MOS transistor MN8, wherein the sources of the MOS transistors MP5 and MP6 are connected to a power supply voltage VH, the gate of the MOS transistor MP5 and the MOS transistor MP6 are connected, the drain of the MOS transistor MN1 is connected to the drain of the MOS transistor MP5, the sources of the MOS transistors MN1 and MN2 are connected to ground, the source of the MOS transistor MN2 is connected to a resistor R1, a resistor R2 and a resistor R3 in series, and then to the drain of the MOS transistor MP6, the gate of the MOS transistor MN2 is connected to a circuit interface of the resistor R1, the resistor R2 and the resistor R3 in series, the gate circuit interface of the MOS transistors MP5 and MP6 is connected to a gate circuit interface of the MOS transistor MP4, the drain of the MOS transistor MN8 is connected to a circuit interface of the resistor R3, the source of the MOS transistor MN8 is connected to a drain circuit interface of the MOS transistor MN2, and the gate of the MOS transistor MN8 is connected to a Schmitt trigger circuit.

[0035] The voltage detection circuit 3 includes a MOS transistor MP7, a MOS transistor MP8, a MOS transistor MN3, a MOS transistor MN4, a MOS transistor MN5, an inverter INV1 and an inverter INV2, wherein the sources of the MOS transistors MP7 and MP8 are connected to a power supply voltage VH, the drain of the MOS transistor MP7 is connected to a resistor R4, the resistor R4 is connected to the gate and the drain of the MOS transistor MN4, the source of the MOS transistor MN4 is connected to the gate and the drain of the MOS transistor MN3, the sources of the MOS transistors MN3 and MN5 are connected to ground, the gate of the MOS transistor MN3 and the MOS transistor MN5 are connected, the drain of the MOS transistor MN5 is connected to the drain of the MOS transistor MP8, the circuit interface connecting the MOS transistors MN5 and MP8 is connected to the inverters INV1 and INV2 connected in series, the gates of the MOS transistors MP7 and MP8 are connected to the gate circuit interface of the MOS transistor MP4, and the inverters INV1 and INV2 connected in series are connected to the gate circuit interface of the MOS transistor MP10 and the MOS transistor MN6.

[0036] The delay circuit 4 includes a MOS transistor MP9, a MOS transistor MP10, a MOS transistor MP11, a MOS transistor MN6 and a MOS transistor MN7, wherein the source and gate of the MOS transistor MP9 and the MOS transistor MP11 are connected to the power supply voltage VH, the drain of the MOS transistor MP9 is connected to the source of the MOS transistor MP10, the drain of the MOS transistor MP11 is connected to the gate of the MOS transistor MN7, the MOS transistor MP10 is connected to the gate of the MOS transistor MN6, the drain of the MOS transistor MP10 is connected to the drain of the MOS transistor MN6, the source of the MOS transistor MN6 is connected to the ground, and the source and drain of the MOS transistor MN7 are connected to the ground.

[0037] In the above circuit, before the reset signal is pulled high, Vy=Vx+I1*(R2+R11+R12) and Vih1=K*I1 in the PTAT current generating circuit 2, and after the reset signal is pulled high, Vy=Vx+I2*(R2+R11) and Vih2=K*I2; since K*I2>K*I1 and Vih2>Vih1, the conditions for generating a reset signal due to external interference can be improved to protect the normal operation of the reset signal. Example

[0038] See also Figure 3A power-on reset circuit includes a startup circuit 1, a PTAT current generating circuit 2, a voltage detection circuit 3 and a delay circuit 4. The startup circuit 1 includes a MOS tube MP1, a MOS tube MP2, a MOS tube MP3 and a MOS tube MP4, wherein the gate of the MOS tube MP3 is connected to ground, the sources of the MOS tube MP3 and the MOS tube MP4 are connected to a power supply voltage VH, the MOS tube MP3 is connected to the drain of the MOS tube MP4, the MOS tube MP1 is connected to the source of the MOS tube MP2, the drain of the MOS tube MP1 is connected to ground, the drain circuit interface of the MOS tube MP3 and the MOS tube MP4 is connected to the source circuit interface of the MOS tube MP1 and the MOS tube MP2, the MOS tube MP4 is connected to the gate of the MOS tube MP9, the gate of the MOS tube MP1 is connected to the gate circuit interface of the MOS tube MN2, the gate of the MOS tube MP2 is connected to the drain circuit interface of the MOS tube MP6, and the drain of the MOS tube MP2 is connected to the source circuit interface of the MOS tube MN2.

[0039] The PTAT current generating circuit 2 comprises a MOS transistor MP5, a MOS transistor MP6, a MOS transistor MP12, a MOS transistor MN1 and a MOS transistor MN2, wherein the sources of the MOS transistors MP5 and MP6 are connected to a power supply voltage VH, the MOS transistors MP5 and MP6 are connected to a gate, the drain of the MOS transistor MN1 is connected to the drain of the MOS transistor MP5, the sources of the MOS transistors MN1 and MN2 are connected to ground, the source of the MOS transistor MN2 is connected to a resistor R1, a resistor R2 and a resistor R3 in series, and then to the drain of the MOS transistor MP6, the gate of the MOS transistor MN2 is connected to a circuit interface of the resistor R1, the resistor R2 and the resistor R3 in series, the gate circuit interface of the MOS transistors MP5 and MP6 is connected to a gate circuit interface of the MOS transistor MP4, the source of the MOS transistor MP12 is connected to a circuit interface of the resistor R3, the drain of the MOS transistor MP12 is connected to a source circuit interface of the MOS transistor MN2, and the gate of the MOS transistor MP12 is connected to a Schmitt trigger circuit.

[0040] The voltage detection circuit 3 includes a MOS transistor MP7, a MOS transistor MP8, a MOS transistor MN3, a MOS transistor MN4, a MOS transistor MN5, an inverter INV1 and an inverter INV2, wherein the sources of the MOS transistors MP7 and MP8 are connected to a power supply voltage VH, the drain of the MOS transistor MP7 is connected to a resistor R4, the resistor R4 is connected to the gate and the drain of the MOS transistor MN4, the source of the MOS transistor MN4 is connected to the gate and the drain of the MOS transistor MN3, the sources of the MOS transistors MN3 and MN5 are connected to ground, the gate of the MOS transistor MN3 and the MOS transistor MN5 are connected, the drain of the MOS transistor MN5 is connected to the drain of the MOS transistor MP8, the circuit interface connecting the MOS transistors MN5 and MP8 is connected to the inverters INV1 and INV2 connected in series, the gates of the MOS transistors MP7 and MP8 are connected to the gate circuit interface of the MOS transistor MP4, and the inverters INV1 and INV2 connected in series are connected to the gate circuit interface of the MOS transistor MP10 and the MOS transistor MN6.

[0041] The delay circuit 4 includes a MOS transistor MP9, a MOS transistor MP10, a MOS transistor MP11, a MOS transistor MN6 and a MOS transistor MN7, wherein the sources of the MOS transistor MP9 and the MOS transistor MP11 are connected to the power supply voltage VH, the drain of the MOS transistor MP9 is connected to the source of the MOS transistor MP10, the drain of the MOS transistor MP11 is connected to the gate of the MOS transistor MN7 and then connected to the Schmitt trigger circuit, the gate of the MOS transistor MP11 is connected to the Schmitt trigger circuit, the MOS transistor MP10 is connected to the gate of the MOS transistor MN6 and then connected to the Schmitt trigger circuit, the drain of the MOS transistor MP10 is connected to the drain of the MOS transistor MN6, the source of the MOS transistor MN6 is connected to the ground, and the source and drain of the MOS transistor MN7 are connected to the ground.

[0042] In the above circuit, after the reset signal is pulled high, it is connected to the MOS tube MP11 of 4 in the delay circuit through the inverter INV1 and the inverter INV2 in the voltage detection circuit 3. When the POR signal of the Schmitt trigger circuit is at a low level, it will not bring additional power consumption. After the reset is released, it can produce a pull-up effect to better protect the POR signal from interference. Example

[0043] See also Figure 4A power-on reset circuit includes a startup circuit 1, a PTAT current generating circuit 2, a voltage detection circuit 3 and a delay circuit 4. The startup circuit 1 includes a MOS tube MP1, a MOS tube MP2, a MOS tube MP3 and a MOS tube MP4, wherein the gate of the MOS tube MP3 is connected to ground, the sources of the MOS tube MP3 and the MOS tube MP4 are connected to a power supply voltage VH, the MOS tube MP3 is connected to the drain of the MOS tube MP4, the MOS tube MP1 is connected to the source of the MOS tube MP2, the drain of the MOS tube MP1 is connected to ground, the drain circuit interface of the MOS tube MP3 and the MOS tube MP4 is connected to the source circuit interface of the MOS tube MP1 and the MOS tube MP2, the MOS tube MP4 is connected to the gates of the MOS tubes MP9-1, MP9-2 and MP9-3, the gate of the MOS tube MP1 is connected to the gate circuit interface of the MOS tube MN2, the gate of the MOS tube MP2 is connected to the drain circuit interface of the MOS tube MP6, and the drain of the MOS tube MP2 is connected to the source circuit interface of the MOS tube MN2.

[0044] The PTAT current generating circuit 2 comprises a MOS transistor MP5, a MOS transistor MP6, a MOS transistor MN1 and a MOS transistor MN2, wherein the sources of the MOS transistors MP5 and MP6 are connected to a power supply voltage VH, the gate of the MOS transistor MP5 and the MOS transistor MP6 are connected, the drain of the MOS transistor MN1 is connected to the drain of the MOS transistor MP5, the sources of the MOS transistors MN1 and MN2 are connected to ground, the source of the MOS transistor MN2 is connected to a resistor R1 and a resistor R2 in series and then to a drain of the MOS transistor MP6, the gate of the MOS transistor MN2 is connected to a circuit interface of the resistor R1 and the resistor R2 in series, and the gate circuit interface of the MOS transistors MP5 and MP6 is connected to the gate circuit interface of the MOS transistor MP4.

[0045] The voltage detection circuit 3 includes a MOS transistor MP7, a MOS transistor MP8, a MOS transistor MN3, a MOS transistor MN4, a MOS transistor MN5, an inverter INV1 and an inverter INV2, wherein the sources of the MOS transistors MP7 and MP8 are connected to a power supply voltage VH, the drain of the MOS transistor MP7 is connected to a resistor R4, the resistor R4 is connected to a gate and a drain of the MOS transistor MN4, the source of the MOS transistor MN4 is connected to a gate and a drain of the MOS transistor MN3, the sources of the MOS transistors MN3 and MN5 are connected to ground, the gate of the MOS transistor MN3 is connected to the gate of the MOS transistor MN5, the drain of the MOS transistor MN5 is connected to the drain of the MOS transistor MP8, the circuit interface connecting the MOS transistors MN5 and MP8 is connected to the inverters INV1 and INV2 connected in series, the gates of the MOS transistors MP7 and MP8 are connected to the gate circuit interface of the MOS transistor MP4, and the inverters INV1 and INV2 connected in series are connected to the gate circuit interface of the MOS transistor MP10 and the MOS transistor MN6.

[0046] The delay circuit 4 includes a MOS transistor MP9-1, a MOS transistor MP9-2, a MOS transistor MP9-3, a MOS transistor MP10, a MOS transistor MN6 and a MOS transistor MN7, wherein the sources of the MOS transistors MP9-1, MP9-2 and MP9-3 are connected to the power supply voltage VH, the drains of the MOS transistors MP9-1, MP9-2 and MP9-3 are connected to the source of the MOS transistor MP10, the MOS transistor MP10 is connected to the gate of the MOS transistor MN6, the drain of the MOS transistor MP10 is connected to the drain of the MOS transistor MN6, the source of the MOS transistor MN6 is connected to the ground, and the source and drain of the MOS transistor MN7 are connected to the ground.

[0047] In the above circuit, the signal output to the delay circuit 4 through the inverter INV1 and the inverter INV2 is pulled up through MP9, and controlling the number of MP9 can control the source and drain currents of MP9, thereby controlling the speed of charging the capacitor, and then controlling the signal pull-up time, thereby achieving the purpose of controlling the low level effective time of the POR signal of the Schmitt trigger circuit.

[0048] In summary: in this power-on reset circuit, the startup circuit 1 is realized by a differential circuit, which ensures the stability of the startup circuit 1; the PTAT current generating circuit 2 is independent of temperature under a certain temperature condition, and the MOS tube is designed in the subthreshold region to reduce the circuit voltage and power consumption; the voltage detection circuit 3 compares the KI point with the input threshold of the series inverter INV1 and the inverter INV2 to generate the required logic signal, and the reset time can be adjusted by the delay circuit 4, and the final Schmitt trigger circuit ensures that the output signal has no burrs; therefore, this circuit realizes low power supply voltage, low power consumption, voltage threshold hysteresis, and adjustable delay, and can be widely used in integrated circuits as a module circuit or a dedicated reset ASIC.

[0049] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A power-on reset circuit, comprising a startup circuit (1), a PTAT current generating circuit (2), a voltage detection circuit (3), and a delay circuit (4), characterized in that: The startup circuit (1) comprises a MOS transistor MP1, a MOS transistor MP2, a MOS transistor MP3 and a MOS transistor MP4, wherein the gate of the MOS transistor MP3 is connected to the ground, the sources of the MOS transistor MP3 and the MOS transistor MP4 are connected to the power supply voltage VH, the drain of the MOS transistor MP3 and the MOS transistor MP4 are connected, the MOS transistor MP1 is connected to the source of the MOS transistor MP2, and the drain of the MOS transistor MP1 is connected to the ground; The PTAT current generating circuit (2) comprises a MOS transistor MP5, a MOS transistor MP6, a MOS transistor MN1, a MOS transistor MN2 and a MOS transistor MN8, wherein the source electrodes of the MOS transistors MP5 and MP6 are connected to a power supply voltage VH, the gate electrodes of the MOS transistors MP5 and MP6 are connected, the drain electrode of the MOS transistor MN1 is connected to the drain electrode of the MOS transistor MP5, the source electrodes of the MOS transistors MN1 and MN2 are connected to ground, the drain electrode of the MOS transistor MN2 is connected to a resistor R1, a resistor R2 and a resistor R3 in series, and then to the drain electrode of the MOS transistor MP6, the gate electrode of the MOS transistor MN2 is connected to a circuit interface of the resistor R1, the resistor R2 and the resistor R3 in series, the gate circuit interface of the MOS transistors MP5 and MP6 is connected to a gate circuit interface of the MOS transistor MP4, the drain electrode of the MOS transistor MN8 is connected to a circuit interface of the resistor R3, the source electrode of the MOS transistor MN8 is connected to a circuit interface of the resistor R4, The drain circuit interface of the MOS tube MN2, the gate of the MOS tube MN8 is connected to the Schmitt trigger circuit; the voltage detection circuit (3) comprises a MOS tube MP7, a MOS tube MP8, a MOS tube MN3, a MOS tube MN4, a MOS tube MN5, an inverter INV1 and an inverter INV2, wherein the source electrodes of the MOS tubes MP7 and MP8 are connected to the power supply voltage VH, the drain electrode of the MOS tube MP7 is connected to the resistor R4, the resistor R4 is connected to the gate and the drain electrode of the MOS tube MN4, the source electrode of the MOS tube MN4 is connected to the gate and the drain electrode of the MOS tube MN3, the source electrodes of the MOS tubes MN3 and MN5 are connected to the ground, the MOS tubes MN3 and MN5 are connected to the gate electrode, the drain electrode of the MOS tube MN5 is connected to the drain electrode of the MOS tube MP8, and the circuit interface connecting the MOS tubes MN5 and MP8 is connected to the inverters INV1 and INV2 connected in series; The delay circuit (4) comprises a MOS transistor MP9, a MOS transistor MP10, a MOS transistor MN6, a MOS transistor MN7, a MOS transistor MP11 and a Schmitt trigger circuit, wherein the source of the MOS transistor MP9 is connected to a power supply voltage VH, the drain of the MOS transistor MP9 is connected to the source of the MOS transistor MP10, the MOS transistor MP10 is connected to the gate of the MOS transistor MN6, the drain of the MOS transistor MP10 is connected to the drain of the MOS transistor MN6, the source of the MOS transistor MN6 is connected to ground, and the source and drain of the MOS transistor MN7 are connected to ground; The POR signal of the Schmitt trigger circuit is connected to the gate of the MOS tube MP11 through an inverter, wherein the drain circuit interface of the MOS tube MP3 and the MOS tube MP4 is connected to the source circuit interface of the MOS tube MP1 and the MOS tube MP2, and the MOS tube MP4 is connected to the gate of the MOS tube MP9; the gate of the MOS tube MP1 is connected to the gate circuit interface of the MOS tube MN2, the gate of the MOS tube MP2 is connected to the drain circuit interface of the MOS tube MP6, and the drain of the MOS tube MP2 is connected to the drain circuit interface of the MOS tube MN2; the gate circuit interface of the MOS tube MP5 and the MOS tube MP6 is connected to the gate circuit interface of the MOS tube MP4; the gate of the MOS tube MP7 and the MOS tube MP8 is connected to the gate circuit interface of the MOS tube MP4; the series-connected inverters INV1 and INV2 are connected to the gate circuit interface of the MOS tube MP10 and the MOS tube MN6.

2. A method for optimizing a power-on reset circuit as claimed in claim 1, characterized in that: The following steps are involved: S1: Before the reset signal is pulled high, Vy=Vx+I1*(R2+R1+R3) in the PTAT current generating circuit (2), Vih1=K*I1, and after the reset signal is pulled high, Vy=Vx+I2*(R2+ R1), Vih2=K*I2; since K*I2>K*I1, Vih2>Vih1, the conditions for generating the reset signal by external interference are improved, protecting the normal operation of the reset signal; Wherein, Vy is the gate voltage of transistor MP2, i.e., the detection voltage of the startup circuit (1), Vx is the gate voltage of transistor NM1, I1 is the bias current generated by the PTAT current generating circuit (2), i.e., the current between the drain and source of transistor MP6, I1=(Vgs_NM2-Vgs_NM1) / (R1+R3), where Vgs_NM2 is the voltage between the gate and source of transistor NM2, Vgs_NM1 is the voltage between the gate and source of transistor NM1, Vih1 is the detection threshold voltage, K is the equivalent detection resistor, and when the power supply voltage exceeds this threshold voltage, the reset signal state starts to flip from a low level to a high level; after the reset is pulled high, since the R3 resistor is bypassed, the bias current generated by the PTAT current generating circuit (2) changes, I2=(Vgs_NM2-Vgs_NM1) / R1, Vih2 is the detection threshold voltage after the reset is pulled high; S2: After the reset signal is pulled high, it is connected to the MOS tube MP11 in the delay circuit (4) through the inverter INV1 and the inverter INV2 in the voltage detection circuit (3). When the POR signal of the Schmitt trigger circuit is at a low level, it will not cause additional power consumption. After the reset is released, it can produce a pull-up effect, thereby better protecting the POR signal from interference. S3: The signal output to the delay circuit (4) through the inverter INV1 and the inverter INV2 is pulled up through the MOS tube MP9. By controlling the number of the MOS tubes MP9, the source and drain currents of the MOS tubes MP9 can be controlled, thereby controlling the speed of charging the capacitor, and further controlling the signal pull-up time, thereby achieving the purpose of controlling the low level effective time of the POR signal of the circuit.

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