Power-on reset and reference voltage composite function circuit based on current comparison and application of power-on reset and reference voltage composite function circuit

Abstract

The invention discloses a power-on reset and reference voltage composite function circuit based on current comparison and application thereof, and the circuit comprises a comparison current and reference voltage generation module, a following current generation module, a current comparison module and a signal output module which are respectively connected with a power circuit. The comparison current and reference voltage generation module generates and outputs stable comparison current and reference voltage, the following current generation module generates following current increasing along with rising of power supply voltage, and the current comparison module generates and outputs a comparison result of the comparison current and the following current. The signal output module generates and outputs a power-on reset signal or a power-off detection signal. Effective power-on reset and power-off detection can be achieved, stable reference voltage can be output, in addition, power-on threshold voltage in the circuit can obtain effective temperature compensation and is not affected by temperature, and the circuit is simple in structure and high in reliability and has high practical value and wide application prospects.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit design, and in particular to a power-on reset and reference voltage composite function circuit based on current comparison and application thereof. Background Art

[0002] With the development of science and technology, integrated circuits have become the basis for all walks of life to realize informatization and intelligence. In the design of integrated circuits, the power-on reset circuit occupies an important position in the chip. When the power supply of the chip rises to a certain level, which is enough for the chip to work normally, the power-on reset circuit outputs a signal to refresh some digital modules of the chip and give the digital modules some initial states. In addition, the reference circuit is also a basic and necessary module of the chip, which provides a voltage that is independent of temperature and process for the chip to use in other modules of the chip.

[0003] The existing power-on reset circuit has a relatively simple function and cannot output the reference voltage at the same time. In addition, the power-on threshold voltage is greatly affected by temperature changes, and the chip operation is unstable. Therefore, designing a composite functional, stable and simple power-on reset circuit has become an urgent problem to be solved. Summary of the invention

[0004] In view of the deficiencies of the prior art, the present invention provides a power-on reset and reference voltage composite function circuit based on current comparison, which can effectively power-on reset and output reference voltage, and can achieve that the power-on threshold voltage is not affected by temperature.

[0005] The present invention solves the technical problem by adopting the following technical solution:

[0006] The present invention provides a power-on reset and reference voltage composite function circuit based on current comparison, comprising a comparison current and reference voltage generation module, a follow-up current generation module, a current comparison module and a signal output module respectively connected to a power supply circuit, wherein:

[0007] The comparison current and reference voltage generation module is configured to generate and output a stable comparison current and reference voltage after the power supply circuit is powered on;

[0008] The following current generating module is configured to generate a following current that increases as the power supply voltage rises;

[0009] The current comparison module is configured to generate and output a comparison result between the comparison current and the follow-up current during power-on or power-off of the power supply circuit;

[0010] The signal output module is configured to generate and output a power-on reset signal or a power-down detection signal based on the comparison result.

[0011] Preferably, the comparison current and the follow-up current are both positively correlated with the temperature;

[0012] The reference voltage is a bandgap reference voltage, which is modulated based on a comparison current and a device voltage with a negative temperature coefficient.

[0013] Preferably, when the power supply voltage exceeds the power-on threshold voltage V por When the following current is greater than the comparison current, the signal output module outputs a power-on reset signal;

[0014] When the supply voltage drops below the power-on threshold voltage V por When the following current is less than the comparison current, the signal output module outputs a power-off detection signal.

[0015] Preferably, the temperature coefficient of the comparison current is constant, the temperature coefficient of the follow-up current is adjustable, and the power-on threshold voltage V por Not related to temperature.

[0016] Preferably, the comparison current and reference voltage generation module specifically includes PMOS tubes PM1-PM8, transistors Q1-Q3, NMOS tube NM2, and resistors R1-R3, wherein:

[0017] The PMOS tubes PM1, PM3, PM5 and PM7 share a common source terminal and are connected to a power supply circuit;

[0018] The drain ends of the PMOS tubes PM1, PM3, PM5 and PM7 are connected to the source ends of PM2, PM4, PM6 and PM8 respectively;

[0019] The PMOS tubes PM1, PM3, PM5 and PM7 have a common gate end and are connected to the drain end of PM2 and connected to one end of the resistor R1; the PM2, PM4, PM6 and PM8 have a common gate end and are connected to the collector of the transistor Q3 and connected to one end of the resistor R1;

[0020] The transistors Q1 and Q3 have a common emitter and are connected to a common ground terminal through a resistor R2;

[0021] The transistors Q1 and Q2 have a common base and are connected to the collector of Q1 and one end of the resistor R3;

[0022] The other end of the resistor R3 is connected to the drain end of the PMOS transistor PM4 and serves as a first output node to output a reference voltage;

[0023] The base of the transistor Q3 is connected to the collector of Q2 and connected to the drain of the PMOS transistor PM6;

[0024] The emitter of the transistor Q2 is connected to the source end of the NMOS transistor NM2 and connected to a common ground end;

[0025] The gate terminal and the drain terminal of the NMOS transistor NM2 are connected to each other and connected to the drain terminal of the PMOS transistor PM8.

[0026] Preferably, the comparison current and reference voltage generation module specifically includes PMOS transistors PM1-PM8, transistors Q1 and Q2, NMOS transistors NM1 and NM2, and resistors R1-R3, wherein:

[0027] The PMOS tubes PM1, PM3, PM5 and PM7 share a common source terminal and are connected to a power supply circuit;

[0028] The drain ends of the PMOS tubes PM1, PM3, PM5 and PM7 are connected to the source ends of PM2, PM4, PM6 and PM8 respectively;

[0029] The PMOS tubes PM1, PM3, PM5 and PM7 have a common gate terminal and are connected to the drain terminal of PM2 and connected to one end of the resistor R1; the PM2, PM4, PM6 and PM8 have a common gate terminal and are connected to the drain terminal of the NMOS tube NM1 and connected to one end of the resistor R1;

[0030] The emitter of the transistor Q1 is connected to the source end of the NMOS tube NM1 and connected to the common ground terminal through the resistor R2;

[0031] The transistors Q1 and Q2 have a common base and are connected to the collector of Q1 and one end of the resistor R3;

[0032] The other end of the resistor R3 is connected to the drain end of the PMOS transistor PM4 and serves as an output node to output a reference voltage;

[0033] The gate terminal of the NMOS tube NM1 is connected to the collector of the transistor Q2 and connected to the drain terminal of the PMOS tube PM6;

[0034] The emitter of the transistor Q2 is connected to the source end of the NMOS transistor NM2 and connected to a common ground end;

[0035] The gate terminal and the drain terminal of the NMOS transistor NM2 are connected to each other and connected to the drain terminal of the PMOS transistor PM8.

[0036] Preferably, the following current generating module specifically includes PMOS tubes PM10 and PM11, transistor Q4, resistors R4 and R5, wherein:

[0037] The source end of the PMOS tube PM10 is connected to the power supply circuit;

[0038] The drain end of the PMOS tube PM10 is connected to the source end of PM11, the gate end of the PMOS tube PM10 is connected to the drain end of PM11 and connected to one end of the resistor R4, the gate end of the PMOS tube PM11 is connected to the other end of the resistor R4 and connected to one end of the resistor R5, and the other end of the resistor R5 is connected to the base and collector of the transistor Q4;

[0039] The emitter of the transistor Q4 is connected to the common ground terminal.

[0040] Preferably, the current comparison module specifically includes a PMOS tube PM9 and an NMOS tube NM3, wherein:

[0041] The source end of the PMOS tube PM9 is connected to the power supply circuit and shares a gate end with the PMOS tube PM10;

[0042] The drain ends of the PMOS tube PM9 and the NMOS tube NM3 are connected and serve as a second output node to output the comparison result;

[0043] The NMOS tubes NM3 and NM2 share a gate terminal and a source terminal.

[0044] Preferably, the signal output module specifically comprises an inverter and a buffer, and the output of the inverter and the input of the buffer are cascaded;

[0045] The input of the inverter is connected to the second output node to output the comparison result;

[0046] The output end of the buffer outputs a power-on reset signal or a power-off detection signal.

[0047] The present invention further provides a chip circuit, wherein the chip circuit comprises the aforementioned power-on reset and reference voltage composite function circuit based on current comparison.

[0048] Compared with the prior art, the present invention has the following beneficial effects:

[0049] The present invention uses a designed comparison current and reference voltage generation module, a follower current generation module, a current comparison module and a signal output module to generate a power-on reset signal by comparing the current sizes in a unique comparison manner, and generates a stable reference voltage for chip use while generating the comparison current. In addition, the matching design can ensure that the power-on threshold voltage does not fluctuate with temperature changes, greatly improving the adaptability of the circuit, and can perform efficient power-on reset detection and power-off detection. In addition, the present invention realizes a complex function design with a simple circuit structure, and the circuit has high reliability, high practical value and broad application prospects.

[0050] Other outstanding essential features and significant improvements of the present invention compared to the prior art are further described in detail in the embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings:

[0052] Figure 1 Schematic diagram of the structure of the power-on reset and reference voltage composite function circuit based on current comparison in Example 1;

[0053] Figure 2 A circuit diagram of the first power-on reset and reference voltage composite function circuit based on current comparison in Example 1;

[0054] Figure 3 A circuit diagram of a second power-on reset and reference voltage composite functional circuit based on current comparison in Example 1;

[0055] Figure 4 This is a simulation diagram of the composite functional circuit in Example 1 at -40°C;

[0056] Figure 5 This is a simulation diagram of the composite functional circuit in Example 1 at 25°C;

[0057] Figure 6 This is a simulation diagram of the composite functional circuit in Example 1 at 125°C. DETAILED DESCRIPTION

[0058] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0059] It should be noted that certain names are used in the specification and claims to refer to specific components. It should be understood that a person of ordinary skill in the art may use different names to refer to the same component. The specification and claims of this application do not use differences in names as a way to distinguish components, but use substantial differences in the functions of components as the criterion for distinguishing components. As used in the specification and claims of this application, "including" or "comprising" is an open term, which should be interpreted as "including but not limited to" or "including but not limited to". The embodiments described in the specific implementation section are preferred embodiments of the present invention and are not intended to limit the scope of the present invention.

[0060] Example 1

[0061] like Figure 1As shown, this embodiment provides a power-on reset and reference voltage composite functional circuit based on current comparison, including a comparison current and reference voltage generation module 1, a follower current generation module 2, a current comparison module 3 and a signal output module 4 respectively connected to the power supply circuit.

[0062] In this embodiment, the comparison current and reference voltage generation module 1 is connected to the power supply circuit and is configured to generate and output a stable comparison current I after the power supply circuit is powered on. PTAT1 and reference voltage V BG In this embodiment, the comparison current I PTAT1 Does not change with the power supply voltage, and the comparison current I PTAT1 The temperature coefficient α1 of the comparison current in this embodiment is constant and is determined by the characteristics of the device itself. In addition, the reference voltage in this embodiment is a bandgap reference voltage, which is modulated based on the comparison current and the device voltage with a negative temperature coefficient. The device voltage with a negative temperature coefficient is commonly seen as the base-emitter voltage V of a transistor. be ;

[0063] The following current generating module 2 in this embodiment is configured to generate a following current I increasing as the power supply voltage increases. PTAT2 During the power-on process, as the power supply voltage increases, the following current I PTAT2 Also increases, the following current I PTAT2 It is also positively correlated with the temperature. The following current I PTAT2 The temperature coefficient α2 decreases as the power supply voltage increases, and can be adjusted by adjusting the resistance in the circuit to control the following current I PTAT2 The temperature coefficient α2 and the comparison current I PTAT1 The temperature coefficient α1 is equal to that of the first embodiment, that is, the temperature coefficient α2 is adjustable.

[0064] The current comparison module 3 in this embodiment is configured to generate and output a comparison current I during the power-on or power-off process of the power supply circuit. PTAT1 With the following current I PTAT2 The comparison results of

[0065] The signal output module 4 in this embodiment is configured to generate and output a power-on reset signal or a power-off detection signal based on the comparison result;

[0066] Specifically, in this embodiment, when the power supply voltage exceeds the power-on threshold voltage V por When the following current I PTAT2 Greater than the comparison current I PTAT1 , the signal output module outputs a power-on reset signal;

[0067] When the power supply voltage drops below the power-on threshold voltage V porWhen the following current I PTAT2 Less than the comparison current I PTAT1 , the signal output module outputs the power-off detection signal.

[0068] In this embodiment, by comparing the current I PTAT1 and follower current I PTAT2 Temperature compensation is performed so that the power-on threshold voltage V por Not affected by temperature.

[0069] like Figure 2 As shown in FIG. 3, in this embodiment, the circuit structure of the comparison current and reference voltage generation module 1, the following current generation module 2, the current comparison module 3 and the signal output module 4 is further specifically introduced:

[0070] The comparison current and reference voltage generation module 1 in this embodiment has two structures, such as Figure 2 As shown, one structure specifically includes PMOS tubes PM1-PM8, triodes Q1-Q3, NMOS tubes NM2, and resistors R1-R3, wherein the PMOS tubes PM1, PM3, PM5, and PM7 have a common source terminal and are connected to a power supply circuit;

[0071] The drain terminals of the PMOS tubes PM1, PM3, PM5 and PM7 are connected to the source terminals of PM2, PM4, PM6 and PM8 respectively;

[0072] The PMOS tubes PM1, PM3, PM5 and PM7 have a common gate terminal and are connected to the drain terminal of PM2 and connected to one end of the resistor R1; the PM2, PM4, PM6 and PM8 have a common gate terminal and are connected to the collector of the transistor Q3 and connected to one end of the resistor R1;

[0073] Transistors Q1 and Q3 have a common emitter and are connected to a common ground terminal through resistor R2;

[0074] The transistors Q1 and Q2 have a common base and are connected to the collector of Q1 and to one end of the resistor R3;

[0075] The comparison current in this embodiment is controlled by the base-emitter area ratio of transistors Q1 and Q2. In this embodiment, the area ratio is set to n:1. In this embodiment, the transistors are NPN transistors, and the voltage V between the base and emitter of the transistors is be Has a negative temperature coefficient;

[0076] The other end of the resistor R3 is connected to the drain end of the PMOS transistor PM4 and serves as a first output node VBG to output a reference voltage;

[0077] The base of transistor Q3 is connected to the collector of Q2 and connected to the drain of PMOS tube PM6;

[0078] The emitter of transistor Q2 is connected to the source end of NMOS tube NM2 and connected to the common ground end;

[0079] The gate terminal and the drain terminal of the NMOS tube NM2 are connected to each other and connected to the drain terminal of the PMOS tube PM8.

[0080] In this embodiment, when the power supply is powered on, the power supply voltage V DD When it rises to a certain value, the comparison current I PTAT1 Stable, does not change with power supply voltage

[0081] Among them, the PMOS tubes PM1, PM2 and the resistor R1 form a common source and common gate structure. The structure of the current mirror makes the branch where the PMOS tubes PM1, PM3, PM5 and PM7 are located equal to the comparison current I PTAT1 ;

[0082] The comparison current I in the transistor Q1 and Q2 branches PTAT1 With a positive temperature coefficient, specifically,

[0083]

[0084] Compare the current with the reference voltage V generated in the reference voltage generation module BG ,Specifically,

[0085] V BG =V b e2 +I P TA1 T ×R3

[0086] Therefore, matching the value of R3 can make the reference voltage V BG It does not change with the changes in process and temperature and can be supplied to other modules in the chip.

[0087] like Figure 3 As shown, the second structure of the comparison current and reference voltage generation module 1 in this embodiment specifically includes PMOS tubes PM1-PM8, transistors Q1 and Q2, NMOS tubes NM1 and NM2, and resistors R1-R3. In the second structure, it is equivalent to replacing the transistor Q3 with an NMOS tube NM1, and other connection methods and devices remain unchanged. This design will reduce the area of ​​the first design. People in this field can choose according to their needs, and will not be elaborated here.

[0088] The following current generating module 2 in this embodiment specifically includes PMOS transistors PM10 and PM11, transistor Q4, and resistors R4 and R5, wherein:

[0089] The source end of the PMOS tube PM10 is connected to the power supply circuit;

[0090] The drain end of the PMOS tube PM10 is connected to the source end of PM11, the gate end of the PMOS tube PM10 is connected to the drain end of PM11 and connected to one end of the resistor R4, the gate end of the PMOS tube PM11 is connected to the other end of the resistor R4 and connected to one end of the resistor R5, and the other end of the resistor R5 is connected to the base and collector of the transistor Q4;

[0091] The emitter of transistor Q4 is connected to the common ground terminal.

[0092] Similar to the comparison current and reference voltage generation module 1, the voltage V between the base and emitter of the transistor be With a negative temperature coefficient, the generated follower current I PTAT2 for:

[0093]

[0094] Where V GSp10 is the voltage between the source and gate of the PMOS tube PM10, when the current is stable I PTAT2 After that, PM10 is guaranteed to be in the saturation zone, and PM11 can be in the saturation zone or in the subthreshold zone.

[0095]

[0096] In the above formula, C ox is the capacitance of the polysilicon gate to the substrate, μ p is the hole mobility, which are all device parameters.

[0097]

[0098] That is, the following current I PTAT2 It increases with the supply voltage and also has a positive temperature coefficient.

[0099] In this embodiment, the current comparison module 3 specifically includes a PMOS transistor PM9 and an NMOS transistor NM3, wherein:

[0100] The source end of the PMOS tube PM9 is connected to the power circuit and shares a gate end with the PMOS tube PM10;

[0101] The drain terminals of the PMOS tube PM9 and the NMOS tube NM3 are connected and serve as a second output node to output the comparison result;

[0102] The NMOS tubes NM3 and NM2 share a gate terminal and a source terminal.

[0103] The signal output module 4 in this embodiment specifically includes an inverter and a buffer. The output of the inverter and the input of the buffer are cascaded. The number of the inverter and the number of the buffer in this embodiment are both less than one.

[0104] The input of the inverter is connected to the second output node to output the comparison result;

[0105] The output end of the buffer outputs a power-on reset signal or a power-off detection signal.

[0106] The working principle and process of the above circuit in this embodiment are further analyzed in detail:

[0107] After the power circuit is powered on, the comparison current is established first and stabilized at I PTAT1 , at this time the comparison current I PTAT1 is larger than the following current, and then, the following current I PTAT2 As the power supply voltage rises, it increases until the power supply voltage reaches the power-on threshold voltage V por , followed by the current I PTAT2 Exceeding the comparison current I PTAT1 , the current comparison module 3 flips and the power-on reset is completed.

[0108] Here, due to the comparison current I PTAT1 and follower current I PTAT2 They all have a positive temperature coefficient, so temperature compensation is required;

[0109] In this embodiment, it is necessary to min ,T max ) temperature range in order to obtain effective temperature compensation, the power-on threshold voltage V por Does not change with temperature,

[0110]

[0111] Where α1 is the comparison current temperature coefficient; I Tmax1 The temperature is T max When comparing current I PTAT1 The value of I Tmin1 The temperature is T min When comparing current I PTAT1 The value of I avg1 Yes (T min ,T max ) Interval comparison current I PTAT1 The average value, ΔT = I Tmax -I Tmin .

[0112] α1 is a constant value determined by the characteristics of the transistor itself.

[0113] Re-order

[0114]

[0115] Similarly, α2 is the comparison current temperature coefficient; I Tmax2 The temperature is T max When following current I PTAT2 The value of I Tmin2 The temperature is T min When following current I PTAT2 The value of I avg2 Yes (T min ,T max ) interval following current I PTAT2 The average value, ΔT = I Tmax -I Tmin .

[0116] α2 decreases as the power supply voltage increases, and can be changed by adjusting the values ​​of resistors R4 and R5. por can be ensured by adjusting

[0117] α2=α1

[0118] I PTAT2 =I PTAT1

[0119] So the power-on threshold voltage V por The urine and stool do not change with temperature.

[0120] In order to further verify the superiority of the present invention, the circuit structure of the present invention is simulated and verified. Specifically, Figure 4-6 1 is a schematic diagram of the power-on reset output of an embodiment of the present invention at different temperatures, which simulates the circuit output schematic diagram at -40°C, 25°C, and 125°C respectively. Specifically,

[0121] like Figure 4 As shown in the figure, at -40℃, the power-on simulation diagram is obtained after 1ms power-on, and the power-on point is 2.353V;

[0122] like Figure 5 As shown in the figure, at 25℃, the power-on simulation diagram obtained after 1ms power-on, the power-on point is 2.345V;

[0123] like Figure 6 As shown in the figure, at 125℃, the power-on simulation diagram obtained after 1ms power-on, the power-on point is 2.357V;

[0124] It can be seen from the above that the present invention can effectively perform power-on reset, and the power-on point is very accurate and is minimally affected by temperature.

[0125] Therefore, the above simulation verification can further confirm that the power-on reset and reference voltage composite function circuit based on current comparison in this embodiment can effectively power-on reset and output reference voltage, and can achieve the power-on threshold voltage not being affected by temperature.

[0126] Example 2

[0127] This embodiment provides a chip circuit, which includes a power-on reset and reference voltage composite function circuit based on current comparison as in the above-mentioned embodiment.

[0128] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0129] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A power-on reset and reference voltage composite function circuit based on current comparison, characterized in that: It includes a comparison current and reference voltage generation module, a follow-up current generation module, a current comparison module and a signal output module respectively connected to the power supply circuit, wherein: The comparison current and reference voltage generation module is configured to generate and output a stable comparison current and reference voltage after the power supply circuit is powered on; The following current generating module is configured to generate a following current that increases as the power supply voltage rises; The current comparison module is configured to generate and output a comparison result between the comparison current and the follow-up current during power-on or power-off of the power supply circuit; The signal output module is configured to generate and output a power-on reset signal or a power-down detection signal based on the comparison result.

2. A power-on reset and reference voltage composite function circuit based on current comparison according to claim 1, characterized in that: The comparison current and the follow-up current are both positively correlated with the temperature; The reference voltage is a bandgap reference voltage, which is modulated based on a comparison current and a device voltage with a negative temperature coefficient.

3. A power-on reset and reference voltage composite function circuit based on current comparison according to claim 2, characterized in that: When the power supply voltage exceeds the power-on threshold voltage V por When the following current is greater than the comparison current, the signal output module outputs a power-on reset signal; When the supply voltage drops below the power-on threshold voltage V por When the following current is less than the comparison current, the signal output module outputs a power-off detection signal.

4. A power-on reset and reference voltage composite function circuit based on current comparison according to claim 3, characterized in that: The temperature coefficient of the comparison current is constant, the temperature coefficient of the follow current is adjustable, and the power-on threshold voltage V por Not related to temperature.

5. The power-on reset and reference voltage composite function circuit based on current comparison according to claim 4, characterized in that: The comparison current and reference voltage generation module specifically includes PMOS tubes PM1-PM8, transistors Q1-Q3, NMOS tube NM2, and resistors R1-R3, wherein: The PMOS tubes PM1, PM3, PM5 and PM7 share a common source terminal and are connected to a power supply circuit; The drain ends of the PMOS tubes PM1, PM3, PM5 and PM7 are connected to the source ends of PM2, PM4, PM6 and PM8 respectively; The PMOS tubes PM1, PM3, PM5 and PM7 have a common gate end and are connected to the drain end of PM2 and connected to one end of the resistor R1; the PM2, PM4, PM6 and PM8 have a common gate end and are connected to the collector of the transistor Q3 and connected to one end of the resistor R1; The transistors Q1 and Q3 have a common emitter and are connected to a common ground terminal through a resistor R2; The transistors Q1 and Q2 have a common base and are connected to the collector of Q1 and one end of the resistor R3; The other end of the resistor R3 is connected to the drain end of the PMOS transistor PM4 and serves as a first output node to output a reference voltage; The base of the transistor Q3 is connected to the collector of Q2 and connected to the drain of the PMOS transistor PM6; The emitter of the transistor Q2 is connected to the source end of the NMOS transistor NM2 and connected to a common ground end; The gate terminal and the drain terminal of the NMOS transistor NM2 are connected to each other and connected to the drain terminal of the PMOS transistor PM8.

6. The power-on reset and reference voltage composite function circuit based on current comparison according to claim 4, characterized in that: The comparison current and reference voltage generation module specifically includes PMOS tubes PM1-PM8, transistors Q1 and Q2, NMOS tubes NM1 and NM2, and resistors R1-R3, wherein: The PMOS tubes PM1, PM3, PM5 and PM7 share a common source terminal and are connected to a power supply circuit; The drain ends of the PMOS tubes PM1, PM3, PM5 and PM7 are connected to the source ends of PM2, PM4, PM6 and PM8 respectively; The PMOS tubes PM1, PM3, PM5 and PM7 have a common gate terminal and are connected to the drain terminal of PM2 and connected to one end of the resistor R1; the PM2, PM4, PM6 and PM8 have a common gate terminal and are connected to the drain terminal of the NMOS tube NM1 and connected to one end of the resistor R1; The emitter of the transistor Q1 is connected to the source end of the NMOS tube NM1 and connected to the common ground terminal through the resistor R2; The transistors Q1 and Q2 have a common base and are connected to the collector of Q1 and one end of the resistor R3; The other end of the resistor R3 is connected to the drain end of the PMOS transistor PM4 and serves as an output node to output a reference voltage; The gate terminal of the NMOS tube NM1 is connected to the collector of the transistor Q2 and connected to the drain terminal of the PMOS tube PM6; The emitter of the transistor Q2 is connected to the source end of the NMOS transistor NM2 and connected to a common ground end; The gate terminal and the drain terminal of the NMOS transistor NM2 are connected to each other and connected to the drain terminal of the PMOS transistor PM8.

7. A power-on reset and reference voltage composite function circuit based on current comparison according to claim 5 or 6, characterized in that: The following current generating module specifically includes PMOS tubes PM10 and PM11, transistor Q4, resistors R4 and R5, wherein: The source end of the PMOS tube PM10 is connected to the power supply circuit; The drain end of the PMOS tube PM10 is connected to the source end of PM11, the gate end of the PMOS tube PM10 is connected to the drain end of PM11 and connected to one end of the resistor R4, the gate end of the PMOS tube PM11 is connected to the other end of the resistor R4 and connected to one end of the resistor R5, and the other end of the resistor R5 is connected to the base and collector of the transistor Q4; The emitter of the transistor Q4 is connected to the common ground terminal.

8. The power-on reset and reference voltage composite function circuit based on current comparison according to claim 7, characterized in that: The current comparison module specifically includes a PMOS transistor PM9 and an NMOS transistor NM3, wherein: The source end of the PMOS tube PM9 is connected to the power supply circuit and shares a gate end with the PMOS tube PM10; The drain ends of the PMOS tube PM9 and the NMOS tube NM3 are connected and serve as a second output node to output the comparison result; The NMOS tubes NM3 and NM2 share a gate terminal and a source terminal.

9. The power-on reset and reference voltage composite function circuit based on current comparison according to claim 8, characterized in that: The signal output module specifically includes an inverter and a buffer, and the output of the inverter and the input of the buffer are cascaded; The input of the inverter is connected to the second output node to output the comparison result; The output end of the buffer outputs a power-on reset signal or a power-off detection signal.

10. A chip circuit, characterized in that: The chip circuit includes a power-on reset and reference voltage composite function circuit based on current comparison as described in any one of claims 1-9.

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