Controlling device shape to improve magnetic tunneling junction device performance

By patterning the design and process of the magnetic tunneling junction device, its shape is controlled to reduce interface defects and lattice dislocations, the problem of low performance of magnetic memory devices in the prior art is solved, and the tunneling magnetoresistance value is significantly improved and Device performance.

CN111919306BActive Publication Date: 2025-01-07TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
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Patent Information

Application Number
CN201880072891.8
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Priority Date
2017-11-13
Filing Date
2018-11-08
Publication Date
2025-01-07
Estimated Expiration
2039-07-07

AI Technical Summary

Technical Problem

In the existing magnetic memory devices, defects in the ferromagnetic/magnesium oxide tunneling barrier interface lead to low tunneling resistance value, and the shape of the crystalline layer affects strain and defect growth, making it difficult to effectively control the device performance.

Method used

By designing and producing a patterned layered magnetic tunneling junction device, controlling its shape to reduce interface defects and lattice dislocations, moving crystal defects to removable structural areas, forming relatively defect-free areas to improve tunneling Magnetic resistance value.

Benefits of technology

It realizes the reduction of interface defect concentration and improves the lattice epitaxial, and improves the tunneling magnetoresistance value, thereby improving the device efficiency.

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Abstract

Successive layers can be sequentially formed on symmetrical curved electrodes to customize the shape of layered thin film devices such as MTJ (magnetic tunneling junction) devices. The electrodes are initially shaped to have a concave or convex surface. The sequentially formed layers can conform to the above shape, causing strain and causing various crystal defects to migrate away from the symmetry axis, while the area around the symmetry axis remains relatively defect-free. The stack can then be patterned to retain only the relatively defect-free areas.
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Description

Technical Field

[0001] Embodiments of the present invention generally relate to magnetic memory devices, and more particularly to the effects of device shape on performance. Background Art

[0002] The crystallographic properties of magnetic memory device structures play a very important role in device performance, especially the ferromagnetic / MgO tunneling barrier interface of MTJ (magnetic tunneling junction) devices. Specifically, the strain in the structure can significantly change the device characteristics for the reasons described below.

[0003] Magnetic memory devices consist of a stack of layers in which two ferromagnetic layers (usually referred to as the reference layer and the free layer) are separated by a thin nonmagnetic dielectric layer (called a barrier layer). In classical physics, electrons cannot flow from one ferromagnetic layer to the other through a non-conductive barrier layer. However, according to quantum mechanics, electrons can tunnel through the barrier layer if the correct conditions exist between the spin of the tunneling electron and the magnetization direction of the two ferromagnetic layers on either side of the barrier layer. The necessary conditions for successful electron tunneling also depend on the interface between the barrier layer and the ferromagnetic layer. Defects in the interface make it difficult to achieve high TMR (tunneling magnetoresistance) values, which measures the ability of electrons to successfully tunnel when the appropriate magnetization conditions are met. These defects are caused by lattice dislocations between the ferromagnetic layer and the nonmagnetic barrier layer, as well as defects generated during the crystalline growth of the material. These undesirable qualities are strain-dependent, which reduces the tunneling magnetoresistance value. These phenomena have been documented in the literature, such as "Strain-enhanced tunneling magnetoresistance in MgO magnetic tunnel junctions" published by Li Ming Long et al. in Scientific Reports 4, Article number 6505 (2014), and "Tuning the magnetic anisotropy of CoFeB grown on flexible substrates" published by Zhang Hao et al. in Chinese Physics B, Volume 24, Number 7-077501.

[0004] In fact, the shape of the crystalline layer affects the strain and stress in the layer, which in turn affects the defect growth in the layer. Controlling the shape of the layer can correspondingly control (or even deliberately manipulate) the strain in the magnetic tunneling junction film stack. Therefore, the process of controlling the shape can improve the performance of the device, such as improving the tunneling magnetoresistance and coercivity of the device. Specifically, if a new shape of the device is properly designed and generated, it can be expected to reduce the interface defect concentration and improve the interface lattice epitaxy to improve the device performance.

[0005] There are known prior art attempts to control shape to affect device performance, such as Ahn et al. (US 7,998,758) and Kim et al. (US 9,305,928). However, these attempts did not use the same method or produce the same effect as described herein. Summary of the invention

[0006] A first subject of the embodiments of the present invention is to provide a method for controlling the shape of a layered magnetic tunneling junction device to improve its performance.

[0007] The second subject of the embodiments of the present invention is to provide a method for reducing interface defect concentration, reducing lattice dislocations, and improving lattice epitaxy to produce measurable tunneling magnetoresistance improvement.

[0008] A third subject of embodiments of the present invention is to provide a method to control and manipulate the shape of a layered device when fabricating the layered device, so as to effectively customize the shape of the layered device.

[0009] A fourth subject of the present invention is to control the shape of a magnetic tunneling junction layered film or similar device structure to control the strain therein so that the crystal defects caused by the strain migrate to a region of the structure that can be removed later.

[0010] These themes are achieved by designing and fabricating patterned layered magnetic tunneling junction devices. Controlling the shape of the device in these ways allows crystalline defects such as vacancies, pinholes, and dislocations in the stack to be moved to undesirable weak regions (which can then be removed). The remaining relatively defect-free portions of the device can have higher coercivity and improved tunneling magnetoresistance values. The new device shape can therefore reduce the interface defect concentration and improve the lattice epitaxy of the interface, which can both improve device performance (e.g., as measured by improved tunneling magnetoresistance values). BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 Figure 2 shows a prior art magnetic tunnel junction device.

[0012] Figure 2 The method according to the embodiment of the present invention forms Figure 1 A device in which the bottom electrode is domed.

[0013] Figure 3 The effect of stacking layered magnetic tunneling junctions is shown, and the stack is formed at Figure 2 on a dome-shaped electrode.

[0014] Figure 4 Display Patterning Figure 3 The stacking effect eliminates the lateral setting area of ​​the stack, and the lateral setting area contains defects caused by the stack being formed on the dome-shaped electrode.

[0015] Figure 5Other electrodes are shown which are concave rather than convex such as dome-shaped electrodes.

[0016] Figure 6 The structure and Figure 3 Similar, but forming a magnetic tunneling junction stack on Figure 5 on the concave electrode.

[0017] Figure 7 Display Patterning Figure 6 The stacking effect eliminates the lateral setting area of ​​the stack, and the lateral setting area contains defects caused by the stack being formed on the concave electrode. DETAILED DESCRIPTION

[0018] First, Figure 1 As shown, standard patterned MTJ (magnetic tunneling junction) layered devices have been commonly used in random access memory (RAM) arrays. Although it is not necessary to use a specific substrate to define the device, for special considerations we will consider devices formed on a functional substrate such as a complementary metal oxide semiconductor substrate. The functional substrate may contain circuits and conductive vias to access the various cells of the device in the random access memory array.

[0019] The device is formed by first providing a complementary metal oxide semiconductor substrate 10 on which the device is to be formed. A bottom electrode (BE) 20 is blanket deposited on the complementary metal oxide semiconductor substrate to appropriately contact the through hole in the substrate. A series of horizontal layers are then sequentially deposited on top of the bottom electrode 20, and the horizontal layers will include a magnetic tunneling junction stack. These layers include a seed layer 30, a pinned magnetic layer 40, a tunneling barrier layer 50, a free magnetic layer 60, and a cap layer 70. A hard mask 80 is deposited on the cap layer. The hard mask is then patterned using a standard photolithography process (not shown), and the patterned hard mask is then used as a guide to pattern the film stack. It is worth noting that the bottom electrode is also patterned as shown, and the dielectric fill material 90 is laterally surrounded by the bottom electrode.

[0020] form Figure 1 The process steps of manufacturing a magnetic tunnel junction in the conventional art are described in detail above, and can be summarized in the flow chart of Table 1 as follows.

[0021]

[0022] Table 1: Figure 1 Process flow

[0023] We will then pair Figures 2 to 4 The method of the present embodiment is described. We note that initially the method will be described for a magnetic tunneling junction device, but it can be implemented for any layered crystalline structure where it is expected that multiple defects will accumulate during growth.

[0024] and Figure 1 Similar to the above-mentioned method of the prior art described in the process flow chart in FIG. 1 , the method of the embodiment of the present invention also starts with a complementary metal oxide semiconductor substrate 10 (although other substrates are also possible), and a bottom electrode layer 20 formed of a conductive material is deposited on this substrate. Figure 2 As shown, this method is different from the above-mentioned prior art method, and can pattern and etch the electrode to form a "dome" (i.e., symmetrical convex) shape 25. It is worth noting that the "dome" or convex shape is axially symmetrical (according to the horizontal axis), so it is more correct to say that it is a cylinder (if the cross-section of the convex surface is semicircular, it is a semi-cylinder).

[0025] There are several ways to give the electrode a convex or cylindrical surface, or indeed to give the electrode a variety of surface shapes other than convex, such as concave as described below. For example, an initial etch may be performed on the electrode material layer to produce a solid rectangular prism. A partial etch (or a series of partial etches) may then be performed to sequentially remove the electrode corners to obtain a rounded surface shape. In addition, sputter etching may be performed to produce a rounded surface shape. To form a concave surface, isotropic physical etching may be performed.

[0026] The results of the sequential deposition process are as follows Figure 3 As shown, a seed layer 35 is first deposited on the convex pillar electrode 25, followed by the deposition of a pinned layer 45, a barrier layer 55, a free layer 65, a cap layer 75, and a hard mask layer 85. Each of these layers sequentially conforms to the shape of the layer below, so that all of the layers conform to the electrode. For the sake of certainty, we note that the above process steps can be implemented on a general magnetic tunneling junction structure having a thickness between approximately (Angstrom) to The seed layer of tantalum, ruthenium, tungsten, or nickel-chromium between the to The cobalt-iron boride between the pinned and free layers has a thickness between approximately to A tunnel barrier layer of aluminum oxide or magnesium oxide between to The convex electrode may have a thickness between approximately 100 nm and 1000 nm, and a width between approximately 50 nm and 500 nm.

[0027] Due to the convex shape of the lower surface, as successive layers are formed and their crystalline structure develops, the inevitable defects (such as pinholes, vacancies, and dislocations) generated by the crystal growth mechanism can move or migrate from the convex top of each successively formed layer, causing the defects to accumulate at the corners where the arc of the lower electrode becomes a horizontal layer. This is the "weak" area of ​​the structure (see the area surrounded by the ellipse 90).

[0028] The stack of small areas on either side of the convex structure peak is relatively defect-free. The film stress can be manipulated by controlling the slope (curvature) of the convexity, and the concentration of lattice dislocations and interface defects can be reduced in the desired areas symmetrically located on either side of the convex structure peak. It is worth noting that the width of the convex surface considered to be relatively defect-free can cover the entire width of most of the arc-shaped area, without covering the weak area 90 in the corner. In most cases, more than half of the width of the convex surface centered at the highest point can be considered defect-free. For example, an electrode with a bottom width of 200nm can produce a defect-free device shape of at least 100nm.

[0029] After patterning the convex structure to create a vertical stack, it is actually Figure 4 The cylindrical cross section shown in the figure, and the gaps in the side 110 can be filled with gap-filling dielectric materials (not shown), and the upper surfaces of the stack and the surrounding dielectric layers are planarized and polished, and the mask layer can be removed to prepare for subsequent process integration. It is worth noting that the process flow shown in Table 2 below briefly describes the formation Figure 4 The sequence of steps in the structure is as described above.

[0030]

[0031] Table 2. Figure 4 Process flow

[0032] like Figure 5 As shown, the bottom electrode 27 of other embodiments of the process is formed to have a concave upper surface and is axially symmetrical.

[0033] like Figure 6 As shown, a film stack of a magnetic tunneling junction (or any layered crystalline structure) can be deposited on the concave bottom electrode 27, and the deposition method is the same as the deposition method on the convex electrode mentioned above. The result of the sequential deposition process is shown in FIG. Figure 6 As shown, a seed layer 37 is first deposited on the concave electrode 27, followed by a pinning layer 47, a barrier layer 57, a free layer 67, a cap layer 77, and a hard mask layer 87. Each of these layers is sequentially conformal to the concave shape layer below, so that all the layers are conformal to the concave shape of the electrode. It is worth noting that the material and size of the material layer can be the same as the above-mentioned material and size used for the convex structure.

[0034] Due to the shape of the underlying concavity, as successive layers are formed and their crystal structure develops, inevitable defects (e.g., pinholes, vacancies, and dislocations) generated by the crystal growth mechanism can move or migrate from the bottom of the concavity of each layer, causing defects to accumulate at the upper corners where the concavity discontinuously merges with the horizontal layers of the substrate 10. The regions containing the stack of cells on either side of the concavity minimum are relatively defect-free. The regions surrounding the discontinuity are referred to as "weak" regions, as shown by the region enclosed by the elliptical region 100. Defects will accumulate in the weak regions. Controlling the shape of the electrode 27 can control the film strain in the sequentially deposited layers and reduce the lattice mismatch and interface defect concentration in specific regions.

[0035] After patterning the concave-shaped structures to produce a vertical stack, the vertical stack has a defect-free concave bottom, e.g. Figure 7 Afterwards, the gaps between the two side portions 110 may be filled with gap-filling dielectric materials, and the upper surfaces of the stack and the surrounding dielectric layers may be planarized and polished to prepare for subsequent process integration (not shown).

[0036] It is worth noting that the process flow shown in Table 3 below briefly describes the formation Figure 7 The sequence of steps is as described above.

[0037]

[0038] Table 3. Figure 7 Process flow chart

[0039] As will be ultimately understood by those skilled in the art, the above details are intended to illustrate embodiments of the present invention and are not intended to limit the embodiments of the present invention. Materials, structures, and dimensions may be adjusted and modified to form and provide layered crystalline magnetic devices such as magnetic tunneling junction devices, and layer strain may be controlled when forming layers to reduce crystal defects and thereby improve device performance. These structures and methods of forming the same are also provided in accordance with the spirit and scope of the embodiments of the present invention as defined by the appended claims.

Claims

1. A method for controlling strain in a layer when forming a magnetic thin film device, comprising: Providing a substrate having a flat upper surface; forming an electrode layer on the substrate, wherein the electrode layer has a flat upper surface; symmetrically shaping the flat upper surface of the electrode layer to form an arcuate surface having an axis of symmetry; Depositing sequentially a layered device structure on the symmetrically shaped upper surface of the electrode, wherein each layer of the layered device structure has a shape corresponding to the symmetrically shaped upper surface of the electrode and has a laterally extending portion on the flat upper surface of the substrate; Then, using the hard mask layer as a guide, removing a plurality of symmetrical portions of the layered device structure, wherein the symmetrical portions are laterally located on each side of the symmetry axis; Thus, a remaining portion of the layered device structure remains, wherein the removed portion includes a weak region, and the curved surface in the weak region intersects with the surrounding flat surface, The layered material in the removed portion includes vacancies, crystal defects, pinholes, and dislocations that migrated to the weak region and accumulated therein when the layered device structure was formed, and the remaining portion of the layered device structure is relatively free of vacancies, crystal defects, pinholes, and dislocations. 2 . The method of claim 1 , further comprising surrounding the remaining portion of the layered device structure with a dielectric filling layer, and planarizing the remaining portion surrounded by the dielectric filling layer to prepare for subsequent process integration.

3. The method of claim 1, wherein the curvature of the layer causes vacancies, crystal defects, pinholes, and dislocations to migrate to laterally disposed regions. The method of claim 1 , wherein the arcuate region is convex.

5. The method of claim 1, wherein the arcuate region is concave.

6. The method of claim 1, wherein the layered device structure comprises: A bottom electrode has an arc-shaped surface symmetrical to an axis, on which are sequentially formed: a seed layer; a ferromagnetic pinning layer; a tunnel barrier layer; a ferromagnetic free layer; a cap layer; and A hard mask layer.

7. The method of claim 6, wherein the seed layer has a thickness between to The ferromagnetic free layer and the ferromagnetic pinned layer are formed by tantalum, ruthenium, tungsten, or nickel-chromium between to The tunnel barrier layer is formed by forming cobalt iron boride between to The cap layer is formed of aluminum oxide or magnesium oxide with a thickness between to Formed between tantalum, tungsten, or magnesium. 8 . The method of claim 6 , wherein the electrode has a thickness between 100 nm and 1000 nm, and a width between 50 nm and 500 nm.

9. The method of claim 8, wherein two regions symmetrically located on either side of a symmetry axis of the layered device structure are removed, and the remaining portion of the layered structure has a width between 50 nm and 500 nm.

10. A controlled shape magnetic layered device having strain-free and defect-free crystalline layers, comprising: a bottom electrode having an initially axially symmetrical arc-shaped surface; A plurality of layers are sequentially formed on the arc-shaped bottom electrode, and the layers formed sequentially have a crystalline structure, wherein the layers are conformally formed on the arc-shaped surface of the bottom electrode to control strain in the layers, Each of the layers has no defects in a first region symmetrical to the symmetry axis of the electrode, but the defects are concentrated in a second region laterally disposed outside the first region, wherein the second region has been removed and the remaining first region has no defects.

11. The device of claim 10, wherein a dielectric filling layer is deposited on both sides of the first region, and the upper surface is planarized and polished in preparation for subsequent integration.

12. The device of claim 10, wherein an initial surface shape of the bottom electrode is convex.

13. The device of claim 10, wherein an initial surface shape of the bottom electrode is concave.

14. The device of claim 11, wherein the bottom electrode and the layer comprise a magnetic tunneling junction device, and the layer comprises: a seed layer; a ferromagnetic pinning layer; a tunnel barrier layer; a ferromagnetic free layer; as well as A cover layer.

15. The device of claim 14, wherein the bottom electrode is a conductive material layer, and the seed layer has a thickness between to The ferromagnetic free layer and the ferromagnetic pinned layer are formed by tantalum, ruthenium, tungsten, or nickel-chromium between to The tunnel barrier layer is formed by forming cobalt iron boride between to The cap layer is formed of aluminum oxide or magnesium oxide with a thickness between to Formed between tantalum, tungsten, or magnesium.

16. The device of claim 15, wherein the bottom electrode is initially formed to have a concave axially symmetrical surface shape.

17. The device of claim 15, wherein the bottom electrode is initially formed to have a convex axially symmetrical surface shape.

Citation Information

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