Single photon avalanche diode (SPAD) microcell array and method of operation thereof

Abstract

Embodiments of the present disclosure generally relate to single photon avalanche diode (SPAD) microcell arrays and methods of operation thereof. A digital optical detector includes a clock signal generator configured to generate a clock signal, the clock signal consisting of clock pulses generated at a predetermined frequency; a single photon avalanche diode (SPAD) configured to turn on and generate an avalanche current in response to receiving a photon, the SPAD including an internal capacitor internally coupled between an anode terminal and a cathode terminal; and an active quenching-recharging circuit triggered by the clock signal. The active quenching-recharging circuit is configured to be activated and deactivated based on the clock signal, wherein the active quenching-recharging circuit is configured to recharge the internal capacitor on a condition that the active quenching-recharging circuit is activated, and wherein the active quenching-recharging circuit is configured to discharge the internal capacitor on a condition that the active quenching-recharging circuit is deactivated.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to photodetector arrays, and more particularly to a single-photon avalanche diode (SPAD) microcell array. BACKGROUND

[0002] Light detection and ranging (LIDAR) is a remote sensing method that uses light in the form of pulsed laser light to measure the range (variable distance) to one or more objects in a field of view. Specifically, light is transmitted toward an object. A single photodetector or photodetector array receives the reflection from the object illuminated by the light and determines the time it takes for the reflection to reach various sensors in the photodetector array. This is also known as measuring the time of flight (ToF). The LIDAR system forms a depth measurement and makes a distance measurement by mapping the distance to the object based on the time of flight calculation. Thus, the time of flight calculation can create a distance map and a depth map that can be used to generate an image.

[0003] The photodetector array generates an analog electrical signal that needs to be converted to the digital domain in order to perform the ToF measurement. For example, an ADC can be used for signal detection and ToF measurement. In this case, each ADC can be used to detect the analog electrical signal from one or more photodiodes to estimate the time interval between a start signal (i.e., corresponding to the time of the transmitted light pulse) and a stop signal (i.e., corresponding to the timing of receiving the analog electrical signal at the ADC) using an appropriate algorithm. Additionally, the electrical signal can pass through a transimpedance amplifier (TIA) before the ADC receives the analog electrical signal, which converts the analog electrical signal from, for example, a current to a voltage. Thus, a LIDAR receiver using a typical photodetector array requires a TIA and an ADC to acquire LIDAR sensor data and perform the ToF measurement. More power is ultimately required and results in reduced measurement accuracy and slower response times.

[0004] Accordingly, it can be desirable to have a digital photodetector array that can be used in a LIDAR receiver system. SUMMARY

[0005] One or more embodiments provide a digital light detector including a clock signal generator configured to generate a clock signal having clock pulses generated at a predetermined frequency; a single-photon avalanche diode (SPAD) configured to turn on and generate an avalanche current in response to receiving a photon, the SPAD including an anode terminal, a cathode terminal, and an internal capacitor internally coupled between the anode terminal and the cathode terminal; and an active quench- recharge circuit triggered by the clock signal. The active quench-recharge circuit is configured to be activated and deactivated based on the clock signal, wherein the active quench-recharge circuit is configured to recharge the internal capacitor on a condition that the active quench-recharge circuit is activated, and wherein the active quench-recharge circuit is configured to discharge the internal capacitor on a condition that the active quench-recharge circuit is deactivated.

[0006] One or more embodiments provide a method of operating a digital light detector. The method includes providing a bias voltage potential; generating a clock signal having clock pulses generated at a predetermined frequency; turning on a single-photon avalanche diode (SPAD) and generating an avalanche current in response to receiving a photon, wherein the SPAD includes an anode terminal, a cathode terminal, and an internal capacitor internally coupled between the anode terminal and the cathode terminal; controlling an activation state of an active quench-recharge circuit based on the clock signal; charging the internal capacitor on a condition that the active quench-recharge circuit is activated; and discharging the internal capacitor on a condition that the active quench-recharge circuit is deactivated.

[0007] One or more embodiments provide a digital silicon photomultiplier (SiPM) device including a clock signal generator configured to generate a clock signal having clock pulses generated at a predetermined frequency; and an array of microcells. Each microcell includes a single-photon avalanche diode (SPAD) configured to turn on and generate an avalanche current in response to receiving a photon, the SPAD including an anode terminal, a cathode terminal, and an internal capacitor internally coupled between the anode terminal and the cathode terminal; an active quench-recharge circuit triggered by the clock signal, wherein the active quench-recharge circuit is configured to be activated and deactivated based on the clock signal, wherein the active quench-recharge circuit is configured to charge the internal capacitor on a condition that the active quench-recharge circuit is activated, wherein the active quench-recharge circuit is configured to discharge the internal capacitor on a condition that the active quench-recharge circuit is deactivated; and a digital output configured to output a digital value corresponding to a potential generated at an output node of the active quench-recharge circuit. The digital SiPM device further includes a summing circuit configured to receive the digital values from the array of microcells and generate a digital pixel value for the SiPM based on a sum of the digital values.

[0008] One or more embodiments provide a method of synchronizing operation of a plurality of single-photon avalanche diodes (SPADs) of a digital silicon photomultiplier (SiPM). The method includes providing a bias voltage potential, generating a clock signal having clock pulses generated at a predetermined frequency, providing the clock signal to a plurality of microcells of the digital SiPM, wherein each microcell of the plurality of microcells includes a corresponding SPAD of a plurality of SPADs and a corresponding active quenching- recharge circuit triggered by the clock signal, controlling an activation state of each active quenching-recharge circuit based on the clock signal, charging an internal capacitor of the corresponding SPAD of the plurality of SPADs on a condition that the corresponding active quenching-recharge circuit is activated, and discharging the internal capacitor of the corresponding SPAD of the plurality of SPADs on a condition that the active quenching-recharge circuit is deactivated.

[0009] One or more embodiments provide a system configured to flexibly configure at least one silicon photomultiplier (SiPM). The system includes an array of microcells, each microcell including a single-photon avalanche diode (SPAD) configured to turn on and generate an avalanche current in response to receiving a photon, the SPAD including an anode terminal, a cathode terminal, and an internal capacitor internally coupled between the anode terminal and the cathode terminal, an active quenching-recharge circuit triggered by a clock signal, wherein the active quenching-recharge circuit is configured to be activated and deactivated based on the clock signal, wherein the active quenching-recharge circuit is configured to recharge the internal capacitor on a condition that the active quenching-recharge circuit is activated, wherein the active quenching-recharge circuit is configured to discharge the internal capacitor on a condition that the active quenching-recharge circuit is deactivated, and a digital output configured to output a digital value corresponding to a potential generated at an output node of the active quenching-recharge circuit. The system further includes a controller configured to dynamically group a portion of the array of microcells to form the SiPM. BRIEF DESCRIPTION OF DRAWINGS

[0010] Embodiments are described herein, with reference to the accompanying drawings.

[0011] Figure 1 is a schematic diagram of a LIDAR scanning system in accordance with one or more embodiments;

[0012] Figure 2 is a schematic block diagram of a LIDAR scanning system in accordance with one or more embodiments.

[0013] Figure 3A is a schematic diagram of a digital SiPM pixel (i.e., a 2D SiPM pixel) in accordance with one or more embodiments;

[0014] Figure 3Bis a schematic diagram of a 2D SiPM pixel array according to one or more embodiments;

[0015] Figure 4 illustrates a digital microcell configured with synchronous active recharge according to one or more embodiments;

[0016] Figures 5A to 5D illustrates an active recharge cycle of a SPAD arranged in series with a transistor according to one or more embodiments;

[0017] Figure 6 is a schematic diagram of a digital sensor element according to one or more embodiments;

[0018] Figure 7A and Figure 7B illustrates the concept of a configurable digital SiPM according to one or more embodiments; and

[0019] Figure 8 is a schematic diagram of a hierarchical adder tree according to one or more embodiments. DETAILED DESCRIPTION

[0020] In the following, various embodiments are described in detail. It should be noted that these embodiments are only for illustrative purposes and should not be construed as limiting. For example, although the embodiments can be described as including a number of features or elements, this should not be construed as indicating that all these features or elements are required to implement the embodiments. Instead, in other embodiments, some of the features or elements can be omitted, or replaced by alternative features or elements. Furthermore, other features or elements can be provided in addition to those explicitly shown and described, e.g. conventional components of a sensor device.

[0021] Features from different embodiments can be combined to form other embodiments unless specifically stated otherwise. Changes or modifications to the described embodiments can be made without departing from the scope of the application. In some instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the embodiments.

[0022] Further, in the following description, identical or similar components or components having identical or similar functions are denoted by the same reference numerals, and repeated explanation of these components can not be given. The description provided for the components denoted by the same reference numerals can be interchanged and utilized.

[0023] Unless otherwise noted, connections or couplings between elements shown in the drawings or described herein can be either direct connections or wireless connections. Still further, such connections or couplings can be indirect connections or couplings through one or more additional intermediate elements, so long as the general purpose of the connection or coupling is substantially maintained. In other words, unless otherwise noted, connections or couplings between elements include indirect connections or couplings and if an element has a connecting or coupling, it is not necessary for the connecting or coupling to be direct.

[0024] In the disclosure, expressions including ordinal numbers, such as “first,” “second,” etc., can modify various elements. However, such elements are not limited by the above expressions. For example, the above expressions do not limit the order and / or importance of the elements. The above expressions are used merely to distinguish an element from other elements for the purpose of identification. For example, although a first block and a second block are both blocks, they indicate different blocks. For another example, a first element can be referred to as a second element, and likewise, a second element can be referred to as a first element, without departing from the scope of the disclosure.

[0025] Embodiments relate to optical sensors and optical sensor systems, and to obtaining information about optical sensors and optical sensor systems. A sensor can refer to a component that converts a physical quantity to be measured into an electrical signal (e.g., a current signal or a voltage signal). The physical quantity can for example include electromagnetic radiation, such as visible light, infrared (IR) radiation, or other types of illumination signals, current, or voltage, but is not limited thereto. For example, an image sensor can be a silicon chip inside a camera that converts photons of light from a lens into a voltage. The larger the active area of the sensor, the more light can be collected to create an image.

[0026] A sensor device as used herein can refer to a device that includes a sensor and other components (e.g., biasing circuitry, an analog-to-digital converter, or a filter). Although in other embodiments, multiple chips or off-chip components can be used to implement a sensor device, a sensor device can be integrated on a single chip.

[0027] In a light detection and ranging (LIDAR) system, a light source transmits pulses of light into a field of view, and the light is reflected from one or more objects by backscattering. Specifically, LIDAR is a direct time-of-flight (ToF) system in which pulses of light (e.g., a laser beam of infrared light) are emitted into a field of view, and a pixel array detects and measures the reflected beams. For example, a photodetector array receives reflections from objects illuminated by the light.

[0028] Currently, photodetector arrays can be used to measure reflected light. The photodetector array can be a one-dimensional (ID) array consisting of multiple photodetector (pixel) rows arranged in a single column; it can also be a two-dimensional (2D) array consisting of multiple photodetector (pixel) rows and multiple photodetector (pixel) columns arranged in a grid-like fashion. Each pixel row or group of adjacent pixel rows can be read out as a measurement signal in the form of raw digital data. Each measurement signal can include data from a single pixel column or from two or more pixel columns corresponding to a selected one or more pixel rows.

[0029] Then, the difference in return times of each light pulse across multiple pixels of the pixel array can be used to make a digital 3D representation of the environment or to generate other sensor data. For example, the light source can emit a single light pulse, and the receiver circuitry electrically coupled to the pixel array can count from the time of emitting the light pulse (corresponding to a start signal) until the time of receiving the reflected light pulse at the receiver (i.e., at the pixel array) (corresponding to a stop signal). Then, the “time of flight” of the light pulse is transformed into a distance.

[0030] Scanning such as wobbling horizontal scanning (e.g., from left to right and from right to left of the field of view) can illuminate the scene in a continuous scanning fashion. Each time the light source fires a laser beam, it produces a scan line in the “field of view”. By emitting successive light pulses along different scanning directions, it is possible to scan an area called the field of view and to detect and image objects within that area. Thus, the field of view represents a scanning plane with a projection center. Raster scanning can also be used.

[0031] Figure 1 is a schematic illustration of a LIDAR scanning system 100 according to one or more embodiments. The LIDAR scanning system 100 is an optical scanning device comprising a transmitter including an illumination unit 10, a transmitter optics 11, and a one-dimensional (ID) MEMS mirror 12 (ID MEMS scanner); and a receiver including a main optics 14 and an optical receiver 15. The optical receiver 15 in the illustration is a 2D photodetector array 15. As further described according to Figure 2 The receiver can also include receiver circuitry such as data acquisition / readout circuitry and data processing circuitry, as further described according to

[0032] While this device represents one example of a LIDAR system, it should be appreciated that other types of LIDAR systems can also be used, such as a LIDAR system for flash LIDAR. Additionally, the LIDAR scanning system 100 can be rotated to scan in different scan directions. For example, the LIDAR scanning system 100 can be rotated 90° to scan in a vertical direction rather than a horizontal direction. Thus, the embodiments described herein are not limited to a particular type of light emitter or TOF system, and can also apply to other types of TOF systems.

[0033] Returning to Figure 1 The photodetector array 15, whether it is a 2D array or a ID array, is arranged so that the intended field of view maps vertically on the vertical extension of the photodetector array 15. A received light beam will hit only a certain row or group of rows of the detector array depending on the vertical angle of the received light beam. The intended field of view also maps horizontally on the horizontal extension of the 2D photodetector array.

[0034] The photodetector array 15 is a digital photodetector array, i.e. a digital silicon photomultiplier array. The digital photodetector array comprises a digital silicon photomultiplier (SiPM) array. Each SiPM comprises a plurality of microcells, each microcell comprising a single-photon avalanche diode (SPAD). Thus, each SiPM comprises an array of SPADs.

[0035] A single-photon avalanche diode (SPAD) is a type of solid-state photodetector in which a photon-generated carrier (via the internal photoeffect) can trigger a short but relatively large avalanche current. This avalanche is produced by a mechanism known as impact ionization, by which a carrier (electron and / or hole) is accelerated to high kinetic energy by a large potential gradient (voltage). If the kinetic energy of the carrier is sufficient (according to the ionization energy of the bulk material), other carriers are freed from the atomic lattice. Thus, in some cases, the number of carriers grows exponentially from just a single carrier. As a result, a SPAD is a photodiode operated above breakdown, where each detected photon produces an avalanche, and thus, each detected photon can be counted.

[0036] Like an avalanche photodiode (APD), a SPAD utilizes the avalanche current triggered by incident radiation of a p-n junction when reverse-biased. The fundamental difference between a SPAD and an APD is that a SPAD is specifically designed to operate at a reverse-bias voltage well above its breakdown voltage. This operation is also known as Geiger mode (as opposed to linear mode in the case of an APD). This is analogous to a Geiger counter.

[0037] In this example, the illumination unit 10 comprises three light sources (e.g., laser diodes or light emitting diodes) that are linearly aligned in a single row and configured to transmit light for scanning a field of view of an object. The light emitted by the light sources is typically infrared light, although light having another wavelength can also be used. Figure 1 As can be seen from the embodiment of Fig. 1, the shape of the light emitted by the light sources is spread in a direction perpendicular to the direction of transmission to form a light beam having a rectangular shape perpendicular to the direction of transmission. The illumination light transmitted from the light sources is directed towards the emitter optics 11, which are configured to focus each laser onto a one-dimensional MEMS mirror 12. For example, the emitter optics 11 can be a lens or a prism.

[0038] When reflected by the MEMS mirror 12, the light from the light sources is vertically aligned to form a one-dimensional vertical scan line SL of infrared light or a vertical strip of infrared light for each emitted laser beam. Each light source of the illumination unit 10 contributes to a different vertical area of the vertical scan line SL. Thus, the light sources can be activated and deactivated simultaneously to obtain a light pulse having a plurality of vertical segments, each corresponding to a respective light source. However, each vertical area or segment of the vertical scan line SL can also be active or inactive independently by switching on or off a corresponding one of the light sources of the illumination unit 10. Thus, a portion or the entire vertical scan line SL of light can be output from the system 100 into the field of view.

[0039] Thus, the emitter of the system 100 is an optical device configured to generate a laser beam based on a laser pulse, the laser beam having a rectangular shape extending in a direction perpendicular to the direction of transmission of the laser beam. As can be seen from Figure 1 As can be seen from the embodiment of Fig. 1, each of the light sources is associated with a different vertical area in the field of view, such that each light source illuminates the vertical scan line only into the vertical area associated with the light source. For example, a first light source illuminates into a first vertical area, while a second light source illuminates into a second vertical area different from the first vertical area.

[0040] Additionally, although three laser sources are shown, it should be appreciated that the number of laser sources is not limited thereto. For example, the vertical scan line SL can be generated by a single laser source, two laser sources, or more than three laser sources.

[0041] The MEMS mirror 12 is a mechanically moving mirror (i.e. a MEMS micro mirror) integrated on a semiconductor chip (not shown). The MEMS mirror 12 according to this embodiment is configured to rotate around a single scan axis and can be said to have only one degree of freedom for scanning. Unlike a 2D-MEMS mirror (2D MEMS scanner), in a ID MEMS mirror the single scan axis is fixed to a non-rotating substrate, thus maintaining its spatial orientation during the swing of the MEMS mirror. Due to this single scan axis of rotation, the MEMS mirror 12 is referred to as a ID MEMS mirror or a ID MEMS scanner. It should be appreciated that a 2D MEMS mirror that swings around two orthogonal scan axes can also be used. Typically, a ID MEMS mirror transmits a scan line of laser light into the field of view. In contrast, a 2D MEMS mirror transmits a scan spot of laser light into the field of view.

[0042] The MEMS mirror 12 is configured to swing “edge-to-edge” around a single scan axis 13, such that the light reflected from the MEMS mirror 12 (i.e. a vertical scan line of light) swings back and forth in the horizontal scan direction. A scan period or swing period is defined, for example, by one complete swing from a first edge (e.g. the left side) of the field of view to a second edge (e.g. the right side) of the field of view and then back to the first edge. The mirror period of the MEMS mirror 12 corresponds to the scan period.

[0043] Thus, by changing the angle of the MEMS mirror 12 on its scan axis 13, the field of view is scanned in the horizontal direction by a vertical light strip. For example, the MEMS mirror 12 can be configured to swing between + / - 15 degrees in the horizontal scan direction to turn the light over + / - 30 degrees (i.e. 60 degrees), constituting the horizontal scan range of the field of view. Thus, the field of view can be scanned line-by-line by the rotation of the MEMS mirror 12 over its extent of movement. One such sequence over the extent of movement (e.g. from -15 degrees to +15 degrees, and vice versa) is referred to as a single scan. Thus, two scans are used per scan period. Multiple scans can be used to generate a distance map and a depth map, and a 3D image is generated by a processing unit. The horizontal resolution of the depth map and image depends on the size of the incremental step in the rotation angle of the MEMS mirror 12 between the two scans.

[0044] While described in the context of a MEMS mirror, it should be appreciated that other ID mirrors or even 2D mirrors can be used. Additionally, the degree of rotation is not limited to + / - 15 degrees, and the field of view can be increased or decreased depending on the application. Thus, the one-dimensional scanning mirror is configured to oscillate about a single scan axis and direct the laser beam in different directions into the field of view. Thus, the transmission technique includes transmitting the light beam from the transmissive mirror oscillating about the single scan axis into the field of view such that the light beam is projected into the field of view as a vertical scan line SL that moves horizontally across the field of view as the transmissive mirror oscillates about the single scan axis. In comparison to a 2D scanning mirror for scanning the field of view using a laser point, which requires the emitter to emit more times to scan the field of view, the LIDAR system using the ID scanning mirror can use a more relaxed emission rate of the illumination unit 10 (i.e., the emitter). Additionally, in comparison to the 2D scanning mirror, the LIDAR system using the ID scanning mirror is generally more resistant to impacts and vibrations, and thus is well suited for automotive applications.

[0045] Upon impact with one or more objects, the transmitted vertical light strip is backscattered reflected by the LIDAR scanning system 100 facing backwards as a reflected vertical line, where the second optical component 14 (e.g., a lens or prism) receives the reflected light. The second optical component 14 directs the reflected light onto the photodetector array 15, which receives the reflected light as a received line RL and is configured to generate an electrical measurement signal. The photodetector array 15 generates a digital measurement signal based on the received light. The electrical measurement signal can be used to generate a 3D map of the environment and / or other object data based on the reflected light (e.g., via ToF calculations and processing).

[0046] The received line RL is shown as a vertical column of light extending along one of the columns of pixels in the longitudinal direction of the column of pixels. The received line has a vertical extent corresponding to the vertical extent of the vertical scan line SL. Figure 1 The vertical scan line SL is shown as having a vertical extent corresponding to three vertical regions of the photodetector array 15. As the vertical scan line SL moves horizontally across the field of view, the vertical column of light RL incident on the 2D photodetector array 15 also moves horizontally across the 2D photodetector array 15. As the direction of the received reflected light beam RL changes, the reflected light beam RL moves from a first edge of the photodetector array 15 to a second edge of the photodetector array 15. The direction of the received reflected light beam RL corresponds to the direction of transmission of the scan line SL.

[0047] In systems using a ID photodetector array rather than a 2D photodetector array, each light beam (i.e., each received line RL) is projected onto a column of the detector array.

[0048] The photodetector array 15 is composed of an array of silicon photomultipliers (SiPMs). Each SiPM can be referred to as a SiPM pixel or SiPM cell. Each SiPM includes a plurality of microcells (i.e., SPAD cells), each microcell including a SPAD. In the examples provided herein, the photodetector array 15 is a two-dimensional (2D) SiPM array including an array of SiPM pixels. As noted above, the photodetector array 15 can be a ID array including a single column of photodiodes. Activation of the photodiodes can be synchronized with the light pulses emitted by the illumination unit 10.

[0049] The photodetector array 15 receives the reflected light pulses as a receive line RL and generates an electrical signal in response thereto. Since the time of transmission of each light pulse from the illumination unit 10 is known, and because light travels at a known speed, a time-of-flight calculation using the electrical signal can determine the distance of the object from the photodetector array 15. A depth map can be plotted of the distance information.

[0050] In one example, for each distance sample, the microcontroller triggers a laser pulse from each of the light sources in the illumination unit 10 and also starts a timer in a time-to-digital converter (TDC) integrated circuit (IC). The laser pulse propagates through the transmission optics, is reflected by the target field, and is captured by one or more receiving photodiodes of the photodetector array 15. Each receiving photodiode emits a short electrical pulse that is read out by a readout circuit.

[0051] A comparator IC identifies the pulse and sends a digital signal to the TDC to stop the timer. The TDC calibrates each measurement using a clock frequency. The TDC sends serial data of the differential time between the start and stop digital signals to the microcontroller, which filters out any erroneous readings, averages a plurality of time measurements, and calculates the distance to the target at a particular field position. By emitting successive light pulses in different directions established by the MEMS mirror 12, a region (i.e., field of view) can be scanned, a three-dimensional image can be generated, and objects within the region can be detected.

[0052] When a laser energy pulse as a vertical scan line SL enters the field of view from the surface of the MEMS mirror 12, a reflected pulse occurs upon the reflection of the laser illumination field of view by an object in the field of view. These reflected pulses arrive as a vertical column of light to the photodetector array 15, the width of these reflected pulses is for example one photodetector pixel and their length is at least partially vertically across the pixel column of the photodetector array 15 in the longitudinal direction. That is, all photodetector pixels in the pixel column or a portion of the photodetector pixels of the pixel column can receive the light stripe. For example, in one instance, all light sources of the illumination unit 10 can be used to generate the scan line SL / receiving line RL. In this case, the receiving line RL can extend along the entire pixel column in the longitudinal direction. In another instance, only a subset of the light sources can be used to generate the scan line SL / receiving line RL. In this case, the receiving line can extend only along a portion of the pixel column in the longitudinal direction.

[0053] In some instances, two or more pixel columns can receive light from the same light stripe. For example, when a portion of the received light stripe hits on an area between two photodetector pixels, two pixel columns can receive light. In this case, the two pixel columns can be partially illuminated by a single light stripe in the width direction.

[0054] On the other hand, as mentioned above, if the illumination unit 10 generates a partial vertical scan line SL, only a portion of the pixel columns of the photodetector array 15 can be illuminated in the longitudinal direction.

[0055] The photodetector array 15 is configured to generate digital measurement signals (electrical signals) based on the reflected light (e.g., via TOF calculations and processing) for generating a 3D map of the environment.

[0056] Figure 2 is a schematic block diagram of a LIDAR scanning system 200 in accordance with one or more embodiments. In particular, Figure 2 Additional features of the LIDAR scanning system 200 are shown, including example processing and control system components, such as MEMS drivers, receiver circuitry, and system controllers.

[0057] The LIDAR scanning system 200 comprises a transmitter unit 21 responsible for the transmitter path of the system 200 and a receiver unit 22 responsible for the receiver path of the system 200. The system further comprises a system controller 23 configured to control components of the transmitter unit 21 and the receiver unit 22 and to receive raw data from the receiver unit 22 and perform processing (e.g. via digital signal processing) thereon for generating object data (e.g. point cloud data). Thus, the system controller 23 comprises at least one processor and / or processing circuitry (e.g. a comparator and a digital signal processor (DSP)) of a signal processing chain for processing the data and a control circuitry (such as a microcontroller) configured to generate control signals. The LIDAR scanning system 200 can further comprise a sensor 26, such as a temperature sensor, providing sensor information to the system controller 23.

[0058] The transmitter unit 21 comprises the illumination unit 10, the MEMS mirror 12, and a MEMS driver 25 configured to drive the MEMS mirror 12. In particular, the MEMS driver 25 actuates and senses the rotational position of the mirror and provides position information of the mirror (e.g. a tilt angle or a rotation degree around a rotational axis) to the system controller 23. Based on this position information, the laser source of the illumination unit 10 is triggered by the system controller 23, the photodiode is activated to sense, thus measure the reflected light signal. Thus, a higher accuracy of the position sensing of the MEMS mirror enables a more accurate and precise control of the other components of the LIDAR system.

[0059] The receiver unit 22 comprises the photodetector array 15 and a receiver circuit 24 comprising an analog readout circuit. As described in more detail below, the SiPM units of the photodetector array 15 can be coupled to a readout channel of the receiver circuit 24, which receives an electrical signal from the readout channel. Additionally, each row of the photodetector array 15 can be selectively coupled to and decoupled from the receiver circuit 24 by a multiplexer. Pixels, rows or columns coupled to the receiver circuit 24 can be referred to as active pixels, rows or columns, while pixels, rows or columns not coupled to the receiver circuit 24 can be referred to as inactive pixels, rows or columns.

[0060] The analog readout circuit comprises N analog output channels (e.g. 32 channels) configured to read out the measurement signals received from selected pixels of the coupled rows of the photodetector array 15. Further, more than one pixel can be selected from a coupled row, multiple rows can be coupled to the output channels simultaneously, and one or more pixels can be selected from each coupled row. The collection of digital data from the photodetector array 15 on the output channels at one time can be referred to as a digital sample, and each output channel can be used to collect a different digital sample. Each sample also corresponds to a sample time at which the measurement signals are read out from the one or more pixels.

[0061] Thus, the receiver circuit 24 can receive digital electrical signals from the photodetectors of the photodetector array 15 and transmit the electrical signals to an analog-to-digital converter (ADC) as raw digital data for ToF measurements and generation of object data (e.g. 3D point cloud data).

[0062] The receiver circuit 24 can also receive a trigger control signal from the system controller 23 which triggers the activation of one or more microcells and vice versa the deactivation of one or more microcells. Thus, the system controller 23 can control which SPADs are enabled and which SPADs are disabled. The readout circuit 24 in turn can be configured to activate or deactivate specific SPADs of the photodetector array 15. The receiver circuit 24 can also receive a gain setting control signal for controlling the gain of one or more photodetectors.

[0063] Figure 3A is a schematic diagram of a digital SiPM pixel 1 (i.e. a 2D SiPM pixel) according to one or more embodiments. Figure 3B is a schematic diagram of a 2D SiPM pixel array according to one or more embodiments.

[0064] In particular, the photodetector array 15 consists of an array of digital SiPM pixels 1 arranged in rows and columns. The digital SiPM pixel 1 comprises an array of microcells 2, each microcell 2 comprising a SPAD 3 in series with a quenching circuit 4 comprising a transistor S R As described in more detail below, the behavior of the transistor S R is similar to a digital switch with an on-resistance Ron. Thus, each SiPM pixel comprises an array of SPADs. In other words, a single SiPM pixel can be referred to as a SPAD array and each SPAD can be referred to as a SPAD pixel.

[0065] Each SPAD is essentially a binary device, either a photon has hit it or not. Upon receiving a photon, the SPAD 3 generates an electrical pulse. The strength of the signal generated by the SiPM is obtained by counting the number of output pulses generated by the SPADs that were active during the measurement time slot (photon counting) or by detecting the accumulated current of all SPADs that resolve each photon event, while the time-dependent shape of the signal is obtained by measuring the time distribution of the output signal (photon timing). The latter can be obtained by operating the SPAD detector in time-correlated single-photon counting (TCSPC).

[0066] In particular, a SPAD is a solid-state photodetector in which a photon-generated carrier (via internal photoeffect) can trigger an avalanche current that is short in duration but relatively large in magnitude. This avalanche is produced by a mechanism called impact ionization, by which a carrier (electron and / or hole) is accelerated to high kinetic energy by a large potential gradient (voltage). If the kinetic energy of the carrier is sufficient (according to the ionization energy of the bulk material), other carriers are freed from the atomic lattice. Thus, in some cases, the number of carriers grows exponentially from just a single carrier.

[0067] The avalanche current rises rapidly [sub-nanosecond rise time] to a macroscopic steady level in the milliamp range. If the primary carrier is a photo-generated carrier, the leading edge of the avalanche pulse [using picosecond time jitter] marks the arrival time of the detected photon. By discharging the bias voltage V BIAS to the breakdown voltage V BD or below, the current continues until the avalanche is quenched. The internal capacitance is the stray or parasitic capacitance of the SPAD and is represented in Figures 5A to 5D by the internal capacitor C D .

[0068] When this happens, the lower electric field is no longer able to accelerate the carriers to ionize by collision with the lattice atoms, and thus the current stops. In order to be able to detect another photon, the bias voltage at the internal capacitance must be raised again (i.e., charged) to above the breakdown voltage. This recharge time causes the SPAD to be blinded or deactivated until the internal capacitance is recharged above the breakdown voltage. The circuit responsible for quenching the avalanche current and subsequently recharging the internal capacitance is called quenching circuit 4. The quenching circuit 4 represents an active quenching and recharge circuit (i.e., active quenching-recharge circuit), which is a quenching and recharge circuit, and can be a transistor or other circuit that performs active quenching and recharge on the SPAD 3. The active quenching and recharge circuit is different from a passive quenching and recharge circuit, which consists only of passive elements such as resistors, which are not actively triggered.

[0069] The operation requires a suitable circuit that senses the leading edge of the avalanche current, generates a standard output pulse synchronized with the avalanche build-up, suppresses the avalanche by lowering the bias to below the breakdown voltage, and restores the photodiode to the operating level (i.e., above the breakdown voltage).

[0070] By coupling the transistor S R With the SPAD 3 coupled in series, each microcell 2 can be constructed as a digital sensor, making the SiPM 1 as a whole an entire digital sensor. As a result, the output of the SiPM 1 does not require an amplifier to amplify the signal it generates, nor an ADC to convert to the digital domain. It has very low noise (close to the photon shot limit), and since no TIA or ADC is needed, the power consumption is low.

[0071] Additionally, each SPAD can be selectively activated and deactivated. For example, a SPAD can be selectively coupled (activated) to or decoupled (deactivated) from the output of the SiPM, or its corresponding suppression circuit can be selectively activated or deactivated, such that the SPAD is no longer recharged to the operating level. However, it should be appreciated that the activation and deactivation of the SPAD is not limited to these example techniques.

[0072] Additionally, the array of SPADs can be a 1D array of SPADs or a 2D array of SPADs. For example, a SiPM pixel can include a 1D array of SPADs, where the SPADs are arranged in a single line (e.g., a single row of SPADs). This type of SiPM pixel can be referred to as a 1D SiPM pixel. Multiple 1D SiPM pixels (each pixel’s output coupled to a readout channel) can be used to create a 2D array of SPADs.

[0073] Alternatively, a SiPM pixel can include a 2D array of SPADs, where the SPADs are arranged in two directions forming multiple rows and columns. This type of SiPM pixel can be referred to as a 2D SiPM pixel. Each 2D SiPM pixel has its own output coupled to a readout channel. Whether a 1D array or a 2D array, each SiPM pixel generates an electrical signal that is output to a corresponding readout channel, which provides the electrical signal to a signal processing chain (not illustrated).

[0074] In Figure 3AIn the example shown in the middle, there are twelve microcells 2 included. Thus, this SiPM 1 has twelve SPADs arranged in an array. The output of the SiPM pixel 1 is accumulated from the electrical signals generated by the SPADs 3. For example, if only one SPAD in the array detects a photon during a measurement period, the output of the SiPM pixel can have an intensity I. On the other hand, if five SPADs in the array each detect a photon during the measurement period, the output of the SiPM pixel 1 can have an intensity 5I. If all of the SPADs in the array detect a photon during the measurement period, the output of the SiPM pixel 1 can have an intensity 12I. As a result, the contributions of all of the SPADs 3 in the SiPM pixel 1 are added together to generate the output signal. The number of SiPM pixels and the number of SPAD pixels within each SiPM pixel are fully configurable.

[0075] Figure 4 Fig. 1 illustrates a digital microcell configured with synchronous active recharge, according to one or more embodiments. In particular, a digital microcell 2 of Figure 3A Fig. 2 is provided in more detail. The digital microcell 2 includes a SPAD 3 and an active quench-recharge circuit 4 including a transistor S R Fig. 3 illustrates a digital microcell readout circuit, according to one or more embodiments. In particular, a microcell readout circuit including a level shifter 5 and a 1-bit memory device 6 is provided. For example, the 1-bit memory device 6 can be a clocked D flip-flop.

[0076] Fig. 4 illustrates a digital microcell configured with synchronous active recharge, according to one or more embodiments. In particular, a digital microcell 2 of R Fig. 5 illustrates a digital microcell readout circuit, according to one or more embodiments. In particular, a microcell readout circuit including a level shifter 5 and a 1-bit memory device 6 is provided. For example, the 1-bit memory device 6 can be a clocked D flip-flop. R Fig. 6 illustrates a digital microcell configured with synchronous active recharge, according to one or more embodiments. In particular, a digital microcell 2 of

[0077] Fig. 7 illustrates a digital microcell configured with synchronous active recharge, according to one or more embodiments. In particular, a digital microcell 2 of R Fig. 8 illustrates a digital microcell configured with synchronous active recharge, according to one or more embodiments. In particular, a digital microcell 2 of BIAS Fig. 9 illustrates a digital microcell configured with synchronous active recharge, according to one or more embodiments. In particular, a digital microcell 2 of Rrepresents a clocked active quench-recharge circuit. When the transistor is off, it quenches SPAD 3, and when it is on, it recharges SPAD 3. It should be appreciated that the clocked active quench-recharge circuit is not limited to a single transistor and can include one or more other circuit elements that perform the equivalent functions of active quenching and recharging based on the clock signal. It should also be appreciated that the active quench-recharge circuit can or can not include a transistor.

[0078] The digital microcell 2 includes an input terminal IN (i.e., the control terminal of transistor S R ), which is coupled to a clock signal generator 7 (e.g., a flip-flop) to receive a clock signal CLK. In this example, the clock signal is a 1 GHz signal, but can be configured based on a desired charge time. Each microcell 2 in the SiPM 1 receives the same clock signal and includes a corresponding 1-bit memory device 6. Further, each microcell in a SiPM array can receive the same clock signal and includes a corresponding 1-bit memory device 6.

[0079] The clock signal CLK actively turns on and off the transistor S R based on whether SPAD 3 is in its operational mode (i.e., its off condition). When SPAD 3 is in the operational mode, its behavior is similar to an open switch, and is considered off. As a result, the node OUT1 coupled between SPAD 3 and transistor S R is pulled low (i.e., an analog logic low). When SPAD 3 receives a photon, the behavior of SPAD 3 is similar to a closed switch, and is turned on, pulling the node OUT1 high (i.e., an analog logic high) to the bias voltage V BIAS . The level shifter 5 receives the analog value from the node OUT1 and converts the analog value to a corresponding digital value (i.e., a digital logic low or a digital logic high).

[0080] Depending on whether the active quench-recharge circuit (e.g., transistor S R ) is placed on the low side or the high side of SPAD 3, and also depending on the specific implementation of the level shifter 5 (which can be inverting), the digital binary signal for the SPAD / microcell can be 0 if no photon is detected, and 1 if a photon is detected, or vice versa.

[0081] When SPAD 3 is in its operational mode, transistor S R remains off, regardless of the value of the clock signal. On the other hand, after the internal capacitor C D (i.e., stray or parasitic capacitance) of SPAD 3 is discharged due to a received photon and after a hold time, the clock pulse (e.g., a high clock value) turns on transistor S Rto the internal capacitor C D be charged so as to place the SPAD 3 back into its operational mode.

[0082] In this example, the transistor S R may be an n-channel transistor. When the transistor S R is turned on, the internal capacitor C D of the SPAD 3 can be recharged to above the breakdown voltage V BIAS of the SPAD 3. BD If the internal capacitor C D has discharged to equal or below the breakdown voltage V BD , then this recharging occurs. If the capacitor C D of the SPAD 3 has been charged to above the breakdown voltage V BD , then no recharging occurs since the transistor S R remains off. Instead, the internal capacitor C D of the SPAD 3 remains above the breakdown voltage V BD , waiting to be triggered by a photon. Thus, after the internal capacitor C D has been discharged by a received photon, the clock signal actively recharges the internal capacitor C D of the SPAD 3.

[0083] In addition, since all microcells 2 receive the same clock signal CLK, the SPADs 3 are recharged synchronously on each clock cycle. By actively recharging the SPADs 3 synchronously, all SPADs are placed into their operational mode (i.e., their off condition) synchronously. That is, those SPADs that have not yet discharged maintain in their operational mode, while those SPADs that have been discharged by a photon since the last clock cycle are recharged and return to their operational mode in preparation for detecting another photon. As a result, on each clock cycle, the entire SiPM or array of SiPMs can be actively and synchronously set into operational mode.

[0084] Furthermore, the transistor S R allows a hold time between the discharge and subsequent recharge of the internal capacitor C D of the SPAD 3. The hold time allows for synchronous recharging between the SPADs. If there were no hold time, the SPADs could be recharged asynchronously with respect to one another. For example, if a resistor were used in place of the transistor S Rthen the SPAD enters the recharging phase immediately after the photon hits the SPAD. As a result, the SPAD charges and discharges at different times based on the received photons, resulting in an output analog signal, which requires further signal processing, averaging, etc. In contrast, in the case of synchronous recharging, a digital signal is generated because all SPADs are set synchronously to be in their operational mode, ready to be triggered by a photon,. The measurement of the SiPM is the digital accumulated signal of its SPADs per clock cycle.

[0085] The clock pulses of the clock signal CLK are configured such that data capture is enabled by the 1-bit memory device 6. As a clocked D-Flip-Flop, the 1-bit memory device 6 is configured to capture the bit value transmitted by the level shifter 5 at each clock pulse (high clock value) and to store and hold the captured bit value until the next clock cycle (or until the data value changes). Thus, the bit value at the output OUT2 is the bit value received from the level shifter 5, which represents the value at OUT1, which bit value is captured due to the clock pulse received at its clock input by the 1-bit memory device 6. The captured bit value is stored for the hold time until the next clock pulse of the next clock cycle starts.

[0086] The hold time allows all SPADs that have discharged during the clock cycle due to a received photon to charge and re-enter the operational mode before the next clock cycle starts. At the next clock cycle, the 1-bit memory device 6 follows the bit value received at its data input by capturing the bit value transmitted by the level shifter 5, which can be a new bit value or the same bit value as in the previous clock cycle. The output OUT2 of the 1-bit memory device 6 transmits the digital signal as output of the microcell 2.

[0087] According to this configuration, a digital sensor is formed without using an amplifier (e.g., TIA) or ADC, thereby providing a low-power solution. Further, the SPADs are recharged by the fixed high-speed clock signal CLK with a short dead-time and a high temporal resolution.

[0088] Figures 5A to 5D Fig. 3 and Fig. 4, respectively, illustrate an active recharging cycle of a SPAD arranged in series with a transistor according to one or more embodiments. Specifically, a cycle of four phases is shown, which includes Figure 5A a (re)charging phase in, Figure 5B an operational mode (off condition) phase in, Figure 5C a photon trigger (discharge) phase in, and Figure 5D a hold time phase in.

[0089] Figures 5A to 5D Fig. 3 and Fig. 4, respectively, illustrate an active recharging cycle of a SPAD arranged in series with a transistor according to one or more embodiments. Specifically, a cycle of four phases is shown, which includes Figure 4The SPAD 3 and transistor S of the micro unit 2 are shown R Schematic diagram. SPAD 3 consists of internal resistance RD, breakdown voltage V BD , switch S, and internal capacitor C D (i.e., parasitic capacitance). Transistor S R Represented by switch SR and internal on-resistance Ron. Both SPAD 3 and transistor are coupled to bias supply V BIAS Specifically, the cathode of SPAD 3 is connected to the bias power supply V BIAS The negative terminal or ground potential of the transistor is coupled to the anode of SPAD 3 and the bias power supply V BIAS between the positive terminals of the

[0090] exist Figure 5A During the (re)charging phase shown, transistor S R It is turned on by the clock pulse of CLK, and the electronic current I flows through the internal capacitor C D , through transistor S R Charge the internal capacitor to the bias voltage V including the on-resistance Ron BIAS SPAD 3 is turned off, so switch S is open. The internal capacitor C D The charging time constant is given by C D *Ron indicates that once the internal capacitance C D is charged to the bias voltage V BIAS , SPAD 3 is considered to be in operational mode.

[0091] exist Figure 5B During the operating mode phase shown, the SPAD 3 remains off. Additionally, the transistor S R is also turned off. As a result, the internal capacitor C D Maintain bias voltage V BIAS , and no current flows through the circuit. The circuit remains in this operating mode (off condition) until a photon is received and an avalanche is triggered at SPAD 3.

[0092] exist Figure 5C During the photon triggering (discharging) phase, SPAD 3 is activated by the received photons and the switch S is closed. By closing the switch S, an avalanche current I D , and the internal capacitor C D Through the internal resistor R D Discharge to breakdown voltage V BD . Used to make the internal capacitor C D The discharge time constant is given by C D *Ron indicates that during this phase, transistor S R Once the internal capacitor CD is discharged to the breakdown voltage V BD , the SPAD turns off, causing the switch S to turn off (i.e., open).

[0093] During the hold phase of Figure 5D , the clock signal CLK applies a hold time until the next clock pulse. The hold time is the time period between the time the internal capacitor C D is discharged to the breakdown voltage V BD and the time the next clock pulse occurs. During the hold time, the SPAD 3 does not conduct (i.e., the switch S is off), the transistor S R is off (i.e., the switch SR is off), the internal capacitor C D is held at the breakdown voltage V BD , and no current flows through the circuit. At the next clock pulse, the transistor S R turns on due to receiving a high clock signal at its control terminal, and the circuit enters the recharge phase shown in Figure 5A . The cycle is then repeated.

[0094] Figure 6 is a schematic diagram of a digital sensor element according to one or more embodiments. The digital sensor element includes a SiPM 1 including a 16x16 array of microcells 2, a summing circuit 8, and a register 9. Each microcell 2 represents a SPAD 3. In this example, each microcell column is electrically coupled to the summing circuit 8 via a corresponding readout channel for receiving a digital output therefrom. Alternatively, the summing circuit 8 can be electrically coupled to each microcell row via a corresponding readout channel for receiving one or more digital outputs therefrom. The summing circuit 8 sums the received digital outputs over each clock cycle of a clock signal CLK and transmits the summed value to the register 9. For the illustrated clock cycle, the output value 12 is provided to the register representing 12 SPADs in the SiPM 1 that received a photon during that clock cycle. As a result, a time series digital signal (i.e., a digital signal that varies over time) is generated as shown on the right side, having a value for each clock cycle. Each value is a discrete value between 0 and a maximum value. In a 16x16 microcell array, the maximum discrete value is 256, for a total of 257 possible discrete signal levels per clock cycle.

[0095] By way of another example and returning reference to Figure 3AIf zero SPADs in SiPM 1 detect a photon during a measurement period (e.g., during a clock period), the pixel value output by SiPM 1 can have a value of 0, which represents the minimum pixel value. If only one SPAD in SiPM 1 detects a photon during a measurement period, the pixel value output by SiPM 1 can have a value of 1. If, on the other hand, five SPADs in SiPM 1 each detect a photon during a measurement period, the pixel value output by SiPM 1 can have a value of 5. If all of the SPADs in SiPM 1 detect a photon during a measurement period, the pixel value output by SiPM 1 can have a value of 12, which represents the maximum pixel value.

[0096] Thus, all of the contributions of the SPADs in SiPM 1 provided by their respective outputs OUT2 are added by summation circuit 8 in each clock period of clock signal CLK to generate a summed digital value for the SiPM. The summed digital value is a pixel value that represents the sum of all the bit values generated by the SPADs for the individual SiPM 1. In an array of SiPMs, each SiPM outputs a pixel value in each clock period that is used to generate an image.

[0097] A digital signal processor (DSP) 30 provided in system controller 23 can also analyze the time series digital signals and distinguish between received laser photons and received ambient light photons (i.e., background light photons). More specifically, DSP 30 can distinguish between pixel values corresponding to received (backscattered) laser light and pixel values corresponding to only noise generated by ambient light. DSP 30 can do this by detecting peaks in the time series digital signals that exceed a predetermined threshold TH. The peaks indicate a concentrated number of photons received at the SiPM, which typically occurs when backscattered laser light is received. Pixel values below threshold TH typically indicate an absence of backscattered laser light at least at an appropriate level and are the result of ambient light.

[0098] Figure 7A and Figure 7B A concept of a configurable digital SiPM is illustrated in accordance with one or more embodiments. In this concept, SPADs are combined into arbitrary groups to create a configurable digital SiPM.

[0099] In Figure 7A , a 6x6 array of digital SiPMs 1 is provided, where each digital SiPM 1 includes a 16x16 array of microcells. In addition, two example backscattered laser beams RX1 and RX2 are shown.

[0100] The laser beam RX1 is a receiving line of the received laser light formed in a 1D MEMS mirror scanner. Due to non-ideal characteristics of the receiving optics, the receiving line is curved. As a result, the laser beam RX1 is at least partially projected on twelve SiPMs arranged in all SiPM rows and two SiPM columns.

[0101] The laser beam RX2 is a receiving spot of the received laser light formed in a 2D MEMS mirror scanner. The laser beam RX2 can be projected on one or more adjacent SiPMs. In this example, the laser beam RX2 is projected on portions of four different SiPMs.

[0102] The system controller 23 can estimate the position on the array at which the laser beam is expected to be received based on both the transmission direction of the transmitted laser beam (i.e. the position of the MEMS mirror 12 around one or both of its scan axes) and the known characteristics of the receiver optics.

[0103] In either case, when using a fixed SiPM configuration, multiple SiPMs can only receive a portion of the laser signal. As such, the adder of the adder circuit can be configured to add the digital pixel values of the target SiPMs in which light is expected to be received, while ignoring the outputs from the SiPMs in which no light is expected to be received. Additionally or alternatively, the target SiPMs in which light is expected to be received can be activated or enabled, while the remaining SiPMs can be deactivated or disabled. However, in a fixed SiPM configuration, the area occupied by the target SiPMs is larger than the area required for detecting the laser signal. As a result, more ambient light is received at those pixels than is necessary, resulting in more noise being detected and reducing the signal-to-noise ratio (SNR).

[0104] Alternatively, in Figure 7B the array can be used as a 96x96 array of microcells, which can be dynamically and flexibly grouped into digital SiPMs 41 based on the position of the desired light. In this case, the SiPMs 41 are not fixed but formed by grouping together adjacent microcells as needed during the runtime of the scanning operation. The grouping of microcells can be done in a 16x16 fashion or by using other array sizes. The grouping can change during the scanning operation as the backscattered light moves across the array of microcells. That is, the grouping can move across the entire array of microcells together with the received beam of light. Still further, the grouping can be selected based on the shape of the backscattered light projected onto the array.

[0105] This can greatly improve the SNR, as it can maximize the area that receives the backscattered laser signal while minimizing the area that does not. Optimizing the use of SPADs in a flexible configuration can not only help minimize the impact of background light, but also minimize power consumption, and can also vary the pixel resolution by increasing or decreasing the size of the SiPM 41. Still further, as the SiPM 41 can be created to correct for any distortions caused by its non-ideal characteristics, inexpensive optics with higher characteristic defects can be used. Still further, in cases where the signal is too strong to increase the dynamic range, certain areas of the array can be disabled.

[0106] The system controller 23 is configured to predict the area of the array that is to receive backscattered laser light, and to identify the microcells 2 in a particular area of the array to group them into one or more SiPMs 41. The area is predicted based on the transmission direction of the transmitted laser beam (i.e. the position of the MEMS mirror 12 about one or both of its scan axes) and the known characteristics of the receiver optics. The system controller 23 can enable the microcells 2 that are grouped into one or more SiPMs 41, while disabling the microcells 2 that are outside of the one or more SiPMs 41 (i.e. outside of the predicted area). The configuration of enabled microcells and formation of SiPMs 41 can be changed on a shot-by-shot basis as the transmitted laser beam is emitted into the field of view at different transmission directions.

[0107] Additionally or alternatively, the system controller 23 can reconfigure the adder circuit according to the grouping of microcells that form the SiPM 41, such that the adder circuit receives the digital values from the grouping of microcells and adds them together to generate a pixel value for the formed SiPM 41. Thus, the system controller 23 can reconfigure the grouping of adders in the adder circuit to conform to each configured SiPM 41.

[0108] Thus, the two grouping methods include grouping the adders, grouping the adder circuit, or disabling individual microcells 2.

[0109] Grouping the adders results in using a hierarchical approach to add a large number of bits. For example, a naive approach or a Wallace tree can be used. Here, the adder branches can be selected to concentrate on a particular rectangular area (i.e. the area of a SiPM 41). Additional adder branches can be selected to concentrate on a second rectangular area corresponding to a second SiPM, and so on. This can be achieved by adding columns along rows, and then adding rows along the edges of the array (or vice versa).

[0110] Deactivating the microcells in regions that do not correspond to a target SiPM 41 is another way of defining a set of active microcells that form one or more target SiPMs 41. This technique can be used to produce one or more SiPMs, or conversely to deactivate any arbitrary shaped region of microcells.

[0111] Figure 8 is a schematic diagram of a hierarchical adder tree 800 according to one or more embodiments. The hierarchical adder tree 800 includes a hierarchy of five tiers of adders representing the tiers of adder circuits described above. The hierarchical adder tree 800 also includes a summing circuit 8 that receives the outputs of the adder circuits. The adder tree adds a total of 32 bits, but outputs 6 bits to represent the result.

[0112] The first tier (tier 1) includes a first plurality of adders 81, each coupled to the outputs OUT2 of a different pair of adjacent microcells. For example, when defining a SiPM 41 having a row of thirty-two microcells, sixteen adders 81 can be used. In this example, each adder 81 can be a half-adder (HA) that generates a 2-bit output value.

[0113] In the second tier (tier 2), the hierarchical adder tree 800 includes a second plurality of adders 82, each coupled to a different pair of adjacent adders 81. The adders 82 can each be formed using a full-adder (FA) and a half-adder, and generate a 3-bit output value.

[0114] In the third tier (tier 3), the hierarchical tier tree 800 includes a plurality of third adders 83, each coupled to a different pair of adjacent adders 82. The adders 83 can each be formed using two full-adders and a half-adder, and generate a 4-bit output value.

[0115] In the fourth tier (tier 4), the hierarchical tier tree 800 includes a fourth plurality of adders 84, each coupled to a different pair of adjacent adders 83. Each adder 84 can be formed using three full-adders and a half-adder, and generate a 5-bit output value. In addition, four 1-bit flip-flops (FFs) 86 can be coupled between the adders 83 and 84 to pipeline the operation.

[0116] In the fifth level (Level 5), the level hierarchy tree 800 includes fifth adders 85, each coupled to a pair of adjacent adders 84. The adders 85 can be formed using four full adders and one half adder, and generate a 6-bit output value, which represents a digital value for a microcell row of the SiPM 41. The 6-bit output value can be transmitted to a clocked memory device 87 including six 1-bit flip-flops. The six flip-flops capture the 6-bit value output by the adder 85 at each clock cycle of a clock signal CLK and output the 6-bit value to a summation circuit 8. The summation circuit 8 adds the 6-bit values received from each microcell row, which defines the SiPM 41 to generate a pixel value for the SiPM 41.

[0117] Additional examples of one or more embodiments are provided.

[0118] The photodetector array includes an array of SiPMs, where each SiPM includes a plurality of microcells, each microcell including a SPAD. The plurality of microcell units can be grouped into one or more SiPM pixels, where the grouping into SiPM pixels can be: flexible (via a configuration file or control signal); contiguous (i.e., a SiPM pixel can include a set of geometrically contiguous microcells); non-contiguous (i.e., a SiPM pixel can include two or more sets of microcells that are geometrically separated or non-contiguous from each other), can include non-detecting microcells that are intentionally blinded or un-biased, the plurality of microcells configured to be dynamically grouped into a plurality of SiPM pixels, and / or one or more SiPMs can be produced on-the-fly between clock cycles and can be reconfigured on-the-fly.

[0119] Additionally, a global reset can be applied to the entire microcell array or a portion of the microcell array.

[0120] Additionally, the photon counting in the SiPM pixels can be started synchronously.

[0121] Additionally, the number of photon counts in the SiPM pixels can be digitally performed during the time between two consecutive resets.

[0122] In view of the above, each pixel is configured to record a time series of the incident light signal with very high timing resolution. For an analog photodetector, this requires a very fast ADC. Since the distance to the target is determined by the arrival time of the pulse, the timing resolution directly determines the distance resolution. The typical timing resolution required is on the order of 1 ns, resulting in an ADC sampling rate on the order of 1 GHz.

[0123] According to one or more embodiments, all SPADs are running (i.e., active) in sync. The result of the photodetection at each SPAD is stored in the corresponding D flip-flop and the SPAD is recharged once per clock cycle. All active SPADs do this simultaneously. Likewise, the summation of the individual bits of a SPAD is done at this clock rate. The result is a very fast stream of values from each of the pixels, effectively one value per nanosecond.

[0124] According to one or more embodiments, the SPADs are freely grouped (i.e., on a dynamic basis) as configurable digital SiPMs to effectively define“pixels” on the fly. These“pixels” are not limited to a fixed raster, but can vary in size, shape, and location in the SPAD array. This allows the sensor to more precisely match the pixels to the shape and expected location of a light pulse. By reducing or increasing the size of the“pixels”, the resolution can also be flexibly increased or decreased. As Figure 7A and Figure 7B This works for both 2D scanning LIDARs that receive a circular light spot at the pixel array, as well as 1D LIDARs that work with a full line of reception, as shown. In the latter case, it is most obvious that the line is subdivided into individual pixels on the microcell array. Since the location of the“pixels” can be freely varied, the sensor can also compensate for distortions of the optical elements, allowing for the use of less expensive lenses.

[0125] In fact, only a small fraction of the microcell array can be active at any given time. This can reduce the power consumption, but equally important, it can also reduce the amount of data that is transferred. It is not possible to transfer data from the entire array off-chip at 1 GHz. In a 1D LIDAR sensor that uses vertical lines, for example, only data from 32 pixels can be transferred at a time.

[0126] It should also be noted that noise and range, TIA, ADC, and power consumption are all major difficulties of current APD solutions, all of which can be improved or eliminated by the present embodiments.

[0127] While the embodiments described herein relate to LIDAR systems, it should be understood that SiPMs can be used for other applications. Thus, the entire SiPM and digital photodetector array are not limited to LIDAR.

[0128] Furthermore, although some aspects have been described in the context of an apparatus, it is clear that separate aspects also correspond to the description of a corresponding method, where a block or device corresponds to a method step or a feature of a method step. Analogously, aspects described in the context of a method step also represent separate aspects of corresponding blocks or items or features of a corresponding apparatus. Some or all of the method steps can be executed by (or using) a hardware apparatus, like for example, a microprocessor, a programmable computer or an electronic circuit. In some embodiments, some one or more of the method steps can be executed by such an apparatus.

[0129] Depending on certain implementation requirements, embodiments provided in the present disclosure can be implemented in hardware or in software. The implementation can be performed using a digital storage medium, for example a floppy disk, a DVD, a Blu-Ray, a CD, a ROM, a PROM, an EPROM, an EEPROM or a FLASH memory, having electronically readable control signals stored thereon, which cooperate (or are capable of cooperating) with a programmable computer system such that the respective method is performed. Therefore, the digital storage medium can be computer readable medium.

[0130] The instructions can be executed by one or more processors, such as one or more central processing units (CPU's), digital signal processors (DSP's), general purpose microprocessors, application-specific integrated circuits (ASIC's), field programmable logic arrays (FPGA's), or other equivalent integrated or discrete logic circuitry. Accordingly, as used herein the term "processor" encompasses any of the above structures or any other structure suitable for implementing the techniques described herein. In addition, in some aspects, the functionality described herein can be provided within dedicated hardware and / or software modules. Also, the techniques could be fully implemented in one or more circuits or logic elements.

[0131] The exemplary embodiments described above are merely meant to be illustrative embodiments. It should be understood by those skilled in the art that modifications and variations to the described devices and details are possible. Therefore, it is intended that only the scope of the appended patent claims limit the disclosure, and not the specific details set forth in the description and explanation of the embodiments herein.

Claims

1. A digital light detector comprising: a clock signal generator configured to generate a clock signal consisting of clock pulses generated at a predetermined frequency; a single-photon avalanche diode (SPAD) configured to turn on and generate an avalanche current in response to receiving a photon, the SPAD comprising an anode terminal, a cathode terminal, and an internal capacitor internally coupled between the anode terminal and the cathode terminal; an active inhibit-recharge circuit comprising an output node and triggered by the clock signal, wherein the active inhibit-recharge circuit is configured to: being activated and deactivated based on the clock signal; recharging the internal capacitor under conditions where the active suppression-recharge circuit is activated; as well as discharging the internal capacitor under a condition where the active suppression-recharge circuit is disabled; a level shifter coupled to the output node and configured to convert an output potential at the output node into a digital value; as well as A clocked 1-bit memory device is configured to receive the clock signal from the clock signal generator, receive the digital value from the level shifter, and output the digital value at each clock pulse of the clock signal on a per clock cycle basis.

2. The digital photodetector of claim 1 , wherein the active suppression-recharge circuit further comprises: a control terminal coupled to the clock signal generator, wherein the control terminal is configured to receive the clock signal to actively charge the internal capacitor based on a charging condition being satisfied; Wherein, the charging condition is satisfied under the condition that the clock pulse of the clock signal is received while the internal capacitor is in a discharged state.

3. The digital light detector according to claim 2, wherein The active suppression-recharge circuit includes a transistor coupled in series with the SPAD, and The transistor includes the control terminal.

4. The digital photodetector of claim 3, wherein the transistor is coupled to the SPAD at the output node.

5. The digital photodetector of claim 2, wherein the internal capacitor discharges in response to the SPAD receiving the photon. 6 . The digital photodetector of claim 2 , wherein the internal capacitor is in the discharged state when a capacitor voltage of the internal capacitor is less than a bias voltage potential.

7. The digital light detector according to claim 6, wherein The SPAD has a breakdown voltage less than the bias voltage potential, and When the capacitor voltage of the internal capacitor is equal to or less than the breakdown voltage, the internal capacitor is in the discharge state.

8. The digital light detector according to claim 6, wherein The active suppression-recharge circuit is configured to turn on in response to the charging condition being met, thereby charging the internal capacitor to the bias voltage potential, and The active suppression-recharge circuit is configured to shut down in response to the internal capacitor being charged to the bias voltage potential, and remain shut down until the charging condition is again met.

9. The digital photodetector of claim 8, wherein the SPAD is configured to turn off in response to the internal capacitor being discharged to the discharged state, and remain off until another photon is received.

10. The digital light detector according to claim 8, wherein The internal capacitor is discharged in response to the SPAD receiving the photon, and The clock signal generator and the active inhibit-recharge circuit impose a hold time between when the internal capacitor is discharged to the discharged state and when the charging condition is met or is met again before enabling the internal capacitor to charge to the bias voltage potential.

11. The digital light detector according to claim 2, wherein The SPAD and the active suppression-recharge circuit are configured to generate a first potential at the output node in response to the SPAD being turned on, and The SPAD and the active suppression-recharge circuit are configured to generate a second potential at the output node in response to the SPAD being turned off. 12 . The digital photodetector of claim 11 , wherein the SPAD is configured to turn off in response to the internal capacitor being discharged to the discharged state, and remain off until another photon is received.

13. The digital photodetector of claim 1, wherein the internal capacitor is a stray capacitance or a parasitic capacitance of the SPAD.

14. A method of operating a digital light detector, the method comprising: providing a bias voltage potential; generating a clock signal, the clock signal consisting of clock pulses generated at a predetermined frequency; turning on a single photon avalanche diode (SPAD) and generating an avalanche current in response to receiving a photon, wherein the SPAD includes an anode terminal, a cathode terminal, and an internal capacitor coupled internally between the anode terminal and the cathode terminal; controlling an activation state of an active inhibition-recharge circuit based on the clock signal; charging the internal capacitor under a condition in which the active suppression-recharge circuit is activated; discharging the internal capacitor under a condition where the active suppression-recharge circuit is disabled; converting an output potential at an output node of the active suppression-recharge circuit into a digital value via a level shifter coupled to the output node of the active suppression-recharge circuit; as well as The clock signal and the digital value from the level shifter are received by a clocked 1-bit memory device and the digital value is output at each clock pulse of the clock signal on a per clock cycle basis.

15. The method of claim 14, wherein charging the internal capacitor further comprises: A charging condition is satisfied, wherein the charging condition is satisfied under the condition that a clock pulse of the clock signal is received while the internal capacitor is in a discharged state.

16. A digital silicon photomultiplier tube device, comprising: a clock signal generator configured to generate a clock signal consisting of clock pulses generated at a predetermined frequency; A microcell array, wherein each microcell comprises: a single-photon avalanche diode (SPAD) configured to turn on and generate an avalanche current in response to receiving a photon, the SPAD comprising an anode terminal, a cathode terminal, and an internal capacitor coupled internally between the anode terminal and the cathode terminal; and an active inhibit-recharge circuit comprising an output node and triggered by the clock signal, wherein the active inhibit-recharge circuit is configured to: being activated and deactivated based on the clock signal; recharging the internal capacitor under conditions where the active suppression-recharge circuit is activated; discharging the internal capacitor under a condition where the active suppression-recharge circuit is disabled; and a digital output configured to output a digital value corresponding to a potential generated at an output node of the active suppression-recharge circuit; and a summing circuit configured to receive digital values ​​from the microcell array and generate a digital pixel value for the silicon photomultiplier tube based on a sum of the digital values, Each microunit also includes: a level shifter coupled to the output node and configured to convert an output potential at the output node into a digital value; and A clocked 1-bit memory device is configured to receive the clock signal from the clock signal generator, receive the digital value from the level shifter, and output the digital value at each clock pulse of the clock signal on a per clock cycle basis.

17. The digital silicon photomultiplier tube device of claim 16, wherein each active suppression-recharge circuit comprises: a control terminal coupled to the clock signal generator, wherein the control terminal is configured to receive the clock signal to actively charge the internal capacitor of the corresponding SPAD based on a charging condition being met; The charging condition is satisfied under the condition that the internal capacitor of the corresponding SPAD is in a discharged state and a clock pulse of the clock signal is received.

18. The digital silicon photomultiplier tube device of claim 16, wherein the internal capacitor is discharged in response to the SPAD receiving the photon.

19. The digital silicon photomultiplier tube device of claim 17, wherein the internal capacitor is in the discharged state when a capacitor voltage of the internal capacitor is less than a bias voltage potential.

20. The digital silicon photomultiplier tube device according to claim 19, wherein The breakdown voltage of each SPAD is less than the bias voltage potential, and Each internal capacitor is configured to be in the discharge state when a capacitor voltage of the internal capacitor is equal to or less than the breakdown voltage.

21. The digital silicon photomultiplier tube device according to claim 20, wherein Each active suppression-recharge circuit is configured to turn on in response to the charging condition being met, thereby charging an internal capacitor of the active suppression-recharge circuit to the bias voltage potential, and Each active suppression-recharge circuit is configured to switch off in response to an internal capacitor of the active suppression-recharge circuit being charged to the bias voltage potential, and to remain off until the charging condition is again met.

22. The digital silicon photomultiplier tube device of claim 21, wherein each SPAD is configured to turn off in response to the internal capacitor of the SPAD being discharged to the discharged state, and remain off until another photon is received.

23. The digital silicon photomultiplier tube device according to claim 21, wherein Each internal capacitor is configured to be discharged in response to the SPAD of the internal capacitor receiving the photon, and The clock signal generator and each active suppression-recharge circuit impose a hold time between the time the corresponding internal capacitor is discharged to the discharged state and the time the charging condition of the corresponding internal capacitor is met or is met again before enabling the corresponding internal capacitor to charge to the bias voltage potential.

24. The digital silicon photomultiplier tube device according to claim 16, wherein The SPAD and each active suppression-recharge circuit are configured to generate a first potential at the output node in response to the corresponding SPAD being turned on, and The SPAD and each active inhibit-recharge circuit are configured to generate a second potential at the output node in response to the corresponding SPAD being turned off.

25. The digital silicon photomultiplier tube device of claim 24, wherein each SPAD is configured to be turned off in response to the internal capacitor of the SPAD being discharged to a discharged state, and to remain off until another photon is received.

26. The digital silicon photomultiplier tube device of claim 16, wherein the array of microcells is synchronously recharged at each clock cycle of the clock signal.

27. The digital silicon photomultiplier tube device of claim 16, wherein at each clock pulse of the clock signal, the discharged SPADs in a discharged state are synchronously recharged so that the corresponding internal capacitor of each of the discharged SPADs is charged to a bias voltage potential.

28. A method for synchronously operating a plurality of single-photon avalanche diodes (SPADs) of a digital silicon photomultiplier tube, the method comprising: providing a bias voltage potential; generating a clock signal, the clock signal consisting of clock pulses generated at a predetermined frequency; providing the clock signal to a plurality of microcells of the digital silicon photomultiplier tube, wherein each microcell of the plurality of microcells comprises a corresponding SPAD of a plurality of SPADs and a corresponding active suppression-recharge circuit triggered by the clock signal; controlling an activation state of each active inhibit-recharge circuit based on the clock signal; charging an internal capacitor of a corresponding SPAD among the plurality of SPADs under a condition that the corresponding active suppression-recharge circuit is activated; discharging an internal capacitor of a corresponding SPAD of the plurality of SPADs under a condition that the corresponding active suppression-recharge circuit is disabled; converting an output potential at an output node of a corresponding active suppression-recharge circuit into a digital value via a level shifter coupled to the output node of the active suppression-recharge circuit; as well as A clock-controlled 1-bit memory device receives the clock signal and the digital value from the level shifter, and outputs the digital value of each microcell in the plurality of microcells at each clock pulse of the clock signal on a per clock cycle basis.

29. The method according to claim 28, further comprising: The activation state of each corresponding active suppression-recharging circuit is controlled based on the clock signal received at the control terminal of each corresponding active suppression-recharging circuit and based on the charging condition of the SPAD corresponding to each corresponding active suppression-recharging circuit being satisfied, wherein the charging condition is satisfied under the condition that a clock pulse of the clock signal is received while the internal capacitor of the corresponding SPAD is in a discharged state.

30. The method of claim 28, further comprising: The digital values ​​output from the plurality of microcells are summed at each clock pulse of the clock signal to generate a digital pixel value for the digital silicon photomultiplier tube based on the sum of the digital values.

31. The method of claim 28, further comprising: The plurality of microcells are synchronously recharged at each clock cycle of the clock signal.

32. The method of claim 28, further comprising: On each clock pulse of the clock signal, the discharged SPADs in the discharged state are synchronously recharged so that a corresponding internal capacitor of each of the discharged SPADs is charged to the bias voltage potential.

33. A system for flexibly configuring at least one silicon photomultiplier (SiPM), the system comprising: A microcell array, each microcell comprising: a single-photon avalanche diode (SPAD) configured to turn on and generate an avalanche current in response to receiving a photon, the SPAD comprising an anode terminal, a cathode terminal, and an internal capacitor internally coupled between the anode terminal and the cathode terminal; an active inhibit-recharge circuit that is triggered by a clock signal, wherein the active inhibit-recharge circuit is configured to be activated and deactivated based on the clock signal; wherein the active suppression-recharge circuit is configured to recharge the internal capacitor under a condition where the active suppression-recharge circuit is activated, wherein the active suppression-recharge circuit is configured to discharge the internal capacitor under a condition where the active suppression-recharge circuit is disabled; and a digital output configured to output a digital value corresponding to a potential generated at an output node of the active suppression-recharge circuit; A controller is configured to dynamically group portions of the microcell array to form a SiPM.

34. The system of claim 33, wherein the controller is configured to determine an area of ​​the microcell array from which backscattered laser light is expected to be received, determine a portion of the microcells located in the determined area, and group the determined portion of the microcells together to form the SiPM.

35. The system of claim 34, wherein The area of ​​the microcell array from which backscattered laser light is expected to be received changes over time, and The controller is configured to reconfigure the SiPM as the region changes over time.

36. The system of claim 35, further comprising: A summing circuit is configured to receive digital values ​​from portions of the microcells and generate a digital pixel value for the SiPM based on a sum of the digital values.

37. The system of claim 33, further comprising: A summing circuit is configured to receive digital values ​​from portions of the microcells and generate a digital pixel value for the SiPM based on a sum of the digital values.

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