A frequency adaptive circuit for a non-contact smart card chip

Abstract

The present invention provides a frequency adaptive circuit for a non-contact smart card chip, which includes a limiting circuit, a bypass current sampling circuit, a current-voltage-current conversion circuit, and a ring oscillator. The structure in which the limiting circuit is sequentially connected to the bypass current sampling circuit, the current-voltage-current conversion circuit, and the ring oscillator newly adds a ring oscillator, and uses the field strength signal to control the output frequency of the ring oscillator to achieve the frequency adaptive function; at the same time, a bypass current sampling circuit is newly added, and the bypass current in the limiting circuit is used as the field strength indication signal, and through the current-voltage-current conversion circuit, the linear range of the control of the output frequency of the ring oscillator is expanded, and the linearity and smoothness of the system frequency's adaptive transformation to the field strength are improved. Compared with the traditional non-contact card system, when the field strength changes for the card adopting the present invention, the switching speed of the system operating frequency is faster, more linear, and more continuous; the hardware implementation has less overhead and lower power consumption.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit non-contact smart cards, and particularly to a frequency adaptive circuit for a non-contact smart card chip. Background Art

[0002] In high-frequency non-contact smart card applications, the card obtains energy from the reader through inductive coupling. The larger the coupling coefficient, the more energy the card obtains and the faster it operates. Conversely, the smaller the coupling coefficient, the less energy the card obtains and the slower it operates. If the operating speed of the card does not match the energy obtained, it will result in energy waste or power-down reset. This technology is called Frequency Adaptive (FA) in the design of non-contact smart card chips. A good frequency adaptive technology has characteristics such as fast response speed, smooth frequency transition, and small hardware overhead.

[0003] In the existing design of non-contact card frequency adaptive circuits, the digital and analog circuits often work together to achieve it. As Figure 1 shown, it is the structural diagram of the frequency adaptive circuit of an existing non-contact smart card chip. The rectifier limiter circuit in the card converts the AC power supply coupled by the antenna into a DC power supply and limits the voltage amplitude to protect the chip safety. The existing frequency adaptive circuit consists of four main circuits: 1) a field strength detection circuit; 2) an ADC circuit; 3) a logic control unit; and 4) a system clock unit. The field strength detection circuit converts the magnetic field strength into a voltage signal VFS; the ADC circuit converts the voltage signal VFS into a six-bit digital signal vfs<5:0>; the logic control unit adjusts the output frequency of the system clock unit according to the magnitude of the input vfs<5:0>.

[0004] However, the existing frequency adaptive circuit of non-contact cards has problems such as complex system structure, high power consumption, slow response time, and uneven frequency switching. At the same time, there is also the problem of insufficient energy utilization efficiency. Summary of the Invention

[0005] Aiming at the deficiencies existing in the above-mentioned prior art, the purpose of the present invention is to provide a frequency adaptive circuit for a non-contact smart card chip. The present invention simplifies the field strength detection circuit, removes the complex ADC circuit and logic control unit in the existing circuit, and newly adds a ring oscillator, and uses the field strength signal to control the output frequency of the ring oscillator to achieve the frequency adaptive function; at the same time, uses the bypass current in the limiter circuit as the field strength indication signal, and through the current-voltage-current conversion circuit, expands the linear range of the control of the output frequency of the ring oscillator, and improves the linearity and smoothness of the system frequency's adaptive transformation to the field strength.

[0006] To achieve the above technical objectives, the technical solution adopted by the present invention is as follows:

[0007] A frequency adaptive circuit for a non-contact smart card chip, the frequency adaptive circuit comprising a limiting circuit, a bypass current sampling circuit, a current-voltage-current conversion circuit, and a ring oscillator. Among them, the limiting circuit is sequentially connected to the bypass current sampling circuit, the current-voltage-current conversion circuit, and the ring oscillator. The current-voltage-current conversion circuit outputs a current to control the output frequency of the ring oscillator;

[0008] The current-voltage-current conversion circuit is divided into a current-voltage conversion circuit and a voltage-current conversion circuit;

[0009] The bypass current sampling circuit is connected to the limiting circuit and samples the bypass current in the limiting circuit at a ratio of 1000:1 as the field strength signal;

[0010] The current-voltage-current conversion circuit is connected to the bypass current sampling circuit. The current-voltage conversion circuit therein converts the sampled current into a voltage signal, and the voltage-current conversion circuit therein converts the voltage signal into a current signal of the ring oscillator. The current-voltage-current conversion circuit is also responsible for filtering out high-frequency noise in the sampled current signal and controlling the loop response speed;

[0011] The ring oscillator is connected to the current-voltage-current conversion circuit, and the output frequency of the ring oscillator is proportional to the output current of the current-voltage-current conversion circuit;

[0012] When the frequency adaptive circuit works, when the field strength increases, the bypass current in the limiting circuit increases, that is, the sampled current increases, the output current of the current-voltage-current conversion circuit increases, and the oscillation frequency of the ring oscillator increases, and the operating speed of the frequency adaptive circuit increases; conversely, when the field strength decreases, the bypass current in the limiting circuit decreases, that is, the sampled current decreases, the output current of the current-voltage-current conversion circuit decreases, and the oscillation frequency of the ring oscillator decreases, and the operating speed of the frequency adaptive circuit slows down.

[0013] Due to the adoption of the structure in which the above-mentioned limiter circuit is sequentially connected to the bypass current sampling circuit, the current-voltage-current conversion circuit, and the ring oscillator, the beneficial effects obtained by the present invention are as follows: A ring oscillator is newly added, and the output frequency of the ring oscillator is controlled by the field strength signal to achieve the frequency adaptive function; at the same time, a bypass current sampling circuit is newly added, and the bypass current in the limiter circuit is used as the field strength indication signal, and through the current-voltage-current conversion circuit, the linear range of the control of the output frequency of the ring oscillator is expanded, and the linearity and smoothness of the system frequency's adaptive transformation to the field strength are improved. Compared with the traditional non-contact card system, when the field strength changes, the operating frequency of the card adopting the present invention switches faster, more linearly, and more continuously; the hardware implementation has less overhead and lower power consumption.

[0014] The following further describes the present invention in conjunction with the drawings and specific embodiments. Brief Description of the Drawings

[0015] Figure 1 is the circuit structure diagram of the frequency adaptive circuit of the existing non-contact smart card chip.

[0016] Figure 2 is the block diagram of the frequency adaptive circuit of the non-contact smart card chip of the present invention.

[0017] Figure 3 is the circuit structure diagram of the frequency adaptive circuit of the non-contact smart card chip in the specific implementation of the present invention.

[0018] Figure 4 is the relationship diagram between the output frequency and the input current of the frequency adaptive circuit of the non-contact smart card chip in the specific implementation of the present invention. Specific Embodiments

[0019] The following specific examples illustrate the embodiments of the present invention. Those skilled in the art can easily understand the other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0020] Refer to Figure 2, which is a block diagram of the frequency adaptive circuit of the contactless smart card chip of the present invention. The frequency adaptive circuit of the contactless smart card chip includes a limiting circuit, a bypass current sampling circuit, a current-voltage-current conversion circuit, and a ring oscillator. Among them, the limiting circuit is sequentially connected to the bypass current sampling circuit, the current-voltage-current conversion circuit, and the ring oscillator. The current-voltage-current conversion circuit outputs a current to control the output frequency of the ring oscillator; the bypass current sampling circuit is connected to the limiting circuit, the current-voltage-current conversion circuit is connected to the bypass current sampling circuit, the ring oscillator is connected to the current-voltage-current conversion circuit, and the ring oscillator outputs a frequency.

[0021] See Figure 3 , which is a structural diagram of the frequency adaptive circuit of the contactless smart card chip in the specific implementation of the present invention. The frequency adaptive circuit of the contactless smart card chip includes a limiting circuit, a bypass current sampling circuit, a current-voltage-current conversion circuit, and a ring oscillator OSC. Among them, the limiting circuit is sequentially connected to the bypass current sampling circuit, the current-voltage-current conversion circuit, and the ring oscillator OSC. The current-voltage-current conversion circuit outputs a current to control the output frequency of the ring oscillator OSC f out; the current-voltage-current conversion circuit is divided into a current-voltage conversion circuit and a voltage-current conversion circuit; the bypass current sampling circuit is connected to the limiting circuit and samples the bypass current Ipass in the limiting circuit at a ratio of 1000:1 as the field strength signal.

[0022] Among them, resistor R1, resistor R2, amplifier 1, and NMOS transistor MN0 form a limiting circuit, and the output voltage VRF is clamped at 3V. When the output voltage VRF is greater than 3V, the sampling voltages of resistor R1 and resistor R2 increase, that is, the voltage at the positive input terminal of amplifier 1 increases, so the output voltage increases, and the bypass current Ipass flowing through NMOS transistor MN0 increases, reducing the output voltage VRF; conversely, the bypass current Ipass decreases, increasing the output voltage VRF, and finally forcing the output voltage VRF to be equal to 3V.

[0023] See Figure 3The middle block diagram is a bypass current sampling circuit, which consists of an NMOS transistor MN1, an NMOS transistor MN2, an NMOS transistor MN3, a PMOS power transistor MP0, a bias voltage VB, and a low-pass filter. The low-pass filter is composed of a resistor R0 and a capacitor C0. The NMOS transistor MN1 is a sampling MOS transistor, and the ratio of the NMOS transistor MN1 to the NMOS transistor MN0 in the limiting circuit is 1000:1; the NMOS transistors MN2 and MN3 are cascode transistors, and the gate terminal bias voltage Vb = 1.2V. The NMOS transistors MN2 and MN3 ensure that the drain terminal voltages of the NMOS transistors MN0 and MN1 are equal, improving the sampling accuracy. The PMOS power transistor MP0 is the diode load of the NMOS transistor MN1. In the electric field strength range of 1~5A / m, the typical value of the bypass current I_PASS is between 1mA and 18mA, then the current Isample sampled by the NMOS transistor MN1 is 1uA~18uA. The resistor R0 and the capacitor C0 form a low-pass filter to filter out high-frequency noise. At the same time, the low-pass filter controls the loop response speed, and the cut-off frequency is usually set at 0.8~2MHz.

[0024] See Figure 3In the right block diagram, there is a current-voltage-current conversion circuit. The current-voltage-current conversion circuit is divided into two parts: a current-voltage conversion circuit and a voltage-current conversion circuit. The PMOS power transistor MP1 and the PMOS power transistor MP0 in the bypass current sampling circuit form a 1:1 current mirror. The mirror current generates a control voltage VC across the resistor R3, forming the current-voltage conversion circuit. When the sampling current Isample increases, the control voltage VC increases; when the resistor R3 is equal to 100Kohm, since the sampling current Isample ranges from 1uA to 18uA, the control voltage VC ranges from 100mV to 1.8V. The tail current IB, resistor R4, resistor R5, PMOS power transistor MP2, PMOS power transistor MP3, NMOS transistor MN4, NMOS transistor MN5, and the reference voltage Vref form the voltage-current conversion circuit. The reference voltage Vref is equal to 0.8V. When VC increases, according to the characteristics of the differential pair circuit, the current IC1 flowing through the PMOS power transistor MP2 decreases. Since IC1 + IC2 = IB remains constant, the current IC2 increases. In this way, the control voltage VC is proportional to the current IC2, realizing the conversion from the voltage VC to the current IC2. The functions of the resistors R4 and R5 are to improve the linearity of the conversion from the voltage VC to the current IC2. IB = 20uA. During the change of the voltage VC from 100mV to 1.8V, the current IC2 increases from 0uA to 20uA. The NMOS transistor MN5 and the NMOS transistor MN6 form a 1:2 current mirror, and the PMOS power transistor MP4 and the PMOS power transistor MP5 form a 1:1 current mirror. These two current mirrors convert the current IC2 into the output current Iosc, and Iosc = 2 * IC2. The value range of the output current Iosc is 0 to 40uA. In summary, when the bypass current Ipass linearly increases from 1mA to 18mA, that is, when the field strength increases from 1A / m to 5A / m, the output current Iosc increases from 0uA to 40uA.

[0025] See Figure 4 , which is the relationship diagram of the output frequency and the field strength of the input current of the frequency adaptive circuit of the non-contact smart card chip in the specific implementation of the present invention. Combining Figure 3 , the ring oscillator OSC is connected to the current-voltage-current conversion circuit, and the output frequency f out of the ring oscillator OSC is proportional to the output current of the current-voltage-current conversion circuit; since the output current Iosc is proportional to the field strength, the relationship between the field strength and the output frequency f out of the ring oscillator OSC is as Figure 4 shown. It can be seen from the figure that the present invention well realizes the automatic adjustment of the chip operating frequency under different field strengths.

[0026] When the frequency adaptive circuit of the non-contact smart card chip is operating, when the field strength increases, the bypass current Ipass in the limiter circuit increases, that is, the sampling current increases, the output current of the current-voltage-current conversion circuit increases, and the oscillation frequency of the ring oscillator OSC increases, and the operating speed of the frequency adaptive circuit increases; conversely, when the field strength decreases, the bypass current Ipass in the limiter circuit decreases, that is, the sampling current decreases, the output current of the current-voltage-current conversion circuit decreases, and the oscillation frequency of the ring oscillator OSC decreases, and the operating speed of the frequency adaptive circuit slows down.

[0027] In the frequency adaptive circuit solution of the present invention, since the adjustment process is realized by pure analog quantity, during the change of the field strength, the change of the output frequency of the ring oscillator OSC will not generate quantization errors like the traditional frequency adaptive circuit solution, and the adjustment of the frequency is smoother. Since modules such as the ADC circuit and the logic control unit are removed, the present invention saves a large amount of hardware overhead and reduces the power consumption of the chip. In terms of response time, the response time of the present invention is determined by the cut-off frequency of the low-pass filter and can be controlled within 5uS, while the traditional frequency adaptive circuit implementation method requires at least 10uS due to the response time limitation of circuits such as the ADC.

[0028] It should be noted that the above embodiments only illustrate the basic idea of the present invention in a schematic manner, and are drawn according to the circuit components related to the present invention rather than the number, shape, device arrangement, and connection method of the circuits in actual implementation. The types, quantities, connection methods, device arrangements, and device parameters of each circuit can be changed arbitrarily during actual implementation.

[0029] The above-described embodiments are only preferred embodiments of the present invention and cannot limit the extension of the technical solution of the present invention. Any modification, equivalent change, and obvious replacement of well-known technologies made by those skilled in the art based on the technical solution of the present invention shall fall within the protection scope of the present invention.

Claims

1. A frequency adaptive circuit for a non-contact smart card chip, characterized in that, The frequency adaptive circuit includes a limiting circuit, a bypass current sampling circuit, a current-voltage-current conversion circuit, and a ring oscillator. Among them, the limiting circuit, the bypass current sampling circuit, the current-voltage-current conversion circuit, and the ring oscillator are connected in sequence; The limiting circuit is used to convert the AC power supply coupled by the antenna into a DC power supply and limit the voltage amplitude; The bypass current sampling circuit is connected to the limiting circuit, and the NMOS transistor MN1 in the bypass current sampling circuit and the NMOS transistor MN0 in the limiting circuit form a ratio of 1000:1, and is used to sample the bypass current in the limiting circuit as a field strength signal according to a ratio of 1000:1; The current-voltage-current conversion circuit is connected to the bypass current sampling circuit, and is used to convert the sampled current into a voltage signal and then convert it into a current signal of the ring oscillator; among them, the current signal is used to control the output frequency of the ring oscillator; The ring oscillator is connected to the current-voltage-current conversion circuit, and is used to generate an output frequency based on the current output by the current-voltage-current conversion circuit, and the output frequency is proportional to the current output by the current-voltage-current conversion circuit.

2. The frequency adaptive circuit according to claim 1, wherein The bypass current sampling circuit includes: NMOS transistor MN1, NMOS transistor MN2, NMOS transistor MN3, and PMOS power transistor MP0; The NMOS transistor MN1 is a sampling MOS transistor; The NMOS transistor MN2 and the NMOS transistor MN3 are casecode transistors, and the gate terminals are connected to a bias voltage; The PMOS power transistor MP0 is a diode load of the NMOS transistor MN1.

3. The frequency adaptive circuit according to claim 2, wherein The bypass current sampling circuit further includes a low-pass filter; the low-pass filter is used to filter out high-frequency noise in the sampled current signal and control the loop response speed.

4. The frequency adaptive circuit according to claim 2, wherein The current-voltage-current conversion circuit includes: a current-voltage conversion circuit, a voltage-current conversion circuit, and a current mirror circuit; The current-voltage conversion circuit is used to convert the sampled current into a control voltage VC; among them, the current-voltage conversion circuit includes: PMOS power transistor MP1 and resistor R3, and the PMOS power transistor MP1 and the PMOS power transistor MP0 in the bypass current sampling circuit form a 1:1 current mirror, and the resistor R3 converts the mirrored current into the control voltage VC; The voltage-current conversion circuit is used to linearly convert the control voltage VC into a current IC2; the voltage-current conversion circuit includes: differential pair PMOS power transistors MP2 and MP3, NMOS transistors MN4 and MN5, resistors R4 and R5; among them, the differential pair PMOS power transistors MP2 and MP3 output currents IC1 and IC2 according to the control voltage VC; The current mirror circuit is used to convert the current IC2 into an output current Iosc; the current mirror circuit includes: an NMOS transistor MN5 and an NMOS transistor MN6 forming a 1:2 current mirror, and a PMOS power transistor MP4 and a PMOS power transistor MP5 forming a 1:1 current mirror.

5. The frequency adaptive circuit according to claim 1, characterized in that The limiting circuit includes: a resistor R1, a resistor R2, an amplifier 1, and an NMOS transistor MN0, and is used to clamp the output voltage VRF at a preset voltage; The resistor R1 and the resistor R2 form a voltage dividing network, the positive input terminal of the amplifier 1 is connected to the voltage dividing network, the output terminal of the amplifier 1 drives the NMOS transistor MN0, and the NMOS transistor MN0 serves as a bypass switch.

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