Semiconductor packaging

Abstract

A semiconductor package may include: a first passivation layer electrically connected to one or more first bumps; a substrate layer including a second passivation layer and a silicon layer; a back-end-of-line (BEOL) layer formed on the substrate layer; and a third passivation layer formed on the BEOL layer electrically connected to one or more second bumps, wherein the substrate layer includes: a first signal through silicon via (TSV) transmitting a first signal between the BEOL layer and a first lower pad; a second signal TSV transmitting a second signal between the BEOL layer and a second lower pad; and a ground TSV disposed between the first signal TSV and the second signal TSV and formed such that one end thereof is connected to the BEOL layer and the other end thereof is floating.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2019-0062277 filed on May 28, 2019, with the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Various example embodiments of the inventive concepts are directed to a semiconductor package. Background Art

[0003] With the rapid development of the electronics industry and user needs, semiconductor packages used in electronic devices require miniaturization, high performance, low power consumption, etc., and three-dimensional integrated circuits (ICs) in the form of three-dimensional stacked chips have attracted attention to achieve such requirements. In addition, research and development of semiconductor packages including through silicon vias (TSVs) for the realization of three-dimensional ICs continues.

[0004] TSV plays a very important role in more advanced semiconductor chips, semiconductor packages and semiconductor systems such as three-dimensional ICs, but it has the problem of crosstalk noise. Crosstalk may occur due to undesired interactions between TSVs, or may occur due to undesired interactions between active components such as metal oxide semiconductor field effect transistors (MOSFETs) and TSVs. Since crosstalk increases the noise margin, which reduces signal reliability and increases the bit error rate in signal transmission, a solution to reduce crosstalk is needed. Summary of the invention

[0005] Aspects of various example embodiments related to the inventive concept provide a semiconductor package capable of reducing crosstalk occurring between TSVs inside the semiconductor package.

[0006] According to some example embodiments of the present inventive concept, a semiconductor package includes: a first passivation layer, including a first lower pad and a second lower pad, the first lower pad and the second lower pad are electrically connected to one or more first bumps, the first passivation layer includes a first back metal and a second back metal; a substrate layer, including a second passivation layer and a silicon layer, the substrate layer is formed on the first passivation layer; a back-end-of-line (BEOL) layer, including a plurality of metal layers, the BEOL layer is formed on the substrate layer; a third passivation layer formed on the BEOL layer, the third passivation layer includes a first upper pad and a second upper pad, the first The upper pad and the second upper pad are electrically connected to the one or more second bumps; and the substrate layer further includes: a first signal through silicon via (TSV) configured to transmit a first signal between the BEOL layer and the first lower pad through the first back metal; a second signal TSV configured to transmit a second signal between the BEOL layer and the second lower pad through the second back metal; and a ground TSV disposed between the first signal TSV and the second signal TSV, the ground TSV including a first end of the ground TSV connected to the BEOL layer and a second end of the ground TSV configured to float.

[0007] According to some example embodiments of the present inventive concept, a semiconductor package includes: a first passivation layer including a first lower pad and a second lower pad, the first passivation layer being electrically connected to one or more first bumps; a substrate layer formed on the first passivation layer; a back-end-of-line (BEOL) layer formed on the substrate layer; and the substrate layer including: a first signal through silicon via (TSV) configured to transmit a first signal between the first lower pad and the BEOL layer; a second signal TSV configured to transmit a second signal between the second lower pad and the BEOL layer; and at least one ground TSV that is not physically connected to the first bump.

[0008] According to some example embodiments of the present invention, a semiconductor package includes: a package substrate; an intermediate layer bonded to the package substrate through one or more first bumps, the intermediate layer including: a first passivation layer, the first passivation layer including a first lower pad and a second lower pad, the first lower pad and the second lower pad being electrically connected to the one or more first bumps, the first passivation layer including a first back metal and a second back metal; a back-end-of-line (BEOL) layer including a plurality of metal layers, the BEOL layer being formed on the substrate layer; the substrate layer including: a second passivation layer and a silicon layer, the substrate layer being formed on the first passivation layer; a first signal through silicon via (TSV) configured to pass through the first back A metal transmits a first signal between the BEOL layer and the first lower pad; a second signal TSV configured to transmit a second signal between the BEOL layer and the second lower pad through a second back metal; and a ground TSV disposed between the first signal TSV and the second signal TSV, the ground TSV including a first end and a second end, the first end being connected to the BEOL layer, and the second end being configured to float; and a third passivation layer formed on the BEOL layer, the third passivation layer including a first upper pad and a second upper pad, the third passivation layer being electrically connected to one or more second bumps; and a first semiconductor chip bonded to the intermediate layer through the one or more second bumps.

[0009] However, aspects of the exemplary embodiments of the present invention are not limited to the aspects set forth herein. The above and other aspects of the exemplary embodiments will become more apparent to those skilled in the art to which the exemplary embodiments pertain by referring to the detailed description of the exemplary embodiments of the present invention given below. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects and features of the inventive concept will become more apparent by describing in detail example embodiments thereof with reference to the accompanying drawings, in which:

[0011] Figure 1 is a diagram for explaining a semiconductor package according to at least one example embodiment of the inventive concept;

[0012] Figure 2 is a diagram for explaining a semiconductor package according to at least one example embodiment of the inventive concept;

[0013] Figure 3 is a diagram for explaining an interposer according to at least one example embodiment of the inventive concept;

[0014] Figures 4 to 8 is a diagram for explaining a horizontal cross-section of an intermediate layer according to various example embodiments of the inventive concept; and

[0015] Figures 9 to 12 are diagrams for explaining intermediate layers according to some example embodiments of the inventive concept. DETAILED DESCRIPTION

[0016] Hereinafter, various exemplary embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0017] Figure 1 is a diagram for explaining a semiconductor package according to at least one example embodiment of the inventive concepts.

[0018] Reference Figure 1 A semiconductor package 1 according to at least one example embodiment of the present inventive concept may include a first semiconductor chip 5, an interposer 10, a second semiconductor chip 12, and a package substrate 20 and / or a printed circuit board 30, etc., but is not limited thereto and may include a greater or lesser number of constituent elements.

[0019] The intermediate layer 10 may be bonded on the package substrate 20 through one or more first bumps C4 Bumps (eg, first C4 bumps, etc.), but example embodiments are not limited thereto.

[0020] The first semiconductor chip 5 may be bonded to the intermediate layer 10 by one or more second bumps uBump (eg, second uBump bumps), but example embodiments are not limited thereto. In some example embodiments of the present inventive concept, the first semiconductor chip 5 may include an application specific integrated circuit (ASIC), but example embodiments are not limited thereto.

[0021] like Figure 1 As shown in , the size of the first bump C4 Bump is greater than the size of the second bump uBump, in other words, the C4 bump is larger than the uBump, but example embodiments are not limited thereto.

[0022] The second semiconductor chip 12 may be arranged in parallel with the intermediate layer 10 and bonded to the package substrate 20, but example embodiments are not limited thereto. The second semiconductor chip 12 may also be bonded to the package substrate 20 using one or more first C4 bumps, but example embodiments are not limited thereto. The package substrate 20 may be bonded to the printed circuit board 30 via a ball grid array (BGA), but is not limited thereto. That is, the printed circuit board 30 may be bonded to the lower portion of the package substrate 20 via a BGA.

[0023] In the illustrated example embodiment, the intermediate layer 10 may transmit signals between semiconductor chips such as the first semiconductor chip 5 and the second semiconductor chip 12, etc. For example, the intermediate layer 10 may transmit a signal sent from the first semiconductor chip 5 to the second semiconductor chip 12, or may transmit a signal sent from the second semiconductor chip 12 to the first semiconductor chip 5, etc.

[0024] Figure 2is a diagram for explaining a semiconductor package according to at least one example embodiment of the inventive concepts.

[0025] Reference Figure 2 The semiconductor package 2 according to at least one example embodiment of the inventive concepts may include a first semiconductor chip 5, an intermediate layer 10, a package substrate 20, a third semiconductor chip 22 and / or a printed circuit board 30, etc., but example embodiments are not limited thereto.

[0026] The intermediate layer 10 may be bonded on the package substrate 20 through one or more first C4 bumps, but example embodiments are not limited thereto.

[0027] The first semiconductor chip 5 may be bonded to the intermediate layer 10 via one or more second uBump bumps, but example embodiments are not limited thereto. In some example embodiments of the present inventive concept, the first semiconductor chip 5 may include an application specific integrated circuit (ASIC), but example embodiments are not limited thereto, and the first semiconductor chip may be other semiconductor devices.

[0028] like Figure 2 As shown in , the size of the first bump C4 Bump is greater than the size of the second bump uBump, but the size is not limited thereto.

[0029] The package substrate 20 may be bonded on the printed circuit board 30 by a ball grid array (BGA), but is not limited thereto. That is, the printed circuit board 30 may be bonded to the lower portion of the package substrate 20 by BGA.

[0030] The third semiconductor chip 22 may be disposed in parallel with the package substrate 20 and may be bonded on the printed circuit board 30 , but example embodiments are not limited thereto. The third semiconductor chip 22 may also be bonded to the printed circuit board 30 using BGA, but example embodiments are not limited thereto.

[0031] According to at least one example embodiment, the intermediate layer 10 may transmit signals between semiconductor devices such as the first semiconductor chip 5 and the third semiconductor chip 22, etc. That is, the intermediate layer 10 may transmit a signal sent from the first semiconductor chip 5 to the third semiconductor chip 22 and / or may transmit a signal sent from the third semiconductor chip 22 to the first semiconductor chip 5, etc.

[0032] Figure 3 is a diagram for explaining an intermediate layer according to at least one example embodiment of the inventive concepts.

[0033] Reference Figure 3 , the intermediate layer 10 according to at least one example embodiment of the inventive concepts may include a first passivation layer 100 , a substrate layer 110 , a BEOL layer 120 , and / or a third passivation layer 130 , etc., but is not limited thereto.

[0034] The first passivation layer 100 may include at least one lower pad, such as a first lower pad 104a and / or a second lower pad 104b, etc., but is not limited thereto. The first lower pad 104a and the second lower pad 104b may be electrically connected to one or more first bumps C4Bump, etc. Therefore, the intermediate layer 10 is bonded to the package substrate 20 through one or more first bumps (e.g., C4 Bump), and the one or more first bumps (e.g., C4 bump) are electrically connected to the first lower pad 104a and the second lower pad 104b, and the intermediate layer 10 may send and / or receive signals, for example, simultaneously send and / or receive signals to / from the second semiconductor chip 12 through the lower pads, the first bumps, and the package substrate 20, etc.

[0035] At the same time, the first passivation layer 100 may also include at least one back metal layer connected to the at least one lower pad, such as a first back metal 102a and / or a second back metal 102b, but is not limited thereto. The first back metal 102a and the second back metal 102b may be electrically connected to the first lower pad 104a and the second lower pad 104b, respectively.

[0036] In addition, the first passivation layer 100 may also include other elements, such as a third back metal 102c between the first back metal 102a and the second back metal 102b. Different from the first back metal 102a and the second back metal 102b that are electrically connected to the first bump C4Bump, the third back metal 102c is not electrically connected to the first bump C4Bump, but can be "floating".

[0037] According to at least one example embodiment, although the first passivation layer 100 is illustrated as including two lower pads and three back metals, those of ordinary skill in the art will appreciate that the number of lower pads and back metals may vary.

[0038] The substrate layer 110 is formed on the first passivation layer 100. The substrate layer 110 may include a second passivation layer 112 and / or a silicon layer 114, etc., but example embodiments are not limited thereto, and other constituent elements may be included in the substrate layer 110. In addition, the substrate layer 110 may be formed on the first passivation layer 100. The silicon layer 114 may include Si.

[0039] The BEOL layer 120 is formed on the substrate layer 110. The BEOL layer 120 may include a plurality of metal layers 121 to 129, but is not limited thereto. For example, the plurality of metal layers (e.g., metal layers 121 to 129) may include a first metal layer 121, a first via layer 122 formed on the first metal layer 121, a second metal layer 123 formed on the first via layer 122, a second via layer 124 formed on the second metal layer 123, a third metal layer 125 formed on the second via layer 124, a third via layer 126 formed on the third metal layer 125, a fourth metal layer 127 formed on the third via layer 126, a fourth via layer 128 formed on the fourth metal layer 127, and an LR layer 129 formed on the fourth via layer 128, etc.

[0040] According to at least one example embodiment, the one or more metal layers may include one or more corresponding metals and / or one or more vias, for example, the first metal layer 121, the second metal layer 123, the third metal layer 125, and the fourth metal layer 127 may include the first metal Mi1, the second metal Mil2, the third metal Mil3, and the fourth metal Mi4, respectively, and the first via layer 122, the second via layer 124, and the third via layer 126 may include the first via Via1, the second via Via2, and the third via Via3, respectively. According to other example embodiments, for example, if necessary, the fourth via layer 128 may also include a fourth via (not shown), etc. In addition, the LR layer 129 may include a first LR and a second LR, but is not limited thereto.

[0041] In some example embodiments of the present inventive concept, the first to fourth metals Mil to Mi4 may include, for example, Cu, etc., but the scope of the example embodiments is not limited thereto. Meanwhile, in some example embodiments of the present inventive concept, the first LR and the second LR may include Al, etc., but the example embodiments are not limited thereto.

[0042] The third passivation layer 130 is formed on the BEOL layer 120. The third passivation layer 130 may include at least one upper pad, such as a first upper pad 132a and a second upper pad 132b, etc. The first upper pad 132a and the second upper pad 132b may be electrically connected to one or more second bumps uBump, etc. Therefore, the intermediate layer 10 is bonded to the first semiconductor chip 5 through one or more second bumps uBump electrically connected to the first upper pad 132a and the second upper pad 132b, and signals may be simultaneously transmitted or received between the semiconductor chips.

[0043] In at least one example embodiment, the substrate layer 110 may include at least one signal TSV for transmitting a signal between the BEOL layer and the one or more first bumps, such as the first signal TSV 116 a and / or the second signal TSV 116 b , etc., but example embodiments are not limited thereto.

[0044] For example, the first signal TSV 116a may transmit a first signal between the BEOL layer 120 and the first lower pad 104a through the first back metal 102a. That is, the first signal TSV 116a may transmit a first signal from the BEOL layer 120 to the first lower pad 104a and / or may transmit a first signal received through the first lower pad 104 to the BEOL layer 120, etc.

[0045] The second signal TSV 116b may transmit the second signal between the BEOL layer 120 and the second lower pad 104b through the second back metal 102b. That is, the second signal TSV 116b may transmit the second signal from the BEOL layer 120 to the second lower pad 104b and / or may transmit the second signal received through the second lower pad 104b to the BEOL layer 120, etc. However, example embodiments are not limited thereto, for example, there may be less than or more than two signal TSVs / lower pads / back metals, etc.

[0046] Here, the first signal TSV 116a may correspond to an aggressor signal TSV causing crosstalk noise, and the second signal TSV 116b may correspond to a victim signal TSV affected by the crosstalk noise caused by the first signal TSV 116a. That is, the crosstalk noise occurs due to undesired interactions between TSVs formed in the substrate layer 110, which may reduce signal reliability, increase bit error rate, and / or cause other undesired performance issues of the intermediate layer and the connected semiconductor device, etc.

[0047] To reduce such crosstalk noise, the substrate layer 110 may further include at least one ground TSV, such as ground TSV 118a. The ground TSV 118a does not carry a signal (e.g., the ground TSV is not configured to transmit / receive a signal), but reduces the crosstalk noise between the first signal TSV 116a and the second signal TSV 116b.

[0048] According to at least one example embodiment, the ground TSV 118a is disposed between the first signal TSV 116a and the second signal TSV 116b and is formed such that one end thereof is connected to the BEOL layer 120 and the other end is floating (eg, the ground TSV is electrically disconnected, etc.).

[0049] Since the ground TSV 118a does not carry a signal, the first bump C4 Bump is not formed at the lower portion thereof. In other words, since the ground TSV 118a does not need to have a function of carrying a signal, it is not necessary and / or necessary to allocate the first bump C4 Bump to the ground TSV 118a. By forming the ground TSV 118a on the substrate layer 110 without allocating and / or connecting to the first bump C4 Bump, the ground TSV 118a can have various arrangements with relatively different numbers between the first signal TSV 116a and the second signal TSV 116b, as described below with reference to Figures 4 to 8 described.

[0050] In at least one example embodiment, one end of the grounded TSV 118a is electrically connected to the first metal Mi1 included in the plurality of metal layers 121 to 129 of the BEOL layer 120. Meanwhile, the first passivation layer 110 may further include a third back metal 102c below the grounded TSV 118a (e.g., the third back metal 102c is formed such that it is physically connected to one end of the grounded TSV 118a). The other end of the grounded TSV 118a may be electrically connected to the third back metal 102c.

[0051] In at least one example embodiment, Figure 3 The floating region F1 indicated by the dotted line in FIG. 1 includes the other end of the ground TSV 118a. That is, the floating region F1 indicates that the ground TSV 118a is floating. In other words, the ground TSV 118a can be electrically disconnected (e.g., open circuit). In addition, in other words, the ground TSV 118a is not connected to the first bump C4 Bump and / or the package substrate (e.g., the package substrate 20).

[0052] In other words, the ground TSV 118 a may be formed to extend from the BEOL layer 120 to the upper surface of the third back metal 102 c , but is not limited thereto.

[0053] The ground TSV 118 a formed in this way may mitigate and / or reduce crosstalk noise between the first signal TSV 116 a and the second signal TSV 116 b .

[0054] Subsequently, a horizontal cross section of the substrate layer 110 along line AA′ will be described.

[0055] Figures 4 to 8 is a diagram for explaining a horizontal cross-section of an intermediate layer according to some example embodiments of the inventive concept.

[0056] Reference Figure 4In at least one example embodiment, a total of sixteen TSVs and a single ground TSV 118a formed in region R1 are shown, but example embodiments are not limited to sixteen TSVs and one ground TSV, and may include a greater or lesser number of TSVs and / or ground TSVs. Sequentially from the upper left, two TSVs are formed on a first bump C4 Bump (e.g., a first C4 bump), the two TSVs forming a ground signal, and then two TSVs are formed on another first bump C4 Bump (e.g., a second C4 bump), the two TSVs forming another ground signal. These four TSVs form a ground pair.

[0057] Next, in the upper right, two TSVs are formed on a first bump C4 Bump, the two TSVs forming a first signal (e.g., the two TSVs forming the first signal are connected to the first C4 bump), and then two TSVs are formed on another first bump C4 Bump, the two TSVs forming a second signal (e.g., the two TSVs forming the second signal are connected to the second C4 bump). These four TSVs form a first signal pair. According to at least one example embodiment, one of the two TSVs forming the first signal may correspond to Figure 3 The second signal TSV 116b.

[0058] Next, at the lower left, two TSVs are formed on one first bump C4 Bump, the two TSVs forming the third signal (e.g., the two TSVs forming the third signal are connected to the third C4 bump), and then two TSVs are formed on another first bump C4 Bump, the two TSVs forming the fourth signal (e.g., the two TSVs forming the fourth signal are connected to the fourth C4 bump). These four TSVs form a second signal pair. According to at least one example embodiment, one of the two TSVs forming the fourth signal may correspond to Figure 3 The first signal TSV 116a.

[0059] Next, in the case of the lower right side, since the description content is the same as that of the case of the upper left side, it will not be repeated.

[0060] According to at least one example embodiment, in a horizontal cross section of the substrate layer 110, one ground TSV 118a may be disposed in a region R1 between the first signal TSV 116a and the second signal TSV 116b, but is not limited thereto. This makes it possible to mitigate crosstalk noise that may occur between the first signal TSV 116a and the second signal TSV 116b.

[0061] Then, refer to Figure 5In at least one example embodiment, a total of sixteen TSVs and two ground TSVs 118a formed in region R2 are shown, and since the description thereof is similar to that of Figure 4 The instructions are the same as those for , so they will not be repeated here.

[0062] According to at least one example embodiment, in the horizontal cross section of the substrate layer 110, two ground TSVs 118a may be disposed in the region R2 between the first signal TSV 116a and the second signal TSV 116b. Specifically, the two ground TSVs 118a may be disposed to be arranged in the horizontal direction. This makes it possible to more effectively mitigate the crosstalk noise that may occur between the first signal TSV 116a and the second signal TSV 116b.

[0063] Then, refer to Figure 6 In at least one example embodiment, a total of sixteen TSVs and four ground TSVs 118a formed in region R3 are shown, and since the description thereof is similar to that of Figure 4 The instructions are the same as those for , so they will not be repeated here.

[0064] According to at least one example embodiment, in a horizontal cross section of the substrate layer 110, four ground TSVs 118a may be disposed in a region R3 between the first signal TSV 116a and the second signal TSV 116b. Specifically, the four ground TSVs 118a may be disposed to be arranged in a horizontal direction. Of course, the scope of the example embodiments of the inventive concept is not limited thereto, and for example, the region R3 may include four or more ground TSVs 118a. This makes it possible to more effectively mitigate crosstalk noise that may occur between the first signal TSV 116a and the second signal TSV 116b.

[0065] Then, refer to Figure 7 In at least one example embodiment, a total of sixteen TSVs and two ground TSVs 118a formed in region R4 are shown, and since the description thereof is similar to that of Figure 4 The instructions are the same as those for , so they will not be repeated here.

[0066] According to at least one example embodiment, in the horizontal cross section of the substrate layer 110, two ground TSVs 118a may be disposed in the region R4 between the first signal TSV 116a and the second signal TSV 116b, but are not limited thereto. Specifically, the two ground TSVs 118a may be disposed to be arranged in a vertical direction. This makes it possible to more effectively mitigate the crosstalk noise that may occur between the first signal TSV 116a and the second signal TSV 116b.

[0067] Then, refer to Figure 8In at least one example embodiment, a total of sixteen TSVs and two ground TSVs 118a formed in region R5 are shown, and since the description thereof is similar to that of Figure 4 The instructions are the same as those for , so they will not be repeated here.

[0068] According to at least one example embodiment, in a horizontal cross section of the substrate layer 110, two ground TSVs 118a may be disposed in a region R5 between the first signal TSV 116a and the second signal TSV 116b. Specifically, the two ground TSVs 118a may be disposed to be arranged in an inclined direction. This makes it possible to more effectively mitigate crosstalk noise that may occur between the first signal TSV 116a and the second signal TSV 116b.

[0069] In the following, the following will describe Figure 3 Various modification examples of the grounded TSV depicted in .

[0070] Figures 9 to 12 is a diagram of intermediate layers for describing various example embodiments according to the inventive concept.

[0071] Reference Fig. 9 According to another exemplary embodiment of the inventive concept, the intermediate layer 10 may include a first passivation layer 100, a substrate layer 110, a BEOL layer 120, and a third passivation layer 130, etc., but is not limited thereto. Figure 3 The description of is the same as that of , so it will not be repeated, and the grounding TSV will be described instead.

[0072] In at least one example embodiment, although the configuration in which the ground TSV 118b is disposed between the first signal TSV 116a and the second signal TSV 116b and the ground TSV 118b is formed such that one end thereof is connected to the BEOL layer 120 and the other end of the ground TSV 118b is floated is similar to the configuration according to Figure 3 The ground TSV 118a is the same as at least one example embodiment of the present invention, but the present example embodiment is different in that the other end (eg, the second end) of the ground TSV 118b is not electrically connected to the third back metal 102c.

[0073] That is, a first end of the ground TSV 118b is electrically connected to the first metal Mi1 included in the plurality of metal layers 121 to 129 of the BEOL layer 120, but a second end of the TSV 118b is not electrically connected to the third back metal 102c.

[0074] In this example embodiment, Fig. 9The floating region F2 indicated by the dotted line in FIG. 1 includes the other end (e.g., the second end) of the ground TSV 1 18b. That is, the floating region F2 indicates that the ground TSV 1 18b is floating, in other words, the ground TSV 1 18b may be electrically disconnected. In addition, in other words, the ground TSV 1 18b is not connected to the C4 Bump, such as the first bump C4 Bump, etc.

[0075] In other words, the grounding TSV 118b may be formed to extend from the BEOL layer 120 to the second passivation layer 112. In addition, the grounding TSV 118b may have Figures 4 to 8 The arrangement in the horizontal cross section of FIG. 1 is shown, but is not limited to this.

[0076] The ground TSV 118 b formed in this way can mitigate crosstalk noise between the first signal TSV 116 a and the second signal TSV 116 b .

[0077] Reference Fig.10 , the intermediate layer 10 according to another exemplary embodiment of the inventive concept may include a first passivation layer 100, a substrate layer 110, a BEOL layer 120, and a third passivation layer 130, etc., but is not limited thereto. Figure 3 The description of is the same as that of , so it will not be repeated, and the grounding TSV will be described instead.

[0078] In at least one example embodiment, the configuration in which the ground TSV 118c is disposed between the first signal TSV 116a and the second signal TSV 116b and the ground TSV 118c is formed such that one end (e.g., the first end) of the ground TSV 118c is connected to the BEOL layer 120 and the other end (e.g., the second end) of the ground TSV 118c is floated is similar to the configuration in which the ground TSV 118c is disposed between the first signal TSV 116a and the second signal TSV 116b and the ground TSV 118c is formed such that one end (e.g., the first end) of the ground TSV 118c is connected to the BEOL layer 120 and the other end (e.g., the second end) of the ground TSV 118c is floated. Figure 3 The configuration in which the ground TSV 118a of at least one example embodiment of the present invention is the same as that in which the other end (eg, the second end) of the ground TSV 118c is not electrically connected to the third back metal 102c is the same as that in the embodiment according to the present invention. Fig. 9 The ground TSV 118 b of at least one example embodiment of FIG.

[0079] That is, one end of the ground TSV 118 c forms an electrical connection with the first metal Mi1 included in the plurality of metal layers 121 to 129 of the BEOL layer 120 , but the other end of the TSV 118 c does not form an electrical connection with the third back metal 102 c .

[0080] In this example embodiment, Fig.10The floating region F3 indicated by the dotted line in FIG. 1 includes the other end of the ground TSV 118c. That is, the floating region F3 indicates that the ground TSV 118c is floating, in other words, the ground TSV 118c may be electrically disconnected. In addition, in other words, the ground TSV 118c is not connected to the C4 bump, such as the first bump C4 Bump, etc.

[0081] However, in the present example embodiment, the grounding TSV 118c may be formed not to extend from the BEOL layer 120 to the second passivation layer 112 but to extend only to the silicon layer 114. In addition, the grounding TSV 118c may have Figures 4 to 8 The arrangement in the horizontal cross section is shown, but is not limited to this.

[0082] Even if the grounded TSV 118 c only extends to the silicon layer 114 instead of the second passivation layer 112, since the vertical length of the intermediate layer 10 is much larger than the interval (e.g., distance) between the lower surface of the intermediate layer 10 and the package substrate 20, the grounded TSV 118 c formed in this way can also mitigate the crosstalk noise between the first signal TSV 116 a and the second signal TSV 116 b.

[0083] Reference Fig.11 According to another exemplary embodiment of the present inventive concept, the intermediate layer 10 and Fig. 9 At least one example embodiment of the present invention is substantially the same, except that a back metal is not formed in the first passivation layer 110 overlapping a lower portion of the ground TSV 118d, or in other words, the first passivation layer 110 does not include a back metal physically connected to a lower portion of the ground TSV 118d.

[0084] In at least one example embodiment, Fig.11 The floating region F4 indicated by the dotted line in FIG. 1 includes the other end (e.g., the second end) of the ground TSV 118 d. That is, the floating region F4 indicates that the ground TSV 118 d is floating, in other words, the ground TSV 118 d may be electrically disconnected. In addition, in other words, the ground TSV 118 d is not connected to the C4 bump, such as the first bump C4 Bump, etc.

[0085] Reference Fig.12 According to another exemplary embodiment of the present inventive concept, the intermediate layer 10 and Fig.10 At least one example embodiment of Figure 1 In at least one example embodiment of the present invention, a back metal is not formed on the first passivation layer 110 overlapping a lower portion of the ground TSV 118e.

[0086] In at least one example embodiment, Fig.12The floating region F5 indicated by the dotted line in FIG. 1 includes the other end (e.g., the second end) of the ground TSV 118e. That is, the floating region F5 indicates that the ground TSV 118e is floating, in other words, the ground TSV 118e may be electrically disconnected. In addition, in other words, the ground TSV 118e is not connected to the C4 bump, such as the first bump C4 Bump.

[0087] By forming a grounded TSV according to various example embodiments of the present invention between an aggressor signal TSV (e.g., a first signal TSV) causing crosstalk noise and a victim signal TSV (e.g., a second signal TSV) affected by the crosstalk noise, the crosstalk noise can be effectively mitigated and / or reduced with only less cost and a simpler manufacturing process compared to other conventional attempts to reduce the crosstalk noise.

[0088] Those skilled in the art will appreciate that many changes and modifications may be made to the exemplary embodiments without substantially departing from the principles of the inventive concept. Therefore, the exemplary embodiments of the disclosed inventive concept are used in a generic and descriptive sense only and not for the purpose of limitation.

[0089] The exemplary embodiments of the present invention have been described with reference to the accompanying drawings, but it can be understood by those skilled in the art that the present invention can be implemented in other specific forms by those skilled in the art without changing the technical concept or basic features of the present invention. In addition, the above exemplary embodiments are only examples and do not limit the scope of rights of the present invention.

Claims

1. A semiconductor package, comprising: A first passivation layer, comprising a first lower pad and a second lower pad, wherein the first lower pad and the second lower pad are electrically connected to one or more first bumps, and the first passivation layer comprises a first back metal and a second back metal; A substrate layer, comprising a second passivation layer and a silicon layer, wherein the substrate layer is formed on the first passivation layer; A back-end-of-line (BEOL) layer, comprising a plurality of metal layers, wherein the BEOL layer is formed on the substrate layer; as well as a third passivation layer formed on the BEOL layer, the third passivation layer comprising a first upper pad and a second upper pad, the first upper pad and the second upper pad being electrically connected to one or more second bumps, and The substrate layer also includes: a first signal through silicon via TSV configured to transmit a first signal between the BEOL layer and the first lower pad through the first back metal; a second signal TSV configured to transmit a second signal between the BEOL layer and the second lower pad through the second back metal; and A ground TSV is disposed between the first signal TSV and the second signal TSV, the ground TSV including a first end of the ground TSV connected to the BEOL layer and a second end of the ground TSV configured to float.

2. The semiconductor package according to claim 1, wherein The one or more first bumps are not physically connected to the ground TSV.

3. The semiconductor package according to claim 1, wherein: The first passivation layer further includes a third back metal overlapping a lower portion of the grounded TSV; and The third back metal does not form an electrical connection with the one or more first bumps.

4. The semiconductor package according to claim 3, wherein: The second end of the ground TSV is electrically connected to the third back metal.

5. The semiconductor package according to claim 3, wherein: The ground TSV is formed to extend from the BEOL layer to an upper surface of the third back metal.

6. The semiconductor package according to claim 3, wherein: The second end of the ground TSV is not electrically connected to the third back metal.

7. The semiconductor package according to claim 3, wherein: The ground TSV is formed to extend from the BEOL layer to the second passivation layer.

8. The semiconductor package according to claim 3, wherein: The ground TSV is formed to extend from the BEOL layer to the silicon layer.

9. The semiconductor package according to claim 1, wherein: The first passivation layer does not include a back metal overlapping a lower portion of the grounded TSV.

10. The semiconductor package according to claim 1, wherein The plurality of metal layers include a first metal; and The first end of the ground TSV is electrically connected to the first metal.

11. A semiconductor package, comprising: A first passivation layer includes a first lower pad and a second lower pad, wherein the first lower pad and the second lower pad are electrically connected to one or more first bumps; a substrate layer formed on the first passivation layer; as well as A back-end BEOL layer is formed on the substrate layer. The substrate layer comprises: a first signal through silicon via TSV configured to transmit a first signal between the first lower pad and the BEOL layer; a second signal TSV configured to transmit a second signal between the second lower pad and the BEOL layer; and At least one ground TSV is disposed between the first signal through silicon via TSV and the second signal TSV and is not physically connected to the first bump.

12. The semiconductor package according to claim 11, wherein The at least one grounded TSV includes a first end connected to the BEOL layer and a second end configured to float.

13. The semiconductor package according to claim 11, wherein In a horizontal cross section of the substrate layer, the at least one ground TSV is disposed between the first signal TSV and the second signal TSV.

14. The semiconductor package according to claim 11, wherein The at least one grounded TSV includes two grounded TSVs; and In a horizontal cross section of the substrate layer, The two ground TSVs are disposed between the first signal TSV and the second signal TSV; and The two ground TSVs are arranged in a horizontal direction.

15. The semiconductor package according to claim 11, wherein The at least one grounded TSV includes four or more grounded TSVs; and In a horizontal cross section of the substrate layer, The four or more ground TSVs are disposed between the first signal TSV and the second signal TSV; and The four or more grounding TSVs are arranged in a horizontal direction.

16. The semiconductor package according to claim 11, wherein The at least one grounded TSV includes two grounded TSVs; and In a horizontal cross section of the substrate layer, The two ground TSVs are disposed between the first signal TSV and the second signal TSV; and The two grounding TSVs are arranged in a vertical direction.

17. The semiconductor package according to claim 11, wherein The at least one grounded TSV includes two grounded TSVs; and In a horizontal cross section of the substrate layer, The two ground TSVs are disposed between the first signal TSV and the second signal TSV; and The two ground TSVs are arranged in an oblique direction.

18. A semiconductor package, comprising: Package substrate; An intermediate layer bonded to the package substrate through one or more first bumps, the intermediate layer comprising: a first passivation layer, the first passivation layer comprising a first lower pad and a second lower pad, the first lower pad and the second lower pad being electrically connected to the one or more first bumps, the first passivation layer comprising a first back metal and a second back metal; A back-end-of-line (BEOL) layer, comprising a plurality of metal layers, wherein the BEOL layer is formed on the substrate layer; The substrate layer comprises: a second passivation layer and a silicon layer, the substrate layer being formed on the first passivation layer; a first signal through silicon via TSV configured to transmit a first signal between the BEOL layer and the first lower pad through the first back metal; a second signal TSV configured to transmit a second signal between the BEOL layer and the second lower pad through the second back metal; and a ground TSV disposed between the first signal TSV and the second signal TSV, the ground TSV including a first end and a second end, the first end being connected to the BEOL layer, and the second end being configured to float; and a third passivation layer formed on the BEOL layer, the third passivation layer comprising a first upper pad and a second upper pad, the first upper pad and the second upper pad being electrically connected to one or more second bumps; and The first semiconductor chip is bonded on the intermediate layer through the one or more second bumps.

19. The semiconductor package according to claim 18, further comprising: A second semiconductor chip is arranged in parallel with the intermediate layer, and the second semiconductor chip is bonded to the packaging substrate. The intermediate layer is configured to transmit a signal from the first semiconductor chip to the second semiconductor chip, or to transmit a signal from the second semiconductor chip to the first semiconductor chip.

20. The semiconductor package according to claim 18, further comprising: A printed circuit board is bonded to the lower portion of the packaging substrate via a ball grid array (BGA); as well as A third semiconductor chip is arranged in parallel with the package substrate and bonded to the printed circuit board, The intermediate layer is configured to transmit a signal from the first semiconductor chip to the third semiconductor chip, or to transmit a signal from the third semiconductor chip to the first semiconductor chip.

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