Detection and correction circuit and method for OSC process deviation and temperature drift

Abstract

The present invention discloses a detection and correction circuit and method for OSC process deviation and temperature drift, including a monitoring voltage difference generating circuit, a voltage amplification and analog-to-digital conversion circuit and an OSC automatic calibration circuit; the output end of the monitoring voltage difference generating circuit is electrically connected to the input end of the voltage amplification and analog-to-digital conversion circuit, and the output end of the voltage amplification and analog-to-digital conversion circuit is electrically connected to the input end of the OSC automatic calibration circuit. The detection and correction circuit and method for OSC process deviation and temperature drift proposed by the present invention have the following advantages: reducing the difficulty of testing and calibrating the OSC clock circuit; simplifying the complexity of OSC design and calibration, and being able to calibrate the frequency drift of OSC caused by temperature changes in real time; simplifying the design difficulty and reducing the chip area; preventing the phenomenon of feedback calibration not converging and OSC frequency instability; simple calibration method can save the use of registers and OTP, with high calibration accuracy and flexible design.

Description

Technical Field

[0001] The present invention relates to the technical field of OSC frequency calibration, and in particular to a detection and correction circuit and method for OSC process deviation and temperature drift. Background Art

[0002] More and more SOC chips integrate high-frequency OSC circuits to replace external crystal oscillator devices, which can not only reduce the cost of use, but also make it more convenient for users to use and reduce the layout area of ​​PCB.

[0003] Technically, the industry currently mainly adjusts the frequency drift of the chip OSC due to process deviation and temperature drift by configuring registers before the chip leaves the factory or when it is powered on, so that the OSC output frequency reaches the design index. Another calibration method is to measure the OSC output frequency in real time, and in turn control and adjust the OSC oscillation frequency. However, this method requires a standard reference frequency. Therefore, how to use a simple method to calibrate the OSC frequency for practical application has become a hot topic in the industry. Based on this, a detection and correction circuit and method for OSC process deviation and temperature drift are proposed. Summary of the invention

[0004] The purpose of the present invention is to provide a detection and correction circuit and method for OSC process deviation and temperature drift, which reduces the difficulty of OSC chip design and product testing cost, increases the reliability and stability of OSC circuit design, thereby improving the competitiveness of the chip, and solves the problems of complex circuits, high cost and low stability required for OSC frequency calibration proposed in the above background technology.

[0005] To achieve the above-mentioned purpose, the present invention provides the following technical solution: a detection and correction circuit for OSC process deviation and temperature drift, including a monitoring voltage difference generating circuit, a voltage amplification and analog-to-digital conversion circuit and an OSC automatic calibration circuit; the output end of the monitoring voltage difference generating circuit is electrically connected to the input end of the voltage amplification and analog-to-digital conversion circuit, and the output end of the voltage amplification and analog-to-digital conversion circuit is electrically connected to the input end of the OSC automatic calibration circuit.

[0006] Preferably, the monitoring voltage difference generating circuit includes a diode Q1, a diode Q2, a diode Q3, a diode Q4, a transistor Q5, a transistor Q6, an nmos diode Q7, an nmos diode Q8, an operational amplifier U1 and a resistor R1, the base of the diode Q1 is connected to the base of the diode Q2 and then connected to the output end of the operational amplifier U1, the emitters of the diodes Q1, Q2, Q3 and Q4 are all connected to the VDD power supply terminal, the collector of the diode Q1 is connected to the positive electrode of the operational amplifier U1 and to the emitter of the transistor Q5, the base of the transistor Q5 is connected to the base of the transistor Q6, and the collector of the transistor Q5 is connected to the base of the transistor Q6. 6 is connected to ground; the collector of the diode Q2 is connected to the cathode of the transistor Q5 and to the input end of the resistor R1, and the output end of the resistor R1 is connected to the emitter of the transistor Q6; the collector of the diode Q3 is connected to the collector of the nmos diode Q7 and to the VMON-A terminal output, the base of the nmos diode Q7 is connected to the VMON-A terminal output, and the emitter of the nmos diode Q7 is grounded; the collector of the diode Q4 is connected to the collector of the nmos diode Q8 and to the VMON-B terminal output, the base of the nmos diode Q8 is connected to the VMON-B terminal output, and the emitter of the nmos diode Q8 is grounded.

[0007] Preferably, the voltage amplification and analog-to-digital conversion circuit includes a resistor Ri1, a resistor Ri2, an amplifier U2 and an A / D converter, the input end of the resistor Ri1 is connected to the VMON-A terminal, the input end of the resistor Ri2 is connected to the VMON-B terminal, the output end of the resistor Ri1 is connected to the positive input end of the amplifier U2 and to the input end of the resistor Rf1, the output end of the resistor Rf1 is connected to the negative output end of the amplifier U2 and then to the positive input end of the A / D converter; the output end of the resistor Ri2 is connected to the positive input end of the amplifier U2 and to the input end of the resistor Rf2, the output end of the resistor Rf2 is connected to the positive output end of the amplifier U2 and then to the negative input end of the A / D converter.

[0008] Preferably, the OSC automatic calibration circuit includes an Nbit corrector, a switch K1, a diode Q9, a diode Q10, a capacitor C1, an amplifier U3 and an amplifier U4, the input end of the Nbit corrector is connected to the output end of the A / D converter, the output end of the Nbit corrector is connected to the input end of the switch K1, the output end of the switch K1 is connected to the base of the diode Q9, and is connected to the collector of the diode Q10 and to the input end of the capacitor C1, the collector of the diode Q9 is connected to the input end of the amplifier U3, the output end of the amplifier U3 is connected to the input end of the amplifier U4, and the output end of the amplifier U4 is connected to the OUT terminal output; the collector of the diode Q10 is connected to the input end of the amplifier U4, and the emitter of the diode Q10, the emitter of the diode Q9 and the output end of the capacitor C3 are connected and then grounded.

[0009] Preferably, the nmos diode Q7 and the nmos diode Q8 are two nmos diodes with large differences in W and L and similar W / L.

[0010] Preferably, the A / D converter is an integral low-speed converter or a SAR low-speed converter.

[0011] Another technical solution provided by the present invention is a detection and correction method for a detection and correction circuit for OSC process deviation and temperature drift, comprising the following steps:

[0012] S1: Use the monitoring voltage difference generating circuit to generate two equal PTAT currents, collect the changing current caused by temperature drift when the chip is working, and transmit it to two nmos diodes with large differences in W and L but similar W / L, namely nmos diode Q7 and nmos diode Q8. NMOS diode Q7 and nmos diode Q8 are connected to generate different voltage outputs;

[0013] S2: A fully differential operational amplifier is used to amplify the generated detection voltage and transmit it to the A / D converter, which converts it into a digital output;

[0014] S3: According to the real-time detection data of the A / D converter and after initialization compensation, the current of OSC is added or subtracted in real time to adjust its output frequency.

[0015] Compared with the prior art, the beneficial effects of the present invention are as follows: the detection and correction circuit and method for OSC process deviation and temperature drift proposed by the present invention have the following advantages:

[0016] 1. Reduce the difficulty of testing and calibration of OSC clock circuit.

[0017] 2. Simplifies the complexity of OSC design and calibration, making it easy to implement.

[0018] 3. The frequency drift of OSC caused by temperature change can be calibrated in real time.

[0019] 4. Unify the process deviation and temperature drift for detection and calibration, simplify the design difficulty and reduce the chip area.

[0020] 5. The real-time calibration method saves the chip digital circuit overhead and prevents the phenomenon of feedback calibration not converging and OSC frequency instability.

[0021] 6. Simple calibration method can save the use of registers and OTP.

[0022] 7. High calibration accuracy and flexible design. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a system block diagram of the present invention;

[0024] Figure 2 A circuit diagram for monitoring differential pressure of the present invention;

[0025] Figure 3 The voltage amplification and analog-to-digital conversion circuit diagram of the present invention;

[0026] Figure 4 The OSC automatic calibration circuit diagram of the present invention;

[0027] Figure 5 It is a schematic diagram of the output voltage of the monitoring circuit of the present invention.

[0028] In the figure: 1. Monitoring voltage difference generating circuit; 2. Voltage amplification and analog-to-digital conversion circuit; 3. OSC automatic calibration circuit. DETAILED DESCRIPTION

[0029] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0030] See also Figure 1 , a detection and correction circuit for OSC process deviation and temperature drift, including a monitoring voltage difference generating circuit 1, a voltage amplification and analog-to-digital conversion circuit 2 and an OSC automatic calibration circuit 3; the output end of the monitoring voltage difference generating circuit 1 is electrically connected to the input end of the voltage amplification and analog-to-digital conversion circuit 2, and the output end of the voltage amplification and analog-to-digital conversion circuit 2 is electrically connected to the input end of the OSC automatic calibration circuit 3.

[0031] See also Figure 2The monitoring voltage difference generating circuit 1 includes a diode Q1, a diode Q2, a diode Q3, a diode Q4, a transistor Q5, a transistor Q6, an nmos diode Q7, an nmos diode Q8, an operational amplifier U1 and a resistor R1. The nmos diode Q7 and the nmos diode Q8 are two nmos tubes with large differences in W and L and similar W / L. The base of the diode Q1 is connected to the base of the diode Q2 and then connected to the output end of the operational amplifier U1. The emitters of the diodes Q1, Q2, Q3 and Q4 are all connected to the VDD power supply terminal. The collector of the diode Q1 is connected to the positive electrode of the operational amplifier U1 and to the emitter of the transistor Q5. The base of the transistor Q5 is connected to the base of the transistor Q6. The bases are connected, the collector of the transistor Q5 is connected to the collector of the transistor Q6 and then grounded; the collector of the diode Q2 is connected to the negative electrode of the transistor Q5, and to the input end of the resistor R1, and the output end of the resistor R1 is connected to the emitter of the transistor Q6; the collector of the diode Q3 is connected to the collector of the nmos diode Q7, and connected to the VMON-A terminal output, the base of the nmos diode Q7 is connected to the VMON-A terminal output, and the emitter of the nmos diode Q7 is grounded; the collector of the diode Q4 is connected to the collector of the nmos diode Q8, and connected to the VMON-B terminal output, the base of the nmos diode Q8 is connected to the VMON-B terminal output, and the emitter of the nmos diode Q8 is grounded.

[0032] See also Figure 3 The voltage amplification and analog-to-digital conversion circuit 2 includes a resistor Ri1, a resistor Ri2, an amplifier U2 and an A / D converter. The A / D converter adopts an integral low-speed converter and a SAR low-speed converter. The input end of the resistor Ri1 is connected to the VMON-A terminal, the input end of the resistor Ri2 is connected to the VMON-B terminal, the output end of the resistor Ri1 is connected to the positive input end of the amplifier U2 and to the input end of the resistor Rf1, the output end of the resistor Rf1 is connected to the negative output end of the amplifier U2 and then connected to the positive input end of the A / D converter; the output end of the resistor Ri2 is connected to the positive input end of the amplifier U2 and to the input end of the resistor Rf2, the output end of the resistor Rf2 is connected to the positive output end of the amplifier U2 and then connected to the negative input end of the A / D converter.

[0033] See also Figure 4The OSC automatic calibration circuit 3 includes an Nbit corrector, a switch K1, a diode Q9, a diode Q10, a capacitor C1, an amplifier U3 and an amplifier U4. The input end of the Nbit corrector is connected to the output end of the A / D converter, the output end of the Nbit corrector is connected to the input end of the switch K1, the output end of the switch K1 is connected to the base of the diode Q9, and is connected to the collector of the diode Q10 and the input end of the capacitor C1, the collector of the diode Q9 is connected to the input end of the amplifier U3, the output end of the amplifier U3 is connected to the input end of the amplifier U4, and the output end of the amplifier U4 is connected to the OUT terminal output; the collector of the diode Q10 is connected to the input end of the amplifier U4, and the emitter of the diode Q10, the emitter of the diode Q9 and the output end of the capacitor C3 are connected and then grounded.

[0034] Another technical solution provided by the present invention is a detection and correction method for a detection and correction circuit of an OSC process deviation and temperature drift, comprising the following steps:

[0035] Step 1: Use the monitoring voltage difference generating circuit 1 to generate two equal PTAT currents, collect the changing current caused by temperature drift when the chip is working, and transmit it to two nmos diodes with large differences in W and L but similar W / L, namely nmos diode Q7 and nmos diode Q8. NMOS diode Q7 and nmos diode Q8 are connected to generate different voltage outputs;

[0036] Step 2: Use a fully differential op amp to amplify the generated detection voltage and transmit it to the A / D converter, which converts it into a digital output;

[0037] Step 3: According to the real-time detection data of the A / D converter and after initialization compensation, the current of OSC is added or subtracted in real time to adjust its output frequency.

[0038] The detection and correction circuit and method for OSC process deviation and temperature drift have the following working principles:

[0039] like Figure 2 As shown, nmos diode Q7 and nmos diode Q8 are in a connected state. The V caused by the change of the width-to-length ratio of the current PTAT and the nmos diode Q7 and the change of the width-to-length ratio of the current PTAT and the nmos diode Q8 is DS The change is used to detect the process deviation and temperature change, which is converted into the V of nmos diode Q7 and nmos diode Q8. DS difference; voltage output varies with process corner and temperature, see Figure 5 It can be seen that the difference in the above changes can be positive or negative when the temperature changes, such as Figure 3As shown, using a differential operational amplifier to amplify this change can also make the subsequent A / D converter quantization conversion easier; in addition, switch K1, capacitor C1 and amplifiers U3 and U4 can be used to sample and amplify this voltage difference. The purpose of using the A / D converter to convert is to digitize the detected change, and use digital methods to feedback control and adjust the drift change of the OSC output, while controlling the calibration accuracy; as shown Figure 4 As shown, during automatic calibration, the offsets such as the offset caused by the detection amplification and the A / D converter conversion can be obtained by calculation, simulation or testing, and these offsets can be used to compensate these fixed deviations by digital addition and subtraction methods to achieve more accurate real-time calibration; using digital changes to adjust the output frequency of OSC in real time can make the OSC output more stable, and can be accurately calibrated without using a reference clock.

[0040] The detection and correction circuit and method for OSC process deviation and temperature drift proposed by the present invention have the following advantages:

[0041] 1. Reduce the difficulty of testing and calibration of OSC clock circuit.

[0042] 2. Simplifies the complexity of OSC design and calibration, making it easy to implement.

[0043] 3. The frequency drift of OSC caused by temperature change can be calibrated in real time.

[0044] 4. Unify the process deviation and temperature drift for detection and calibration, simplify the design difficulty and reduce the chip area.

[0045] 5. The real-time calibration method saves the chip digital circuit overhead and prevents the phenomenon of feedback calibration not converging and OSC frequency instability.

[0046] 6. Simple calibration method can save the use of registers and OTP.

[0047] 7. High calibration accuracy and flexible design.

[0048] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A detection and correction circuit for OSC process deviation and temperature drift, characterized in that: The invention comprises a monitoring voltage difference generating circuit (1), a voltage amplifying and analog-to-digital conversion circuit (2) and an OSC automatic calibration circuit (3); the output end of the monitoring voltage difference generating circuit (1) is electrically connected to the input end of the voltage amplifying and analog-to-digital conversion circuit (2), and the output end of the voltage amplifying and analog-to-digital conversion circuit (2) is electrically connected to the input end of the OSC automatic calibration circuit (3); The monitoring voltage difference generating circuit (1) comprises a diode Q1, a diode Q2, a diode Q3, a diode Q4, a transistor Q5, a transistor Q6, an nmos diode Q7, an nmos diode Q8, an operational amplifier U1 and a resistor R1, wherein the base of the diode Q1 is connected to the base of the diode Q2 and then connected to the output end of the operational amplifier U1, the emitters of the diodes Q1, Q2, Q3 and Q4 are all connected to the VDD power supply terminal, the collector of the diode Q1 is connected to the positive electrode of the operational amplifier U1 and to the emitter of the transistor Q5, the base of the transistor Q5 is connected to the base of the transistor Q6, the collector of the transistor Q5 is connected to the collector of the transistor Q6 and then grounded; the collector of the diode Q2 is connected to the positive electrode of the operational amplifier U1 and to the emitter of the transistor Q5, the base of the transistor Q5 is connected to the base of the transistor Q6, the collector of the transistor Q5 is connected to the collector of the transistor Q6 and then grounded; the collector of the diode Q2 is connected to the positive electrode of the operational amplifier U1 and to the emitter of the transistor Q5. It is connected to the negative electrode of the transistor Q5 and to the input end of the resistor R1, and the output end of the resistor R1 is connected to the emitter of the transistor Q6; the collector of the diode Q3 is connected to the collector of the nmos diode Q7 and connected to the VMON-A terminal output, the base of the nmos diode Q7 is connected to the VMON-A terminal output, and the emitter of the nmos diode Q7 is grounded; the collector of the diode Q4 is connected to the collector of the nmos diode Q8 and connected to the VMON-B terminal output, the base of the nmos diode Q8 is connected to the VMON-B terminal output, and the emitter of the nmos diode Q8 is grounded, wherein the nmos diode Q7 and the nmos diode Q8 are both nmos tubes with large differences in W and L and similar W / L.

2. The detection and correction circuit for OSC process deviation and temperature drift as claimed in claim 1, characterized in that: The voltage amplification and analog-to-digital conversion circuit (2) comprises a resistor Ri1, a resistor Ri2, an amplifier U2 and an A / D converter, wherein the input end of the resistor Ri1 is connected to the VMON-A terminal, the input end of the resistor Ri2 is connected to the VMON-B terminal, the output end of the resistor Ri1 is connected to the positive input end of the amplifier U2 and to the input end of the resistor Rf1, the output end of the resistor Rf1 is connected to the negative output end of the amplifier U2 and then to the positive input end of the A / D converter; the output end of the resistor Ri2 is connected to the positive input end of the amplifier U2 and to the input end of the resistor Rf2, the output end of the resistor Rf2 is connected to the positive output end of the amplifier U2 and then to the negative input end of the A / D converter.

3. The detection and correction circuit for OSC process deviation and temperature drift according to claim 1, characterized in that: The OSC automatic calibration circuit (3) comprises an Nbit corrector, a switch K1, a diode Q9, a diode Q10, a capacitor C1, an amplifier U3 and an amplifier U4, wherein the input end of the Nbit corrector is connected to the output end of the A / D converter, the output end of the Nbit corrector is connected to the input end of the switch K1, the output end of the switch K1 is connected to the base of the diode Q9, and is connected to the collector of the diode Q10 and the input end of the capacitor C1, the collector of the diode Q9 is connected to the input end of the amplifier U3, the output end of the amplifier U3 is connected to the input end of the amplifier U4, and the output end of the amplifier U4 is connected to the OUT terminal output; the collector of the diode Q10 is connected to the input end of the amplifier U4, and the emitter of the diode Q10, the emitter of the diode Q9 and the output end of the capacitor C3 are connected and then grounded.

4. The detection and correction circuit for OSC process deviation and temperature drift as claimed in claim 2, characterized in that: The A / D converter adopts one of an integral low-speed converter and a SAR low-speed converter.

5. A detection and correction method for a detection and correction circuit for OSC process deviation and temperature drift as claimed in claim 1, characterized in that: The steps include: S1: using the monitoring voltage difference generating circuit (1) to generate two equal PTAT currents, collecting the changing current generated by the temperature drift when the chip is working and transmitting it to two nmos diodes with large differences in W and L but similar W / L, namely nmos diode Q7 and nmos diode Q8, nmos diode Q7 and nmos diode Q8 are connected to generate different voltage outputs; S2: A fully differential operational amplifier is used to amplify the generated detection voltage and transmit it to the A / D converter, which converts it into a digital output; S3: According to the real-time detection data of the A / D converter and after initialization compensation, the current of OSC is controlled in real time to adjust its output frequency; Among them, an A / D converter is used to convert the detected changes into digital form, and a digital method is used to feedback control and adjust the drift changes of the OSC output, so that the calibration accuracy can be controlled; during automatic calibration, calculation, simulation or testing are used to obtain the offset caused by detection amplification and A / D converter conversion, and then digital addition and subtraction methods are used to compensate for these fixed deviations to achieve more accurate real-time calibration.

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