Slew rate adjustment circuit, buffer circuit, and slew rate adjustment method

Abstract

A slew rate adjusting circuit, a buffer circuit, and a slew rate adjusting method are disclosed. The slew rate adjusting circuit includes an adjusting transistor configured to provide an adjusting current into an output port of an operational amplifier, a first transistor connected between a power line of the operational amplifier and the adjusting transistor, and a second transistor connected between the first transistor and an output node of the output port, wherein the adjusting transistor is turned on by the second transistor in response to a difference between an input voltage and an output voltage being equal to or greater than a reference voltage, and the adjusting current is provided to the output port in response to the adjusting transistor being turned on.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0067454, filed on June 7, 2019, with the Korean Intellectual Property Office under 35 USC 119(a), the entire disclosure of which is incorporated herein by reference for all purposes. Technical Field

[0003] The following description relates to a slew rate regulation circuit. The following description also relates to a buffer circuit that includes the slew rate regulation circuit. The following description further relates to a slew rate regulation method. Background Technology

[0004] Buffer circuits can be used to buffer signals. For example, buffer circuits can be used in various fields of output signal processing, such as source drive circuits and gate drive circuits in display devices.

[0005] Meanwhile, in the display field, due to the increase in capacitance and decrease in horizontal frequency caused by the expansion of the circuit, the slew rate of the buffer circuit may become a factor to be considered when forming the buffer circuit. Summary of the Invention

[0006] This summary is provided to introduce some concepts in a simplified form, which are further described in the detailed description below. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to serve as an aid in determining the scope of the claimed subject matter.

[0007] In one general aspect, a slew rate regulation circuit includes: a regulating transistor configured to provide a regulating current to an output port of an operational amplifier; a first transistor connected between the operational amplifier's power line and the regulating transistor; and a second transistor connected between the first transistor and an output node of the output port, wherein the regulating transistor is turned on in response to a difference between an input voltage and an output voltage equal to or greater than a reference voltage, and the regulating current is provided to the output port in response to the turning on of the regulating transistor.

[0008] The regulating current can be supplied from the power line to the output node via the regulating transistor.

[0009] The second transistor can turn on in response to the difference between the input voltage and the output voltage being equal to or greater than the reference voltage, the regulating transistor can turn on in response to the second transistor turning on, and the regulating current can be supplied to the output node via the regulating transistor in response to the regulating transistor turning on.

[0010] The regulation transistor, the first transistor, and the second transistor can be metal oxide semiconductor field effect transistors (MOSFETs), a source terminal of the second transistor can be connected to the output node, a drain terminal of the second transistor can be connected to a gate terminal of the regulation transistor, a source terminal of the regulation transistor can be connected to the power line, and a drain terminal of the regulation transistor can be connected to the output node.

[0011] The regulation transistor and the second transistor can be metal oxide semiconductor field effect transistors (MOSFETs), a source terminal of the second transistor can be connected to the output node, a drain terminal of the second transistor can be connected to a gate terminal of the regulation transistor, a source terminal of the regulation transistor can be connected to the power line, and a drain terminal of the regulation transistor can be connected to the output node.

[0012] The slew rate regulation circuit can further include an enable transistor connected to the regulation transistor, the first transistor, and the second transistor, wherein the enable transistor can be configured to control whether the second transistor is turned on in response to receiving an enable signal.

[0013] A positive regulation current can be provided via the regulation transistor in response to the operational amplifier operating through the up pull current.

[0014] A negative regulation current can be provided via the regulation transistor in response to the operational amplifier operating through the down pull current.

[0015] The slew rate regulation circuit can further include an additional transistor connected to the regulation transistor, the first transistor, and the second transistor, wherein the second transistor can be configured to turn on the additional transistor in response to a difference between the input voltage and the output voltage being equal to or greater than a reference voltage, and an additional current can be provided to the output node in response to the additional transistor being turned on.

[0016] In another general aspect, a buffer circuit includes an operational amplifier configured to output an output voltage via an output node by amplifying an input voltage, a regulation current generation circuit configured to provide a regulation current to an output port of the operational amplifier to regulate a slew rate of the output port, and a control circuit configured to control the regulation current generation circuit to provide the regulation current in response to a difference between the input voltage and the output voltage being equal to or greater than a reference voltage.

[0017] The regulation current generation circuit can further include a regulation transistor connected between a power line of the operational amplifier, the output node, and the control circuit, wherein the regulation current can be provided to the output node via the regulation transistor by turning on the regulation transistor according to a control of the control circuit in response to the difference between the input voltage and the output voltage being equal to or greater than the reference voltage.

[0018] The adjustment current can be provided to the output node from the power line via an adjustment transistor.

[0019] The control circuit can include a first transistor connected to the power line and a second transistor connected between the first transistor and the output node, wherein the adjustment transistor can be turned on by the second transistor in response to the difference between the input voltage and the output voltage being equal to or greater than a reference voltage.

[0020] The adjustment transistor and the second transistor can be metal oxide semiconductor field effect transistors (MOSFETs), wherein a source terminal of the second transistor can be connected to the output node, a drain terminal of the second transistor can be connected to a gate terminal of the adjustment transistor, a source terminal of the adjustment transistor can be connected to the power line, and a drain terminal of the adjustment transistor can be connected to the output node.

[0021] The buffer circuit can further include an enable transistor connected to the adjustment transistor, the first transistor, and the second transistor, wherein the enable transistor can be configured to control whether the second transistor is turned on in response to an enable signal.

[0022] The buffer circuit can further include an additional transistor connected to the adjustment transistor, the first transistor, and the second transistor, wherein the additional transistor can be turned on by the second transistor in response to the difference between the input voltage and the output voltage being equal to or greater than a reference voltage, and can provide an additional current to the output node in response to the additional transistor being turned on.

[0023] In another general aspect, a slew rate adjustment method includes receiving an input voltage input to an operational amplifier, receiving an output voltage output from the operational amplifier, and providing an adjustment current to an output port of the operational amplifier to reduce a transition time of the output voltage based on a difference between the input voltage and the output voltage.

[0024] Providing the adjustment current can include providing the adjustment current in response to the difference between the input voltage and the output voltage being equal to or greater than a reference voltage.

[0025] The slew rate in the case where the difference between the input voltage and the output voltage is equal to or greater than the reference voltage can be greater than the slew rate in the case where the difference between the input voltage and the output voltage is less than the reference voltage.

[0026] A size of the adjustment current can be determined based on the difference between the input voltage and the output voltage.

[0027] In another general aspect, a slew rate adjustment circuit includes an adjustment transistor, a first transistor connected between a power line of an operational amplifier and the adjustment transistor, and a second transistor connected between an output node of the first transistor and an output port of the operational amplifier, wherein the adjustment transistor is turned on by the second transistor in response to a difference between an input voltage and an output voltage being equal to or greater than a reference voltage, and the adjustment transistor provides an adjustment current into the output port in response to being turned on.

[0028] The adjustment current can be provided into the output node from the power line via the adjustment transistor.

[0029] The second transistor can be turned on in response to the difference between the input voltage and the output voltage being equal to or greater than the reference voltage, the adjustment transistor can be turned on in response to the second transistor being turned on, and the adjustment current can be provided to the output node via the adjustment transistor in response to the adjustment transistor being turned on.

[0030] The adjustment transistor, the first transistor, and the second transistor can be metal oxide semiconductor field effect transistors (MOSFETs), a source terminal of the second transistor can be connected to the output node, a drain terminal of the second transistor can be connected to a gate terminal of the adjustment transistor, a source terminal of the adjustment transistor can be connected to the power line, and a drain terminal of the adjustment transistor can be connected to the output node.

[0031] Other features and aspects will become apparent from the following detailed description, drawings and claims. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 is a graph illustrating a buffer circuit according to an example.

[0033] Figure 2 is a graph illustrating an operational amplifier and a slew rate adjustment circuit according to an example.

[0034] Figure 3 is a graph illustrating a buffer circuit according to an example in detail.

[0035] Figure 4 is a graph illustrating a plot of an output voltage according to whether a slew rate adjustment circuit is present according to an example.

[0036] Figure 5 is a graph illustrating a buffer circuit according to an example in detail.

[0037] Figure 6 is a graph illustrating a buffer circuit according to an example in detail.

[0038] Figure 7 is a graph illustrating a flowchart of a slew rate adjustment method according to an example.

[0039] Figure 8 FIG. 1 is a diagram conceptually illustrating a display device including a buffer circuit according to an example.

[0040] Throughout the drawings and the detailed description, identical reference labels can refer to like elements. The drawings can not be to scale and the dimensions, proportions, and other particulars shown in the drawings can have been exaggerated for the purpose of clarity, illustration, and convenience. DETAILED DESCRIPTION

[0041] The following detailed description is presented to aid in understanding the method, apparatus, and / or system described herein. It will be apparent, however, that various changes, modifications, and equivalents can be made to the method, apparatus, and / or system described herein, in light of the disclosure. For example, the order in which steps are presented is merely illustrative and not limiting unless otherwise specified, and the steps can be performed in any order, unless otherwise specified. Additionally, features described herein can be implemented in software, hardware, or a combination thereof, as would be understood by a person of ordinary skill in the art. Furthermore, features described herein can be omitted for increased clarity and conciseness, as would be understood by a person of ordinary skill in the art.

[0042] The features described herein can be embodied in different forms, and should not be construed as limited to the examples described herein. Rather, the examples described herein have been provided merely for the purposes of illustration so as to enable those with ordinary skill in the art to make and use the methods, apparatus, and / or systems described herein. Many modifications and variations will be apparent to those with ordinary skill in the art upon reading this disclosure, and it is intended to cover in the appended claims all such modifications and variations.

[0043] Throughout the specification, where an element, such as a layer, region, or substrate, is described as being "on," "connected to," or "coupled to" another element, it can be directly on, connected, or coupled to the other element, or one or more other elements can be interposed therebetween. In contrast, where an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element, there are no other elements interposed therebetween.

[0044] As used herein, the term "and / or" includes any one of the associated listed items, as well as any combination of any two or more of the associated listed items.

[0045] Although terms such as "first," "second," and "third" can be used herein to describe various components, features, regions, layers and / or sections, these components, features, regions, layers and / or sections should not be limited thereby. Instead, these terms are only used to distinguish one component, feature, region, layer or section from another component, feature, region, layer or section. Thus, terms describing the examples described herein, such as first, second, and third, are also intended to refer to the aforementioned components, features, regions, layers and / or sections.

[0046] To facilitate description, spatially relative terms, such as "above," "on," "below," and "below," can be used herein to describe the relationship between one element and another element as shown in the drawings. Such spatially relative terms are intended to include different orientations of the device in use or operation, in addition to the orientation depicted in the drawings. For example, if the device in the drawings is turned over, an element described as being "above" or "on" another element would be "below" or "below" the other element with respect to the other element. Therefore, the term "above" includes both upward and downward orientations depending on the spatial orientation of the device. The device can also be oriented in other ways (e.g., rotated 90 degrees or at other orientations), and the spatially relative terms used herein should be interpreted accordingly.

[0047] The terminology used herein is for the purpose of describing various examples only and is not intended to be limiting of the present disclosure. The singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises," "comprising," "includes," and "including" specify the presence of stated features, numbers, operations, components, elements, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, operations, components, elements, and / or combinations thereof.

[0048] Changes in shape shown in the drawings can occur due to manufacturing techniques and / or tolerances. Therefore, the examples described herein are not limited to the specific shapes shown in the drawings, but include changes in shape that occur during manufacturing.

[0049] As will be apparent, features of the examples described herein can be combined in various ways. Furthermore, although the examples described herein have a variety of configurations, other configurations are possible as will be apparent to those of ordinary skill in the art in view of the disclosure herein.

[0050] In this document, note that the use of the term "may" with respect to examples or embodiments, for example, what can include or implement examples or embodiments, means that at least one example or embodiment exists, in which the feature is included or implemented, but that not all examples and embodiments necessarily include or implement the feature.

[0051] The present example has been made in consideration of the above-mentioned problems occurring in the related art, and an object of the present example is to provide a slew rate adjustment circuit capable of increasing a slew rate of an output port of an operational amplifier without increasing current consumption in the output port, a buffer circuit including the slew rate adjustment circuit, and a slew rate adjustment method.

[0052] The slew rate adjustment circuit according to the example can increase a slew rate of an operational amplifier by providing an adjustment current to the operational amplifier when a difference between an input voltage and an output voltage exceeds a threshold voltage, thereby providing a fast slew.

[0053] The slew rate adjustment circuit according to the example can increase a slew rate in an output port without causing a change in consumed current in the output port, and thus can prevent a device from being overheated.

[0054] Figure 1 FIG. 1 is a diagram illustrating a buffer circuit according to an example. Referring to FIG. 1, a buffer circuit 100 can receive an input voltage VIN, and can output an output voltage VOUT by using the input voltage VIN. According to an example, the buffer circuit 100 can perform a buffering function on the input voltage VIN, and can output the output voltage VOUT as a result of the buffering function. For example, the output voltage VOUT can be generated by the buffer circuit 100 by amplifying the input voltage VIN. Figure 1

[0055] Meanwhile, in the present disclosure, receiving an arbitrary voltage can mean electrically connecting a line supplying an arbitrary voltage and a corresponding configuration.

[0056] The buffer circuit 100 can include an operational amplifier 110 and a slew rate adjustment circuit 120. According to a non-limiting example, the buffer circuit 100 can include a plurality of operational amplifiers and a plurality of slew rate adjustment circuits, but in other non-limiting examples, a single operational amplifier 110 and a slew rate adjustment circuit 120 can be sufficient.

[0057] ​The operational amplifier 110 can output an output voltage VOUT by amplifying an input voltage VIN. Ideally, the operational amplifier 110 can output the output voltage VOUT by immediately responding to the input of the input voltage VIN. However, in reality, a time, i.e., a slew rate, can pass in a transition from the input voltage VIN to the output voltage VOUT. Such a slew rate can be considered as a slew rate of the operational amplifier 110.

[0058] The slew rate adjustment circuit 120 can adjust the slew rate of the operational amplifier 110. According to an example, the slew rate adjustment circuit 120 can receive the input voltage VIN and the output voltage VOUT from the operational amplifier 110, and can adjust a transition time from the input voltage VIN to the output voltage VOUT based on the received input voltage VIN and the output voltage VOUT. For example, when an absolute value of a difference between the input voltage VIN and the output voltage VOUT of the operational amplifier 110 exceeds a reference value, the slew rate adjustment circuit 120 can be activated, and the slew rate adjustment circuit 120 can accordingly reduce the transition time from the input voltage VIN to the output voltage VOUT.

[0059] Figure 2 FIG. 1 is a diagram illustrating an operational amplifier and a slew rate adjustment circuit according to an example. Referring to FIG. 1, an operational amplifier 110 can include an input port 111, a load 113, and an output port 115. Figure 1 and Figure 2 According to an example of FIG. 1, the operational amplifier 110 can include the input port 111, the load 113, and the output port 115.

[0060] The input port 111 can receive an input voltage VIN and an output voltage VOUT, and can determine a difference between a magnitude of the input voltage VIN and a magnitude of the output voltage VOUT. Further, in an example of FIG. 1, the input port 111 of the operational amplifier 110 can be electrically connected to the load 113. Figure 2

[0061] The load 113 can determine a gain of the operational amplifier 110. According to an example, the load 113 can amplify the input voltage VIN according to the determined gain, and can transmit the resulting input voltage to the output port 115.

[0062] The load 113 can transmit a driving signal DS to control the output port 115. For example, the driving signal DS can be a pull-up current or a pull-down current used in the operational amplifier 110.

[0063] The output port 115 can output an output voltage VOUT in response to the driving signal DS. According to an example, the output port 115 can output the output voltage VOUT as a result of being turned on by the driving signal DS.

[0064] ​The output port 115 can receive the adjustment current ADI from the slew rate adjustment circuit 120, and thus, can adjust the slew rate of the output port 115.

[0065] The output voltage VOUT output from the output port 115 can be provided again to the input port 111.

[0066] According to Figure 2 The slew rate adjustment circuit 120 according to an example can include an adjustment current generation circuit 121 and a control circuit 123.

[0067] In such an example, the adjustment current generation circuit 121 can be connected to the output port 115 of the operational amplifier 110. The adjustment current generation circuit 121 can adjust the slew rate of the output port 115 by providing the adjustment current ADI to the output port 115. According to an example, the adjustment current generation circuit 121 can provide the adjustment current ADI to the output port 115. Thus, the adjustment current generation circuit 121 can adjust the slew rate of the output port 115 by making a transition from the input voltage VIN to the output voltage VOUT faster than a previous slew rate at which the input voltage VIN was transitioned to the output voltage VOUT through the output port 115.

[0068] Meanwhile, without limiting a direction of a current flow of the adjustment current ADI, as long as the adjustment current ADI to the output port 115 can include an example in which a current flows from the output port 115 into the adjustment current generation circuit 121 and an example in which a current flows from the adjustment current generation circuit 121 into the output port 115 through an operation of the adjustment current generation circuit 121.

[0069] The control circuit 123 can output a control signal CS for controlling the adjustment current generation circuit 121. According to an example, the control circuit 123 can output the control signal CS to the adjustment current generation circuit 121 according to a difference between the input voltage VIN and the output voltage VOUT. Further, the adjustment current generation circuit 121 can provide the adjustment current ADI to the output port 115 by being activated or enabled in response to the control signal CS.

[0070] The slew rate adjustment circuit 120 according to an example can adjust the slew rate of the output port 115 according to a difference between the input voltage VIN and the output voltage VOUT.

[0071] Figure 3 is a diagram illustrating a buffer circuit according to an example in detail. Referring to Figure 1 to Figure 3 The output port 115 can receive the supply voltages VDD1 and VDD2 by being connected to the power lines VL1 and VL2 according to an example of

[0072] The output port 115 can include two drive transistors DTR1 and DTR2. According to an example, the output port 115 can include a first drive transistor DTR1 connected between the first power line VL1 and the output node NOUT, and a second drive transistor DTR2 connected to the second power line VL2 and the output node NOUT.

[0073] According to an example, the first drive transistor DTR1 can be a PMOS transistor, and the second drive transistor DTR2 can be an NMOS transistor. In such an example, a gate terminal of the first drive transistor DTR1 can be connected to the load 113, a source terminal of the first drive transistor DTR1 can be connected to the first power line VL1, and a drain terminal of the first drive transistor DTR1 can be connected to the output node NOUT. Additionally, a gate terminal of the second drive transistor DTR2 can be connected to the load 113, a source terminal of the second drive transistor DTR2 can be connected to the second power line VL2, and a drain terminal of the second drive transistor DTR2 can be connected to the output node NOUT.

[0074] The first drive transistor DTR1 can turn on in response to receiving a first drive signal DS1 transmitted from the load 113, and the second drive transistor DTR2 can turn on by receiving a second drive signal DS2 transmitted from the load 113. According to an example, the first drive transistor DTR1 can be a pull-up transistor, and the second drive transistor DTR2 can be a pull-down transistor.

[0075] The first drive transistor DTR1 and the second drive transistor DTR2 can operate in a complementary manner. For example, when the first drive transistor DTR1 turns on, the second drive transistor DTR2 can turn off, and when the first drive transistor DTR1 turns off, the second drive transistor DTR2 can turn on.

[0076] The adjustment current generation circuit 121 can be connected to the output node NOUT. According to an example, the adjustment current generation circuit 121 can include two adjustment transistors MTR1 and MTR2 for providing an adjustment current to the output node NOUT.

[0077] For example, the adjustment current generation circuit 121 can include a first adjustment transistor MTR1 connected between the first power line VL1 and the output node NOUT, and can include a second adjustment transistor MTR2 connected between the second power line VL2 and the output node NOUT.

[0078] According to non-limiting examples, the first adjustment transistor MTR1 can be a PMOS and the second adjustment transistor MTR2 can be an NMOS. In such examples, the gate terminal of the first adjustment transistor MTR1 can be connected to the control circuit 123, the source terminal of the first adjustment transistor MTR1 can be connected to the first power line VL1, and the drain terminal of the first adjustment transistor MTR1 can be connected to the output node NOUT and the load 113. The gate terminal of the second adjustment transistor MTR2 can be connected to the control circuit 123, the source terminal of the second adjustment transistor MTR2 can be connected to the second power line VL2, and the drain terminal of the second adjustment transistor MTR2 can be connected to the output node NOUT and the load 113. For example, the compensation capacitors CP1 and CP2 can be connected between the adjustment transistors MTR1 and MTR2 and the load 113, respectively. In such examples, the first compensation capacitor CP1 can be connected between the first adjustment transistor MTR1 and the load 113, and the second compensation capacitor CP2 can be connected between the second adjustment transistor MTR2 and the load 113. The compensation capacitors CP1 and CP2 can be used for Miller compensation, where Miller compensation is a technique for stabilizing a circuit using a capacitor in a negative feedback fashion.

[0079] The first adjustment transistor MTR1 can be turned on in response to receiving the first control signal CS1 transmitted from the control circuit 123, and the second adjustment transistor MTR2 can be turned on in response to receiving the second control signal CS2 transmitted from the control circuit 123.

[0080] The control circuit 123 can output the control signals CS1 and CS2 for activating the adjustment current generation circuit 121. According to an example, the control circuit 123 can include a first transistor TR1, a second transistor TR2, a third transistor TR3, and a fourth transistor TR4.

[0081] The first transistor TR1 can be connected to the first power line VL1, and the second transistor TR2 can be connected between the first transistor TR1 and the output node NOUT. According to an example, the first adjustment transistor MTR1 can be connected between the first transistor TR1 and the second transistor TR2.

[0082] According to non-limiting examples, the first transistor TR1 can be a PMOS transistor and the second transistor TR2 can be an NMOS transistor. In such examples, the gate terminal of the first transistor TR1 can be connected to the load 113, the source terminal of the first transistor TR1 can be connected to the first power line VL1, and the drain terminal of the first transistor TR1 can be connected to the drain terminal of the second transistor TR2 and to the gate terminal of the first regulation transistor MTR1. Moreover, in such examples, the gate terminal of the second transistor TR2 can receive the input voltage VIN, the drain terminal of the second transistor TR2 can be connected to the drain terminal of the first transistor TR1 and to the gate terminal of the first regulation transistor MTR1, and the source terminal of the second transistor TR2 can be connected to the output node NOUT.

[0083] The second transistor TR2 can be conductive when the absolute value of the difference between the input voltage VIN and the output voltage VOUT is equal to or greater than the absolute value of the threshold voltage of the second transistor TR2. For example, when the second transistor TR2 is an NMOS, the second transistor TR2 can be conductive when the difference between the input voltage VIN and the output voltage VOUT is equal to or greater than the threshold voltage of the second transistor TR2.

[0084] At the same time, the operating conditions of NMOS and PMOS can be substantially the same, except for the mere sign difference. Therefore, the "difference between the input voltage VIN and the output voltage VOUT" can correspond to the absolute value. Considering that the amplitude of the relevant calculation is obtained using the absolute value operation (as the sign is not important for these considerations), therefore, in the following, for ease of description, it can be assumed, in examples, that the difference between the input voltage VIN and the output voltage VOUT being equal to or greater than the threshold voltage means that the absolute value of the difference between the input voltage VIN and the output voltage VOUT is equal to or greater than the absolute value of the threshold voltage.

[0085] According to non-limiting examples, the third transistor TR3 can be an NMOS transistor and the fourth transistor TR4 can be a PMOS transistor. In such examples, the gate terminal of the third transistor TR3 can be connected to the load 113, the source terminal of the third transistor TR3 can be connected to the second power line VL2, and the drain terminal of the third transistor TR3 can be connected to the drain terminal of the fourth transistor TR4 and to the gate terminal of the second regulation transistor MTR2. Moreover, in such examples, the gate terminal of the fourth transistor TR4 can receive the input voltage VIN, the drain terminal of the fourth transistor TR4 can be connected to the drain terminal of the third transistor TR3 and to the gate terminal of the second regulation transistor MTR2, and the source terminal of the fourth transistor TR4 can be connected to the output node NOUT.

[0086] In an example, the fourth transistor TR4 can turn on when a difference between the input voltage VIN and the output voltage VOUT is equal to or greater than a threshold voltage of the fourth transistor TR4.

[0087] Hereinafter, the operation of the slew rate adjustment circuit 120 is described in more detail with reference to an example of Figure 3 As described in more detail above, a time, i.e., a transition time, can pass during a transition from the input voltage VIN to the output voltage VOUT, and the slew rate adjustment circuit 120 of the example is able to increase the slew rate without causing an increase in current consumption. According to the example, the threshold voltage of all transistors shown in the example of Figure 3

[0088] The operation of the slew rate adjustment circuit 120 when the first drive transistor DTR1 is turned on will be described in more detail. In a pull-up operation, when the input voltage VIN is input, the first drive transistor DTR1 can be turned on by controlling the load 113, and the output voltage VOUT can be output.

[0089] In such an example, it can be assumed that a difference between the input voltage VIN and the output voltage VOUT can exceed the threshold voltage. For example, the input voltage VIN can match the first supply voltage VDD1. Accordingly, in such an example, the second transistor TR2 can turn on. Accordingly, the first adjustment transistor MTR1 can be turned on by receiving a voltage from the node X1. In other words, the second transistor TR2 can output the first control signal CS1 for turning on the first adjustment transistor MTR1. When the first adjustment transistor MTR1 is turned on, a first adjustment current ADI1 can be transmitted into the output node NOUT through the first adjustment transistor MTR1 based on the first supply voltage. Accordingly, a transition time to the output voltage VOUT into the output node NOUT can be reduced, and as a result, the slew rate of the output port 115 can be increased.

[0090] For example, the first adjustment current ADI1 can be provided into the output node NOUT from the first power line VL1 through the first adjustment transistor MTR1.

[0091] In other words, the slew rate adjustment circuit 120 can increase the slew rate of the output port 115 when a difference between the input voltage VIN and the output voltage VOUT exceeds the threshold voltage.

[0092] ​Subsequently, when the difference between the input voltage VIN and the output voltage VOUT does not exceed the threshold voltage, the second transistor TR2 can turn off, and the first regulation transistor MTR1 can turn off by receiving a voltage from the node X1. In other words, the second transistor TR2 can output the first control signal CS1 for turning off the first regulation transistor MTR1. The output voltage VOUT can be output by turning off the first regulation transistor MTR1 and by turning on only the first drive transistor DTR1.

[0093] In other words, when the difference between the input voltage VIN and the output voltage VOUT does not exceed the threshold voltage, the slew rate regulation circuit 120 can be disabled.

[0094] The operation of the slew rate regulation circuit 120 when the second drive transistor DTR2 is turned on is similar to the operation discussed in more detail above. In the pull-down operation, when the input voltage VIN is input, the second drive transistor DTR2 can be turned on by the control of the load 113, and the output voltage VOUT can be output.

[0095] In such an example, it can be assumed that the difference between the input voltage VIN and the output voltage VOUT exceeds the threshold voltage. For example, the input voltage VIN can be the second supply voltage VDD2. In such an example, the fourth transistor TR4 can be turned on, and the second regulation transistor MTR2 can be turned on by receiving a voltage from the node X2. In other words, the fourth transistor TR4 can output the second control signal CS2 for turning on the second regulation transistor MTR2. Accordingly, the second regulation transistor MTR2 can be turned on, and thus the second regulation current ADI2 can be transmitted into the output node NOUT by the second regulation transistor MTR2 based on the second supply voltage VDD2. Accordingly, the transition time to the output voltage VOUT into the output node NOUT can be reduced, and thus as a result, the slew rate of the output port 115 can be increased.

[0096] For example, the second regulation current ADI2 can be provided into the output node NOUT from the second power line VL2 by the second regulation transistor MTR2.

[0097] Subsequently, when the difference between the input voltage VIN and the output voltage VOUT does not exceed the threshold voltage, the fourth transistor TR4 can turn off, and the second regulation transistor MTR2 can turn off by receiving a voltage from the node X2. In other words, the fourth transistor TR4 can output the second control signal CS2 for turning off the second regulation transistor MTR2. The output voltage VOUT can be output by turning off the second regulation transistor MTR2 and by turning on only the second drive transistor DTR2.

[0098] Accordingly, the slew rate adjustment circuit 120 according to the example can increase the slew rate of the output port 115 by providing the adjustment current ADI into the output port 115. In particular, the adjustment current ADI provided from the slew rate adjustment circuit 120 can not flow into the drive transistors DTR1 and DTR2 and, thus, no change in the current consumption in the drive transistors can occur.

[0099] In other words, the slew rate adjustment circuit 120 according to the example can increase the slew rate of the output port 115 without causing an increase in the current consumption of the output port 115. In other words, the device can be prevented from overheating, which would otherwise result from the increased slew rate, which would lead to a high current consumption, which would generate a large amount of heat.

[0100] In addition, based on the example, the slew rate adjustment circuit 120 can determine the current level of the adjustment current ADI based on the difference between the input voltage VIN and the output voltage VOUT, i.e., the characteristics of the transistors, and an increase in the slew rate can be achieved as a result of the characteristics by example when the difference between the input voltage VIN and the output voltage VOUT becomes large, and thus, the slew rate can be increased.

[0101] Figure 4 is a graph showing a plot of the output voltage according to whether a slew rate adjustment circuit is present according to the example. Reference is made to Figure 1 to Figure 4 According to the example of Figure 4 The explanatory information presented in the plot of Figure 4 can confirm that the slew rate of the output port when the slew rate adjustment circuit 120 according to the example is present 1 can be greater than the slew rate of the output port when the slew rate adjustment circuit 120 is not provided 2. In particular, as described in more detail above, when the difference between the input voltage VIN and the output voltage VOUT exceeds the threshold voltage, which is shown in as the fast slew portion, the slew rate adjustment circuit 120 can increase the slew rate of the output port 115 by providing the adjustment current ADI into the output port 115.

[0102] Figure 5 is a graph showing a buffer circuit according to the example in detail. Reference is made to Figure 1 to Figure 5 According to the example of Figure 5 The control circuit 123 of the example of Figure 3 may be the same as the control circuit 123 of the example of Figure 5 The difference of the control circuit 123 of the example of

[0103] A first enable transistor ETR1 can be connected between the first transistor TR1 and the second transistor TR2, and a second enable transistor ETR2 can be connected between the third transistor TR3 and the fourth transistor TR4. According to a non-limiting example, the first enable transistor ETR1 can be a PMOS transistor, and the second enable transistor ETR2 can be an NMOS transistor.

[0104] For example, the first enable transistor ETR1 can be turned on in response to receiving a first enable signal EN1. A source terminal of the first enable transistor ETR1 can be connected between a drain terminal of the first transistor TR1 and a gate terminal of the first regulation transistor MTR1. A drain terminal of the first enable transistor ETR1 can be connected to a drain terminal of the second transistor TR2. The second enable transistor ETR2 can be turned on in response to receiving a second enable signal EN2. A source terminal of the second enable transistor ETR2 can be connected between a drain terminal of the third transistor TR3 and a gate terminal of the second regulation transistor MTR2. A drain terminal of the second enable transistor ETR2 can be connected to a drain terminal of the fourth transistor TR4.

[0105] According to a non-limiting example, the first enable signal EN1 provided to the first enable transistor ETR1 can be the second power supply voltage VDD2 or a ground voltage, and the second enable signal EN2 provided to the second enable transistor ETR2 can be the first power supply voltage VDD1, but EN1 and EN2 are not limited to such examples, and in other examples, other voltages can be used for EN1 and / or EN2.

[0106] Whether to output the control signals CS1 and CS2 can be set by manipulating the enable transistors ETR1 and ETR2. According to an example, whether to turn on the second transistor TR2 can be determined based on whether the first enable transistor ETR1 is turned on. Thus, whether to output the first control signal CS1 can also be determined based on such a method. In addition, whether to turn on the fourth transistor TR4 can be determined based on whether the second enable transistor ETR2 is turned on. Thus, whether to output the second control signal CS2 can also be determined based on such a method.

[0107] In other words, Figure 5 The enable transistors ETR1 and ETR2 of the example of FIG. 1 can be transistors for setting whether to enable the slew rate regulation circuit 120. When the enable transistors ETR1 and ETR2 are turned off, the slew rate regulation circuit 120 can also be correspondingly disabled, and when the enable transistors ETR1 and ETR2 are turned on, the slew rate regulation circuit 120 can also be correspondingly activated.

[0108] The operations of the slew rate adjustment circuit 120 when the enable transistors ETR1 and ETR2 are turned on or turned off are the same as those of the slew rate adjustment circuit 120 described above with reference to the examples, and thus the description of such operations is omitted for the sake of brevity. Figure 3

[0109] Figure 6 is a diagram that illustrates a buffer circuit according to an example in detail. With reference to the example of Figure 1 to Figure 6 , the control circuit 123 of the example of Figure 6 may be the same as the control circuit 123 of the example of Figure 3 , except that it further includes a first additional transistor ATR1 and a second additional transistor ATR2.

[0110] The first additional transistor ATR1 can be connected to the first transistor TR1, the first adjustment transistor MTR1, the load 113, and the second transistor TR2. The second additional transistor ATR2 can be connected to the third transistor TR3, the second adjustment transistor MTR2, the load 113, and the fourth transistor TR4. According to an example, the first additional transistor ATR1 can be a PMOS transistor, and the second additional transistor ATR2 can be an NMOS transistor.

[0111] For example, a gate terminal of the first additional transistor ATR1 can be connected between the first transistor TR1 and the second transistor TR2, a source terminal of the first additional transistor ATR1 can be connected to the load 113 and the first compensation capacitor CP1, and a drain terminal of the first additional transistor ATR1 can be connected to a source terminal of the second transistor TR2. A gate terminal of the second additional transistor ATR2 can be connected between the third transistor TR3 and the fourth transistor TR4, a source terminal of the second additional transistor ATR2 can be connected between the load 113 and the second compensation capacitor CP2, and a drain terminal of the second additional transistor ATR2 can be connected to a source terminal of the fourth transistor TR4.

[0112] The operations of the slew rate adjustment circuit 120 when the first drive transistor DTR1 is turned on are described in more detail below. In a pull-up operation, when the input voltage VIN is input, the first drive transistor DTR1 can be turned on based on the control of the load 113, and the first drive transistor DTR1 can output the output voltage VOUT.

[0113] ​In such an example, it can be assumed that the difference between the input voltage VIN and the output voltage VOUT exceeds the threshold voltage. For example, the input voltage VIN can be the first supply voltage VDD1. In such an example, the second transistor TR2 can be turned on. Accordingly, both the first regulation transistor MTR1 and the first additional transistor ATR1 can be turned on by receiving the voltage from the node XI. When both the first regulation transistor MTR1 and the first additional transistor ATR1 are turned on, the first regulation current ADI1 can be transmitted into the output node NOUT through the first regulation transistor MTR1 based on the first supply voltage VDD1. In addition, unlike the example of Figure 3 the first additional current can also be transmitted into the output node NOUT through the first additional transistor ATR1. Accordingly, the transition time to the output voltage VOUT in the output node NOUT can be reduced, and thus the slew rate of the output port 115 can be correspondingly increased.

[0114] For example, the first additional current can be provided into the output node NOUT from the load 113 through the first additional transistor ATR1.

[0115] Assuming that the rest of the configuration of the circuit except for including the first additional transistor ATR1 is the same, the increase in the slew rate produced by the slew rate regulation circuit 120 of the example of Figure 6 may be greater than the increase in the slew rate produced by using the slew rate regulation circuit 120 of the example of Figure 3 .

[0116] Subsequently, when the difference between the input voltage VIN and the output voltage VOUT does not exceed the threshold voltage, the second transistor TR2 can be turned off, and the first regulation transistor MTR1 and the first additional transistor ATR1 can also be turned off by the voltage of the node XI. The output voltage VOUT is output by turning on only the first drive transistor DTR1.

[0117] The operation of the slew rate regulation circuit 120 when the second drive transistor DTR2 is turned on is similar to those discussed above. In a pull-down operation, when the input voltage VIN is input, the second drive transistor DTR2 can be turned on by the control of the load 113, and the output voltage VOUT can be accordingly output.

[0118] In the present disclosure, it is assumed that the difference between the input voltage VIN and the output voltage VOUT can exceed a threshold voltage. For example, the input voltage VIN can be the second supply voltage VDD2. In such an example, the fourth transistor TR4 can turn on. Thus, both the second regulation transistor MTR2 and the second additional transistor ATR2 can turn on by receiving a voltage from the node X2. When both the second regulation transistor MTR2 and the second additional transistor ATR2 turn on, the second regulation current ADI2 can be transmitted through the second regulation transistor MTR2 to the output node NOUT based on the second supply voltage VDD2. In addition, unlike the example of Figure 3 the second additional current can also be transmitted through the second additional transistor ATR2 to the output node NOUT. Thus, the transition time to the output voltage VOUT in the output node NOUT can be reduced, and thus the slew rate of the output port 115 can be increased accordingly.

[0119] For example, the second additional current can be provided from the load 113 to the output node NOUT through the second additional transistor ATR2.

[0120] Subsequently, when the difference between the input voltage VIN and the output voltage VOUT does not exceed the threshold voltage, the fourth transistor TR4 can turn off, and the second regulation transistor MTR2 and the second additional transistor ATR2 can turn off by receiving a voltage from the node X2. The output voltage VOUT can be output by turning on only the second drive transistor DTR2.

[0121] In an example, when the sizes of the respective transistors of the slew rate regulation circuit 120 are appropriately adjusted, for example, as discussed above, the sum of the sizes or sizes of the transistors included in the slew rate regulation circuit 120 in the example of Figure 6 may be the same as the sum of the sizes of the transistors included in the slew rate regulation circuit 120 in the example of Figure 3 .

[0122] Figure 7 is a diagram showing a flowchart of a slew rate regulation method according to an example. The slew rate regulation method shown in Figure 1 to Figure 6 may be performed by the slew rate regulation circuit 120 as described with reference to the example of Figure 7 .

[0123] With reference to the example of Figure 1 to Figure 7 , in S110, the slew rate regulation circuit 120 can receive an input voltage VIN input to the operational amplifier 110. According to an example, the input voltage VIN input to the operational amplifier 110 can be input to at least one of the transistors included in the slew rate regulation circuit 120.

[0124] In S120, the slew rate adjustment circuit 120 can receive the output voltage VOUT output from the operational amplifier 110. According to an example, the output voltage VOUT output from the operational amplifier 110 can be input to at least one of the transistors included in the slew rate adjustment circuit 120.

[0125] In S130, the slew rate adjustment circuit 120 can provide the adjustment current ADI to the output port 115 of the operational amplifier 110 based on a difference between the input voltage VIN and the output voltage VOUT. As described above, when the difference between the input voltage VIN and the output voltage VOUT is equal to or greater than the reference voltage, the slew rate adjustment circuit 120 can reduce the transition time to the output voltage VOUT by providing the adjustment current ADI to the operational amplifier 110.

[0126] In other words, when the difference between the input voltage VIN and the output voltage VOUT is equal to or greater than the reference voltage, the slew rate adjustment circuit 120 can reduce the transition time to the output voltage VOUT by additionally providing the adjustment current ADI to the operational amplifier 110. When the difference between the input voltage VIN and the output voltage VOUT is less than the reference voltage, the slew rate adjustment circuit 120 can not provide the adjustment current ADI to the operational amplifier 110. Accordingly, the slew rate in the case where the difference between the input voltage VIN and the output voltage VOUT is equal to or greater than the reference voltage can be greater than the slew rate in the case where the difference between the input voltage VIN and the output voltage VOUT is less than the reference voltage.

[0127] According to an example, the slew rate adjustment circuit 120 can determine a current level of the adjustment current ADI based on the difference between the input voltage VIN and the output voltage VOUT. Accordingly, when the difference between the input voltage VIN and the output voltage VOUT becomes greater, the slew rate can also become greater, and when the difference between the input voltage VIN and the output voltage VOUT becomes smaller, the slew rate can also become smaller. Accordingly, the slew rate adjustment circuit 120 can thus adaptively adjust the transition time to the output voltage VOUT according to the difference in magnitude between the output voltage VOUT and the input voltage VIN.

[0128] Figure 8 FIG. 1 is a conceptual diagram illustrating a display device including a buffer circuit according to an example. Referring to FIG. 1, a display device 1000 can include a display panel 200, a display driving circuit 300, a gate driving circuit 400, and a timing controller 500. Figure 8 According to an example of FIG. 1, the display device 1000 can include the display panel 200, the display driving circuit 300, the gate driving circuit 400, and the timing controller 500. However, this is a non-limiting example, and in other examples, other elements can be present in addition to and / or instead of these elements.

[0129] According to an example, the display apparatus 1000 can be an apparatus capable of displaying an image or a video. For example, the display apparatus 1000 can refer to a smart phone, a tablet personal computer, a mobile phone, a video phone, an e-book reader, a computer, a camera, or a wearable apparatus, by way of non-limiting example, but the display apparatus 1000 is not limited to these enumerated examples, and in other examples, other apparatuses having a display activity are used as the display apparatus 1000.

[0130] The display panel 200 can include a plurality of sub-pixels P arranged in rows and columns. For example, the display panel 200 can be implemented using any one of the following by way of non-limiting example: a light emitting diode (LED) display, an organic LED (OLED) display, an active matrix OLED (AMOLED) display, an electrochromic display (ECD), a digital micromirror device (DMD), an actuated mirror device (AMD), a grating light valve (GLV), a plasma display panel (PDP), an electroluminescent display (ELD), and a vacuum fluorescent display (VFD), but the display panel 200 is not limited to these enumerated examples, and in other examples, other apparatuses providing an image / video display capability, e.g., by using sub-pixels, are used as the display panel 200.

[0131] The display panel 200 can include a plurality of gate lines GL1 to GLn arranged in rows, where n is a natural number. The display panel 200 can further include a plurality of data lines DL1 to DLm arranged in columns, where m is a natural number. Accordingly, the display panel 200 can include sub-pixels P formed at respective intersections between the plurality of gate lines GL1 to GLn and the plurality of data lines DL1 to DLm. The display panel 200 can include a plurality of horizontal lines, and a horizontal line can be configured with sub-pixels P connected to a gate line. During one horizontal period (1H), sub-pixels arranged in a horizontal line can be driven, and during a subsequent 1H, sub-pixels arranged in another horizontal line can be driven.

[0132] Each of the sub-pixels P can include a light emitting diode (LED) and a diode driving circuit independently driving the LED. Each diode driving circuit can be connected to a gate line and a data line, and each LED can be connected between the diode driving circuit and a power supply voltage, e.g., a ground voltage, by way of non-limiting example.

[0133] Each diode driving circuit can include a switching element, for example, a thin film transistor (TFT), connected to the gate line GL1 to GLn. When the switching element is turned on by providing a gate-on signal to the gate line GL1 to GLn, the diode driving circuit can provide an image signal or a pixel signal to the LED, the image signal or the pixel signal being provided from the data line DL1 to DLm connected to the diode driving circuit. The LED can output an optical signal associated with the image signal.

[0134] Each sub-pixel P can be one of a red element R outputting red light, a green element G outputting green light, and a blue element B outputting blue light. In the display panel 200, the red element, the green element, and the blue element can be arranged according to various methods. According to non-limiting examples, the sub-pixels P of the display panel 200 can be arranged in a repeating manner in the order of R, G, B, and G or in the order of B, G, R, and G. For example, the sub-pixels P of the display panel 200 can be arranged according to an RGB stripe structure or an RGB Pentile structure, but the display panel 200 is not limited to these specific examples.

[0135] The gate driving circuit 400 can sequentially provide a gate-on signal to the plurality of gate lines GL1 to GLn in response to a gate control signal GCS. For example, the gate control signal GCS can include a gate start pulse indicating a start time of outputting the gate-on signal and a gate shift clock controlling timing of each gate-on signal.

[0136] When the gate start pulse is input, the gate driving circuit 400 can sequentially generate a gate-on signal, for example, a logically high gate voltage, in response to the gate shift clock and can sequentially provide the gate-on signal to the plurality of gate lines GL1 to GLn. In such an example, during a time period in which the gate-on signal is not provided to the plurality of gate lines GL1 to GLn, a gate-off signal, for example, a logically low gate voltage, can be provided to the plurality of gate lines GL1 to GLn.

[0137] The display driving circuit 300 can convert digital image data DATA to an analog image signal in response to a data control signal DCS and can provide the resulting image signal to the plurality of data lines DL1 to DLm. The display driving circuit 300 can also provide an image signal associated with one horizontal line to the corresponding plurality of data lines DL1 to DLm during a 1H horizontal period.

[0138] The display driving circuit 300 can include a buffer circuit 100 that transmits a signal to the data lines DL1 to DLm. Such a buffer circuit 100 can be the buffer circuit 100 described with reference to Figure 1 to Figure 6 .

[0139] The buffer circuit 100 can transmit a signal into the display panel 200. The display driving circuit 300 can convert the image data DATA into an image signal in response to receiving the data control signal DCS. The display driving circuit 300 can convert such image data into an image signal of a gray voltage associated with the image data DATA, and can output the resulting image signal into the plurality of data lines DL1 to DLm through the buffer circuit 100.

[0140] The timing controller 500 can receive external video image data RGB, and can process the video image data RGB according to the structure of the display panel 200, or can generate image data DATA by converting the video image data. Further, the timing controller 500 can transmit the image data DATA into the display driving circuit 300.

[0141] The timing controller 500 can receive a plurality of control signals from an external host device. The control signals can include a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, and a clock signal DCLK, which are commonly shown as SYNC in the example. Figure 8

[0142] The timing controller 500 can generate a gate control signal GCS and a data control signal DCS for controlling the gate driving circuit 400 and the display driving circuit 300, respectively, based on the received control signals. The timing controller 500 can also control various driving timings of the gate driving circuit 400 and the display driving circuit 300 based on the gate control signal GCS and the data control signal DCS it receives.

[0143] According to an example, the timing controller 500 can control the gate driving circuit 400 so that the gate driving circuit 400 can provide a gate-on signal to the plurality of gate lines GL1 to GLn based on the gate control signal GCS. The timing controller 500 can control the display driving circuit 300 so that the display driving circuit 300 can provide an image signal to the plurality of data lines DL1 to DLm based on the data control signal DCS.

[0144] Each configuration of the display device 1000 can be employed in a circuit capable of performing a corresponding function.

[0145] Figure 1 to Figure 8 ​The buffer circuit 100, the operational amplifier 110, the input port 111, the load 113, the output port 115, the slew rate adjustment circuit 120, the adjustment current generation circuit 121, the control circuit 123, the display device 1000, the display panel 200, the display driving circuit 300, the gate driving circuit 400, and the timing controller 500 that perform the operations described in this application are implemented by hardware components configured to perform the operations described in this application, which are performed by the hardware components. Examples of the hardware components that can be used to perform the operations described in this application include buffers, transistors, controllers, sensors, generators, drivers, memories, comparators, arithmetic logic units, adders, subtractors, multipliers, dividers, integrators, and any other electronic components configured to perform the operations described in this application, as appropriate.

[0146] While the present disclosure includes specific examples, it will be apparent to those skilled in the art after understanding the disclosure provided herein that various changes in form and details can be made to these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects in each example should be considered as being applicable to similar features or aspects in other examples. Suitable results can be achieved if the described techniques are performed in a different order, and / or if the components of the described systems, architectures, devices, or circuits are combined in a different manner, and / or if the components of the described systems, architectures, devices, or circuits are replaced or supplemented by other components or equivalents thereof. Therefore, the scope of the disclosure is defined not by the specific embodiments described herein, but by the appended claims and their equivalents, and all variations within the scope of the claims and their equivalents are intended to be embraced.

Claims

1. A slew rate adjustment circuit, the slew rate adjustment circuit comprising: an adjustment transistor configured to provide an adjustment current into an output port of an operational amplifier in response to the adjustment transistor being turned on; a first transistor connected between a power line of the operational amplifier and the adjustment transistor; a second transistor connected between the first transistor and an output node of the output port, an enable transistor connected to the adjustment transistor, the first transistor, and the second transistor, wherein the enable transistor is configured to control whether the second transistor is turned on in response to receiving an enable signal, wherein the adjustment transistor is turned on by the second transistor in response to a difference between an input voltage and an output voltage being equal to or greater than a reference voltage.

2. The slew rate adjustment circuit of claim 1, wherein, the adjustment current is provided from the power line into the output node via the adjustment transistor.

3. The slew rate adjustment circuit of claim 1, wherein, the second transistor is turned on in response to the difference between the input voltage and the output voltage being equal to or greater than the reference voltage, the adjustment transistor is turned on in response to the second transistor being turned on, and the adjustment current is provided to the output node via the adjustment transistor in response to the adjustment transistor being turned on.

4. The slew rate adjustment circuit of claim 1, wherein, the adjustment transistor, the first transistor, and the second transistor are metal oxide semiconductor field effect transistors, a source terminal of the second transistor is connected to the output node, a drain terminal of the second transistor is connected to a gate terminal of the adjustment transistor, a source terminal of the adjustment transistor is connected to the power line, and a drain terminal of the adjustment transistor is connected to the output node.

5. The slew rate adjustment circuit of claim 1, wherein, the adjustment transistor and the second transistor are metal oxide semiconductor field effect transistors, a source terminal of the second transistor is connected to the output node, a drain terminal of the second transistor is connected to a gate terminal of the adjustment transistor, a source terminal of the adjustment transistor is connected to the power line, and a drain terminal of the adjustment transistor is connected to the output node.

6. The slew rate adjustment circuit of claim 1, wherein, a positive adjustment current is provided via the adjustment transistor in response to the operational amplifier operating with a pull-up current.

7. The slew rate adjustment circuit of claim 1, wherein, a negative adjustment current is provided via the adjustment transistor in response to the operational amplifier operating with a pull-down current.

8. The slew rate adjustment circuit of claim 1, further comprising an additional transistor connected to the adjustment transistor, the first transistor, and the second transistor, wherein, the second transistor is configured to turn on the additional transistor in response to the difference between the input voltage and the output voltage being equal to or greater than the reference voltage, and to provide an additional current to the output node in response to the additional transistor being turned on.

9. A buffer circuit, the buffer circuit comprising: an operational amplifier configured to output an output voltage via an output node by amplifying an input voltage; an adjustment current generation circuit comprising an adjustment transistor and configured to provide an adjustment current into an output port of the operational amplifier to adjust a slew rate of the output port; a compensation capacitor connected between the operational amplifier and a drain terminal of the regulation transistor and configured to perform a compensation operation, the drain terminal of the regulation transistor being directly connected to the output node and the compensation capacitor; and a control circuit configured to control the regulation current generation circuit to provide the regulation current in response to a difference between the input voltage and the output voltage being equal to or greater than a reference voltage.

10. The snubber circuit of claim 9, wherein, the regulation transistor is connected between a power line of the operational amplifier, the output node, and the control circuit, wherein, in response to the difference between the input voltage and the output voltage being equal to or greater than the reference voltage, the regulation current is provided to the output node via the regulation transistor by turning on the regulation transistor according to the control of the control circuit.

11. The snubber circuit of claim 10, wherein, the regulation current is provided to the output node from the power line via the regulation transistor.

12. The snubber circuit of claim 10, wherein, the control circuit includes: a first transistor connected to the power line; and a second transistor connected between the first transistor and the output node, wherein the regulation transistor is turned on by the second transistor in response to the difference between the input voltage and the output voltage being equal to or greater than the reference voltage.

13. The snubber circuit of claim 12, wherein, the regulation transistor and the second transistor are metal oxide semiconductor field effect transistors, wherein a source terminal of the second transistor is connected to the output node, a drain terminal of the second transistor is connected to a gate terminal of the regulation transistor, the source terminal of the regulation transistor is connected to the power line, and a drain terminal of the regulation transistor is connected to the output node.

14. The snubber circuit of claim 12, further comprising an enable transistor connected to the regulation transistor, the first transistor, and the second transistor, wherein, the enable transistor is configured to control whether to turn on the second transistor in response to an enable signal.

15. The snubber circuit of claim 12, further comprising an additional transistor connected to the regulating transistor, the first transistor, and the second transistor, wherein, the additional transistor is turned on by the second transistor in response to the difference between the input voltage and the output voltage being equal to or greater than the reference voltage, and an additional current is provided to the output node in response to the additional transistor being turned on.

16. A slew rate adjustment method, the method comprising: receiving an input voltage input to an operational amplifier; receiving an output voltage output from the operational amplifier via an output node; performing a compensation operation with a compensation capacitor connected between the operational amplifier and a drain terminal of a regulation transistor, the drain terminal of the regulation transistor being directly connected to the output node and the compensation capacitor; and providing a regulation current to an output port of the operational amplifier to reduce a transition time of the output voltage based on a difference between the input voltage and the output voltage.

17. The method of claim 16, wherein, providing the regulation current includes providing the regulation current in response to the difference between the input voltage and the output voltage being equal to or greater than a reference voltage.

18. The method of claim 17, wherein, a slew rate in a case where the difference between the input voltage and the output voltage is equal to or greater than the reference voltage is greater than a slew rate in a case where the difference between the input voltage and the output voltage is less than the reference voltage.

19. The method of claim 16, wherein, a magnitude of the regulation current is determined based on the difference between the input voltage and the output voltage.

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