Integrated circuit device and method for manufacturing the same

Abstract

The present application provides an integrated circuit device and a method for preparing the same, which relates to the field of semiconductor technology. An isolation segment that suppresses the leakage current path of two adjacent transistors can be formed through a simple process. The integrated circuit device includes: a substrate and a fin protruding from the substrate, and the integrated circuit device also includes two adjacent transistors, and the two adjacent transistors use the two interval sections on the fin as their respective channels; wherein a portion of the fin located between the two interval sections is processed to obtain an isolation segment, and the isolation segment is used to suppress the current transfer between the two channels of the two adjacent transistors.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to an integrated circuit device and a method for manufacturing the same. Background Art

[0002] In the design and manufacture of integrated circuits, in order to reduce the leakage current of transistors, an isolation segment needs to be formed between adjacent transistors arranged together. Figure 1 As shown, taking two transistors as an example, when the two transistors are designed to be placed together, the active regions 50 of the two transistors cannot be directly connected together, and an isolation segment 70 is usually required to be formed between the two transistors so that the two transistors can work independently and the electrical characteristics and logical operations do not affect each other. Therefore, how to achieve isolation between transistors is a very important technical point. Summary of the invention

[0003] The present application provides an integrated circuit device and a method for manufacturing the same, which can form an isolation segment for suppressing leakage current paths of two adjacent transistors through a simple process.

[0004] In order to achieve the above objectives, this application adopts the following technical solutions:

[0005] The first aspect of the present application provides an integrated circuit device, comprising: a substrate and a fin protruding from the substrate, the integrated circuit device also comprising two adjacent transistors, the two adjacent transistors using two interval sections on the fin as their respective channels; wherein a portion of the fin located between the two interval sections is processed to obtain an isolation section, the isolation section is used to suppress the current transfer between the two channels of the two adjacent transistors. By processing a portion of the fin located between the two interval sections through a simple process, the current transfer between the two channels of the two transistors can be suppressed, the structure and stress of the transistors on both sides of the isolation section are less affected, the variability of the device characteristic parameters introduced is minimized, the area resources occupied by the isolation section are smaller, and no special winding resources need to be designed.

[0006] Optionally, the fin comprises a first semiconductor layer, wherein the isolation is doped with inert atoms.

[0007] Optionally, the fin includes a first semiconductor layer, and a thickness of the first semiconductor layer in the isolation segment is smaller than a thickness of channels of two adjacent transistors.

[0008] Optionally, the fin includes a first semiconductor layer and an auxiliary layer that are alternately arranged, the auxiliary layer includes a gate material layer and a gate dielectric material layer wrapped outside the gate material layer, and the isolation segment and the channel are formed in the first semiconductor layer.

[0009] Optionally, the inert atoms include at least one of hydrogen atoms, oxygen atoms, nitrogen atoms, carbon atoms, and silicon atoms.

[0010] In the second aspect, a method for preparing an integrated circuit device is provided, wherein a fin protruding from the substrate is formed on a substrate; at least two first dummy gates and at least one second dummy gate are formed; at least two first dummy gates and at least one second dummy gate are arranged along the gate length direction, and each second dummy gate is located between two adjacent first dummy gates; the first dummy gate and the second dummy gate are both in contact with two opposite side surfaces and the top surface of the fin; an interlayer insulating layer is formed, and the upper surface of the interlayer insulating layer is flush with the upper surfaces of the first dummy gate and the second dummy gate; at least the second dummy gate is removed, and the exposed portion of the fin after the second dummy gate is removed is processed to form an isolation segment to inhibit the current from passing through the exposed portion of the fin after the second dummy gate is removed. Since the upper surfaces of the first dummy gate and the second dummy gate are exposed after the interlayer insulating layer is formed, the second dummy gate can be removed by a simple process, so that the semiconductor thin slice exposed after the second dummy gate is removed can be processed to form an isolation segment that inhibits the leakage current path of two adjacent transistors. When the isolation segment is formed based on this method, it has the advantages of less impact on the structure and stress of transistors on both sides of the isolation segment, minimal variability in the introduced device characteristic parameters, less area resources occupied by the isolation segment, and no need to design special winding resources.

[0011] Optionally, the fin includes a first semiconductor layer; the portion of the fin exposed after the second dummy gate is removed is processed to form an isolation segment to inhibit current transmission in the portion of the fin exposed after the second dummy gate is removed, including: using a process selected from plasma treatment, plasma implantation, and ion implantation to dope inert atoms in the portion of the first semiconductor layer exposed after the second dummy gate is removed to insulate the exposed portion of the first semiconductor layer.

[0012] Optionally, the inert atoms include at least one of hydrogen atoms, oxygen atoms, nitrogen atoms, carbon atoms, and silicon atoms.

[0013] Optionally, the fin includes a first semiconductor layer; the portion of the fin exposed after the second dummy gate is removed is processed to form an isolation segment to inhibit current transmission in the portion of the fin exposed after the second dummy gate is removed, including: using an etching process to process the portion of the first semiconductor layer exposed after the second dummy gate is removed, so that the morphology of the exposed portion of the first semiconductor layer changes.

[0014] Optionally, an etching process is used to process a portion of the first semiconductor layer exposed after the second dummy gate is removed, so that the morphology of the exposed portion of the first semiconductor layer is changed, including: using an etching process to process at least a portion of the first semiconductor layer exposed after the second dummy gate is removed, so that the thickness of the exposed portion of the first semiconductor layer is thinned along a direction perpendicular to the gate length direction or the thickness direction of the substrate.

[0015] Optionally, an etching process is used to process the portion of the first semiconductor layer exposed after the second dummy gate is removed, so that the morphology of the exposed portion of the first semiconductor layer changes, including: using an etching process to process the fins exposed after the second dummy gate is removed, so that the shape of the exposed portion of the first semiconductor layer changes.

[0016] Optionally, the fin is composed of a first semiconductor layer; at least the second dummy gate is removed, and the portion of the fin exposed after the second dummy gate is removed is processed to form an isolation segment to inhibit current from being transmitted in the portion of the fin exposed after the second dummy gate is removed, including: removing the second dummy gate, and processing the portion of the fin exposed after the second dummy gate is removed to form an isolation segment to inhibit current from being transmitted in the portion of the fin exposed after the second dummy gate is removed; after forming the isolation segment, the method for preparing the integrated circuit device also includes: removing the first dummy gate, and forming a gate dielectric layer and a gate at the positions where the first dummy gate and the second dummy gate are removed, respectively.

[0017] Optionally, the fin includes multiple layers of first semiconductor layers and multiple layers of second semiconductor layers, and the first semiconductor layers and the second semiconductor layers are alternately arranged along the thickness direction of the substrate; before forming the interlayer insulating layer, the preparation method of the integrated circuit device also includes: forming side walls on both sides of the first dummy gate and the second dummy gate along the gate length direction; removing the fins not covered by the first dummy gate and the side walls on both sides thereof, and the second dummy gate and the side walls on both sides thereof; processing the area covered by the side walls of the second semiconductor layer of the retained fin to form an inner side wall, and the remaining area not covered by the side walls is used as a sacrificial layer; at least the second dummy gate is removed, and the exposed portion of the fin after the second dummy gate is removed is processed, including: removing the first dummy gate, the second dummy gate and the sacrificial layer, and processing the exposed portion of the fin after the second dummy gate is removed to form an isolation section to inhibit current from being transmitted in the exposed portion of the fin after the second dummy gate is removed; forming a gate dielectric layer and a gate at the position where the first dummy gate and the second dummy gate are removed; and forming a gate material layer and a gate dielectric material layer wrapped around the gate material at the position of the sacrificial layer as an auxiliary layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A schematic diagram of forming an isolation segment between adjacent transistors provided in the prior art;

[0019] Figure 2 A schematic diagram of a process for preparing an integrated circuit device provided in the present application;

[0020] Figure 3 A schematic flow chart of another method for preparing an integrated circuit device provided in the present application;

[0021] Figure 4a A schematic diagram of forming a fin on a substrate provided in the present application;

[0022] Figure 4b Another schematic diagram of forming fins on a substrate provided in the present application;

[0023] Figure 5a For Figure 4a A schematic diagram of forming a first dummy gate and a second dummy gate on the basis;

[0024] Figure 5b for Figure 5a A1A1′ sectional view;

[0025] Figure 5c for Figure 5a A schematic cross-sectional view in the direction of B1B1′;

[0026] Figure 5d for Figure 5a Schematic diagram of the cross section in the C1C1′ direction;

[0027] Figure 6a For Figure 5a Schematic diagram of forming side walls on the foundation;

[0028] Figure 6b for Figure 6a A2A2′ sectional view;

[0029] Figure 7a For Figure 6a Schematic diagram of forming source and drain on the basis;

[0030] Figure 7b for Figure 7a A3A3′ sectional view;

[0031] Figure 8a For Figure 7a Schematic diagram of forming an interlayer insulating layer on a basis;

[0032] Figure 8b for Figure 8a A4A4′ sectional view;

[0033] Figure 9a For Figure 8a Schematic diagram of the base after removing the second false grid;

[0034] Figure 9b for Figure 9a A5A5′ sectional view;

[0035] Fig.9c for Figure 9a A schematic cross-sectional view in the direction of B5B5′;

[0036] Figure 9d A schematic diagram of forming a first photosensitive layer exposing the second dummy gate on the interlayer insulating layer before removing the second dummy gate;

[0037] Fig.10a For Figure 9a Schematic diagram of forming an isolation section on the basis;

[0038] Fig.10b for Fig.10a A6A6′ sectional view;

[0039] Fig.10c for Fig.10a A schematic cross-sectional view in the direction of B6B6′;

[0040] Fig.11a For Fig.10a A schematic diagram of forming a gate dielectric layer and a gate on the basis;

[0041] Fig.11b for Fig.11a A7A7′ sectional view;

[0042] Fig.11c for Fig.11a A schematic cross-sectional view in the direction of B7B7′;

[0043] Fig.11d for Fig.11a A schematic cross-sectional view in the direction of C7C7′;

[0044] Fig.12 A schematic flow chart of another method for preparing an integrated circuit device provided in the present application;

[0045] Fig.13a A schematic diagram of forming a fin and a first dummy gate and a second dummy gate on a substrate provided in the present application;

[0046] Fig.13b for Fig.13a A schematic cross-sectional view in the direction of D1D1′;

[0047] Fig.13c for Fig.13a Schematic cross-sectional view in the direction of E1E1′;

[0048] Fig.13d for Fig.13a A schematic cross-sectional view in the F1F1′ direction;

[0049] Fig.14a For Fig.13a A schematic diagram of forming a sidewall on the basis and removing the fins not covered by the first dummy gate and the sidewalls on both sides thereof, and the second dummy gate and the sidewalls on both sides thereof;

[0050] Fig.14b for Fig.14a A schematic cross-sectional view in the direction of D2D2′;

[0051] Fig.14c For Fig.14b Schematic diagram of forming inner wall and sacrificial layer on the basis;

[0052] Fig.15a For Fig.14a Schematic diagram of forming source and drain on the basis;

[0053] Fig.15b for Fig.15a A schematic cross-sectional view in the direction of D3D3′;

[0054] Fig.16a For Fig.15a Schematic diagram of forming an interlayer insulating layer on a basis;

[0055] Fig.16b for Fig.16a A schematic cross-sectional view in the direction of D4D4′;

[0056] Fig.17a For Fig.16a A schematic diagram of a base after the first dummy gate, the second dummy gate and the sacrificial layer are removed;

[0057] Fig.17b for Fig.17a A schematic cross-sectional view in the direction of D5D5′;

[0058] Fig.17c for Fig.17a A schematic cross-sectional view in the direction of E5E5′;

[0059] Fig.17d for Fig.17a A schematic cross-sectional view in the direction of F5F5′;

[0060] Fig.17e A schematic diagram of forming a second photosensitive layer in the area where the second dummy gate is exposed and removed before processing the first semiconductor layer in the fin exposed after the second dummy gate is removed;

[0061] Fig.18a For Fig.17b A schematic cross-sectional view in the direction of D5D5′ after the isolation section is formed on the foundation;

[0062] Fig.18b For Fig.17c A schematic cross-sectional view in the direction of E5E5′ after the isolation section is formed on the foundation;

[0063] Fig.18c For Fig.17d A schematic cross-sectional view in the direction of F5 to F5′ after the isolation section is formed on the foundation;

[0064] Fig.19a For Fig.17a A schematic diagram of forming a gate dielectric layer and a gate on the basis;

[0065] Fig.19b for Fig.19a A schematic cross-sectional view in the direction of D7D7′;

[0066] Fig.19c for Fig.19a A schematic cross-sectional view in the direction of E7E7′;

[0067] Fig.19d for Fig.19a Schematic diagram of the cross-section along F7F7′.

[0068] Reference numerals:

[0069] 10-substrate; 20-fin; 31-first dummy gate; 32-second dummy gate; 40-side wall; 50-active area; 51-source; 52-drain; 53-channel area; 60-interlayer insulating layer; 70-isolation segment; 81-first photosensitive layer; 82-second photosensitive layer; 91-gate dielectric layer; 92-gate; 231-first semiconductor layer; 232-second semiconductor layer; 233-inner side wall; 234-sacrificial layer; 235-auxiliary layer; 2351-gate material layer; 2352-gate dielectric material layer; 100-transistor. DETAILED DESCRIPTION

[0070] The embodiment of the present application provides a method for preparing an integrated circuit device, such as Figure 2 As shown, including:

[0071] S10, such as Figure 4a As shown, a fin 20 protruding from the substrate 10 is formed on the substrate 10 .

[0072] There may be one or more fins 20. When there are more than one fin 20, the fins 20 may be divided into multiple groups, each group including at least one fin 20. When each group includes multiple fins 20, the multiple fins 20 are arranged in parallel. The thickness t of the fin 20 may be in the nanometer level, and the thickness direction of the fin 20 is perpendicular to the gate length direction and the thickness direction of the substrate 10.

[0073] The fin 20 may be substantially rectangular in shape. In this case, the fin 20 has four side surfaces extending vertically from the upper surface of the substrate 10 and a top surface located on the four side surfaces, and the top surface may be substantially parallel to the upper surface of the substrate 10 .

[0074] Figure 4a A group of three fins 20 is used for illustration, but the present application is not limited thereto. Figure 4b As shown, a group may also include only one fin 20 . Figure 4a and Figure 4bOnly a group of fins 20 are shown to be formed on the substrate 10 , but the present application is not limited thereto and may be determined according to the design of a specific integrated circuit device.

[0075] The method for manufacturing an integrated circuit device provided in the embodiment of the present application is exemplarily described by forming three fins 20 on a substrate 10 , with the three fins 20 forming a group.

[0076] S11, such as Figure 5a or Fig.13a As shown, at least two first dummy gates 31 and at least one second dummy gate 32 are formed; at least two first dummy gates 31 and at least one second dummy gate 32 are arranged along the gate length direction X, and each second dummy gate 32 is located between two adjacent first dummy gates 31; the first dummy gate 31 and the second dummy gate 32 are both in contact with the two opposite side surfaces and the top surface of the fin 20.

[0077] Exemplarily, regardless of being the first dummy gate 31 or the second dummy gate 32, along the thickness t direction of the fin 20, the first dummy gate 31 and the second dummy gate 32 both span across each fin 20 in a group, and contact the two side surfaces of each fin 20 perpendicular to the thickness direction of the fin 20 and the top surface between the two side surfaces.

[0078] When a plurality of groups of fins 20 are formed on the substrate 10 , the first dummy gate 31 and the second dummy gate 32 straddling each group of fins 20 are not connected.

[0079] In a plane parallel to the top surface of the fin 20 , the thickness direction of the fin 20 is perpendicular to the gate length direction X. Since the top surface of the fin 20 is substantially parallel to the upper surface of the substrate 10 , the thickness direction of the fin 20 is also perpendicular to the gate length direction X in the plane of the upper surface of the substrate 10 .

[0080] The above-mentioned “first dummy gate” and “second dummy gate” are called “dummy gates” because for the integrated circuit device finally prepared, the “first dummy gate” and “second dummy gate” will be removed and a real gate will be formed.

[0081] S14, such as Figure 8a or Fig.16a As shown, an interlayer insulating layer 60 is formed, and the upper surface of the interlayer insulating layer 60 is flush with the upper surfaces of the first dummy gate 31 and the second dummy gate 32 .

[0082] S15, such as Figures 9a to 9c or Figure 10a to Figure 10c or Fig.17a as well as Figure 18a to Figure 18c As shown, at least the second dummy gate 32 is removed, and the portion of the fin 20 exposed after the second dummy gate 32 is removed is processed to form an isolation segment 70 to inhibit current from passing in the portion of the fin 20 exposed after the second dummy gate 32 is removed.

[0083] That is, the isolation segment 70 has a function of suppressing the flow of current therein.

[0084] Optionally, the exposed portion of the fin 20 after the second dummy gate 32 is removed may be processed in the following two ways.

[0085] Method 1: using one of plasma trimming, plasma doping and ion implantation processes, the exposed portion of the fin 20 after the second dummy gate 32 is removed is doped with inert atoms, so that at least a portion of the exposed portion of the fin 20 is insulated to form an isolation segment 70 .

[0086] The inert atoms here are different from ordinary impurity atoms. Ordinary impurity atoms have 3 or 5 outermost electrons. Ordinary impurity atoms can be ionized in the silicon lattice. Impurity atoms that produce free electrons are called donors, and impurity atoms that produce free holes are called acceptors. Inert atoms are injected into the silicon lattice, which has the effect of destroying the silicon lattice and the semiconductor band structure and inhibiting the generation of carriers. Exemplarily, the inert atom is at least one of a hydrogen atom (H), an oxygen atom (O), a nitrogen atom (N), a carbon atom (C), and a silicon atom (Si).

[0087] Method 2: using an etching process to process at least a portion of the exposed portion of the fin 20 after the second dummy gate 32 is removed, so as to change the morphology of the exposed fin 20 and form an isolation segment 70 .

[0088] For example, a hydrogen baking (H2baking) process may be used to process at least a portion of the exposed portion of the fin 20 after the second dummy gate 32 is removed, so as to change the morphology of the exposed fin 20. H2baking is a gas phase etching-surface treatment technology.

[0089] The change in morphology includes reducing the thickness of the exposed fin 20 in a direction perpendicular to the gate length direction X or the thickness direction of the substrate 10 , or changing the shape of the exposed fin 20 .

[0090] In some embodiments, before forming the interlayer insulating layer 60, it is necessary to form the sidewall 40, the source 51 and the drain 52, and the method for preparing the integrated circuit device further includes:

[0091] S12, such as Figure 6a or Fig.14a As shown, along the gate length direction X, spacers 40 are formed on both sides of the first dummy gate 31 and the second dummy gate 32 .

[0092] S13, such as Figure 7a to Figure 7b or Figure 15a-15b As shown, a source 51 and a drain 52 are respectively formed on both sides of each first dummy gate 31 along the gate length direction X.

[0093] Based on the above steps, Fig.10b As shown, when a source 51 and a drain 52 are respectively formed on both sides of each first dummy gate 31 along the gate length direction X, the region of the fin 20 covered by the first dummy gate 31 forms a channel region 53 .

[0094] On this basis, since the integrated circuit device includes multiple transistors, for each transistor, it includes a gate, a source 51 and a drain 52, and the area covered by the gate between the source 51 and the drain 52 forms a channel region 53. It can be seen that a transistor can be formed on both sides of the second dummy gate 32 respectively.

[0095] As mentioned above, although a real gate will be formed at the position of the second dummy gate 32 after the second dummy gate 32 is removed, an isolation segment 70 is formed after the exposed portion of the fin 20 after the second dummy gate 32 is removed. The purpose of forming the isolation segment 70 is to suppress the leakage current path of the transistors on both sides thereof. Therefore, the isolation segment 70 is basically insulated. It can be seen that the real gate formed at the position of the second dummy gate 32 does not have a normal channel opening characteristic.

[0096] It should be noted that the words "upper surface", "top surface" and the like mentioned in the present application all refer to the surface of the corresponding structure on one side away from the substrate 10. For example, the upper surface of the interlayer insulating layer 60 refers to the upper surface of the interlayer insulating layer 60 away from the substrate 10. The upper surface of the first dummy gate 31 refers to the upper surface of the interlayer insulating layer 60 away from the substrate 10.

[0097] The present application provides a method for preparing an integrated circuit device. Since the upper surfaces of the first dummy gate 31 and the second dummy gate 32 are exposed after forming the interlayer insulating layer 60, the second dummy gate 32 can be removed by a simple process, so that the exposed portion of the fin 20 after the second dummy gate 32 is removed can be processed to form an isolation segment 70 that suppresses the leakage current path of two adjacent transistors. When the isolation segment 70 is formed based on this method, it has the advantages of less influence on the structure and stress of the transistors on both sides of the isolation segment 70, minimum variability of the introduced device characteristic parameters, less area resources occupied by the isolation segment 70, and no need to design special winding resources.

[0098] Compared with the single diffusion break (SDB) and double diffusion break (DDB) technologies, which suppress the leakage current path by forming a groove and filling it with insulating materials, it will cause a large stress change, resulting in a large change in the parameters of the adjacent transistors. The formation method of the isolation segment 70 in the integrated circuit device preparation process provided by the present application can maintain the structural integrity of the part exposed after the second dummy gate 32 of the fin 20 is removed or partially retain the structural integrity, resulting in a relatively small stress change.

[0099] Compared with SWAP N / P workfunction metal (SWAP N / P), the essence of SWAP N / P is to set the threshold voltage of the isolation device to a relatively high level, so that the leakage current of the isolation device is suppressed as much as possible, which is essentially an electrical shutdown. However, SWAP N / P makes the integration process of the metal gate work function more complicated, and the restricted design rules limit the use of SWAP N / P. The formation method of the isolation segment 70 in the integrated circuit device preparation process provided in the present application will not complicate the metal gate work function integration process.

[0100] The essence of gate fixing is to fix the gate potential of the isolation device to a high voltage (VDD) or a low voltage (VSS), so that the P-type or N-type isolation device is in a forced off state. However, gate fixing takes up more contact and winding resources in design. Compared with gate fixing (Gate Tie), the formation method of the isolation segment 70 in the integrated circuit device preparation process provided by the present application does not require the use of the gate potential.

[0101] Taking the integrated circuit device including a fin field-effect transistor (Fin Field-Effect Transistor, FinFET) as an example, the embodiment of the present application also provides another method for preparing the integrated circuit device, such as Figure 3 As shown, including:

[0102] S20, such as Figure 4a As shown, a fin 20 protruding from the substrate 10 is formed on the substrate 10 .

[0103] In some embodiments, the substrate 10 and the fins 20 are formed by etching a semiconductor substrate, that is, grooves are formed in the semiconductor substrate by photolithography or etching, the protruding portions between adjacent grooves form the fins 20 , and the semiconductor substrate at the bottom of the fins 20 forms the substrate 10 .

[0104] In this case, the substrate 10 and the fin 20 are made of the same material, which can be one of bulk silicon, silicon germanium, silicon carbide, silicon-on-insulator (SOI), and silicon germanium on insulator (SGOI).

[0105] In some other embodiments, the fin 20 is formed on the upper surface of the substrate 10 by an epitaxial process.

[0106] Based on this, one way to form the fin 20 is to epitaxially grow a semiconductor film layer on the upper surface of the substrate 10, etch the semiconductor film layer until the upper surface of the substrate 10 is exposed, form grooves in the semiconductor film layer, and form the fin 20 as the protruding parts between adjacent grooves.

[0107] Another way to form the fin 20 is to form an isolation layer on the upper surface of the substrate 10, etch the isolation layer until the upper surface of the substrate 10 is exposed, and form a groove in the isolation layer; on this basis, the fin 20 is epitaxially formed in the groove, and after the fin 20 is formed, the isolation layer is etched so that the surface of the isolation layer is lower than the top surface of the fin 20.

[0108] The material of the substrate 10 may be one of bulk silicon, silicon germanium, silicon carbide, SOI, and GOI; the material of the fin 20 may be one of silicon, silicon germanium, germanium, or silicon carbide. The material of the fin 20 may be the same as or different from that of the substrate 10.

[0109] S21, such as Figure 5a , Figure 5b , Figure 5c and Figure 5d As shown, at least two first dummy gates 31 and at least one second dummy gate 32 are formed; at least two first dummy gates 31 and at least one second dummy gate 32 are arranged along the gate length direction X, and each second dummy gate 32 is located between two adjacent first dummy gates 31; the first dummy gate 31 and the second dummy gate 32 are both in contact with two opposite side surfaces and the top surface of the fin 20.

[0110] In the embodiment of the present application, the first dummy gate 31 is used to occupy space and position for the real gate and gate dielectric layer to be formed subsequently, and thus, the first dummy gate 31 needs to be removed subsequently. As for the second dummy gate 32, its main purpose is to form the isolation segment 70 in the subsequent process, and thus, the size of the second dummy gate 32 can be determined according to the size of the isolation segment 70.

[0111] The materials of the first dummy gate 31 and the second dummy gate 32 can be the same, and the materials of the first dummy gate 31 and the second dummy gate 32 can be at least one of polycrystalline silicon, amorphous silicon, and amorphous carbon. Since materials such as polycrystalline silicon, amorphous silicon, and amorphous carbon are easy to etch, have good shape retention, and are easy to remove, when the first dummy gate 31 and the second dummy gate 32 are formed of at least one material of polycrystalline silicon, amorphous silicon, and amorphous carbon, the first dummy gate 31 and the second dummy gate 32 can have good morphology, stable structure, and be easy to remove.

[0112] The first dummy gate 31 and the second dummy gate 32 can be simultaneously formed by photolithography and etching processes.

[0113] S22, such as Figure 6a and Figure 6b As shown, along the gate length direction X, spacers 40 are formed on both sides of the first dummy gate 31 and the second dummy gate 32 .

[0114] The sidewall spacer 40 protects the first dummy gate 31 and the second dummy gate 32 , and enables the source and drain to be formed on both sides of the first dummy gate 31 in a self-aligned manner in the subsequent process of forming the source and the drain.

[0115] The material of the spacer 40 may be silicon nitride (Si3N4), silicon oxynitride (SiON), etc. The spacer 40 may be formed, for example, by an isotropic deposition-anisotropic etching method.

[0116] S23, such as Figure 7a and Figure 7b As shown, a source 51 and a drain 52 are respectively formed on both sides of each first dummy gate 31 along the gate length direction X.

[0117] Those skilled in the art will appreciate that the source 51 and the drain 52 are formed in the region of the fin 20 that is not covered by the first dummy gate 31 and the spacers 40 on both sides thereof and the second dummy gate 32 and the spacers on both sides thereof.

[0118] For the first dummy gate 31 on one side of the second dummy gate 32, when the source 51 and the drain 52 are formed on both sides of the first dummy gate 31 along the gate length direction X, one of the source 51 and the drain 52 is located between the first dummy gate 31 and the second dummy gate 32. Similarly, for the first dummy gate 31 on the other side of the second dummy gate 32, when the source 51 and the drain 52 are formed on both sides of the first dummy gate 31 along the gate length direction X, one of the source 51 and the drain 52 is located between the first dummy gate 31 and the second dummy gate 32.

[0119] From this we can see that Figure 7bAs shown, the region of the fin 20 covered by the first dummy gate 31 forms a channel region 53. The projection of the channel region 53 on the substrate 10 overlaps with the projection of the first dummy gate 31 on the substrate 10.

[0120] After S23, the source 51, drain 52 and channel region 53 of the FinFET have been formed on one side of the second dummy gate 32 along the gate length direction X. Similarly, the source 51, drain 52 and channel region 53 constituting the FinFET have been formed on the other side of the second dummy gate 32 along the gate length direction X.

[0121] When forming an N-type FinFET, silicon germanium (SiGe) containing boron (B) can be epitaxially grown on both sides of the first dummy gate 31 along the gate length direction X through a selective epitaxial process, thereby forming a source 51 and a drain 52. When forming a P-type FinFET, silicon (Si) containing phosphorus (P) can be epitaxially grown on both sides of the first dummy gate 31 along the gate length direction X through a selective epitaxial process, thereby forming a source 51 and a drain 52.

[0122] It should be noted that Figure 7a It is illustrated that multiple sources 51 and multiple drains 52 are respectively formed on both sides of the first dummy gate 31 along the gate length direction X (the "multiple" here can be consistent with the number of fins 20), but the present application is not limited to this. The multiple sources 51 on one side of the first dummy gate 31 along the gate length direction X can be merged into one source 51, and the multiple drains 52 on the other side of the first dummy gate 31 along the gate length direction X can be merged into one drain 52.

[0123] S24, such as Figure 8a and Figure 8b As shown, an interlayer insulating layer 60 is formed, and the upper surface of the interlayer insulating layer 60 is flush with the upper surfaces of the first dummy gate 31 and the second dummy gate 32 .

[0124] Optionally, by depositing an insulating material, such as silicon oxide, silicon nitride, etc., and performing a chemical mechanical polishing (CMP) process, the upper surface of the interlayer insulating layer 60 is made flush with the upper surfaces of the first dummy gate 31 and the second dummy gate 32, thereby exposing the first dummy gate 31 and the second dummy gate 32.

[0125] S25, such as Figure 9a , Figure 9b and Fig.9c As shown, the second dummy gate 32 is removed.

[0126] To avoid removing the first dummy gate 31 when removing the second dummy gate 32, after S24 and before S25, Figure 9dAs shown, a first photosensitive layer 81 is formed by a photolithography process, and the first photosensitive layer 81 exposes the second dummy gate 32, so that the first photosensitive layer 81 protects the first dummy gate 31. The material of the first photosensitive layer 81 may be photoresist, for example.

[0127] When the second dummy gate 32 is removed, the first dummy gate 31 is retained in order to protect the channel region 53 .

[0128] On this basis, a wet etching or dry etching process can be used to remove the second dummy gate 32. After the second dummy gate 32 is removed, the area of ​​the fin 20 covered by the second dummy gate 32 is exposed. The projection of the exposed portion of the fin 20 after the second dummy gate 32 is removed on the substrate 10 overlaps with the projection of the second dummy gate 32 on the substrate 10.

[0129] S26, such as Fig.10a , Fig.10b and Fig.10c As shown, the exposed portion of the fin 20 after the second dummy gate 32 is removed is processed to form an isolation segment 70 to inhibit current from being transmitted in the exposed portion of the fin 20 after the second dummy gate 32 is removed.

[0130] By processing the exposed portion of the fin 20 after the second dummy gate 32 is removed, the conductivity of the exposed portion of the fin 20 after the second dummy gate 32 is removed can be changed, so that the conductivity is reduced or even completely insulated. After the isolation segment 70 is formed, the isolation segment 70 can suppress the leakage current path between the two adjacent transistors.

[0131] After the second dummy gate 32 of the fin 20 is removed, the semiconductor layer in the exposed portion is processed to form an isolation segment to suppress current transmission in the exposed portion of the fin 20 after the second dummy gate 32 is removed. The following two methods can be used.

[0132] Method 1: Using one of plasma treatment, plasma implantation, and ion implantation processes, the portion of the first semiconductor layer 231 exposed after the second dummy gate 32 is removed is doped with inert atoms to change the conductivity of the portion of the first semiconductor layer 231 exposed after the second dummy gate 32 is removed, thereby forming an isolation segment 70.

[0133] For example, the conductivity of the first semiconductor layer 231 exposed after the second dummy gate 32 is removed can be changed by injecting at least one of H, O, N, Si, C, etc. into the first semiconductor layer 231 exposed after the second dummy gate 32 is removed, thereby forming the isolation segment 70.

[0134] For the portion of the first semiconductor layer 231 exposed after the second dummy gate 32 is removed, the entire first semiconductor layer 231 exposed after the second dummy gate 32 is removed may be processed, or a partial area of ​​the entire first semiconductor layer 231 exposed after the second dummy gate 32 is processed, as long as the purpose of suppressing the leakage current path can be achieved.

[0135] Method 2: Using an etching process, the portion of the first semiconductor layer 231 exposed after the second dummy gate 32 is removed is processed to change the morphology of the exposed portion of the first semiconductor layer 231 to change the conductivity of the first semiconductor layer 231 exposed after the second dummy gate 32 is removed, thereby forming an isolation segment 70.

[0136] The etching process includes at least one of dry etching, wet etching, and atomic layer etching.

[0137] Among them, changing the morphology of the portion of the first semiconductor layer 231 exposed after the second dummy gate 32 is removed may be to reduce the thickness t of at least a portion of the exposed first semiconductor layer 231. For example, an etching process is used to process the portion of the first semiconductor layer 231 exposed after the second dummy gate 32 is removed, so that the thickness t of the exposed portion of the first semiconductor layer 231 is reduced along the direction perpendicular to the gate length direction X or the thickness direction of the substrate 10. The extent of the thinning is based on the isolation effect that the current new process can provide. For example, it can be thinned by 30%-70% based on the thickness of the semiconductor layer, or relative to the thickness of the channel, for example, from the original 5-7nm to 2-3nm.

[0138] When the thickness t of the exposed portion of the first semiconductor layer 231 after the second dummy gate 32 is removed is reduced, the threshold voltage of the first semiconductor layer 231 with reduced thickness t is increased, so that the leakage current is greatly reduced, thereby suppressing the leakage current path.

[0139] Alternatively, an etching process may be used to process the fin 20 exposed after the second dummy gate 32 is removed, so that the shape of the exposed portion of the first semiconductor layer 231 is changed.

[0140] When a method is adopted to change the shape of the portion of the first semiconductor layer 231 exposed after the second dummy gate 32 is removed, for example, the exposed first semiconductor layer 231 can be etched into a dumbbell shape, or the exposed first semiconductor layer 231 can be broken along the gate length direction X to block the leakage current path, thereby achieving the suppression of the leakage current path.

[0141] Or it may be other forms of morphological changes, as long as such morphological changes can suppress the leakage current path, they belong to the protection scope of this application.

[0142] Based on the above S20 - S26 , the second dummy gate 32 can be removed by a simple process, and the first semiconductor layer 231 exposed after the second dummy gate 32 is removed is processed to form an isolation segment 70 for suppressing the leakage current path of two adjacent FinFETs.

[0143] After S26, a real gate may be formed through a Replacement Metal Gate (RMG) process.

[0144] Based on this, the method for preparing the integrated circuit device further includes:

[0145] S27, such as Fig.11a , Fig.11b , Fig.11c and Fig.11d As shown, the first dummy gate 31 is removed, and a gate dielectric layer 91 and a gate 92 are formed at the positions where the first dummy gate 31 and the second dummy gate 32 are removed, respectively.

[0146] Optionally, the gate dielectric layer 91 and the gate 92 are made by using a high-k dielectric layer + a metal gate (High-k metal gate, HKMG).

[0147] It should be noted that, since the first photosensitive layer 81 is formed after S24 and before S25 , the first photosensitive layer 81 should be removed before removing the first dummy gate 31 in S27 .

[0148] In addition, although a gate dielectric layer 91 and a gate 92 are also formed above the isolation segment 70 , the gate 92 does not have a normal channel turn-on characteristic.

[0149] Thus, after S27 , a FinFET is formed on both sides of the region where the isolation segment 70 is located. Each fin field effect transistor includes a source 51 , a drain 52 , a channel region 53 , a gate dielectric layer 91 and a gate 92 .

[0150] Based on this, a contact structure may be formed later on the source 51, drain 52, and gate 92 of the transistor (i.e., the source 51, drain 52, and gate 92 of the transistor are away from the side of the substrate 10). In addition, the interconnection between transistors may be realized through a metal wiring layer and a metal through-hole layer.

[0151] Taking the integrated circuit device including the stacked gate-all-around nanosheet transistor as an example, the embodiment of the present application provides another method for preparing the integrated circuit device, such as Fig.12 As shown, including:

[0152] S30, such as Fig.13a , Fig.13b , Fig.13c and Fig.13d As shown, a fin 20 protruding from the substrate 10 is formed on the substrate 10, and the fin 20 includes a plurality of first semiconductor layers 231 and a plurality of second semiconductor layers 232. The first semiconductor layers 231 and the second semiconductor layers 232 are alternately stacked along the thickness direction of the substrate 10, and the thickness direction t of the fin 20 is perpendicular to the gate length direction X and the thickness direction of the substrate 10.

[0153] Here, the "multi-layer" in the multi-layer first semiconductor layer 231 and the multi-layer second semiconductor layer 232 refers to at least two layers, and the specific number of layers can be reasonably set according to needs. The first layer formed is the first semiconductor layer 231 or the second semiconductor layer 232, and the last layer formed is the first semiconductor layer 231 or the second semiconductor layer 232. There is no limitation in the embodiments of the present application. Among them, the material of the first semiconductor layer 231 is different from the material of the second semiconductor layer 232.

[0154] Optionally, the fin 20 is formed on the upper surface of the substrate 10 by an epitaxial process.

[0155] Based on this, one way to form the fin 20 is: epitaxially grow multiple layers of the first semiconductor layer 231 and multiple layers of the second semiconductor layer 232 on the upper surface of the substrate 10, and the first semiconductor layer 231 and the second semiconductor layer 232 are alternately formed along the thickness direction of the substrate 10; then, etch the first semiconductor layer 231 and the second semiconductor layer 232 until the upper surface of the substrate 10 is exposed, and grooves are formed in the first semiconductor layer 231 and the second semiconductor layer 232, and the protruding portions between adjacent grooves form the fin 20.

[0156] Another way to form the fin 20 is to form an isolation layer on the upper surface of the substrate 10, etch the isolation layer until the upper surface of the substrate 10 is exposed, and form a groove in the isolation layer; on this basis, epitaxially form multiple first semiconductor layers 231 and multiple second semiconductor layers 232 in the groove, and the first semiconductor layers 231 and the second semiconductor layers 232 are alternately formed along the thickness direction of the substrate 10, so as to form the fin 20 in the groove. Afterwards, the isolation layer is etched back so that the surface of the isolation layer is lower than the top surface of the fin 20.

[0157] The material of the substrate 10 may be one of bulk silicon, silicon germanium, silicon carbide, SOI, and GOI; the material of the fin 20 may be one of silicon, silicon germanium, germanium, or silicon carbide.

[0158] S31, such as Fig.13a , Fig.13b , Fig.13c and Fig.13dAs shown, at least two first dummy gates 31 and at least one second dummy gate 32 are formed; at least two first dummy gates 31 and at least one second dummy gate 32 are arranged along the gate length direction X, and each second dummy gate 32 is located between two adjacent first dummy gates 31; the first dummy gate 31 and the second dummy gate 32 are both in contact with two opposite side surfaces and the top surface of the fin 20.

[0159] The first dummy gate 31 is used to occupy space and position for the real gate and gate dielectric layer to be formed subsequently, so the first dummy gate 31 needs to be removed later. As for the second dummy gate 32, its main purpose is to form the isolation segment 70 in the subsequent process, so the size of the second dummy gate 32 can be determined according to the size of the isolation segment 70.

[0160] The first dummy gate 31 and the second dummy gate 32 are made of the same material. The material of the first dummy gate 31 and the second dummy gate 32 can be at least one of polysilicon, amorphous silicon, and amorphous carbon.

[0161] The first dummy gate 31 and the second dummy gate 32 can be simultaneously formed by photolithography and etching processes.

[0162] S32, such as Fig.14a and Fig.14b As shown, along the gate length direction X, spacers 40 are formed on both sides of the first dummy gate 31 and the second dummy gate 32 .

[0163] The sidewall spacer 40 protects the first dummy gate 31 and the second dummy gate 32 , and enables the source and drain to be formed on both sides of the first dummy gate 31 in a self-aligned manner in the subsequent process of forming the source and the drain.

[0164] S33, such as Fig.14a and Fig.14b As shown, the fin 20 not covered by the first dummy gate 31 and the sidewalls 40 on both sides thereof, the second dummy gate 32 and the sidewalls 40 on both sides thereof are removed; and, as shown in FIG. Fig.14c As shown, the area of ​​the second semiconductor layer 232 of the retained fin 20 covered by the spacer 40 is processed to form an inner spacer 233 , and the remaining area of ​​the second semiconductor layer 232 not covered by the spacer 40 is used as a sacrificial layer 234 .

[0165] Optionally, the area covered by the sidewall 40 in the second semiconductor layer 232 of the retained fin 20 is processed by a selective oxidation process, so that the area covered by the sidewall 40 in the second semiconductor layer 232 of the retained fin 20 is oxidized, so that the oxidized part of the area forms the inner sidewall 233. The area covered by the sidewall 40 in the retained second semiconductor layer 232 is, that is, the area not covered by the first dummy gate 31 and the second dummy gate 32 in the retained second semiconductor layer 232.

[0166] S34, such as Fig.15a and Fig.15b As shown, a source 51 and a drain 52 are respectively formed on both sides of each first dummy gate 31 along the gate length direction X.

[0167] Those skilled in the art will appreciate that the source 51 and the drain 52 are formed in regions not covered by the first dummy gate 31 and the spacers 40 on both sides thereof and the second dummy gate 32 and the spacers on both sides thereof.

[0168] For the first dummy gate 31 on one side of the second dummy gate 32, when the source 51 and the drain 52 are formed on both sides of the first dummy gate 31 along the gate length direction X, one of the source 51 and the drain 52 is located between the first dummy gate 31 and the second dummy gate 32. Similarly, for the first dummy gate 31 on the other side of the second dummy gate 32, when the source 51 and the drain 52 are formed on both sides of the first dummy gate 31 along the gate length direction X, one of the source 51 and the drain 52 is located between the first dummy gate 31 and the second dummy gate 32.

[0169] From this we can see that Fig.15b As shown, the region of the fin 20 covered by the first dummy gate 31 forms a channel region 53. The projection of the channel region 53 on the substrate 10 overlaps with the projection of the first dummy gate 31 on the substrate 10.

[0170] After S34, the source 51, the drain 52, and the channel region 53 constituting the stacked ring-gate nanosheet transistor have been formed on one side of the second dummy gate 32 along the gate length direction X. Similarly, the source 51, the drain 52, and the channel region 53 constituting the stacked ring-gate nanosheet transistor have been formed on the other side of the second dummy gate 32 along the gate length direction X.

[0171] When forming an N-type stacked gate-all-around nanosheet transistor, SiGe containing B can be epitaxially grown on both sides of the first dummy gate 31 along the gate length direction X through a selective epitaxial process, thereby forming a source 51 and a drain 52. When forming a P-type stacked gate-all-around nanosheet transistor, Si containing P can be epitaxially grown on both sides of the first dummy gate 31 along the gate length direction X through a selective epitaxial process, thereby forming a source 51 and a drain 52.

[0172] It should be noted that Fig.15a It is illustrated that multiple sources 51 and multiple drains 52 are respectively formed on both sides of the first dummy gate 31 along the gate length direction X (the "multiple" here can be consistent with the number of fins 20), but the present application is not limited to this. The multiple sources 51 on one side of the first dummy gate 31 along the gate length direction X can be merged into one source 51, and the multiple drains 52 on the other side of the first dummy gate 31 along the gate length direction X can be merged into one drain 52.

[0173] S35, such as Fig.16a and Fig.16b As shown, an interlayer insulating layer 60 is formed, and the upper surface of the interlayer insulating layer 60 is flush with the upper surfaces of the first dummy gate 31 and the second dummy gate 32 .

[0174] Optionally, by depositing an insulating material, such as silicon oxide, silicon nitride, etc., and by using a CMP process, the upper surface of the interlayer insulating layer 60 is flush with the upper surfaces of the first dummy gate 31 and the second dummy gate 32, thereby exposing the first dummy gate 31 and the second dummy gate 32.

[0175] The upper surface of the interlayer insulating layer 60 is flush with the upper surfaces of the first dummy gate 31 and the second dummy gate 32 , that is, the upper surfaces of the first dummy gate 31 and the spacers 40 on both sides thereof, and the upper surfaces of the second dummy gate 32 and the spacers 40 on both sides thereof are exposed.

[0176] S36, such as Fig.17a , Fig.17b , Fig.17c and Fig.17d As shown, the first dummy gate 31 , the second dummy gate 32 and the sacrificial layer 234 are removed.

[0177] Since the material of the first semiconductor layer 231 is different from the material of the second semiconductor layer 232 , the sacrificial layer 234 may be removed by a wet removal process using flowing etching liquid.

[0178] S37, such as Fig.18a , Fig.18b and Fig.18c As shown, the exposed portion of the fin 20 after the second dummy gate 32 is removed is processed to form an isolation segment to inhibit current from being transmitted in the exposed portion of the fin 20 after the second dummy gate 32 is removed.

[0179] Since the sacrificial layer 234 has been removed in S36, only the first semiconductor layer 231 actually exists in the portion of the fin 20 exposed after the second dummy gate 32 is removed. Therefore, processing the portion of the fin 20 exposed after the second dummy gate 32 is removed is actually processing the portion of the first semiconductor layer 231 of the fin 20 exposed after the second dummy gate 32 is removed.

[0180] In order to avoid affecting the channel region 53 exposed after the first dummy gate 31 is removed when processing the exposed portion of the first semiconductor layer 231 in the fin 20 after the second dummy gate 32 is removed, after S36 and before S37, Fig.17e As shown, the second photosensitive layer 82 is formed by a photolithography process, and the second photosensitive layer 82 exposes the area after the second dummy gate 32 is removed. In this way, the first photosensitive layer 81 can protect the area after the first dummy gate 31 is removed.

[0181] Those skilled in the art understand that by processing the exposed portion of the first semiconductor layer 231 of the fin 20 after the second dummy gate 32 is removed, the conductivity of the first semiconductor layer 231 can be changed to reduce its conductivity or even completely insulate it. After the isolation segment 70 is formed, the isolation segment 70 can suppress the leakage current path between the two adjacent transistors.

[0182] Optionally, the exposed portion of the first semiconductor layer 231 of the fin 20 after the second dummy gate 32 is removed may be processed in the following two ways.

[0183] Method 1: using one of plasma treatment, plasma implantation and ion implantation, the exposed portion of the first semiconductor layer 231 of the fin 20 after the second dummy gate 32 is removed is doped with inert atoms to insulate the exposed portion of the first semiconductor layer 231 .

[0184] For example, the conductivity of the portion of the first semiconductor layer 231 of the fin 20 exposed after the second dummy gate 32 is removed can be changed by injecting H, O, N, Si, C, etc. into the portion of the first semiconductor layer 231 of the fin 20 exposed after the second dummy gate 32 is removed.

[0185] For the portion of the first semiconductor layer 231 of the fin 20 exposed after the second dummy gate 32 is removed, the entire portion of the first semiconductor layer 231 exposed after the second dummy gate 32 of the fin 20 can be processed, or a partial area of ​​the portion of the first semiconductor layer 231 of the fin 20 exposed after the second dummy gate 32 is removed can be processed, as long as the purpose of suppressing the leakage current path can be achieved.

[0186] Method 2: Use an etching process to process the portion of the first semiconductor layer 231 of the fin 20 exposed after the second dummy gate 32 is removed, so that the morphology of the portion of the first semiconductor layer 231 of the fin 20 exposed after the second dummy gate 32 is removed is changed, so as to change the conductivity of the portion of the first semiconductor layer 231 of the fin 20 exposed after the second dummy gate 32 is removed.

[0187] The etching process includes at least one of dry etching, wet etching, and atomic layer etching.

[0188] Among them, changing the morphology of the portion of the first semiconductor layer 231 of the fin 20 exposed after the second dummy gate 32 is removed can be achieved by thinning the thickness of at least a portion of the portion of the first semiconductor layer 231 of the fin 20 exposed after the second dummy gate 32 is removed, along a direction perpendicular to the gate length direction X or the thickness direction of the substrate 10, or by changing the shape of the portion of the first semiconductor layer 231 of the fin 20 exposed after the second dummy gate 32 is removed, or by other morphological changes. As long as such morphological changes can achieve the suppression of the leakage current path, they are within the protection scope of the present application.

[0189] When the thickness of the exposed portion of the first semiconductor layer 231 of the fin 20 after the second dummy gate 32 is removed is thinned, the threshold voltage of the thinned first semiconductor layer 231 of the fin 20 is increased, so that the leakage current is greatly reduced, thereby achieving the suppression of the leakage current path.

[0190] When a method is adopted to change the shape of the portion of the first semiconductor layer 231 of the fin 20 exposed after the second dummy gate 32 is removed, for example, the shape of the portion of the first semiconductor layer 231 of the fin 20 exposed after the second dummy gate 32 is removed can be etched into a dumbbell shape, or, along the gate length X, the portion of the first semiconductor layer 231 of the fin 20 exposed after the second dummy gate 32 is removed can be broken to block the leakage current path, thereby achieving the suppression of the leakage current path.

[0191] Based on the above S30 - S37 , the exposed portion of the first semiconductor layer 231 of the fin 20 after the second dummy gate 32 is removed can be processed by a simple process to suppress the leakage current path of two adjacent transistors.

[0192] After S37, the real gate can be formed through the RMG process.

[0193] Based on this, the method for preparing the integrated circuit device further includes:

[0194] S38, such as Fig.19a , Fig.19b , Fig.19c and Fig.19d As shown, the positions where the first dummy gate 31 and the second dummy gate 32 are removed form a gate dielectric layer 91 and a gate 92 ; a gate material layer 2351 and a gate dielectric material layer 2352 wrapped around the gate material layer 2351 are formed at the position of the sacrificial layer 234 as an auxiliary layer 235 .

[0195] The gate material layer 2351 and the gate dielectric material layer 2352 in the auxiliary layer 235 may be formed, for example, by an ALD (Atomic Layer Deposition) process.

[0196] Optionally, the gate dielectric layer 91 and the gate 92 are made by using a high-k dielectric layer + a metal gate (High-k metal gate, HKMG).

[0197] It should be noted that, since the second photosensitive layer 82 for protecting the first dummy gate 31 removal region is formed before processing the first semiconductor layer 231 , the second photosensitive layer 82 should be removed before forming the gate dielectric layer 91 and the gate 92 .

[0198] In addition, although a gate dielectric layer 91 and a gate 92 are also formed above the isolation segment 70 , the gate 92 does not have a normal channel turn-on characteristic.

[0199] Thus, after S38 , a stacked gate-all-around nanosheet transistor is formed on both sides of the region where the isolation segment 70 is located. Each stacked gate-all-around nanosheet transistor includes a source 51 , a drain 52 , a channel region 53 , a gate dielectric layer 91 and a gate 92 .

[0200] Based on this, a contact structure may be formed later on the source 51, drain 52, and gate 92 of the transistor (i.e., the source 51, drain 52, and gate 92 of the transistor are away from the side of the substrate 10). In addition, the interconnection between transistors may be realized through a metal wiring layer and a metal through-hole layer.

[0201] The embodiment of the present application also provides an integrated circuit device, such as Figures 11a to 11d or Figure 19a to Figure 19d As shown, it includes a substrate 10 and a fin 20 protruding from the substrate 10, and the integrated circuit device also includes two adjacent transistors 100, and the two adjacent transistors 100 use the two interval sections on the fin 20 as their respective channels 53; wherein, a portion of the fin 20 located between the two interval sections is processed to obtain an isolation section 70, and the isolation section 70 is used to suppress the current transfer between the two channels 53 of the two adjacent transistors 100.

[0202] Those skilled in the art should understand that the portion on the fin 20 is used as the channel 53 of the transistor 100, so the fin 20 must include a film layer structure made of semiconductor material. The fin 20 may be a semiconductor layer, or the fin 20 may include an alternately arranged stacked structure, some of which are semiconductor layers.

[0203] Figures 11a to 11d and Figure 19a to Figure 19dIt is only taken as an example that three fins 20 are included on the substrate 10, the three fins 20 form a group, and two transistors 100 share one fin 20. Multiple groups of fins 20 can be set as needed, and the number of fins 20 included in each group is not limited. Multiple transistors 100 can share one fin 20, and isolation sections 70 are provided between the channels 53 of any adjacent transistors 100 sharing the same fin 20.

[0204] Here, the isolation segment 70 is used to suppress the current transfer between the two channels 53 of the two transistors 100. The isolation segment 70 may include a break region to block the current transfer between the two channels 53 of the two transistors 100; or the isolation segment 70 may have a special structure that prevents the current between the two channels 53 of the two transistors 100 from being transferred through the isolation segment 70.

[0205] The integrated circuit device may be a microprocessor, a memory, a logic element, or other device made of an integrated circuit.

[0206] The integrated circuit device provided in the embodiment of the present application can suppress the current transfer between the two channels 53 of the two transistors 100 by processing a portion of the fin 20 located between the two interval sections through a simple process, has little impact on the structure and stress of the transistors 100 on both sides of the isolation section 70, introduces minimal variability in device characteristic parameters, occupies a smaller area resource of the isolation section 70, and does not require the design of special winding resources.

[0207] In some embodiments, Figures 11a to 11d As shown, the fin 20 includes a first semiconductor layer 231 , and the isolation segment 70 is doped with inert atoms.

[0208] That is, the isolation segment 70 is obtained by doping the first semiconductor layer 231 with inert atoms.

[0209] Of course, the doping here is only performed on the portion serving as the isolation segment 70 as needed, and the portion serving as the channel 53 is not doped.

[0210] The inert atoms may include, for example, at least one of hydrogen atoms, oxygen atoms, nitrogen atoms, carbon atoms, and silicon atoms.

[0211] In some embodiments, the fin 20 includes a first semiconductor layer 231 , and a thickness t of the first semiconductor layer 231 in the isolation segment 70 is smaller than a thickness t of the channels 53 of two adjacent transistors 100 .

[0212] That is, the thickness t of the isolation segment 70 in the first semiconductor layer 231 along the direction perpendicular to the distance between the source 51 and the drain 52 of the transistor 10 is smaller than the thickness t of the channel 53 of the two transistors 100 .

[0213] The shape of the isolation segment 70 may be, for example, a rectangle, and the thickness t of each portion of the isolation segment 70 is smaller than the thickness t of the channels 53 of the two transistors 100 .

[0214] The isolation segment 70 may also be in a dumbbell shape, and the thickness t of the middle portion of the isolation segment 70 is smaller than the thickness t of the channels 53 of the two transistors 100 .

[0215] The shape of the isolation segment 70 may also include a break portion, and the thickness t (thickness is 0) of the isolation segment 70 at the break portion is smaller than the thickness t of the channels 53 of the two transistors 100 .

[0216] Of course, the isolation segment 70 may also be in other shapes as long as it can suppress the current transfer between the two channels 53 of the two transistors 100 .

[0217] In some embodiments, Figure 19a to Figure 19d As shown, the fin 20 includes a first semiconductor layer 231 and an auxiliary layer 235 that are alternately arranged. The auxiliary layer 235 includes a gate material layer 2351 and a gate dielectric material layer 2352 wrapped around the gate material layer 2351 . The isolation segment 70 and the channel 53 are formed in the first semiconductor layer 231 .

[0218] Here, the portion of the first semiconductor layer 231 used for the isolation segment 70 is doped with inert atoms, and the portion of the first semiconductor layer 231 used for the channel 53 is not doped with inert atoms. The first semiconductor layer 231 and the auxiliary layer 235 are alternately arranged, and the auxiliary layer 235 only plays an auxiliary role and does not actually play the role of the isolation segment 70 or the channel 53. Therefore, when the fin 20 includes multiple layers of the first semiconductor layer 231 and multiple layers of the auxiliary layer 235, some segments in the multiple layers of the first semiconductor layer 231 are used as the isolation segment 70 or the channel 53.

[0219] The number of the first semiconductor layer 231 and the auxiliary layer 235 is not limited and can be set reasonably as needed. In addition, whether the layer closest to the substrate 10 and the layer farthest from the substrate 10 is the first semiconductor layer 231 or the auxiliary layer 235 is not limited here.

[0220] The above are only specific implementations of the present application, but the protection scope of the application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. An integrated circuit device, characterized in that: include: A substrate and a fin protruding from the substrate, wherein the integrated circuit device further comprises two adjacent transistors, and the two adjacent transistors use two interval sections on the fin as respective channels; Wherein, a portion of the fin located between the two segments of the interval is processed to obtain an isolation segment, and the isolation segment is used to suppress current transfer between two channels of the two adjacent transistors; The fin includes a first semiconductor layer, and the isolation segment is obtained by doping the first semiconductor layer between two segments of the fin located in the interval with inert atoms to insulate a portion of the first semiconductor layer; wherein the inert atoms will not be ionized in the silicon lattice of the fin.

2. The integrated circuit device according to claim 1, wherein: The fin includes a first semiconductor layer and an auxiliary layer which are alternately arranged, the auxiliary layer includes a gate material layer and a gate dielectric material layer wrapped outside the gate material layer, and the isolation segment and the channel are formed in the first semiconductor layer.

3. The integrated circuit device according to claim 1 or 2, characterized in that: The inert atoms include at least one of hydrogen atoms, oxygen atoms, nitrogen atoms, carbon atoms and silicon atoms.

4. A method for preparing an integrated circuit device, characterized in that: include: forming a fin on a substrate and protruding from the substrate; forming at least two first dummy gates and at least one second dummy gate; At least two of the first dummy gates and at least one of the second dummy gates are arranged along the gate length direction, and each of the second dummy gates is located between two adjacent first dummy gates; the first dummy gate and the second dummy gate are both in contact with two opposite side surfaces and a top surface of the fin; forming an interlayer insulating layer, wherein an upper surface of the interlayer insulating layer is flush with upper surfaces of the first dummy gate and the second dummy gate; At least the second dummy gate is removed, and a portion of the fin exposed after the second dummy gate is removed is processed to form an isolation segment, so as to suppress current transmission in the portion of the fin exposed after the second dummy gate is removed; The fin includes a first semiconductor layer, and the exposed portion of the fin after the second dummy gate is removed is processed to form an isolation segment, including: The first semiconductor layer between the exposed portions of the fin after the second dummy gate is removed is doped with inert atoms, so that a portion of the first semiconductor layer is insulated to form an isolation segment; wherein the inert atoms will not be ionized in the silicon lattice of the fin.

5. The method for preparing an integrated circuit device according to claim 4, characterized in that: The step of doping the first semiconductor layer between the exposed portions of the fin after the second dummy gate is removed with inert atoms so that a portion of the first semiconductor layer is insulated to form an isolation segment comprises: A process selected from the group consisting of plasma treatment, plasma implantation and ion implantation is used to dope the exposed portion of the first semiconductor layer after the second dummy gate is removed with inert atoms, so as to insulate the exposed portion of the first semiconductor layer.

6. The method for preparing an integrated circuit device according to claim 4, wherein: The inert atoms include at least one of hydrogen atoms, oxygen atoms, nitrogen atoms, carbon atoms and silicon atoms.

7. The method for preparing an integrated circuit device according to any one of claims 4 to 6, characterized in that: The fin is composed of a layer of the first semiconductor layer; At least the second dummy gate is removed, and a portion of the fin exposed after the second dummy gate is removed is processed to suppress current transmission in the portion of the fin exposed after the second dummy gate is removed to form an isolation segment, including: The second dummy gate is removed, and a portion of the fin exposed after the second dummy gate is removed is processed to suppress current transmission in the portion of the fin exposed after the second dummy gate is removed, so as to form the isolation segment; After forming the isolation segment, the method for preparing the integrated circuit device further includes: removing the first dummy gate, and forming a gate dielectric layer and a gate at the positions where the first dummy gate and the second dummy gate are removed, respectively.

8. The method for preparing an integrated circuit device according to any one of claims 4 to 6, characterized in that: The fin comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers, wherein the first semiconductor layers and the second semiconductor layers are alternately arranged along a thickness direction of the substrate; Before forming the interlayer insulating layer, the method for preparing the integrated circuit device further comprises: forming sidewalls on both sides of the first dummy gate and the second dummy gate along the gate length direction; Removing the fins that are not covered by the first dummy gate and the sidewalls on both sides thereof, and the second dummy gate and the sidewalls on both sides thereof; The second semiconductor layer of the retained fin is processed in the area covered by the sidewall to form an inner sidewall, and the remaining area not covered by the sidewall is used as a sacrificial layer; At least the second dummy gate is removed, and a portion of the fin exposed after the second dummy gate is removed is processed to suppress current transmission in the portion of the fin exposed after the second dummy gate is removed to form an isolation segment, including: The first dummy gate, the second dummy gate and the sacrificial layer are removed, and a portion of the fin exposed after the second dummy gate is removed is processed to suppress current transmission in the portion of the fin exposed after the second dummy gate is removed, so as to form the isolation segment; After forming the isolation segment, the method for preparing the integrated circuit device also includes: forming a gate dielectric layer and a gate at the position where the first dummy gate and the second dummy gate are removed; forming a gate material layer and a gate dielectric material layer wrapped around the gate material at the position of the sacrificial layer as an auxiliary layer.

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