Integrated circuit device and method for manufacturing the same

Abstract

An integrated circuit device (100) comprises a semiconductor substrate (101) having a resistivity of at least 100 Ω.cm. An electrically insulating layer (102) is in contact with the semiconductor substrate (101). The electrically insulating layer (102) is susceptible to inducing a parasitic surface conductive layer in the semiconductor substrate (101) that is in contact with the electrically insulating layer (102). A circuit (103) is located on the electrically insulating layer. The circuit (103) comprises a portion (105) capable of inducing an electric field in the semiconductor substrate. The integrated circuit device (100) comprises a depletion inducing junction (108, 109), at least a portion of which is contained in the semiconductor substrate (101). The depletion inducing junction (108, 109) is capable of autonomously inducing a depletion region in the semiconductor substrate (101), the depletion region being in contact with a portion of the electrically insulating layer (102) located between two portions (104, 105) of the circuit (103).

Description

Technical Field

[0001] One aspect of the present invention relates to an integrated circuit device, the integrated circuit device comprising a semiconductor substrate and an electrically insulating layer in contact with the semiconductor substrate. The integrated circuit device may include circuits adapted to operate at relatively high frequencies (e.g., frequencies above 100 MHz). Another aspect of the present invention relates to a method of manufacturing an integrated circuit device. Background Art

[0002] An article entitled "Fabrication and Characterization of High Resistivity SOI Wafers for RF Applications" by Lederer et al., published in ECS Trans. 2008, Vol. 16, No. 8, pp. 165-174, provides an overview of the problems associated with parasitic surface conduction in oxidized high-resistivity silicon wafers (e.g., high-resistivity silicon on insulator). In such wafers, parasitic surface conduction is associated with the presence of free carriers at the substrate surface. Most of these problems are suppressed when the substrate surface is passivated with a trap-rich layer of a material such as polysilicon.

[0003] The technique for making substrate-passivated high-resistivity silicon on insulator wafers consists in depositing a 300nm silicon layer on a high-resistivity silicon substrate by low-pressure chemical vapor deposition (LPCVD) at 525°C. At such low temperatures, silicon is deposited in its amorphous form and is therefore thermodynamically unstable. The top silicon layer can then be recrystallized into polysilicon by a rapid thermal annealing at 950°C for 15s. The passivated high-resistivity silicon on an insulator substrate is then obtained by using conventional bonding operations and the so-called Smart-Cut process, except in the case where bonding is performed between an oxidized donor wafer and the passivated high-resistivity substrate.

[0004] Patent publication US20150228714A1 describes a radio frequency integrated circuit having a silicon-on-insulator substrate, the silicon-on-insulator substrate including a buried oxide layer disposed above the silicon substrate. The silicon-on-insulator substrate has a silicon layer disposed above the buried oxide layer. The integrated circuit includes a transistor disposed on the silicon layer, and a guard ring surrounding the transistor on the silicon layer in the silicon-on-insulator substrate. A depletion region on the silicon substrate corresponding to an area surrounding the transistor is defined by applying a voltage to the guard ring. With this configuration, isolation of radio frequency transmission lines on the silicon-on-insulator substrate is also possible. Summary of the invention

[0005] There is a need for a solution to counter parasitic surface conduction that better meets at least one of the following criteria: moderate cost, ease of integrated circuit fabrication, and compatibility with different integrated circuit fabrication technologies.

[0006] According to one aspect of the present invention as defined in solution 1, there is provided an integrated circuit device comprising:

[0007] A semiconductor substrate having a resistivity of at least 100 Ω.cm;

[0008] an electrically insulating layer in contact with the semiconductor substrate, the electrically insulating layer being susceptible to inducing a parasitic surface conductive layer in the semiconductor substrate in contact with the electrically insulating layer; and

[0009] a circuit located on the electrically insulating layer,

[0010] The integrated circuit device comprises a depletion inducing junction, at least a portion of which is contained in the semiconductor substrate, and the depletion inducing junction is suitable for autonomously inducing a depletion region in the semiconductor substrate, the depletion region being connected to a portion of the electrical insulating layer located between two portions of the circuit.

[0011] Compared to the techniques described in the aforementioned articles, which include fabricating substrate-passivated high-resistivity silicon on an insulator, the depletion-inducing junction as defined above can be realized at a lower cost. Compared to the techniques described in the aforementioned patent publications, which require a specific design of the guard ring and the fabrication of the guard ring, the depletion-inducing junction as defined above can be realized at a lower cost. Therefore, the integrated circuit device as defined above also allows for greater versatility in design and fabrication.

[0012] Furthermore, the depletion-inducing junction may be compatible with techniques that utilize a buried oxide layer to define the back gate terminal of a transistor to improve channel control and transistor performance. In contrast, in the techniques described in the above-mentioned article, the definition of the back gate may be very difficult.

[0013] Another advantage is that the depletion-induced junction is resistant to thermal variations during the manufacturing of integrated circuits. In contrast, in the technology described in the above article, there is a risk of partial recrystallization of the polysilicon trap-rich layer. This reduces the number of traps and thus degrades the electrical properties of the semiconductor substrate.

[0014] According to another aspect of the present invention as defined in claim 10, a semiconductor wafer is provided. The semiconductor wafer is suitable for manufacturing the integrated circuit device as described above.

[0015] According to yet another aspect of the present invention as defined in claim 11, there is provided a method for manufacturing the integrated circuit device as described above.

[0016] For illustrative purposes, some embodiments of the present invention are described in detail with reference to the accompanying drawings. In this description, additional features will appear and its advantages will become apparent. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a schematic cross-sectional view of a first embodiment of an integrated circuit device including a plurality of depletion inducing junctions.

[0018] Figure 2 is a schematic semi-transparent top view of a first embodiment of an integrated circuit device including a plurality of depletion inducing junctions.

[0019] Figure 3 : is a graph plotting the carrier concentration in the upper substrate layer according to the horizontal position in the upper substrate layer in the first embodiment of the integrated circuit device.

[0020] Figure 4 is a graph plotting the resistivity in the upper substrate layer as a function of the horizontal position in the upper substrate layer in the first embodiment of the integrated circuit device.

[0021] Figure 5 is a schematic cross-sectional view of a second embodiment of an integrated circuit device including a plurality of depletion inducing junctions.

[0022] Figure 6 is a schematic cross-sectional view of a third embodiment of an integrated circuit device including a plurality of depletion inducing junctions.

[0023] Figure 7 is a schematic semi-transparent top view of a fourth embodiment of an integrated circuit device including a plurality of depletion inducing junctions.

[0024] Figure 8 is a schematic cross-sectional view of a fourth embodiment of an integrated circuit device including a plurality of depletion inducing junctions.

[0025] Fig. 9 is a schematic semi-transparent top view of an array of multiple depletion inducing junctions for use in inductors in integrated circuit devices.

[0026] Fig.10 is a schematic semi-transparent top view of an array of multiple depletion-inducing junctions used in two circuits in an integrated circuit device.

[0027] Fig.11 is a schematic semi-transparent top view of a checkerboard of multiple depletion-inducing junctions used in a variety of circuits in integrated circuit devices.

[0028] Fig.12 is a schematic cross-sectional view of a fifth embodiment of an integrated circuit device including a plurality of depletion inducing junctions.

[0029] Fig.13 is a schematic cross-sectional view of an integrated circuit device arranged to generate a depletion region by means of an electrical conductor receiving a bias voltage. DETAILED DESCRIPTION

[0030] Figure 1 and Figure 2 An integrated circuit arrangement 100 is schematically shown. Figure 1 A schematic cross-sectional view of an integrated circuit device 100 is provided. Figure 2 A semi-transparent top view of the integrated circuit device 100 is provided.

[0031] The integrated circuit device includes a semiconductor substrate 101, an electrical insulating layer 102 in contact with the semiconductor substrate, and a circuit 103 located on the electrical insulating layer 102. The semiconductor substrate 101 may contain, for example, silicon, germanium, gallium arsenide, or any other type of material or component in which a circuit can be formed. In the following, it is assumed that the semiconductor substrate 101 substantially contains silicon. The electrical insulating layer 102 may substantially contain, for example, silicon oxide.

[0032] The semiconductor substrate 101 has a relatively high resistivity. For example, the semiconductor substrate 101 may have a resistivity of at least 100 Ω.cm. As another example, the semiconductor substrate 101 may have a resistivity of at least 1 kΩ.cm. The electrical insulating layer 102 is prone to induce a parasitic surface conductive layer in the semiconductor substrate 101 that is connected to the electrical insulating layer 102. This is discussed in the above-mentioned article entitled "Fabrication and Characterization of High Resistivity SOI Wafers for RF Applications".

[0033] In this embodiment, the circuit 103 includes a coplanar waveguide having three conductive strips 104, 105, 106. One conductive strip 105 may constitute a signal line; the other two conductive strips 104, 106 may constitute a signal ground line. The conductive strip 105 constituting the signal line is capable of inducing an electric field in the semiconductor substrate 101 when a signal is present on the signal line. In the case where the above-mentioned parasitic surface conductive layer is present in the semiconductor substrate 101, this constitutes a parasitic conductive path, through which a part of the signal may reach the two conductive strips 104, 106 constituting the signal ground line. This may potentially affect the performance of the coplanar waveguide.

[0034] The integrated circuit device 100 includes a plurality of pairs of doped regions 107 in a semiconductor substrate 101 near an electrical insulating layer 102. In a pair of doped regions 108 and 109, one doped region and the other doped region are adjacent to each other and have opposite polarities. That is, one doped region 108 may be P-type, while the other doped region 109 may be N-type.

[0035] The multiple pairs of doped regions 107 constitute multiple depletion inducing junctions. More specifically, a pair of doped regions 108, 109 constitutes a depletion inducing junction that induces a depletion region extending from the electrical insulating layer 102 into the semiconductor substrate 101. At least one depletion region is located between the conductive strip 105 constituting the signal line and each of the two conductive strips 104, 106 constituting the signal ground line. That is, the depletion inducing junction autonomously induces a depletion region in the semiconductor substrate 101 that is in contact with a portion of the electrical insulating layer 102 that is located between two portions of the circuit 103. The term "autonomously" refers to the fact that the depletion inducing junction does not need to receive a bias voltage to induce a depletion region in the semiconductor substrate 101.

[0036] Figure 3 1 is a graph showing the carrier concentration in the upper layer of the semiconductor substrate 101 in which there are multiple pairs of doped regions 107. The graph includes a horizontal axis representing the horizontal position in the upper layer. The graph includes a vertical axis representing the free charge carrier concentration, which is expressed as the number of carriers per cubic centimeter. The graph includes two curves. The solid curve represents N-type carriers, i.e., electrons, and the dashed curve represents P-type carriers, i.e., holes. Figure 3 The graph of φ shows a depletion region 301 between the P-doped region 108 and the N-doped region 109 .

[0037] Figure 4 is a graph showing the resistivity in the upper layer of the semiconductor substrate 101 in which a plurality of pairs of doping regions 107 exist. The graph includes similar Figure 3 The graph includes a horizontal axis representing the horizontal position in the upper layer. The graph includes a vertical axis representing the resistivity, which is expressed in Ω.cm.

[0038] Figure 4 The graph of shows that the resistivity is relatively high in the depletion region 301. The depletion region 301 extending from the electrically insulating layer 102 into the semiconductor substrate 101 thus counteracts the parasitic surface conduction. Figure 1 , a depletion region 301 in the semiconductor substrate 101 is connected to a portion of the electrically insulating layer 102 that may be located between two portions of the circuit 103 .

[0039] Figure 5 The integrated circuit device 500 is schematically shown. Figure 1An alternative to the integrated circuit device 100 shown. Figure 5 A schematic cross-sectional view of the integrated circuit device 500 is provided. This embodiment can be based on Figure 1 and Figure 2 The embodiment shown is obtained by omitting one doped region 109 in each of the pairs of regions 108, 109. The polarity of the remaining doped region 109 is opposite to the polarity of the free charge carriers in the adjacent region where the bulk of the semiconductor substrate 101 meets the electrically insulating layer 102. For example, it is assumed that the free charge carriers are electrons. In that case, Figure 5 The doped regions shown in may be of P-type.

[0040] Figure 6 The integrated circuit device 600 is schematically shown. Figure 1 and Figure 5 An alternative to the integrated circuit arrangements 100 , 500 shown. Figure 6 A schematic cross-sectional view of the integrated circuit device is provided. This embodiment can be based on Figure 1 and Figure 2 The embodiment shown is obtained by adding a relatively thin electrically insulating layer 601 to the integrated circuit device 100. The relatively thin electrically insulating layer 601 is in contact with the main body of the semiconductor substrate 101. The thickness of the relatively thin electrically insulating layer 601 may be less than 100 nm. In this embodiment, the plurality of pairs of doped regions 103 constituting the plurality of depletion induced junctions are at least partially contained in a semiconductor layer 602, which is in contact with the relatively thin electrically insulating layer 601 on the side opposite to the side where the relatively thin electrically insulating layer 601 is in contact with the semiconductor substrate layer 101.

[0041] Figure 7 and Figure 8 The integrated circuit device 700 is schematically shown. Figure 1 , Figure 5 and Figure 6 An alternative to the integrated circuit arrangements 100 , 500 , 600 shown. Figure 7 A schematic semi-transparent top view of the integrated circuit device 700 is provided. Figure 8 A schematic cross-sectional view of the integrated circuit device 700 is provided. This embodiment can be based on Figure 1 and Figure 2The embodiment shown is obtained by adding a set of electrical contacts 701, through which a bias voltage can be applied to multiple pairs of doped regions 108, 109, which form multiple depletion inducing junctions. The multiple pairs of doped regions 108, 109 can induce depletion regions according to the bias voltage. This can improve the electrical linearity of the upper layer of the semiconductor substrate 101, and thus prevent signal distortion in the circuit 103.

[0042] Fig. 9 The diagram schematically shows a plurality of depletion inducing junctions 901 in an array of inductors 901 used in an integrated circuit device. Fig. 9 A schematic semi-transparent top view of an array of multiple depletion inducing junctions 901 applied to an inductor 902 is provided. The depletion inducing junctions 901 are arranged in a ring-like manner around a portion of the inductor 901 capable of inducing an electric field in a semiconductor substrate on which the inductor 901 is formed.

[0043] Fig.10 An array of multiple depletion inducing junctions 1001 applied to two circuit sections 1002 , 1003 is schematically shown. Fig.10 A schematic semi-transparent top view of an array of multiple depletion inducing junctions 1001 applied to two circuit portions 1002, 1003 is provided. The multiple depletion inducing junctions 1001 are arranged in a ring-like manner around the portions 1002, 1003 of the circuit capable of inducing an electric field in a semiconductor substrate on which the circuit portions 1002, 1003 are formed.

[0044] Fig.11 The diagram schematically shows a checkerboard-shaped plurality of depletion inducing junctions 1101 applied to various circuits in an integrated circuit device. Fig.11 A schematic semi-transparent top view of a checkerboard-shaped plurality of depletion inducing junctions 1101 is provided for application in a variety of circuits.

[0045] Fig.12 The integrated circuit device 1200 is schematically shown. Figure 1 , Figure 5 , Figure 6 , Figure 7 and Figure 8 An alternative to the integrated circuit arrangements 100, 500, 600, 700 shown. Fig.12 A schematic cross-sectional view of the integrated circuit device 1200 is provided.

[0046] The integrated circuit device 1200 includes a semiconductor substrate 1201, an electrical insulation layer 1202 in contact with the semiconductor substrate 1201, and a circuit 1203 located on the electrical insulation layer 1202. An electrical conductor 1204 traverses the electrical insulation layer 1202 and contacts the semiconductor substrate 1201. This forms a Schottky contact, which allows a depletion region 1205 to extend to the contact. This cancels out parasitic surface conduction between two parts 1206, 1207 of the circuit 1203.

[0047] Fig.13 There is schematically shown an integrated circuit device arranged to generate a depletion region by means of an electrical conductor receiving a bias voltage, rather than by means of a depletion inducing junction as described above. Fig.13 A schematic cross-sectional view of an integrated circuit device 1300 is provided. The integrated circuit device 1300 includes a semiconductor substrate 1301 , an electrical insulation layer 1302 in contact with the semiconductor substrate 1301 , and a circuit 1303 located on the electrical insulation layer 1302 .

[0048] The electrical conductor 1304 is located on or in the electrically insulating layer 1302. The electrical conductor 1304 receives a bias voltage that induces free charge carriers in a region extending from the electrically insulating layer 1302 into the semiconductor substrate 1301. Thus, the polarity of the induced free charge carriers is opposite to the polarity of the free charge carriers in an adjacent region where the bulk of the semiconductor substrate 1301 meets the electrically insulating layer 1302. This creates a depletion region 1305 that cancels out parasitic surface conduction between the two portions 1306, 1307 of the circuit 1303.

[0049] The semiconductor wafer may be suitable for manufacturing an integrated circuit device according to any of the embodiments described above. The semiconductor wafer may include a semiconductor substrate, an electrically insulating layer in contact with the semiconductor substrate, and a semiconductor layer located on the electrically insulating layer, in which a circuit may be formed. The semiconductor substrate includes a depletion inducing junction suitable for autonomously inducing a depletion region in the semiconductor substrate, the depletion region being in contact with a portion of the electrically insulating layer.

[0050] In the methods of manufacturing integrated circuit devices according to some embodiments that have been described, the depletion inducing junction may be formed using process steps that are also used to form the circuit.

[0051] In another method of manufacturing an integrated circuit device according to some embodiments that has been described, a depletion inducing junction is at least partially formed using at least one of the following techniques: deep implantation and diffusion.

[0052] Notice

[0053] The embodiments described above with reference to the accompanying drawings are given by way of illustration. The present invention can be implemented in many different ways. To illustrate this, some alternatives are briefly described.

[0054] The present invention may be applied to various types of products or methods involving integrated circuits on semiconductor substrates.

[0055] The term "circuit" should be understood in a broad sense. The term may include any entity having a function involving electrical quantities, such as micro-electromechanical systems (MEMS), transmission lines, electrical connections.

[0056] Generally, there are many different ways to implement the present invention, and different embodiments may have different topologies. In any given topology, a single entity may perform several functions, or several entities may jointly perform a function. In this respect, the accompanying drawings are very schematic.

[0057] The above description shows that the embodiments described with reference to the accompanying drawings illustrate the present invention, rather than limiting it. The present invention can be implemented in a variety of alternative ways within the scope of the appended claims. All changes that fall within the equivalent meaning and scope of the claims should be included within their scope. Any reference signs in the claims should not be interpreted as limiting the claims. The verb "comprise" in the claims does not exclude the presence of other elements or steps than those listed in the claims. This also applies to similar verbs such as "comprise" and "have". An element mentioned in the singular in a claim relating to a product does not exclude that the product may include multiple such elements. Similarly, a step mentioned in the singular in a claim relating to a method does not exclude that the method may include multiple such steps. The fact that each dependent claim defines each additional feature does not exclude a combination of additional features other than those reflected in the claim.

Claims

1. An integrated circuit device (100), comprising: A semiconductor substrate (101) having a resistivity of at least 100 Ω.cm; An electrical insulating layer (102) in contact with the semiconductor substrate, the electrical insulating layer being susceptible to inducing a parasitic surface conductive layer in contact with the electrical insulating layer in the semiconductor substrate; as well as A circuit (103) is located on the electrical insulating layer, The integrated circuit device comprises a plurality of depletion inducing junctions (107), the depletion inducing junctions (107) being at least partially contained in the semiconductor substrate, the plurality of depletion inducing junctions being suitable for autonomously inducing a plurality of depletion regions (301) in contact with the electrical insulating layer in the semiconductor substrate, wherein the depletion inducing junctions are arranged in one of the following manners: an array manner and a checkerboard manner, and wherein at least some of the plurality of depletion inducing junctions are in contact with a portion of the electrical insulating layer located between two portions (104, 105) of the circuit.

2. The integrated circuit device according to claim 1, wherein: The depletion induced junction (108, 109) comprises a doped region (108) located in the semiconductor substrate (101) adjacent to the electrically insulating layer (102), the polarity of the doped region being opposite to the polarity of free charge carriers in an adjacent region where the main body of the semiconductor substrate meets the electrically insulating layer.

3. The integrated circuit device according to claim 2, wherein: The depletion inducing junction (108, 109) comprises another doped region (109) located in the semiconductor substrate (101) close to the electrical insulating layer (102), wherein the one doped region and the other doped region are connected to each other and have opposite polarities.

4. The integrated circuit device according to claim 1, wherein: The depletion-inducing junction includes an electrical conductor (1204) that traverses the electrical insulating layer (1202) and contacts the semiconductor substrate (1201) to form a Schottky contact.

5. The integrated circuit arrangement according to any of claims 1 to 4, comprising a set of electrical contacts (701) through which a bias voltage can be applied to at least some of the plurality of depletion inducing junctions.

6. The integrated circuit device according to any one of claims 1 to 4, wherein: At least some of the plurality of depletion inducing junctions arranged in an array-like manner are further disposed in a loop manner around at least one of the two portions of the circuit.

7. A semiconductor wafer, wherein the semiconductor wafer is suitable for manufacturing an integrated circuit device (100) according to any one of claims 1 to 6, the semiconductor wafer comprising: A semiconductor substrate having a resistivity of at least 100 Ω.cm; an electrically insulating layer in contact with the semiconductor substrate, the electrically insulating layer being susceptible to inducing a parasitic surface conductive layer in the semiconductor substrate in contact with the electrically insulating layer; as well as a semiconductor layer, located on the electrical insulating layer, in which a circuit can be formed, The semiconductor wafer comprises a plurality of depletion inducing junctions (107), the depletion inducing junctions (107) being at least partially contained in the semiconductor substrate, the plurality of depletion inducing junctions being suitable for autonomously inducing a plurality of depletion regions (301) connected to the electrical insulating layer in the semiconductor substrate, wherein the depletion inducing junctions are arranged in one of the following manners: an array manner and a checkerboard manner.

8. A method for manufacturing an integrated circuit device (100) according to any one of claims 1 to 6, the method comprising the following steps: A plurality of depletion inducing junctions (107) are formed, the depletion inducing junctions (107) being at least partially located in a semiconductor substrate having a resistivity of at least 100 Ω.cm, the depletion inducing junctions being formed to autonomously induce a plurality of depletion regions (301) in the semiconductor substrate, the depletion regions (301) being in contact with a portion of an electrical insulating layer, the electrical insulating layer being susceptible to inducing a parasitic surface conductive layer in contact with the electrical insulating layer in the semiconductor substrate, wherein the depletion inducing junctions are formed so that they are arranged in one of the following manners: an array-like manner and a checkerboard-like manner.

9. The manufacturing method according to claim 8, wherein: The depletion inducing junction is formed using the same process steps used to form the circuit.

10. The manufacturing method according to claim 8, wherein: The depletion inducing junction is at least partially formed using at least one of the following techniques: implantation and diffusion.

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