Dicing tape and dicing die bonding film

Abstract

The present invention relates to a dicing tape and a dicing die bonding film. The dicing tape of the present invention has an adhesive layer laminated on a base material layer, and the tensile storage modulus of the dicing tape at -5°C is 100 MPa or more.

Description

[0001] Cross-references of related applications

[0002] This application claims the priority of Japanese Patent Application No. 2019-110200, which is incorporated by reference into the description of the present application specification. Technical Field

[0003] The present invention relates to a dicing tape and a dicing die-bonding film. Background Art

[0004] As is well known, conventionally, in the manufacture of semiconductor devices, a dicing tape or a dicing die-bonding film is used to obtain a semiconductor chip for die bonding.

[0005] The dicing tape is configured by laminating an adhesive layer on a base material layer, and the dicing die-bonding film is configured by laminating a die-bonding layer on the adhesive layer of the dicing tape in a releasable manner.

[0006] It is also known that as a method for obtaining a semiconductor chip (Die) for chip bonding using the above-mentioned cutting chip bonding film, a method having the following steps is adopted: a half-cutting step, in which a groove is formed on the semiconductor wafer in order to process the semiconductor wafer into a chip (Die) by cutting, and the semiconductor wafer is then ground to make the thickness thinner; a back grinding step, in which the semiconductor wafer after the half-cutting step is ground to make the thickness thinner; a mounting step, in which one surface of the semiconductor wafer after the back grinding step (for example, the surface on the opposite side to the circuit surface) is attached to the chip bonding layer to fix the semiconductor wafer to the cutting tape; an expansion step, in which the interval between the semiconductor chips processed by the half-cutting is enlarged; a cut maintaining step, in which the interval between the semiconductor chips is maintained; a picking step, in which the chip bonding layer and the adhesive layer are peeled off to take out the semiconductor chip in a state with the chip bonding layer attached; and a chip bonding step, in which the semiconductor chip in a state with the chip bonding layer attached is bonded to an adherend (for example, a mounting substrate, etc.).

[0007] In the cut maintaining step, hot air (eg, 100 to 130° C.) is directed toward the dicing tape to heat shrink the tape and then cool and solidify the tape, thereby maintaining the distance (cut) between adjacent semiconductor chips to be cut.

[0008] Furthermore, in the expansion step, the die bonding layer is cut into a size corresponding to the size of the plurality of singulated semiconductor chips.

[0009] In a method for obtaining a semiconductor chip for chip bonding using a cutting chip bonding film as described above, patent document 1 discloses: by using a cutting tape having specific physical properties (a cutting tape having an initial elastic modulus of 200 MPa or more and 380 MPa or less at -10°C and a Tanδ (loss modulus / storage modulus) of 0.080 or more and 0.3 or less at -10°C), and carrying out the above-mentioned expansion process under low temperature conditions of -15 to 5°C, the cutting properties (for example, ease of cutting, uniform cutting properties, etc.) from the above-mentioned semiconductor wafer to multiple semiconductor chips in the above-mentioned expansion process can be improved.

[0010] Prior art literature

[0011] Patent Literature

[0012] Patent Document 1: Japanese Patent Application Publication No. 2015-185591 Summary of the invention

[0013] Problem that the invention aims to solve

[0014] As described in Patent Document 1, by using a dicing tape having specific properties and performing the expansion process under the low temperature conditions, the cutting properties of the semiconductor wafer are improved. However, when the semiconductor wafer is cut into a plurality of semiconductor chips by expansion under low temperature conditions using a dicing tape and a dicing chip bonding film, it is necessary to further improve the cutting properties of the semiconductor wafer.

[0015] In particular, when a semiconductor wafer is cut into a plurality of small semiconductor chips (for example, semiconductor chips having a size of 12 mm in length×4 mm in width×0.055 mm in thickness), it is necessary to further improve the cutting property of the semiconductor wafer.

[0016] Therefore, an object of the present invention is to provide a dicing tape and a dicing die-bonding film capable of further improving the cutting performance of a semiconductor wafer into a plurality of semiconductor chips based on expansion under low temperature conditions.

[0017] Solutions for solving problems

[0018] The dicing tape of the present invention has an adhesive layer laminated on a base material layer.

[0019] The dicing tape has a tensile storage modulus at -5°C of 100 MPa or more.

[0020] In the above-mentioned cutting tape, preferably:

[0021] The 30% tensile stress at -5°C is 5.5 N / 10 mm or more.

[0022] In the above-mentioned cutting tape, preferably:

[0023] The 30% tensile stress at room temperature is 3.2 N / 10 mm or more.

[0024] In the above-mentioned cutting tape, preferably:

[0025] The ratio of the 30% tensile stress at -5°C to the 30% tensile stress at room temperature is 1.7 or more.

[0026] The dicing die-bonding film of the present invention comprises:

[0027] A dicing tape having an adhesive layer laminated on a base layer, and

[0028] a die bonding layer laminated on the adhesive layer of the dicing tape,

[0029] The dicing die-bonding film has a tensile storage modulus at -5°C of 100 MPa or more. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 : A cross-sectional view showing the structure of a dicing tape according to one embodiment of the present invention.

[0031] Figure 2 : A cross-sectional view showing the structure of a dicing die-bonding film according to one embodiment of the present invention.

[0032] Figure 3A : A cross-sectional view schematically showing a state of half-cutting processing in a method for manufacturing a semiconductor integrated circuit.

[0033] Figure 3B : A cross-sectional view schematically showing a state of half-cutting processing in a method for manufacturing a semiconductor integrated circuit.

[0034] Figure 3C : A cross-sectional view schematically showing a state of backside grinding processing in a method for manufacturing a semiconductor integrated circuit.

[0035] Figure 3D : A cross-sectional view schematically showing a state of backside grinding processing in a method for manufacturing a semiconductor integrated circuit.

[0036] Figure 4A : A cross-sectional view schematically showing the state of a mounting process in a method for manufacturing a semiconductor integrated circuit.

[0037] Figure 4B : A cross-sectional view schematically showing the state of a mounting process in a method for manufacturing a semiconductor integrated circuit.

[0038] Figure 5A : A cross-sectional view schematically showing the state of a low-temperature expansion process in a method for manufacturing a semiconductor integrated circuit.

[0039] Figure 5B : A cross-sectional view schematically showing the state of a low-temperature expansion process in a method for manufacturing a semiconductor integrated circuit.

[0040] Figure 5C : A cross-sectional view schematically showing the state of a low-temperature expansion process in a method for manufacturing a semiconductor integrated circuit.

[0041] Fig. 6A : A cross-sectional view schematically showing the state of an expansion process at room temperature in a method for manufacturing a semiconductor integrated circuit.

[0042] Figure 6B : A cross-sectional view schematically showing the state of an expansion process at room temperature in a method for manufacturing a semiconductor integrated circuit.

[0043] Figure 7 : A cross-sectional view schematically showing the state of a cut maintaining step in a method for manufacturing a semiconductor integrated circuit.

[0044] Figure 8 : A cross-sectional view schematically showing the state of a pickup process in a method for manufacturing a semiconductor integrated circuit.

[0045] Description of Reference Numerals

[0046] 1. Substrate layer

[0047] 2 Adhesive layer

[0048] 3. Chip bonding layer

[0049] 10 Cutting tape

[0050] 20 Cutting die bonding film

[0051] 1a1st resin layer

[0052] 1b Second resin layer

[0053] 1c The third resin layer

[0054] G Back Grinding Tape

[0055] H retainer

[0056] J Suction fixture

[0057] P pin component

[0058] R cutting ring

[0059] T Wafer Processing Tape

[0060] U lifting member

[0061] WSemiconductor Wafer (Semiconductor Chip) DETAILED DESCRIPTION

[0062] An embodiment of the present invention will be described below.

[0063] [Cutting tape]

[0064] like Figure 1 As shown, the dicing tape 10 of the present embodiment has the adhesive layer 2 laminated on the base material layer 1, and has a tensile storage modulus of 100 MPa or more at -5°C.

[0065] The reason why the cutting properties of the semiconductor wafer attached to the dicing tape 10 are improved by setting the tensile storage elastic modulus of the dicing tape 10 at -5°C to 100 MPa or more is considered to be as follows.

[0066] In order to improve the cutting properties (such as cutting ease and uniform cutting properties) of the semiconductor wafer attached to the dicing tape 10 when it is cut into a plurality of semiconductor chips by expansion, it is necessary to apply sufficient tensile force to the entire dicing tape 10 when starting to cut the semiconductor wafer.

[0067] Here, it is considered that when the cutting tape 10 is relatively soft at the beginning of cutting, that is, when the tensile storage modulus of the cutting tape 10 is relatively small, the tensile force at the beginning of cutting is absorbed by the cutting tape 10 as it approaches from the outer edge portion to the central portion of the cutting tape 10, and thus gradually decreases. Therefore, it is considered that it is difficult to fully apply the tensile force at the beginning of cutting to the entire cutting tape 10.

[0068] In contrast, the dicing tape 10 of the present embodiment has a large tensile storage modulus of 100 MPa or more, and therefore it is considered that the tensile force at the start of cutting is not easily absorbed by the dicing tape 10 as it approaches from the outer edge portion to the central portion of the dicing tape 10. Therefore, the tensile force at the start of cutting can be fully applied to the entire dicing tape 10, resulting in the easy cutting of a semiconductor wafer into a plurality of semiconductor chips, and the easy acquisition of relatively uniformly cut semiconductor chips, that is, the cutting performance from a semiconductor wafer into a plurality of semiconductor chips can be further improved.

[0069] It should be noted that, as described in the embodiment section described later, by making the tensile storage modulus of the dicing tape 10 at -5°C above 100 MPa, the cutting properties when cutting a semiconductor wafer (for example, a semiconductor wafer with a diameter of 200 mm (8 inches)) into small semiconductor chips (for example, 12 mm in length × 4 mm in width × 0.55 mm in thickness) can be further improved.

[0070] The present inventors presume the reason is as follows.

[0071] When cutting semiconductor wafers of the same size, the smaller the size of the semiconductor chips after cutting, the narrower the intervals between the grooves (lines) formed in the semiconductor wafer in the half-cutting process, so the number of grooves formed on the semiconductor wafer increases. As a result, the elongation of the grooves in the expansion process decreases.

[0072] Therefore, when the semiconductor wafer is cut into small semiconductor chips in the expansion process, it is necessary to generate high stress at a lower elongation in order to suppress the occurrence of cutting defects.

[0073] Here, the elastic modulus refers to the slope of stress with respect to elongation (amount of strain) when the base material layer is stretched. Therefore, it is considered that a high elastic modulus can generate a high stress at a lower elongation.

[0074] Furthermore, in the expansion process using the dicing tape 10, from the viewpoint of good cutting performance when cutting the semiconductor wafer into a plurality of small semiconductor chips and that the tensile force does not cause the dicing tape 10 to break, the method of using a temperature of -5°C for expansion is optimal. Therefore, it is believed that by setting the tensile storage modulus at -5°C to a higher value such as 100 MPa or more, high stress can be generated with a lower elongation.

[0075] The present inventors estimate that, as a result, it is possible to further improve the cutting performance when cutting the semiconductor wafer into small semiconductor chips.

[0076] The dicing tape 10 of the present embodiment preferably has a tensile storage modulus at -5°C of 400 MPa or less.

[0077] Thus, sufficient tensile force is applied to the dicing tape 10 as a whole, and the dicing tape 10 becomes easier to stretch, thereby suppressing the breakage of the dicing tape 10 caused by the tensile force when the semiconductor wafer attached to the dicing tape 10 is cut into semiconductor chips, and further improving the cutting performance from the semiconductor wafer to multiple semiconductor chips.

[0078] Furthermore, by setting the tensile storage modulus at -5°C to 400 MPa or less, it is possible to further improve the cutting property of a semiconductor wafer into a plurality of small semiconductor chips.

[0079] The tensile storage modulus at -5°C can be determined as follows.

[0080] Specifically, a 40 mm long (measurement length) and 10 mm wide cut tape is used as a test piece, and a solid viscoelasticity measuring device (e.g., model RSAIII, manufactured by Rheometric Scientific Co., Ltd.) is used to measure the tensile storage modulus of the test piece at a temperature range of -50 to 100° C. under the conditions of a frequency of 1 Hz, a deformation of 0.1%, a heating rate of 10° C. / min, and a distance between the clamps of 22.5 mm. At this time, the tensile storage modulus can be obtained by reading the value at -5° C.

[0081] In addition, the said measurement was performed by stretching the said test piece in MD direction (resin flow direction).

[0082] The dicing tape 10 of the present embodiment preferably has a 30% tensile stress at -5°C of 5.5 N / 10 mm or more.

[0083] The dicing tape 10 of the present embodiment preferably has a 30% tensile stress at -5°C of 30 N / 10 mm or less.

[0084] Thus, sufficient tensile force is applied to the entire cutting tape 10 during expansion, and the cutting tape 10 becomes easier to stretch. Therefore, during the process of expanding the cutting tape 10 attached to the semiconductor wafer and cutting the semiconductor wafer into semiconductor chips, the cutting tape breakage caused by the expansion can be suppressed, and the cutting performance from the semiconductor wafer to multiple semiconductor chips can be further improved.

[0085] Furthermore, by setting the 30% tensile stress at -5°C to 30 N / 10 mm or less, it is possible to further improve the cutting property of a semiconductor wafer into a plurality of small semiconductor chips.

[0086] The dicing tape 10 of the present embodiment preferably has a 30% tensile stress of 3.2 N / 10 mm or more at room temperature (23° C.).

[0087] The 30% tensile stress at room temperature (23°C) is preferably 30 N / 10 mm or less.

[0088] Thus, sufficient tensile force is applied to the entire cutting tape 10 during expansion, and the cutting tape 10 becomes easier to stretch. Therefore, during the process of expanding the cutting tape 10 attached to the semiconductor wafer and cutting the semiconductor wafer into semiconductor chips, the cutting tape breakage caused by the expansion can be suppressed, and the cutting performance from the semiconductor wafer to multiple semiconductor chips can be further improved.

[0089] Furthermore, by setting the 30% tensile stress at room temperature to 30 N / 10 mm or less, it is possible to further improve the cutting property of a semiconductor wafer into a plurality of small semiconductor chips.

[0090] The 30% tensile stress at -5°C and room temperature can be determined as follows.

[0091] Specifically, it can be obtained as follows: a cut tape having a length of 100 mm and a width of 10 mm is used as a test piece, and the test piece is stretched using a tensile testing machine (Tensilon universal testing machine, manufactured by Shimadzu Corporation) at a measuring temperature (-5°C and room temperature (23°C ± 1°C), at a distance between clamps of 50 mm and a tensile speed of 100 mm / min, and the stress at which the elongation reaches 30% (distance between clamps of 65 mm) is measured.

[0092] In addition, the said measurement was performed by stretching the said test piece in MD direction (resin flow direction).

[0093] The dicing tape 10 of the present embodiment preferably has a ratio of 30% tensile stress at -5°C to 30% tensile stress at room temperature of 1.7 or more.

[0094] The dicing tape 10 of the present embodiment preferably has a ratio of 30% tensile stress at -5°C to 30% tensile stress at room temperature of 3.0 or less.

[0095] Thus, sufficient tensile force is applied to the entire cutting tape 10 during expansion, and the cutting tape 10 becomes easier to stretch. Therefore, during the process of expanding the cutting tape 10 attached to the semiconductor wafer and cutting the semiconductor wafer into semiconductor chips, the cutting tape breakage caused by the expansion can be suppressed, and the cutting performance from the semiconductor wafer to multiple semiconductor chips can be further improved.

[0096] Furthermore, by setting the ratio of the 30% tensile stress at -5°C to the 30% tensile stress at room temperature to 3.0 or less, it is possible to further improve the cutting property of the semiconductor wafer into a plurality of small semiconductor chips.

[0097] The substrate layer 1 supports the adhesive layer 2. The substrate layer 1 contains a resin. Examples of the resin contained in the substrate layer 1 include polyolefins, polyesters, polyurethanes, polycarbonates, polyetheretherketones, polyimides, polyetherimides, polyamides, wholly aromatic polyamides, polyvinyl chloride, polyvinylidene chloride, polyphenylene sulfide, fluororesins, cellulose resins, and silicone resins.

[0098] Examples of the polyolefin include homopolymers of α-olefins, copolymers of two or more α-olefins, block polypropylene, random polypropylene, and copolymers of one or two or more α-olefins and other vinyl monomers.

[0099] As the homopolymer of α-olefin, preferably a homopolymer of α-olefin having a carbon number of 2 to 12. Examples of such a homopolymer include ethylene, propylene, 1-butene, and 4-methyl-1-pentene.

[0100] Examples of copolymers of two or more α-olefins include ethylene / propylene copolymers, ethylene / 1-butene copolymers, ethylene / propylene / 1-butene copolymers, ethylene / α-olefin copolymers having a carbon number of 5 to 12, propylene / ethylene copolymers, propylene / 1-butene copolymers, and propylene / α-olefin copolymers having a carbon number of 5 to 12.

[0101] Examples of copolymers of one or more α-olefins and other vinyl monomers include ethylene-vinyl acetate copolymers (EVA) and the like.

[0102] The polyolefin may be what is called an α-olefin-based thermoplastic elastomer. Examples of the α-olefin-based thermoplastic elastomer include a combination of a propylene-ethylene copolymer and a propylene homopolymer, and a propylene-ethylene-α-olefin terpolymer having 4 or more carbon atoms.

[0103] As a commercially available product of the α-olefin-based thermoplastic elastomer, for example, Vistamaxx 3980 (manufactured by ExxonMobil Chemical Company) which is a propylene-based elastomer resin can be mentioned.

[0104] The base material layer 1 may contain one kind of the above-mentioned resins, or may contain two or more kinds of the above-mentioned resins.

[0105] In addition, when the adhesive layer 2 contains the ultraviolet curing adhesive described later, the base material layer 1 is preferably configured to have ultraviolet transmittance.

[0106] The substrate layer 1 may be a single-layer structure or a laminated structure. The substrate layer 1 may be obtained by non-stretching molding or by stretching molding, preferably by stretching molding. When the substrate layer 1 is a laminated structure, the substrate layer 1 preferably has a layer containing an elastomer (hereinafter referred to as an elastomer layer) and a layer containing a non-elastic body (hereinafter referred to as a non-elastic body layer).

[0107] By making the substrate layer 1 a substrate layer having an elastomer layer and a non-elastic layer, the elastomer layer can function as a stress relaxation layer for relaxing tensile stress. That is, the tensile stress generated in the substrate layer 1 can be reduced, so that the substrate layer 1 can have appropriate hardness and be easier to stretch.

[0108] This can improve the cutting performance of the semiconductor wafer into a plurality of semiconductor chips.

[0109] Furthermore, it is possible to suppress the base material layer 1 from being cracked and damaged during expansion in the cutting step.

[0110] It should be noted that, in this specification, the elastomer layer refers to a low elastic modulus layer having a lower tensile storage modulus at room temperature than that of the non-elastic layer. As the elastomer layer, a tensile storage modulus at room temperature of 10 MPa or more and 100 MPa or less can be listed, and as the non-elastic layer, a tensile storage modulus at room temperature of 200 MPa or more and 500 MPa or less can be listed.

[0111] The elastomer layer may contain one type of elastomer or two or more types of elastomers, and preferably contains an α-olefin-based thermoplastic elastomer.

[0112] The non-elastic layer may contain one type of non-elastic, or may contain two or more types of non-elastics, and preferably contains the metallocene PP described below.

[0113] In the case where the substrate layer 1 has an elastomer layer and a non-elastic layer, the substrate layer 1 preferably has a three-layer structure (non-elastic layer / elastic layer / non-elastic layer) with the elastomer layer as the center layer and the non-elastic layers on the two opposite sides of the center layer (refer to Figure 1 ). It should be noted that Figure 1 In FIG. 1 , one non-elastic layer is represented as a first resin layer 1 a , the elastic layer is represented as a second resin layer 1 b , and the other non-elastic layer is represented as a third resin layer 1 c .

[0114] In addition, as described above, in the incision maintaining step, hot air (e.g., 100 to 130° C.) is directed to the dicing die bonding film maintained in an expanded state at room temperature (e.g., 23° C.) to heat-shrink the dicing die bonding film and then cool and solidify it, so the outermost layer of the base material layer 1 preferably contains a resin having a melting point close to the temperature of the hot air directed to the dicing tape. As a result, the outermost layer melted by the hot air can be more quickly solidified.

[0115] As a result, the incision can be more fully maintained in the incision maintaining step.

[0116] In the case where the substrate layer 1 is a laminated structure of an elastomer layer and a non-elastic layer, the elastomer layer includes an α-olefin thermoplastic elastomer, and the non-elastic layer includes a polyolefin such as metallocene PP described later, the elastomer layer preferably includes 50% by mass or more and 100% by mass or less of an α-olefin thermoplastic elastomer relative to the total mass of the elastomer forming the elastomer layer, more preferably includes 70% by mass or more and 100% by mass or less, further preferably includes 80% by mass or more and 100% by mass or less, particularly preferably includes 90% by mass or more and 100% by mass or less, and the best is to include 95% by mass or more and 100% by mass or less. By including an α-olefin thermoplastic elastomer in the above range, the affinity between the elastomer layer and the non-elastic layer is improved, so that the substrate layer 1 can be extruded relatively easily. In addition, the elastomer layer can function as a stress relaxation layer, so that the semiconductor wafer attached to the dicing tape can be efficiently cut.

[0117] In the case where the substrate layer 1 is a laminated structure of an elastomer layer and a non-elastic layer, the substrate layer 1 is preferably obtained by coextrusion molding, wherein the coextrusion molding coextrudes an elastomer and a non-elastic body to form a laminated structure of an elastomer layer and a non-elastic body layer. As coextrusion molding, any suitable coextrusion molding commonly performed when manufacturing a film, a sheet, etc. can be adopted. In coextrusion molding, from the perspective of being able to efficiently and cheaply obtain the substrate layer 1, preferably an inflation method or a coextrusion T-die method is adopted.

[0118] In the case of obtaining the substrate layer 1 with a laminated structure by co-extrusion molding, the elastomer layer and the non-elastic layer are in contact in a heated and molten state, so it is preferred that the melting point difference between the elastomer and the non-elastic is small. By making the melting point difference small, it is possible to suppress excessive heat from being applied to either the elastomer or the non-elastic body with a low melting point, thereby suppressing the thermal degradation of either the elastomer or the non-elastic body with a low melting point and the generation of by-products. In addition, it is also possible to suppress the following situation: the viscosity of either the elastomer or the non-elastic body with a low melting point is excessively reduced, resulting in poor lamination between the elastomer layer and the non-elastic layer. The melting point difference between the elastomer and the non-elastic body is preferably above 0°C and below 70°C, and more preferably above 0°C and below 55°C.

[0119] The melting points of the elastomer and the non-elastic body can be measured by differential scanning calorimetry (DSC) analysis, for example, by using a differential scanning calorimeter (DSC Q2000 manufactured by TA INSTRUMENTS), heating to 200° C. at a heating rate of 5° C. / min under a nitrogen stream, and determining the peak temperature of the endothermic peak.

[0120] The thickness of the base layer 1 is preferably 55 μm to 195 μm, more preferably 55 μm to 190 μm, further preferably 55 μm to 170 μm, and most preferably 60 μm to 160 μm. By setting the thickness of the base layer 1 to the above range, the dicing tape can be manufactured efficiently, and the semiconductor wafer attached to the dicing tape can be cut efficiently.

[0121] The thickness of the base material layer 1 can be determined, for example, by measuring the thickness at five randomly selected points using a direct-reading thickness meter (model R-205 manufactured by PEACOCK), and calculating the arithmetic average of these thicknesses.

[0122] In the base material layer 1 formed by laminating an elastomer layer and a non-elastic layer, the ratio of the thickness of the non-elastic layer to the thickness of the elastomer layer is preferably 1 / 25 or more and 1 / 3 or less, more preferably 1 / 25 or more and 1 / 3.5 or less, further preferably 1 / 25 or more and 1 / 4 or less, particularly preferably 1 / 22 or more and 1 / 4 or less, and the best is 1 / 20 or more and 1 / 4 or less. By setting the ratio of the thickness of the non-elastic layer to the thickness of the elastomer layer to the above range, the semiconductor wafer attached to the dicing tape can be cut more efficiently.

[0123] The elastomer layer may be a single layer (1 layer) structure or a laminated structure. The elastomer layer is preferably a structure of 1 to 5 layers, more preferably a structure of 1 to 3 layers, further preferably a structure of 1 to 2 layers, and the best is a 1-layer structure. When the elastomer layer is a laminated structure, all layers may contain the same elastomer, or at least 2 layers may contain different elastomers.

[0124] The non-elastic layer may be a single layer (1 layer) structure or a laminated structure. The non-elastic layer is preferably a structure of 1 to 5 layers, more preferably a structure of 1 to 3 layers, further preferably a structure of 1 to 2 layers, and a 1-layer structure is the best. When the non-elastic layer is a laminated structure, all layers may contain the same non-elastic body, or at least 2 layers may contain different non-elastic bodies.

[0125] The non-elastic layer preferably contains a polypropylene resin (hereinafter referred to as metallocene PP) as a polymerization product obtained by using a metallocene catalyst as a non-elastic. As the metallocene PP, a propylene / α-olefin copolymer as a polymerization product of a metallocene catalyst can be cited. By making the non-elastic layer contain metallocene PP, a dicing tape can be efficiently manufactured, and a semiconductor wafer attached to the dicing tape can be efficiently cut.

[0126] Examples of commercially available metallocene PP include WINTEC WXK1233 and WINTEC WMX03 (both manufactured by Japan Polypropylene Co., Ltd.).

[0127] Here, the metallocene catalyst is a catalyst comprising a transition metal compound of Group 4 of the periodic table (so-called metallocene compound), wherein the transition metal compound of Group 4 of the periodic table comprises a ligand having a cyclopentadienyl skeleton, and a cocatalyst capable of reacting with the metallocene compound to activate the metallocene compound into a stable ionic state, and the metallocene catalyst comprises an organic aluminum compound as required. The metallocene compound is a cross-linked metallocene compound capable of stereoregular polymerization of propylene.

[0128] Among the above-mentioned propylene / α-olefin copolymers as polymerization products of metallocene catalysts, preferred are propylene / α-olefin random copolymers as polymerization products of metallocene catalysts. Among the above-mentioned propylene / α-olefin random copolymers as polymerization products of metallocene catalysts, preferred are copolymers selected from propylene / α-olefin random copolymers as polymerization products of metallocene catalysts having a carbon number of 2, propylene / α-olefin random copolymers as polymerization products of metallocene catalysts having a carbon number of 4, and propylene / α-olefin random copolymers as polymerization products of metallocene catalysts having a carbon number of 5. Among these, propylene / ethylene random copolymers as polymerization products of metallocene catalysts are the best.

[0129] With regard to the propylene / α-olefin random copolymer which is a polymerization product of the metallocene catalyst, from the viewpoint of co-extrusion film-forming property with the above-mentioned elastomer layer and the cutting property of the semiconductor wafer attached to the dicing tape, it is preferred that the melting point is above 80°C and below 140°C, in particular above 100°C and below 130°C.

[0130] The melting point of the propylene / α-olefin random copolymer as the polymerization product of the metallocene catalyst can be measured by the above-mentioned method.

[0131] Here, if the above-mentioned elastomer layer is arranged at the outermost layer of the substrate layer 1, when the substrate layer 1 is made into a roll, the above-mentioned elastomer layers arranged at the outermost layer are easy to stick to each other (easy to stick together). Therefore, it becomes difficult to unwind the substrate layer 1 from the roll. In contrast, the preferred mode of the substrate layer 1 of the above-mentioned laminated structure is non-elastic layer / elastic layer / non-elastic layer, that is, the non-elastic layer is arranged at the outermost layer, so the substrate layer 1 of this form has excellent anti-blocking property. Thereby, it is possible to suppress the delay caused by blocking in the manufacture of semiconductor devices using the dicing tape 10.

[0132] The non-elastic layer preferably contains a resin having a melting point of 100° C. to 130° C. and a molecular weight dispersion (mass average molecular weight / number average molecular weight) of 5 or less. Examples of such a resin include metallocene PP.

[0133] By making the non-elastic layer contain the above-mentioned resin, the non-elastic layer can be cooled and solidified more quickly in the incision maintaining step. Therefore, it is possible to more fully suppress the shrinkage of the base layer 1 after the dicing tape is heat-shrunk.

[0134] Thereby, in the incision maintaining step, the incision can be more fully maintained.

[0135] The adhesive layer 2 contains an adhesive. The adhesive layer 2 holds the semiconductor wafer to be singulated into semiconductor chips by bonding.

[0136] Examples of the adhesive include an adhesive whose adhesive force can be reduced by an external action during use of the dicing tape 10 (hereinafter referred to as an adhesive-reducing type adhesive).

[0137] When an adhesive of an adhesion-reducing type is used as an adhesive, the adhesive layer 2 can be used separately in a state showing a higher adhesive force (hereinafter referred to as a high adhesive state) and a state showing a lower adhesive force (hereinafter referred to as a low adhesive state) during the use of the dicing tape 10. For example, when a semiconductor wafer attached to the dicing tape 10 is provided for cutting, the high adhesive state is used to suppress the floating or peeling of a plurality of semiconductor chips singulated by cutting the semiconductor wafer from the adhesive layer 2. In contrast, after cutting the semiconductor wafer, the low adhesive state is used to pick up a plurality of singulated semiconductor chips so that the plurality of semiconductor chips can be easily picked up from the adhesive layer 2.

[0138] Examples of the adhesion-reducing adhesive include an adhesive that can be cured by irradiation with radiation during use of the dicing tape 10 (hereinafter referred to as a radiation-curing adhesive).

[0139] Examples of the radiation-curable adhesive include adhesives that are cured by irradiation with electron beams, ultraviolet rays, α rays, β rays, γ rays, or X rays. Of these, adhesives that are cured by irradiation with ultraviolet rays (ultraviolet curable adhesives) are preferably used.

[0140] Examples of the radiation-curable adhesive include additive-type radiation-curable adhesives comprising a base polymer such as an acrylic polymer, and a radiation-polymerizable monomer component or a radiation-polymerizable oligomer component having a radiation-polymerizable carbon-carbon double bond or other functional group.

[0141] Examples of the acrylic polymer include acrylic polymers containing monomer units derived from (meth)acrylic acid esters, and examples of (meth)acrylic acid esters include alkyl (meth)acrylates, cycloalkyl (meth)acrylates, and aryl (meth)acrylates.

[0142] The adhesive layer 2 may contain an external crosslinking agent. As the external crosslinking agent, any type can be used as long as it can react with the acrylic polymer as the base polymer to form a crosslinked structure. As such an external crosslinking agent, for example, polyisocyanate compounds, epoxy compounds, polyol compounds, aziridine compounds, and melamine-based crosslinking agents can be cited.

[0143] Examples of the radiation polymerizable monomer component include urethane (meth)acrylate, trimethylolpropane tri(meth)acrylate, pentaerythritol tri(meth)acrylate, pentaerythritol tetra(meth)acrylate, dipentaerythritol monohydroxy penta(meth)acrylate, dipentaerythritol hexa(meth)acrylate, and 1,4-butanediol di(meth)acrylate. Examples of the radiation polymerizable oligomer component include various oligomers such as urethane, polyether, polyester, polycarbonate, and polybutadiene. The content ratio of the radiation polymerizable monomer component and the radiation polymerizable oligomer component in the radiation curing adhesive can be selected within a range that appropriately reduces the adhesiveness of the adhesive layer 2.

[0144] The radiation-curable adhesive preferably contains a photopolymerization initiator. Examples of the photopolymerization initiator include α-ketol compounds, acetophenone compounds, benzoin ether compounds, ketal compounds, aromatic sulfonyl chloride compounds, photoactive oxime compounds, benzophenone compounds, thioxanthone compounds, camphorquinone, haloketones, acylphosphine oxides, and acylphosphonates.

[0145] The pressure-sensitive adhesive layer 2 may contain, in addition to the above-mentioned components, a cross-linking accelerator, a tackifier, an antioxidant, a colorant such as a pigment or a dye, and the like.

[0146] The thickness of the adhesive layer 2 is preferably 1 μm or more and 50 μm or less, more preferably 2 μm or more and 30 μm or less, and further preferably 5 μm or more and 25 μm or less.

[0147] [Dicing Die Bonding Film]

[0148] Afterwards, refer to Figure 2 The dicing die-bonding film 20 will be described. In the description of the dicing die-bonding film 20 , the parts that overlap with the dicing tape 10 will not be described repeatedly.

[0149] like Figure 2 As shown, the dicing die-bonding film 20 of the present embodiment includes a dicing tape 10 in which an adhesive layer 2 is laminated on a base layer 1 , and a die-bonding layer 3 laminated on the adhesive layer 2 of the dicing tape 10 .

[0150] In the dicing die-bonding film 20 , a semiconductor wafer is attached to the die-bonding layer 3 .

[0151] When the semiconductor wafer is cut using the dicing die-bonding film 20, the die-bonding layer 3 is also cut together with the semiconductor wafer. The die-bonding layer 3 is cut into a size corresponding to the size of the plurality of singulated semiconductor chips. Thus, a semiconductor chip with the die-bonding layer 3 can be obtained.

[0152] As described above, the tensile storage modulus at -5°C of the dicing tape 10 for dicing the die-bonding film 20 is 100 MPa or more.

[0153] Here, usually, the die bonding layer 3 of the cut die bonding film 20 mostly contains an acrylic resin having a glass transition temperature (Tg) of about 0°C, so setting the temperature of the expansion process to a temperature lower than the Tg of the acrylic resin will cause it to become easy to break. On the other hand, if the temperature of the expansion process is excessively lowered, the elastic modulus of the die bonding layer 3 will increase to a level that hinders the cutting property of the die bonding layer 3. Therefore, from the viewpoint of the cutting property of the die bonding layer 3, the temperature of the expansion process is preferably set to -5°C.

[0154] Therefore, in the expansion process using the cutting chip bonding film 20, from the perspective of good cutting performance when cutting the semiconductor wafer into multiple small semiconductor chips as described above, and the cutting tape 10 is not prone to breakage due to tensile force, and from the perspective of the cutting performance of the chip bonding layer 3, it is considered that the best solution is to use a temperature of -5°C for the expansion process.

[0155] Therefore, it is considered that, for the dicing die-bonding film 20 , by setting the tensile storage modulus at −5° C. to a high value of 100 MPa, a high stress can be generated at a lower elongation.

[0156] As a result, it is estimated that the cutting property when cutting the semiconductor wafer into small semiconductor chips can be further improved.

[0157] As described above, the dicing tape 10 for dicing the die-bonding film 20 preferably has a tensile storage modulus of 400 MPa or less at -5°C.

[0158] In addition, as described above, the dicing tape 10 for dicing the chip bonding film 20 preferably has a 30% tensile stress of 5.5 N / 10 mm or more at -5°C, preferably has a 30% tensile stress of 3.2 N / 10 mm at room temperature, and preferably has a ratio of 30% tensile stress at -5°C to 30% tensile stress at room temperature of 1.7 or more.

[0159] Furthermore, as described above, the dicing tape 10 for dicing the die-bonding film 20 preferably has a 30% tensile stress of 30 N / 10 mm or less at -5°C, and preferably has a 30% tensile stress of 30 N / 10 mm or less at room temperature.

[0160] The die-bonding layer 3 preferably has thermosetting properties. The die-bonding layer 3 can be given thermosetting properties by including at least one of a thermosetting resin and a thermoplastic resin having a thermosetting functional group.

[0161] When the die bonding layer 3 contains a thermosetting resin, examples of such thermosetting resins include epoxy resins, phenolic resins, amino resins, unsaturated polyester resins, polyurethane resins, silicone resins, and thermosetting polyimide resins, etc. Among these, epoxy resins are preferably used.

[0162] Examples of the epoxy resin include bisphenol A type, bisphenol F type, bisphenol S type, brominated bisphenol A type, hydrogenated bisphenol A type, bisphenol AF type, biphenyl type, naphthalene type, fluorene type, phenol novolac type, o-cresol novolac type, trihydroxyphenylmethane type, tetraphenolethane type, hydantoin type, triglycidyl isocyanurate type, and glycidylamine type epoxy resins.

[0163] Examples of the phenolic resin as a curing agent for the epoxy resin include novolac-type phenolic resins, resol-type phenolic resins, and polyoxystyrene such as polyparaoxystyrene.

[0164] When the die bonding layer 3 includes a thermoplastic resin having a thermosetting functional group, such a thermoplastic resin may include, for example, an acrylic resin containing a thermosetting functional group. Among the acrylic resins containing a thermosetting functional group, an acrylic resin containing a monomer unit derived from a (meth)acrylate may be included.

[0165] For a thermosetting resin having a thermosetting functional group, a curing agent can be selected according to the type of the thermosetting functional group.

[0166] The die bonding layer 3 may contain a thermal curing catalyst from the viewpoint of sufficiently advancing the curing reaction of the resin component or increasing the curing reaction rate. Examples of the thermal curing catalyst include imidazole compounds, triphenylphosphine compounds, amine compounds, and trihaloborane compounds.

[0167] The chip bonding layer 3 may include a thermoplastic resin. The thermoplastic resin acts as a binder. As thermoplastic resins, for example, natural rubber, butyl rubber, isoprene rubber, chloroprene rubber, ethylene-vinyl acetate copolymer, ethylene-acrylic acid copolymer, ethylene-acrylate copolymer, polybutadiene resin, polycarbonate resin, thermoplastic polyimide resin, polyamide 6 and polyamide 6,6 and other polyamide resins, phenoxy resins, acrylic resins, saturated polyester resins such as PET and PBT, polyamide-imide resins, fluororesins, etc. The above-mentioned thermoplastic resins may be used alone or in combination of two or more. As the above-mentioned thermoplastic resin, acrylic resins are preferred from the viewpoint of having few ionic impurities and high heat resistance and being easy to ensure the connection reliability based on the chip bonding layer.

[0168] The acrylic resin is preferably a polymer containing monomer units derived from (meth)acrylate as the largest monomer unit in terms of mass ratio. Examples of (meth)acrylate include alkyl (meth)acrylate, cycloalkyl (meth)acrylate, and aryl (meth)acrylate. The acrylic resin may include monomer units derived from other components that can be copolymerized with (meth)acrylate. Examples of the other components include functional group-containing monomers such as carboxyl-containing monomers, anhydride monomers, hydroxyl-containing monomers, glycidyl-containing monomers, sulfonic acid-containing monomers, phosphoric acid-containing monomers, acrylamide, acrylonitrile, and various multifunctional monomers. From the viewpoint of achieving high cohesion in the chip bonding layer, the acrylic resin is preferably a copolymer of (meth)acrylate (especially (meth)acrylate alkyl ester having an alkyl group with a carbon number of 4 or less) and a carboxyl group-containing monomer, a nitrogen atom-containing monomer, or a polyfunctional monomer (especially a polyglycidyl-based polyfunctional monomer), and more preferably a copolymer of ethyl acrylate and butyl acrylate, acrylic acid, acrylonitrile, or polyglycidyl (meth)acrylate.

[0169] The die bonding layer 3 may contain one or more other components as necessary. Examples of other components include flame retardants, silane coupling agents, and ion scavengers.

[0170] The thickness of the die bond layer 3 is preferably 40 μm or more, more preferably 60 μm or more, and further preferably 80 μm or more. The thickness of the die bond layer 3 is preferably 200 μm or less, more preferably 160 μm or less, and further preferably 120 μm or less.

[0171] The dicing die-bonding film 20 of the present embodiment can be used as an auxiliary tool for manufacturing a semiconductor integrated circuit, for example. A specific example of using the dicing die-bonding film 20 will be described below.

[0172] Hereinafter, an example using the dicing die-bonding film 20 including a single base material layer 1 will be described.

[0173] The method for manufacturing a semiconductor integrated circuit has the following steps: a half-cutting step, in which a groove is formed on a semiconductor wafer in order to process the semiconductor wafer into a die by cutting, and then the semiconductor wafer is ground to reduce the thickness; a back grinding step, in which the semiconductor wafer after the half-cutting step is ground to reduce the thickness; a mounting step, in which one side of the semiconductor wafer after the back grinding step (for example, the side on the opposite side to the circuit side) is attached to the die bonding layer 3 to fix the semiconductor wafer to the dicing tape 10; an expansion step, in which the interval between the semiconductor chips processed by the half-cutting is expanded; a cut maintenance step, in which the interval between the semiconductor chips is maintained; a pick-up step, in which the die bonding layer 3 is peeled off from the adhesive layer 2 to take out the semiconductor chip (die) in a state where the die bonding layer 3 is attached; and a die bonding step, in which the semiconductor chip (die) in a state where the die bonding layer 3 is attached is bonded to an adherend. When implementing these steps, the dicing tape (dicing die bonding film) of this embodiment is used as a manufacturing auxiliary tool.

[0174] In the half-cutting process, Figure 3A and Figure 3B As shown in FIG. 1 , a half-cutting process is performed to cut the semiconductor integrated circuit into small pieces (dies). Specifically, a wafer processing tape T (see FIG. 1 ) is attached to the surface of the semiconductor wafer W opposite to the circuit surface. Figure 3A ). In addition, the dicing ring R is mounted on the wafer processing tape T (refer to Figure 3A ). A groove for dividing is formed in a state where the wafer processing tape T is attached (refer to Figure 3B ). In the back grinding process, such as Figure 3C and Figure 3D Specifically, a back grinding tape G is attached to the surface on which the grooves are formed, and on the other hand, the wafer processing tape T attached initially is peeled off (see Figure 3C ). Grinding is performed with the back grinding tape G attached until the semiconductor wafer W reaches a predetermined thickness (see Figure 3D ).

[0175] During the installation process, Figure 4A to Figure 4B As shown, after the dicing ring R is mounted on the adhesive layer 2 of the dicing tape 10, the semiconductor wafer W (see FIG. 1 ) which has been half-cut is attached to the exposed surface of the die bonding layer 3. Figure 4A ). Thereafter, the back grinding tape G is peeled off from the semiconductor wafer W (see Figure 4B ).

[0176] In the expansion process, Figure 5A to Figure 5C As shown, the dicing ring R is fixed to the holder H of the expansion device. The dicing die bonding film 20 is lifted from the lower side using the lifting member U provided in the expansion device, thereby stretching the dicing die bonding film 20 and expanding it in the surface direction (see Figure 5B ). Thus, the semiconductor wafer W that has been half-cut is cut under a specific temperature condition. The temperature condition is, for example, -20 to 5°C, preferably -15 to 0°C, and more preferably -10 to -5°C. The extended state is released by lowering the lifting member U (see Figure 5C ).

[0177] Furthermore, in the expansion process, Figure 6A to Figure 6B As shown, the dicing tape 10 is stretched under a higher temperature condition (eg, room temperature (23° C.)) to expand the area. Thus, the cut adjacent semiconductor chips W are separated in the plane direction of the film surface, and the interval is further increased.

[0178] Here, the dicing die-bonding film 20 of the present embodiment can further improve the cutting property from a semiconductor wafer to a plurality of semiconductor chips by expansion under low temperature conditions because the tensile storage modulus of the die-bonding tape 10 at -5°C is 100 MPa or more.

[0179] In the incision maintenance process, Figure 7 As shown, hot air (eg, 100 to 130° C.) is directed toward the dicing tape 10 to heat shrink the dicing tape 10, and then the dicing tape 10 is cooled and solidified, thereby maintaining the distance (kerf) between the cut adjacent semiconductor chips W.

[0180] In the picking process, Figure 8 As shown, the semiconductor chip W with the die bonding layer 3 attached thereto is peeled off from the adhesive layer 2 of the dicing tape 10. Specifically, the pin member P is raised to lift up the semiconductor chip W to be picked up through the dicing tape 10. The lifted semiconductor chip is held by the suction jig J.

[0181] In the die bonding step, the semiconductor chip W with the die bonding layer 3 attached thereto is bonded to an adherend.

[0182] In the above-mentioned manufacturing of the semiconductor integrated circuit, an example in which the dicing die-bonding film 20 is used as an auxiliary tool is described. However, when the dicing tape 10 is used as an auxiliary tool, the semiconductor integrated circuit can be manufactured in the same manner as described above.

[0183] Matters disclosed by this specification include the following matters. (1)

[0185] A dicing tape comprising an adhesive layer laminated on a base material layer,

[0186] The dicing tape has a tensile storage modulus at -5°C of 100 MPa or more.

[0187] According to the above configuration, since the tensile storage modulus of the dicing tape at -5°C is 100 MPa or more, the dicing tape can have a relatively high hardness.

[0188] Therefore, when the dicing tape is attached to a semiconductor wafer and expanded under low temperature conditions (eg, -15°C to 5°C) to cut the semiconductor wafer into a plurality of semiconductor chips, sufficient tensile force can be applied to the entire dicing tape at the start of expansion.

[0189] Therefore, it is easy to cut the semiconductor wafer into a plurality of semiconductor chips, and it is easy to obtain semiconductor chips that are cut relatively uniformly.

[0190] That is, the cutting property of the semiconductor wafer can be further improved. (2)

[0192] The dicing tape according to the above (1), wherein the tensile storage modulus at -5°C is 400 MPa or less.

[0193] According to the above-mentioned structure, sufficient tensile force is applied to the entire cutting tape and the cutting tape is made to stretch more easily. Therefore, the breakage of the cutting tape caused by the tensile force when the semiconductor wafer attached to the cutting tape is cut into multiple semiconductor chips can be further suppressed, and the cutting property from the semiconductor wafer to multiple semiconductor chips can be improved.

[0194] Furthermore, by setting the 30% tensile stress at -5°C to 30 N / 10 mm or less, the cutting property of the semiconductor wafer into a plurality of small semiconductor chips can be further improved. (3)

[0196] The dicing tape according to (1) or (2) above, wherein the 30% tensile stress at -5°C is 5.5 N / 10 mm or more.

[0197] According to the above structure, the 30% tensile stress at -5°C is greater than 5.5N / 10mm. Therefore, when the dicing tape is attached to a semiconductor wafer and expanded under low temperature conditions to cut the semiconductor wafer into multiple semiconductor chips, the dicing tape can have a greater hardness during expansion.

[0198] Therefore, it becomes easier to cut the semiconductor wafer into a plurality of semiconductor chips, and it becomes easier to obtain relatively uniformly cut semiconductor chips.

[0199] That is, the cutting property of the semiconductor wafer can be further improved. (4)

[0201] The dicing tape according to any one of (1) to (3) above, wherein the 30% tensile stress at -5°C is 30 N / 10 mm or less.

[0202] According to the above-mentioned structure, sufficient tensile force is applied to the entire cutting tape during expansion, and the cutting tape is made to stretch more easily. Therefore, during the period when the cutting tape attached to the semiconductor wafer is expanded and the semiconductor wafer is cut into multiple semiconductor chips, the breakage of the cutting tape caused by the expansion can be further suppressed, and the cutting property from the semiconductor wafer to multiple semiconductor chips can be improved.

[0203] Furthermore, by setting the 30% tensile stress at -5°C to 30 N / 10 mm or less, the cutting property of the semiconductor wafer into a plurality of small semiconductor chips can be further improved. (5)

[0205] The dicing tape according to any one of (1) to (4) above, wherein 30% tensile stress at room temperature is 3.2 N / 10 mm or more.

[0206] According to the above structure, the 30% tensile stress at room temperature is greater than 3.2N / 10mm. Therefore, when the dicing tape is attached to a semiconductor wafer and expanded under low temperature conditions to cut the semiconductor wafer into multiple semiconductor chips, the cutting property of the semiconductor wafer can be further improved during expansion.

[0207] In addition, it is possible to suppress the transfer of the tensile stress generated by the dicing tape between the cut semiconductor chips to the semiconductor chip side.

[0208] Therefore, it is possible to relatively suppress a situation in which a large force is applied to the outer edge portion of the semiconductor chip and the outer edge portion of the semiconductor chip is lifted from the surface of the dicing tape (chip lift). (6)

[0210] The dicing tape according to any one of (1) to (5) above, wherein a 30% tensile stress at room temperature is 30 N / 10 mm or less.

[0211] According to the above-mentioned structure, sufficient tensile force is applied to the entire cutting tape during expansion, and the cutting tape is made to stretch more easily. Therefore, during the period when the cutting tape attached to the semiconductor wafer is expanded and the semiconductor wafer is cut into multiple semiconductor chips, the breakage of the cutting tape caused by the expansion can be further suppressed, and the cutting property from the semiconductor wafer to multiple semiconductor chips can be improved.

[0212] Furthermore, by setting the 30% tensile stress at room temperature to 30 N / 10 mm or less, it is possible to further improve the cutting property of a semiconductor wafer into a plurality of small semiconductor chips. (7)

[0214] The dicing tape according to any one of (1) to (6) above, wherein a ratio of 30% tensile stress at -5°C to 30% tensile stress at room temperature is 1.7 or more.

[0215] According to the above-mentioned structure, the ratio of the 30% tensile stress at -5°C to the 30% tensile stress at room temperature is greater than 1.7. Therefore, when the cutting tape is attached to the semiconductor wafer and expanded under low temperature conditions to cut the semiconductor wafer into multiple semiconductor chips, the cutting property of the semiconductor wafer can be further improved during the expansion.

[0216] In addition, chip floating caused by the transfer of tensile stress generated by the dicing tape to the semiconductor chip side can be relatively suppressed. (8)

[0218] The dicing tape according to any one of (1) to (7) above, wherein a ratio of 30% tensile stress at -5°C to 30% tensile stress at room temperature is 3.0 or less.

[0219] According to the above-mentioned structure, sufficient tensile force is applied to the entire cutting tape during expansion, and the cutting tape is made to stretch more easily. Therefore, during the period when the cutting tape attached to the semiconductor wafer is expanded to cut the semiconductor wafer into multiple semiconductor chips, the cutting tape caused by the expansion can be further broken and the cutting property from the semiconductor wafer to multiple semiconductor chips can be improved.

[0220] Furthermore, by setting the ratio of the 30% tensile stress at -5°C to the 30% tensile stress at room temperature to 3.0 or less, the cutting property of the semiconductor wafer into a plurality of small semiconductor chips can be further improved. (9)

[0222] The dicing tape according to any one of (1) to (8) above, wherein the base layer has a three-layer structure having an elastic layer as a central layer and non-elastic layers on both surfaces of the central layer facing each other.

[0223] According to the above configuration, the elastic layer can function as a stress relaxation layer for relaxing tensile stress. That is, the tensile stress generated in the base layer can be relatively reduced, so that the base layer can have an appropriate hardness and be relatively easy to stretch.

[0224] Therefore, the cutting performance of the semiconductor wafer into a plurality of semiconductor chips can be improved.

[0225] In addition, the base material layer can be prevented from being broken and damaged during expansion in the cutting step. (10)

[0227] A dicing die bonding film comprising:

[0228] A dicing tape having an adhesive layer laminated on a base layer, and

[0229] a die bonding layer laminated on the adhesive layer of the dicing tape,

[0230] The dicing die-bonding film has a tensile storage modulus at -5°C of 100 MPa or more.

[0231] According to the above configuration, when the dicing tape is attached to a semiconductor wafer and expanded under low temperature conditions (eg, -15°C to 5°C) to cut the semiconductor wafer into a plurality of semiconductor chips, sufficient tensile force can be applied to the entire dicing tape at the start of expansion.

[0232] Therefore, the cutting property of the semiconductor wafer can be further improved, and the cutting property of the die bonding layer can be improved.

[0233] It should be noted that the dicing tape and dicing die bonding film of the present invention are not limited to the above-mentioned embodiments. In addition, the dicing tape and dicing die bonding film of the present invention are not limited to the above-mentioned effects. The dicing tape and dicing die bonding film of the present invention can be variously modified within the scope of the present invention.

[0234] Example

[0235] The following examples are provided to further illustrate the present invention in detail, but are not intended to limit the scope of the present invention.

[0236] [Example 1]

[0237] <Molding of base material layer>

[0238] Two types of three-layer extrusion T-die molding machines were used to mold a substrate layer having a three-layer structure of A layer / B layer / C layer (a three-layer structure in which the B layer is the center layer and the A layer and the C layer are laminated on both sides of the B layer as outer layers). Metallocene PP (trade name: WINTEC WXK1233, manufactured by Japan Polypropylene Co., Ltd.) was used as the resin of the A layer and the C layer, and EVA (trade name: Evaflex EV250, manufactured by Mitsui DuPont Polychemical Co., Ltd.) was used as the resin of the B layer.

[0239] The extrusion molding was performed at a die temperature of 190°C. That is, the A layer, the B layer, and the C layer were extruded at 190°C. The thickness of the substrate layer obtained by extrusion molding was 100 μm. It should be noted that the thickness ratio (layer thickness ratio) of the A layer, the B layer, and the C layer was A layer: B layer: C layer = 1:10:1.

[0240] After the molded base material layer is sufficiently cured, the cured base material layer is wound into a roll to produce a roll body.

[0241] <Production of cutting tape>

[0242] The adhesive composition was applied from the roll substrate layer to one surface of the substrate layer using an applicator to a thickness of 10 μm. The substrate layer coated with the adhesive composition was heated and dried at 110° C. for 3 minutes to form an adhesive layer, thereby obtaining a dicing tape.

[0243] The above-mentioned adhesive composition was prepared as follows.

[0244] First, 173 parts by mass of INA (isononyl acrylate), 54.5 parts by mass of HEA (hydroxyethyl acrylate), 0.46 parts by mass of AIBN (2,2′-azobisisobutyronitrile), and 372 parts by mass of ethyl acetate were mixed to obtain a first resin composition.

[0245] Thereafter, the first resin composition was added to the round-bottomed separable flask of the polymerization experimental apparatus equipped with a round-bottomed separable flask (capacity 1 L), a thermometer, a nitrogen inlet tube and a stirring blade, and the liquid temperature of the first resin composition was brought to room temperature (23° C.) while stirring the first resin composition, and the interior of the round-bottomed separable flask was purged with nitrogen for 6 hours.

[0246] Next, while nitrogen was flowing into the round-bottom separable flask, the first resin composition was stirred while the liquid temperature of the first resin composition was maintained at 62° C. for 3 hours, and then further maintained at 75° C. for 2 hours to polymerize the INA, HEA, and AIBN to obtain a second resin composition. Thereafter, the flow of nitrogen into the round-bottom separable flask was stopped.

[0247] The second resin composition was cooled until the liquid temperature reached room temperature, and then 52.5 parts by mass of 2-isocyanatoethyl methacrylate (manufactured by Showa Denko K.K., trade name "Karenz MOI (registered trademark)") as a compound having a polymerizable carbon-carbon double bond and 0.26 parts by mass of dibutyltin IV dilaurate (manufactured by Wako Pure Chemical Industries, Ltd.) were added to the second resin composition to obtain a third resin composition, and the obtained third resin composition was stirred in an air atmosphere at a liquid temperature of 50°C for 24 hours.

[0248] Thereafter, 0.75 parts by mass of CORONATE L (isocyanate compound) and 2 parts by mass of Omnirad 127 (photopolymerization initiator) were added to the third resin composition relative to 100 parts by mass of the polymer solid content, and the third resin composition was diluted with ethyl acetate to a solid content concentration of 20% by mass, thereby preparing an adhesive composition.

[0249] <Production of Dicing Die Bonding Film>

[0250] 100 parts by mass of an acrylic resin (manufactured by Nagase Chemical Co., Ltd., trade name "SG-P3", glass transition temperature 12°C), 46 parts by mass of an epoxy resin (manufactured by Mitsubishi Chemical Corporation, trade name "JER1001"), 51 parts by mass of a phenolic resin (manufactured by Meiwa Chemicals Co., Ltd., trade name "MEH-7851ss"), 191 parts by mass of spherical silica (manufactured by Admatechs, trade name "SO-25R"), and 0.6 parts by mass of a curing catalyst (manufactured by Shikoku Chemicals Co., Ltd., trade name "CUREZOL PHZ") are added to methyl ethyl ketone and mixed to obtain a chip bonding composition having a solid content concentration of 20% by mass.

[0251] Afterwards, the chip bonding composition is applied on the silicone-treated surface of a PET-based separator (50 μm thick) serving as a release liner using an applicator in a manner to a thickness of 10 μm, and the composition is dried at 130°C for 2 minutes to remove the solvent from the chip bonding composition, thereby obtaining a chip bonding sheet having a chip bonding layer stacked on the release liner.

[0252] Thereafter, after the side of the die-bonding sheet on which the release sheet is not laminated is bonded to the pressure-sensitive adhesive layer of the dicing tape, the release liner is peeled from the die-bonding layer to obtain a dicing die-bonding film having a die-bonding layer.

[0253] The dicing tape obtained as described above was measured for tensile storage modulus at -5°C and 30% tensile stress at -5°C and 23°C as follows. In addition, the floating of the chip from the dicing die bonding film during expansion (hereinafter referred to as chip floating) and the cutability of the chip and the die bonding layer (hereinafter referred to as cutability) were evaluated.

[0254] (Tensile storage modulus at -5°C)

[0255] A test piece of 40 mm in length (measurement length) × 10 mm in width was cut out from the cutting tape of Example 1, and the tensile storage modulus of the test piece was measured in the temperature range of -50 to 100°C using a solid viscoelasticity measuring apparatus (model RSAIII, manufactured by Rheometric Scientific Co., Ltd.) under the conditions of frequency 1 Hz, deformation 0.1%, heating rate 10°C / min, and distance between clamps 22.5 mm. At this time, the tensile storage modulus at -5°C was calculated by reading the value of the tensile elastic modulus at -5°C.

[0256] (30% tensile stress at -5°C and room temperature)

[0257] A test piece of 100 mm in length and 10 mm in width was cut out from the cutting tape of Example 1. The test piece was stretched using a tensile testing machine (Tensilon universal testing machine, manufactured by Shimadzu Corporation) at a measuring temperature (-5°C and room temperature) with a clamp distance of 50 mm and a tensile speed of 100 mm / min, and the stress at which the elongation reached 30% (clamp distance of 65 mm) was measured.

[0258] (Evaluation of chip floating)

[0259] A bare wafer (300 mm in diameter) and a dicing ring were attached to the dicing die bonding film of Example 1. Then, the semiconductor wafer and the die bonding layer were cut using a die separation device DDS230 (manufactured by DISCO Corporation), and the chip floating after cutting was evaluated. The bare wafer was cut into bare chips of a size of 12 mm in length × 4 mm in width × 0.055 mm in thickness.

[0260] It should be noted that a warped wafer was used as a bare wafer.

[0261] A warped wafer was produced as follows.

[0262] First, the following (a) to (f) were dissolved in methyl ethyl ketone to obtain a warpage control composition having a solid content concentration of 20% by mass.

[0263] (a) Acrylic resin (manufactured by Nagase Chemical Co., Ltd., trade name "SG-70L"): 5 parts by mass

[0264] (b) Epoxy resin (manufactured by Mitsubishi Chemical Corporation, trade name "JER828"): 5 parts by mass

[0265] (c) Phenolic resin (produced by Meiwa Chemicals Co., Ltd., trade name "LDR8210"): 14 parts by mass

[0266] (d) Epoxy resin (manufactured by Mitsubishi Chemical Corporation, trade name "MEH-8005"): 2 parts by mass

[0267] (e) Spherical silica (manufactured by Admatechs, trade name "SO-25R"): 53 parts by mass

[0268] (f) Phosphorus-based catalyst (TPP-K): 1 part by mass

[0269] Afterwards, the warp adjusting composition was applied to the silicone-treated surface of a PET-based separator (thickness 50 μm) serving as a release liner with a thickness of 25 μm using an applicator, and dried at 130°C for 2 minutes to remove the solvent from the warp adjusting composition to obtain a warp adjusting sheet having a warp adjusting layer stacked on the release liner.

[0270] Afterwards, a laminator (manufactured by MCK, model MRK-600) was used to attach the bare wafer to the side of the warp adjustment sheet that was not laminated with the peeling liner at 60°C, 0.1 MPa, and 10 mm / s, and the wafer was placed in an oven and heated at 175°C for 1 hour to thermally cure the resin of the warp adjustment layer, thereby shrinking the warp adjustment layer to obtain a warped bare wafer.

[0271] After shrinking the warp adjustment layer, a wafer processing tape (manufactured by Nitto Denko Corporation, trade name "V-12SR2") was attached to the side of the warped bare wafer on which the warp adjustment layer was not laminated, and then a dicing ring was fixed to the warped bare wafer by means of the wafer processing tape. Thereafter, the warp adjustment layer was removed from the warped bare wafer.

[0272] Using a dicing apparatus (manufactured by DISCO, Model 6361), grooves 100 μm deep from the warped bare wafer were formed in a grid pattern (20 μm wide) on the entire surface (hereinafter referred to as one surface) from which the warp adjusting layer was removed.

[0273] Thereafter, a back grinding tape is bonded to one surface of the warped bare wafer, and the wafer processing tape is removed from the other surface (the surface opposite to the one surface) of the warped bare wafer.

[0274] Thereafter, the warped bare wafer was ground from the other surface side using a back grinder (manufactured by DISCO Corporation, model DGP8760) until the thickness of the warped bare wafer reached 55 μm (0.055 mm), and the obtained wafer was referred to as a warped wafer.

[0275] Specifically, chip floating was evaluated as follows.

[0276] First, a cold expansion unit is used to cut the bare wafer and the chip bonding layer under the conditions of an expansion temperature of -5°C, an expansion speed of 100 mm / sec, and an expansion amount of 12 mm to obtain a semiconductor chip with a chip bonding layer.

[0277] After that, the expansion was carried out at room temperature, an expansion speed of 1 mm / sec, and an expansion distance of 5 mm. Then, while maintaining the expansion state, the dicing die bonding film at the boundary portion with the outer edge of the bare wafer was thermally shrunk at a heating temperature of 200°C, a heating distance of 18 mm, and a rotation speed of 5° / sec.

[0278] Then, for the surface of the substrate layer of the cut die bonding film, the floating state of the semiconductor chip with the die bonding layer is photographed by microscope observation and binarized to calculate the floating area. Then, the case where the floating area is less than 4% is evaluated as 0, and the case where it is more than 4% is evaluated as ×.

[0279] (Evaluation of cutting properties)

[0280] A bare wafer (diameter 300 mm) and a dicing ring were attached to the dicing die-bonding film of Example 1. Thereafter, the bare wafer and the die-bonding layer were cut using a die separation apparatus DDS230 (manufactured by DISCO Corporation).

[0281] The bare wafer is cut into bare chips with a size of 3.2 mm in length×1.4 mm in width×0.025 mm in thickness.

[0282] Specifically, the cutting property was evaluated as follows.

[0283] First, a bare wafer and a chip bonding layer were cut by a cold expansion unit at an expansion temperature of -5°C, an expansion speed of 100 mm / sec, and an expansion amount of 14 mm to obtain a semiconductor chip with a chip bonding layer.

[0284] After that, the expansion was carried out at room temperature, an expansion speed of 1 mm / sec, and an expansion distance of 10 mm. Then, while maintaining the expansion state, the dicing die bonding film at the boundary portion with the outer edge of the bare wafer was thermally shrunk at a heating temperature of 200°C, a heating distance of 18 mm, and a rotation speed of 5° / sec.

[0285] Then, the cut portion of the semiconductor chip with the chip bonding layer was observed under a microscope, and the cut rate was calculated. Then, the case where the cut rate was 90% or more was evaluated as 0, and the case where the cut rate was less than 90% was evaluated as ×.

[0286] [Example 2]

[0287] The dicing tape and dicing die-bonding film of Example 2 were obtained in the same manner as in Example 1 except that the thickness of the base material layer was 80 μm.

[0288] In addition, about the dicing tape of Example 2, in the same manner as in Example 1, the tensile storage modulus at -5°C and the 30% tensile stress at -5°C and 23°C were measured.

[0289] Furthermore, the dicing die-bonding film of Example 2 was evaluated for die floating and cutting properties.

[0290] [Example 3]

[0291] The dicing tape and dicing die-bonding film of Example 3 were obtained in the same manner as in Example 1 except that the EVA constituting the B layer (center layer) of the base layer was Evaflex EV550 (manufactured by Mitsui DuPont Polychemical Co., Ltd.) and the base layer was 80 μm.

[0292] In addition, about the dicing tape of Example 3, in the same manner as in Example 1, the tensile storage modulus at -5°C and the 30% tensile stress at -5°C and 23°C were measured.

[0293] Furthermore, the dicing die-bonding film of Example 3 was evaluated for die floating and cutting properties.

[0294] [Example 4]

[0295] The dicing tape and dicing die-bonding film of Example 4 were obtained in the same manner as in Example 1 except that the resin of the B layer was made into a propylene-based elastomer (trade name: Vistamaxx 3980, manufactured by ExxonMobil Chemical Company).

[0296] In addition, about the dicing tape of Example 4, in the same manner as in Example 1, the tensile storage modulus at -5°C and the 30% tensile stress at -5°C and 23°C were measured.

[0297] Furthermore, the dicing die-bonding film of Example 4 was evaluated for die floating and cutting properties.

[0298] [Example 5]

[0299] The dicing tape and dicing die-bonding film of Example 5 were obtained in the same manner as in Example 1 except that the thickness of the base material layer was 80 μm and the thickness ratio of the base material layer was A layer:B layer:C layer=1:4:1.

[0300] In addition, about the dicing tape of Example 5, in the same manner as in Example 1, the tensile storage modulus at -5°C and the 30% tensile stress at -5°C and 23°C were measured.

[0301] Furthermore, about the dicing die-bonding film of Example 5, the die floating and the cutting property were evaluated.

[0302] [Example 6]

[0303] The dicing tape and dicing die-bonding film of Example 6 were obtained in the same manner as in Example 1 except that the metallocene PP constituting the A layer and the C layer (outer layer) of the base layer was WINTEC WMX03 (manufactured by Japan Polypropylene Co., Ltd.).

[0304] In addition, about the dicing tape of Example 6, in the same manner as in Example 1, the tensile storage modulus at -5°C and the 30% tensile stress at -5°C and 23°C were measured.

[0305] Furthermore, about the dicing die-bonding film of Example 6, the die floating and the cutting property were evaluated.

[0306] [Example 7]

[0307] The dicing tape and dicing die-bonding film of Example 7 were obtained in the same manner as in Example 1, except that the EVA resin of the layer B constituting the base layer was made into Ultrathene 651 (manufactured by Tosoh Corporation).

[0308] In addition, about the dicing tape of Example 7, in the same manner as in Example 1, the tensile storage modulus at -5°C and the 30% tensile stress at -5°C and 23°C were measured.

[0309] Furthermore, the dicing die-bonding film of Example 7 was evaluated for die floating and cutting properties.

[0310] [Example 8]

[0311] A dicing tape and a dicing die-bonding film of Example 8 were obtained in the same manner as in Example 1 except that the base material layer had a single-layer structure and the thickness of the base material layer was 125 μm.

[0312] The substrate layer was molded using a single-layer extrusion T-die molding machine. A propylene-based elastomer (trade name: Vistamaxx 3980, manufactured by ExxonMobil Chemical Company) was used as the resin for the substrate layer.

[0313] In addition, about the dicing tape of Example 8, in the same manner as in Example 1, the tensile storage modulus at -5°C and the 30% tensile stress at -5°C and 23°C were measured.

[0314] Furthermore, the dicing die-bonding film of Example 8 was evaluated for die floating and cutting properties.

[0315] [Example 9]

[0316] A dicing tape and a dicing die-bonding film of Example 9 were obtained in the same manner as in Example 8 except that the thickness of the base material layer was 100 μm.

[0317] In addition, about the dicing tape of Example 9, in the same manner as in Example 1, the tensile storage modulus at -5°C and the 30% tensile stress at -5°C and 23°C were measured.

[0318] Furthermore, the dicing die-bonding film of Example 9 was evaluated for die floating and cutting properties.

[0319] [Comparative Example 1]

[0320] A dicing tape and a dicing die-bonding film of Comparative Example 1 were obtained in the same manner as in Example 8, except that the resin of the base material layer was made into Evaflex EV250 (manufactured by Mitsui DuPont Polychemical Co., Ltd.).

[0321] In addition, about the dicing tape of Comparative Example 1, in the same manner as in Example 1, the tensile storage modulus at -5°C and the 30% tensile stress at -5°C and 23°C were measured.

[0322] Furthermore, the dicing die-bonding film of Comparative Example 1 was evaluated for die floating and cutting properties.

[0323] [Comparative Example 2]

[0324] A dicing tape and a dicing die-bonding film of Comparative Example 2 were obtained in the same manner as in Comparative Example 1 except that the thickness of the base material layer was 100 μm.

[0325] In addition, about the dicing tape of Comparative Example 2, in the same manner as in Example 1, the tensile storage modulus at -5°C and the 30% tensile stress at -5°C and 23°C were measured.

[0326] Furthermore, about the dicing die-bonding film of Comparative Example 2, chip floating and cutting properties were evaluated.

[0327] The following Table 1 shows the measurement results of the tensile storage modulus at -5°C and the tensile stress at -5°C and 23°C of the dicing tape of each example, and the evaluation results of the die lift and cutting property of the dicing die-bonding film of each example.

[0328]

Table 1

[0329]

[0330] As can be seen from Table 1, the values ​​of the tensile storage modulus at -5°C of the dicing tapes of Examples 1 to 9 were all 100 MPa or more, and the dicing die-bonding films of Examples 1 to 9 were excellent in cutting properties.

[0331] In addition, as can be seen from Table 1, the dicing die-bonding films of Examples 1 to 7 including the dicing tapes of Examples 1 to 7, that is, the dicing tapes having a three-layer structure as the base material layer, can all suppress chip floating.

[0332] In contrast, it was found that the values ​​of the tensile storage modulus at -5°C of the dicing tapes of Comparative Examples 1 and 2 were both lower than 100 MPa, and the dicing die-bonding films of Comparative Examples 1 and 2 had poor cutting properties and could not suppress chip floating.

[0333] It should be noted that although the results shown in Table 1 are about the dicing die-bonding film, it is expected that the same results as those shown in Table 1 can be obtained by using a dicing tape included in the dicing die-bonding film.

Claims

1. A dicing tape comprising an adhesive layer laminated on a base material layer, The substrate layer is a single layer or a laminated structure. When the substrate layer is a single-layer structure, the substrate layer is an elastomer layer, and the elastomer layer contains an α-olefin-based thermoplastic elastomer. When the substrate layer has a laminated structure, the substrate layer has an elastomer layer and a non-elastic layer, and has a structure in which the non-elastic layer is arranged on both sides of the elastomer layer, the elastomer layer contains an α-olefin-based thermoplastic elastomer, and the non-elastic layer contains a polypropylene resin that is a polymerization product obtained using a metallocene catalyst, The adhesive layer contains a radiation-curable adhesive as an adhesive, The radiation curing adhesive comprises an acrylic polymer and a compound having a polymerizable carbon-carbon double bond. The dicing tape has a tensile storage modulus at -5°C of 100 MPa or more.

2. The cutting tape according to claim 1, wherein: The 30% tensile stress at -5°C is 5.5 N / 10 mm or more.

3. The cutting tape according to claim 1 or 2, wherein: The 30% tensile stress at room temperature is 3.2 N / 10 mm or more.

4. The cutting tape according to claim 1, wherein: The ratio of the 30% tensile stress at -5°C to the 30% tensile stress at room temperature is 1.7 or more.

5. The cutting tape according to claim 2, wherein: The ratio of the 30% tensile stress at -5°C to the 30% tensile stress at room temperature is 1.7 or more.

6. The cutting tape according to claim 3, wherein: The ratio of the 30% tensile stress at -5°C to the 30% tensile stress at room temperature is 1.7 or more.

7. A dicing die bonding film comprising: A dicing tape having an adhesive layer laminated on a base layer, and a die bonding layer laminated on the adhesive layer of the dicing tape, The substrate layer is a single layer or a laminated structure. When the substrate layer is a single-layer structure, the substrate layer is an elastomer layer, and the elastomer layer contains an α-olefin-based thermoplastic elastomer. When the substrate layer has a laminated structure, the substrate layer has an elastomer layer and a non-elastic layer, and has a structure in which the non-elastic layer is arranged on both sides of the elastomer layer, the elastomer layer contains an α-olefin-based thermoplastic elastomer, and the non-elastic layer contains a polypropylene resin that is a polymerization product obtained using a metallocene catalyst, The adhesive layer contains a radiation-curable adhesive as an adhesive, The radiation curing adhesive comprises an acrylic polymer and a compound having a polymerizable carbon-carbon double bond. The dicing tape has a tensile storage modulus at -5°C of 100 MPa or more.

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