Method for manufacturing semiconductor device
By forming an insulating film on the annular convex and inclined portions of the semiconductor wafer and cutting and separation using the cutting tape, the problems of low yield and serious wafer damage in the prior art are solved, and a higher yield and lower damage risk are achieved.
Patent Information
- Application Number
- CN202311735930.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-09-14
- Filing Date
- 2023-12-15
- Publication Date
- 2025-03-14
AI Technical Summary
In the existing semiconductor device manufacturing method, it is difficult to effectively improve the yield rate, especially in the process of cutting and separation, it is easy to cause damage to the semiconductor wafer.
The first insulating film is formed on the annular convex and inclined portion of the semiconductor wafer, and the wafer is cut off with the help of the cutting tape, so that the annular convex and inclined portion are separated from the concave portion, and then separated from the cutting tape. By optimizing the thickness and area distribution of the insulating film, the adhesion force with the cutting tape is reduced and the damage to the semiconductor wafer is reduced.
The yield rate of semiconductor devices is improved, the damage of semiconductor wafers during cutting and separation is reduced, and the reliability of the manufacturing process is enhanced.
Smart Images
Figure CN119626896A_ABST
Abstract
Description
[0001] Related Applications
[0002] This application claims the priority of Japanese Patent Application No. 2023-149072 (filing date: September 14, 2023) as a basic application. The present application incorporates the entire contents of the basic application by reference. Technical Field
[0003] An embodiment of the present invention relates to a method for manufacturing a semiconductor device. Background Art
[0004] Development of power semiconductor devices designed for power control, including semiconductor elements such as MOSFET (Metal-Oxide-Semiconductor Field-Effect-Transistor) and IGBT (Insulated Gate Bipolar Transistor), is underway for a wide range of fields, including power generation and transmission, rotating machines such as pumps and blowers, power supply devices for communication systems and factories, railways using AC motors, electric vehicles, and household electrical products.
[0005] Generally, a semiconductor device is thinned so that a semiconductor wafer has a desired thickness. Examples of the thinning method include the Taiko process, wet etching, and dry etching. Summary of the invention
[0006] A semiconductor device of an embodiment and a method for manufacturing a semiconductor device of an embodiment have the following steps: a step of forming a first insulating film on an annular convex portion and an inclined portion of a semiconductor wafer, wherein the semiconductor wafer has a first surface and a second surface opposite to the first surface, an annular convex portion on the outer periphery of the first surface, a concave portion on the center side, and an inclined portion connecting the annular convex portion and the concave portion; a step of setting a dicing tape on the semiconductor wafer on the first surface side; a step of cutting the semiconductor wafer to separate the annular convex portion and the inclined portion from the concave portion; and a step of separating the separated annular convex portion and the inclined portion from the dicing tape.
[0007] According to the present embodiment, a method for manufacturing a semiconductor device with a high yield can be provided. BRIEF DESCRIPTION OF THE DRAWINGS
[0008] Figure 1 It is a flowchart of the manufacturing method of the semiconductor device of embodiment.
[0009] Figure 2 It is a cross-sectional view schematically showing the steps of a method for manufacturing a semiconductor device according to an embodiment.
[0010] Figure 3 It is a schematic plan view showing the steps of a method for manufacturing a semiconductor device according to an embodiment.
[0011] Figure 4 It is a cross-sectional view schematically showing the steps of a method for manufacturing a semiconductor device according to an embodiment.
[0012] Figure 5 It is a cross-sectional view schematically showing the steps of a method for manufacturing a semiconductor device according to an embodiment.
[0013] Figure 6 It is a cross-sectional view schematically showing the steps of a method for manufacturing a semiconductor device according to an embodiment.
[0014] Figure 7 It is a cross-sectional view schematically showing the steps of a method for manufacturing a semiconductor device according to an embodiment.
[0015] Figure 8 It is a flowchart of the manufacturing method of the semiconductor device of embodiment.
[0016] Fig. 9 It is a cross-sectional view schematically showing the steps of a method for manufacturing a semiconductor device according to an embodiment.
[0017] Fig.10 It is a cross-sectional view schematically showing the steps of a method for manufacturing a semiconductor device according to an embodiment.
[0018] Fig.11 It is a cross-sectional view schematically showing the steps of a method for manufacturing a semiconductor device according to an embodiment.
[0019] Fig.12 It is a cross-sectional view schematically showing the steps of a method for manufacturing a semiconductor device according to an embodiment.
[0020] Fig.13 It is a cross-sectional view schematically showing the steps of a method for manufacturing a semiconductor device according to an embodiment.
[0021] Fig.14 It is a cross-sectional view schematically showing the steps of a method for manufacturing a semiconductor device according to an embodiment.
[0022] Fig.15 It is a cross-sectional view schematically showing the steps of a method for manufacturing a semiconductor device according to an embodiment.
[0023] Fig.16 It is a cross-sectional view schematically showing the steps of a method for manufacturing a semiconductor device according to an embodiment.
[0024] Fig.17 It is a cross-sectional view schematically showing the steps of a method for manufacturing a semiconductor device according to an embodiment.
[0025] Fig.18 It is a cross-sectional view schematically showing the steps of a method for manufacturing a semiconductor device according to an embodiment.
[0026] Fig.19 It is a cross-sectional view schematically showing the steps of a method for manufacturing a semiconductor device according to an embodiment.
[0027] Fig. 20 It is a cross-sectional view schematically showing the steps of a method for manufacturing a semiconductor device according to an embodiment.
[0028] Fig.21 It is a partial schematic cross-sectional view of a semiconductor wafer and a first insulating film according to an embodiment. DETAILED DESCRIPTION
[0029] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following description, the same or similar components are denoted by the same reference numerals, and the description of the components already described may be omitted.
[0030] (First Embodiment)
[0031] The manufacturing method of the semiconductor device of the first embodiment has the following steps: a step of forming a first insulating film on the annular convex portion and the inclined portion of a semiconductor wafer (first step), wherein the semiconductor wafer has a first surface and a second surface opposite to the first surface, has an annular convex portion on the outer periphery of the first surface, has a concave portion on the center side, and has an inclined surface connecting the annular convex portion and the concave portion; a step of setting a dicing tape on the semiconductor wafer on the first surface side (second step); a step of cutting the semiconductor wafer to separate the annular convex portion and the inclined portion from the concave portion (third step); and a step of separating the separated annular convex portion and the inclined portion from the dicing tape (fourth step).
[0032] In the embodiment, the type and structure of the specific semiconductor device are not limited. The semiconductor device of the embodiment is, for example, an integrated circuit, a diode, or a transistor. The semiconductor device of the embodiment is, for example, a FET (field effect transistor), a MOSFET, an IGBT, a HEMT (high electron mobility transistor), or a Schottky barrier diode.
[0033] Figure 1 FIG. 1 is a flowchart of a method for manufacturing a semiconductor device according to a first embodiment. Figure 2 to Figure 7 Detailed cross-sectional views and top views showing the steps of the method for manufacturing the semiconductor device according to the first embodiment are shown.
[0034] Reference Figure 2 Schematic cross-sectional diagram of the process, Figure 3 The process diagram and Figure 4The first step of forming the first insulating film 2 on the annular convex portion C and the inclined portion B of the semiconductor wafer 1 is described with reference to the schematic cross-sectional view of the process. The semiconductor wafer 1 has a first surface X and a second surface Y opposite to the first surface X, and has an annular convex portion C on the outer periphery of the first surface X, a concave portion A on the center side, and an inclined portion B connecting the annular convex portion C and the concave portion A. In the first embodiment and other embodiments, the schematic cross-sectional view of each process is, for example, Figure 3 The process is schematically shown in a cross-sectional view taken along the line a-a' of the top view.
[0035] A first insulating film 2 is formed on the annular convex portion C and the inclined portion B of the first surface X of the semiconductor wafer 1 .
[0036] The semiconductor wafer 1 is a member in which a semiconductor element region is formed on a substrate whose center side is thinned by, for example, a TAIKO process, wet etching, dry etching, etc. The semiconductor wafer 1 is, for example, a circular wafer.
[0037] The semiconductor wafer 1 has a concave portion A, an inclined portion B, and an annular convex portion C from the center side toward the outer peripheral side. The inclined portion B connects the concave portion A and the annular convex portion C.
[0038] The side where the recessed portion A of the semiconductor wafer 1 exists is referred to as a first surface X (back surface). The surface of the semiconductor wafer 1 opposite to the first surface X is referred to as a second surface Y (front surface).
[0039] A semiconductor element region is formed in the recess A of the semiconductor wafer 1. The semiconductor wafer 1 is not particularly limited to Si, SiC, GaN, etc. The recess A is a flat surface or a substantially flat surface. The recess A preferably has no protrusions on the periphery (the connecting edge F between the recess A and the inclined portion B is circular or substantially circular).
[0040] Since the outer peripheral portion is thick, the strength of the recessed portion A on the center side is high even if the thickness is reduced. Since the strength is high, it is easy to process the semiconductor element region, electrode pad, etc.
[0041] In the first embodiment, the electrodes of the semiconductor device are not shown on the first surface X side and the second surface Y side of the semiconductor wafer 1, but a portion of the electrodes may be formed on the first surface X side and / or the second surface Y side of the semiconductor wafer 1 before the first process, or a portion of the electrodes may be formed on the first surface X side and / or the second surface Y side of the semiconductor wafer 1 between the first process and the second process before the first process.
[0042] There is an annular protrusion C thicker than the recessed portion A on the periphery of the semiconductor wafer 1. The semiconductor wafer 1 has a so-called rim shape. There is a flat surface D or / and a substantially flat surface D on the inclined portion B side of the annular protrusion C. The annular protrusion C has no protrusion on the center side (the boundary portion (connecting edge) E between the annular protrusion C and the inclined portion B is preferably circular or substantially circular). The flat surface D or / and the substantially flat surface D of the annular protrusion C is the surface other than the curved surface portion on the outer peripheral side of the annular protrusion C. There may also be concavities and convexities on the flat surface D or / and the substantially flat surface D of the annular protrusion C accompanying the formation of the recessed portion A.
[0043] The center side of the inclined portion B is connected to the recessed portion A. The outer peripheral side of the inclined portion B is connected to the annular convex portion C. The inclined portion B is inclined relative to the surface of the recessed portion A. The inclination angle R (taper angle) of the inclined portion B is the angle of the surface of the inclined portion B relative to the surface of the recessed portion A. The inclination angle R is adjusted when the recessed portion A is formed.
[0044] The tilt angle R is preferably 20[°] or more and 75[°] or less, and more preferably 30[°] or more and 60[°] or less. When the tilt angle R is small, the volume of the recess A tends to be small, and the ineffective area tends to increase. When the tilt angle R is large, the effective area can be increased. When the tilt angle R is close to a right angle, it is difficult to form the first insulating film 2 and is not preferred.
[0045] The inclined portion B has a surface similar to the side surface of a truncated cone. The surface of the inclined portion B is an inclined surface with fine concavities and convexities. The inclined portion B may have a surface having a curved surface or a step from the annular convex portion C side toward the concave portion A side.
[0046] exist Figure 1 The process schematically shows a cross-sectional view of a semiconductor wafer 1, and a first insulating film 2 is formed to obtain Figure 2 The first insulating film 2 can be formed by performing photolithography using a mask after being integrally formed on the first surface X by low-temperature plasma CVD (plasma-enhanced chemical vapor deposition). The first insulating film 2 can also be a film obtained by inkjet printing, a heat-cured resin film, a sealing material processed into the shape of the first insulating film 2, and a coating film. When a film obtained by inkjet printing, a heat-cured resin film, a sealing material processed into the shape of the first insulating film 2, and a coating film are used as the first insulating film 2, it is preferable to heat or sinter these films.
[0047] The temperature of the semiconductor wafer 1 when forming the first insulating film 2 by low-temperature plasma CVD is preferably 200 [° C.] or lower.
[0048] The first insulating film 2 is preferably an inorganic insulating film. The first insulating film 2 is preferably SiO 2 The first insulating film 2 may be made of SiO 2 A laminated film of two or more selected from the group consisting of a SiN film, a SiON film, and a SiN film. The first insulating film 2 may contain an organic substance such as a resin.
[0049] The first insulating film 2 is formed on the surface of the annular convex portion C on the first surface X side of the semiconductor wafer 1 and the inclined portion B. The first insulating film 2 is preferably formed on the boundary E (edge or corner) between the surface of the annular convex portion C on the first surface X side of the semiconductor wafer 1 and the inclined portion B.
[0050] The first insulating film 2 is bonded to the dicing tape 3 with a weaker bonding force than the first surface X of the semiconductor wafer 1. Therefore, the portion where the first insulating film 2 is formed and the dicing tape 3 are easily separable.
[0051] The first insulating film 2 is preferably formed on 40% or more and 100% or less of the area of the surface of the annular convex portion C on the first surface X side of the semiconductor wafer 1. The outer peripheral side of the annular convex portion C may be a curved surface and the first insulating film 2 may not be formed on this portion. The first insulating film 2 is preferably formed on 50% or more and 100% or less of the area of the flat surface D or / and the substantially flat surface D in the surface of the annular convex portion C on the first surface X side of the semiconductor wafer 1, more preferably on 60% or more and 100% or less, and further preferably on 70% or more and 100% or less.
[0052] In addition, Figure 2 In the component, the configuration in which the flat surface D or / and the substantially flat surface D of the annular protrusion C are exposed is also included in the embodiment. In this case, it is preferred that the first insulating film 2 is formed on 50% or more and 90% or less of the area of the flat surface D or / and the substantially flat surface D in the surface of the annular protrusion C on the first surface X side of the semiconductor wafer 1, more preferably the first insulating film 2 is formed on 60% or more and 90% or less, and further preferably the first insulating film 2 is formed on 70% or more and 90% or less. In this case, it is preferred that the first insulating film 2 is formed on 50% or more and 80% or less of the area of the flat surface D or / and the substantially flat surface D in the surface of the annular protrusion C on the first surface X side of the semiconductor wafer 1, more preferably the first insulating film 2 is formed on 60% or more and 80% or less, and further preferably the first insulating film 2 is formed on 70% or more and 80% or less.
[0053] The thickness of the first insulating film 2 on the annular protrusion C ( Figure 4 The distance between EG) is preferably greater than 10 [nm] and less than 3 [μm].
[0054] The thickness of the first insulating film 2 on the inclined portion B (the thickness of the first insulating film 2 on the inclined portion B, the average value of the thickness of the first insulating film 2 in the vertical direction from the surface of the inclined portion B) is preferably 10 [nm] or more and 3 [μm] or less.
[0055] The thickness of the first insulating film 2 on the annular convex portion C is preferably 1.0 times or more of the thickness of the first insulating film 2 on the inclined portion B, and more preferably 1.2 times or more and 3 times or less of the thickness of the first insulating film 2 on the inclined portion B.
[0056] The first insulating film 2 is preferably a film that is continuous from the annular convex portion C side toward the inclined portion B side. The thickness of the first insulating film 2 at the boundary E between the surface of the annular convex portion C and the inclined portion B is preferably 10 [nm] or more.
[0057] The first insulating film 2 is preferably formed on 1% to 100% of the area of the inclined portion B, more preferably 5% to 80%, and even more preferably 10% to 50%.
[0058] When the inclination angle R is less than 20[°] and less than 30[°], it is preferred to form the first insulating film 2 at more than 1% and less than 80% of the area of the inclined portion B, more preferably at more than 5% and less than 50%, and further preferably at more than 10% and less than 30%.
[0059] When the inclination angle R is greater than 30[°] and less than 75[°], it is preferred to form the first insulating film 2 at more than 1% and less than 100% of the area of the inclined portion B, more preferably at more than 20% and less than 80%, and further preferably at more than 30% and less than 50%.
[0060] Next, refer to Figure 5 The step (second step) of providing the dicing tape 3 on the semiconductor wafer 1 on the first surface X side will be described with reference to the schematic cross-sectional view of the step. The second step is performed between the first step and the third step.
[0061] exist Figure 4 In the illustrated example, a dicing tape is provided on the first surface X side of the semiconductor wafer 1 on which a component of the first insulating film 2 is formed.
[0062] The dicing tape 3 is selected appropriately according to the cutting method to be used in the subsequent cutting step. The dicing tape 3 is a tape for protecting and fixing the semiconductor wafer 1 in the subsequent cutting step.
[0063] The dicing tape 3 is in contact with the first insulating film 2 and the semiconductor wafer 1. In the case where an insulating film or a conductive film (not shown) is provided on the first surface X side of the semiconductor wafer 1, these insulating films or conductive films are in contact with the dicing tape 3. The dicing tape 3 is preferably in direct contact with the first insulating film 2. Including the case where an insulating film or a conductive film (not shown) is provided on the first surface X side of the semiconductor wafer 1, the connection method between the component having the first insulating film 2 formed on the first surface X side of the semiconductor wafer 1 and the dicing tape 3 is not limited to Figure 5 The process is shown in a cross-sectional diagram.
[0064] The area where the flat surface D or / and the substantially flat surface D of the annular protrusion C directly contacts the cutting belt 3 is preferably greater than 0% and less than 20% of the area of the flat surface D or / and the substantially flat surface D of the annular protrusion C, more preferably greater than 0% and less than 10%, further preferably greater than 0% and less than 5%, and further preferably greater than 0% and less than 3%.
[0065] The area where the flat surface D or / and the substantially flat surface D of the annular protrusion C directly contacts the cutting belt 3 is preferably greater than 1% and less than 20% of the area of the flat surface D or / and the substantially flat surface D of the annular protrusion C, more preferably greater than 1% and less than 10%, and further preferably greater than 1% and less than 5%.
[0066] Next, refer to Figure 6 The step (third step) of cutting the semiconductor wafer 1 to separate the annular convex portion C and the inclined portion B from the concave portion A will be described with reference to the schematic cross-sectional view of the step. The third step is performed between the second step and the fourth step.
[0067] For example, the semiconductor wafer 1 is cut by blade cutting or laser cutting. The cutting in the third step is not to separate the semiconductor device into individual chips. In the third step, the position of the concave portion A on the side of the inclined portion B is cut into a quasi-circular shape (circular or substantially circular). By cutting the semiconductor wafer 1, the donut-shaped component 1B in which the annular convex portion C and the inclined portion B are integrated is separated from the disc-shaped component 1A including the concave portion A of the semiconductor wafer 1.
[0068] Next, refer to Figure 5 as well as Figure 6 The step (fourth step) of separating the separated annular convex portion C and the inclined portion B from the dicing tape 3 will be described with reference to the schematic cross-sectional view of the step. The fourth step is performed after the third step.
[0069] Will Figure 5 The annular component (rim portion) 1B of the cut component is lifted in the direction of the arrow, so that the separated annular convex portion C and the inclined portion B of the annular component 1B are separated from the cutting belt 3.
[0070] By forming the first insulating film 2 on the flat surface D or / and the substantially flat surface D and the inclined portion B of the annular convex portion C, the annular convex portion C and the inclined portion B after separation as the annular component 1B can be separated with a weak force from the dicing tape 3. By separating with a weak force, it is possible to reduce damage such as cracks in the concave portion A of the disc-shaped component 1A of the semiconductor wafer 1 during separation.
[0071] From the viewpoint of reducing damage to the semiconductor wafer 1 on the side of the recessed portion A when peeling off the annular protrusion C and the inclined portion B of the semiconductor wafer 1 formed with a first insulating film from a die attach film, the inclination angle R is preferably greater than 20[°] and less than 75[°], and more preferably greater than 30[°] and less than 60[°].
[0072] From the viewpoint of reducing damage to the semiconductor wafer 1 on the recessed portion A side when peeling the annular protrusion C and the inclined portion B of the semiconductor wafer 1 formed with the first insulating film from the wafer adhesive film, the thickness of the first insulating film 2 on the annular protrusion C is preferably greater than 10 [nm] and less than 3 [μm].
[0073] From the viewpoint of reducing damage to the semiconductor wafer 1 on the recessed portion A side when peeling the annular convex portion C and the inclined portion B of the semiconductor wafer 1 formed with the first insulating film from the dicing tape 3, the thickness of the first insulating film 2 on the inclined portion B is preferably greater than 10 [nm] and less than 3 [μm].
[0074] The higher the average concavo-convex height of the annular convex portion C on the first surface X side is, the stronger the bonding force between the dicing tape 3 and the semiconductor wafer 1 is.
[0075] When the average unevenness height on the first surface X side of the annular convex portion C is greater than 5 [nm] and less than 30 [nm], from the viewpoint of reducing damage to the semiconductor wafer 1 on the recessed portion A side when the annular convexity C and the inclined portion B of the semiconductor wafer 1 formed with the first insulating film are peeled off from the dicing tape 3, when the average unevenness height on the first surface X side of the annular convex portion C is greater than 5 [nm] and less than 30 [nm], the thickness of the first insulating film 2 on the annular convex portion C is preferably greater than 50 [nm] and less than 3 [μm], more preferably greater than 100 [nm] and less than 2 [μm], and further preferably greater than 200 [nm] and less than 1 [μm].
[0076] When the average unevenness height on the first surface X side of the annular convex portion C is greater than 5 [nm] and less than 30 [nm], from the viewpoint of reducing damage to the semiconductor wafer 1 on the recessed portion A side when the annular convexity C and the inclined portion B of the semiconductor wafer 1 formed with the first insulating film are peeled off from the dicing tape 3, when the average unevenness height on the first surface X side of the annular convex portion C is greater than 5 [nm] and less than 30 [nm], the thickness on the inclined portion B of the first insulating film 2 is preferably greater than 50 [nm] and less than 3 [μm], more preferably greater than 100 [nm] and less than 2 [μm], and further preferably greater than 200 [nm] and less than 1 [μm].
[0077] When the average unevenness height on the first surface X side of the annular convex portion C is greater than 5 [nm] and less than 30 [nm], from the viewpoint of reducing damage to the semiconductor wafer 1 on the recessed portion A side when the annular convexity C and the inclined portion B of the semiconductor wafer 1 formed with the first insulating film are peeled off from the dicing tape 3, when the average unevenness height on the first surface X side of the annular convex portion C is greater than 5 [nm] and less than 30 [nm], the thickness of the first insulating film 2 on the annular convex portion C is preferably greater than 50 [nm] and less than 3 [μm], more preferably greater than 100 [nm] and less than 2 [μm], and further preferably greater than 200 [nm] and less than 1 [μm].
[0078] When the average unevenness height on the first surface X side of the annular convex portion C is greater than 5 [nm] and less than 30 [nm], from the viewpoint of reducing damage to the semiconductor wafer 1 on the recessed portion A side when the annular convexity C and the inclined portion B of the semiconductor wafer 1 formed with the first insulating film are peeled off from the dicing tape 3, when the average unevenness height on the first surface X side of the annular convex portion C is greater than 5 [nm] and less than 30 [nm], the thickness on the inclined portion B of the first insulating film 2 is preferably greater than 50 [nm] and less than 3 [μm], more preferably greater than 100 [nm] and less than 2 [μm], and further preferably greater than 200 [nm] and less than 1 [μm].
[0079] After the fourth step, a semiconductor device (eg, a bare chip) can be manufactured through any steps.
[0080] By adopting the semiconductor device manufacturing method of the embodiment, the separation property of the dicing tape 3 is improved, and damage to the semiconductor wafer 1 including the recessed portion A where the semiconductor element region is formed can be reduced, thereby contributing to improving the manufacturing yield of the semiconductor device.
[0081] (Second Embodiment)
[0082] The manufacturing method of the semiconductor device of the second embodiment has the following steps: a step of forming a first insulating film on the annular convex portion and the inclined portion of a semiconductor wafer (first step), wherein the semiconductor wafer has a first surface and a second surface opposite to the first surface, has an annular convex portion on the outer periphery of the first surface, has a concave portion on the center side, and has an inclined portion connecting the annular convex portion and the concave portion; a step of forming a first conductive film on the first surface on the inner peripheral side of the first insulating film (fifth step); a step of forming a second insulating film on the first insulating film and on the first conductive film (sixth step); a step of forming a second conductive film on the second surface side (seventh step); a step of removing the second insulating film (eighth step); a step of setting a dicing tape on the semiconductor wafer on the first surface side (second step); a step of cutting the semiconductor wafer to separate the annular convex portion and the inclined portion from the concave portion (third step); and a step of separating the separated annular convex portion and the inclined portion from the dicing tape (fourth step).
[0083] The second embodiment relates to a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device in the second embodiment is a modified example of the method for manufacturing a semiconductor device in the first embodiment. The method for manufacturing a semiconductor device in the second embodiment is a more specific method of the method for manufacturing a semiconductor device in the first embodiment. The description of the contents common to the first and second embodiments is omitted.
[0084] Figure 8 This is a flowchart of a method for manufacturing a semiconductor device according to the second embodiment. Figure 2 to Figure 7 A cross-sectional view schematically showing a process of manufacturing a semiconductor device according to the first embodiment and a plan view schematically showing a process.
[0085] Reference Figures 9 to 13 The process schematic cross-sectional view illustrates a process (first process) of forming a first insulating film 2 on an annular convex portion C and an inclined portion B of a semiconductor wafer 1, wherein the semiconductor wafer 1 has a first surface X and a second surface Y which is opposite to the first surface X, has an annular convex portion C on the outer periphery of the first surface X, has a recessed portion A on the center side, and has an inclined portion B connecting the annular convex portion C and the recessed portion A.
[0086] In the first step of the second embodiment, the first insulating film 2 is formed on the entire first surface X of the semiconductor wafer 1 and processed, so that the first insulating film 2 is formed on the annular convex portion C and the inclined portion B.
[0087] First, in Fig. 9 The first insulating film 2 is formed integrally on the first surface X of the component shown in the schematic cross-sectional view of the process, and a first insulating film 2 is obtained. Fig.10 The process schematically shows the components in a cross-sectional view. Fig. 9The component shown in the schematic cross-sectional view of the process has an electrode pad 4 and a protective film 5 on the second surface Y side.
[0088] The electrode pad 4 is, for example, a conductive metal film electrically connected to the semiconductor device. The electrode pad 4 is an electrode of the semiconductor device.
[0089] The protective film 5 is an insulating film covering the electrode pads 4. It is preferable that the electrode pads 4 are not exposed on the surface of the protective film 5. The protective film 5 is an insulating film mainly composed of an insulating resin such as polyethylene, naphthalene, polyolefin, or polyethylene terephthalate.
[0090] After the first insulating film 2 is formed entirely on the first surface X of the semiconductor wafer 1, a resist (mask) 6 is formed to obtain Fig.11 The first insulating film 2 is made of SiO by plasma CVD, for example. 2 Film formation: The film formation temperature is, for example, 200 [° C.] in consideration of the heat resistance of the protective film 5 .
[0091] Next, use Fig.11 The process schematically shows that the first insulating film 2 is processed by the resist 6 of the component, and the second insulating film 2 formed in the concave portion A and the inclined portion B of the semiconductor wafer 1 is removed to obtain Fig.12 For example, by wet etching, SiO 2 The first insulating film 2 of the film is processed to remove the first insulating film 2 at a portion where the resist 6 is not formed.
[0092] Next, remove Fig.12 The process schematically shows a cross-sectional view of the resist 6 of the component, obtaining Fig.13 The process schematically shows the components in a cross-sectional view.
[0093] Reference Figure 14-15 The step (fifth step) of forming the first conductive film 7 on the first surface X on the inner peripheral side of the first insulating film 2 will be described with reference to the schematic cross-sectional view of the step.
[0094] The fifth step is a step of forming the first conductive film 7 on the first surface X on the inner peripheral side of the first insulating film 2 where the first insulating film 2 is not formed. The fifth step is performed between the first step and the sixth step.
[0095] like Fig.14 As shown in the schematic cross-sectional diagram of the process, Fig.13 The protective film 5 of the component of the schematic cross-sectional view is removed by peeling the protective film 5. It is preferred that furnace annealing is performed after removing the protective film 5.
[0096] Then, in Fig.14The components shown in the schematic cross-sectional view of the process are formed by sputtering or the like on the first surface X of the first insulating film 2 on the inner peripheral side where the first insulating film 2 is not formed, thereby obtaining Fig.15 The process schematically shows the components in a cross-sectional view.
[0097] The first conductive film 7 is formed so as not to overlap with the first insulating film 2. The first insulating film 2 and the first conductive film 7 may be directly in contact with each other along the surface direction of the first surface X, or may be separated. Including the case where the first insulating film 2 and the first conductive film 7 are directly in contact with each other along the surface direction of the first surface X, it is preferred that the first conductive film 7 and the first insulating film 2 are in contact with each other along the stacking direction ( Fig.15 The first insulating film 2 is not stacked with the semiconductor wafer 1 in the stacking direction. When the first conductive film 7 is stacked on the first insulating film 2, the first conductive film 7 is easily peeled off from the interface of the stacked portion, which is not preferable.
[0098] The surface of the first insulating film 2 formed on the annular protrusion C facing the semiconductor wafer 1 side is preferably not in direct contact with the first conductive film 7 on the opposite side. In addition, it is preferred that the surface of the first insulating film 2 formed on the inclined portion B is not in direct contact with the first conductive film 7 on the opposite side to the surface of the first conductive film 7 facing the semiconductor wafer 1 side.
[0099] The distance between the first insulating film 2 and the first conductive film 7 in the plane direction of the first plane X is preferably 0.0 [mm] or more and 2.0 [mm] or less, and more preferably 0.0 [mm] or more and 1.0 [mm] or less.
[0100] From the viewpoint of forming the first conductive film 7 in a manner that the first conductive film 7 is not stacked on the first insulating film 2, the distance separating the first insulating film 2 and the first conductive film 7 along the surface direction of the first surface X is preferably greater than 0.1 [mm] and less than 2.0 [mm], and more preferably greater than 0.2 [mm] and less than 1.0 [mm].
[0101] It is preferable to use an outer peripheral mask covering the first insulating film 2 so that the first conductive film 7 is not stacked on the first insulating film 2. The outer peripheral mask has a circular opening, and the metal film is deposited in the region within the opening. The outer peripheral mask is, for example, a susceptor or a clamp.
[0102] The first conductive film 7 is preferably a continuous film having no openings and not divided.
[0103] Reference Fig.16 The step (sixth step) of forming the second insulating film 8 on the first insulating film 2 and the first conductive film 7 will be described with reference to the schematic cross-sectional view of the step.
[0104] The sixth step is a step of forming the second insulating film 8 on the entire first surface X side of the semiconductor wafer 1 on the first insulating film 2 and the first conductive film 7. The sixth step is performed between the fifth step and the seventh step.
[0105] exist Fig.15 The second insulating film 8 is formed on the components shown in the schematic cross-sectional view of the process. Before the sixth process is performed, the first insulating film 2 is formed on the annular convex portion C in the first process, and the annular convex portion C is fully covered by the insulating film. Therefore, the second insulating film 8 can be formed without paying too much attention to the coverage of the first insulating film 2 and the first conductive film 7.
[0106] Since the flat surface D of the annular convex portion C and / or the boundary E between the substantially flat surface D and the inclined portion B is covered by the first insulating film 2 , the second insulating film 8 is preferably formed so that the surface of the first conductive film 7 is not exposed.
[0107] The flat surface D of the annular convex portion C and / or the boundary portion E between the substantially flat surface D and the inclined portion B are covered by the first insulating film 2, so the second insulating film 8 is preferably formed to cover the surface of the semiconductor wafer 1 in the gap portion between the first insulating film 2 and the first conductive film 7. Fig.15 As shown in the schematic cross-sectional view of the process, the second insulating film 8 may also be filled in the gap between the first insulating film 2 and the first conductive film 7 .
[0108] The second insulating film 8 preferably includes an inorganic insulating film, a resin insulating film, or an insulating film of an inorganic insulator and a resin.
[0109] The second insulating film 8 is, for example, a coating film, but may be a film formed by other methods.
[0110] The first surface X side of the semiconductor wafer 1 is entirely covered by the first insulating film 2 and the second insulating film 8. Therefore, it is preferable to reduce or eliminate abnormal metal precipitation in the semiconductor wafer 1 and / or the first conductive film 7 in the subsequent eighth step. When the eighth step is omitted, the seventh step can be omitted.
[0111] When the fifth step is omitted, the second insulating film 8 is formed on the surface of the opening on the first surface X side of the semiconductor wafer 1 .
[0112] When electrodes are not formed on both surfaces of the semiconductor wafer 1 after the first insulating film 2 is formed, the fifth step, the sixth step, the seventh step, and the eighth step are omitted.
[0113] Reference Fig.17 The step (seventh step) of forming the second conductive film 9 on the second surface Y side will be described with reference to the schematic cross-sectional view of the step.
[0114] The seventh step is a step of forming the second conductive film 9 on the electrode pad 4 by electroless plating or the like on the second surface Y. The seventh step is performed between the sixth step and the eighth step.
[0115] Reference Fig.18 as well as Fig.19 The step (eighth step) of removing the second insulating film 8 is described with reference to the schematic cross-sectional view of the step.
[0116] The eighth step is a step of removing the second insulating film 8 on the side of the first surface X by peeling or the like. The eighth step is performed between the seventh step and the second step.
[0117] When the sixth step is performed, in the case where the second insulating film 8 is formed in the gap between the first insulating film 2 and the first conductive film 7, Fig.18 As shown in the schematic cross-sectional view of the process, the second insulating film 8 remains in the gap between the first insulating film 2 and the first conductive film 7. Fig.19 As shown in the schematic cross-sectional view of the process, the second insulating film 8 in the gap portion between the first insulating film 2 and the first conductive film 7 is removed.
[0118] Next, refer to Fig. 20 The step (second step) of providing the dicing tape 3 on the semiconductor wafer 1 on the first surface X side will be described with reference to the schematic cross-sectional view of the step. The second step is performed between the eighth step and the third step.
[0119] As in the first embodiment, the dicing tape 3 is adhered to the semiconductor wafer 1 on the first surface X side. Then, as in the first embodiment, the third step and the fourth step are performed to manufacture a semiconductor device.
[0120] By adopting the method for manufacturing a semiconductor device of the embodiment, the separation property of the dicing tape 3 is improved, and the damage to the semiconductor wafer 1 including the recessed portion A in which the semiconductor element region is formed can be reduced, thereby contributing to improving the yield rate of manufacturing semiconductor devices. In addition, the abnormal precipitation during the plating of the second conductive film 9 can be reduced, thereby contributing to improving the yield rate of manufacturing semiconductor devices.
[0121] (Third Embodiment)
[0122] The manufacturing method of the semiconductor device of the third embodiment has the following steps: a step of forming a first insulating film on the annular convex portion and the inclined portion of a semiconductor wafer (first step), wherein the semiconductor wafer has a first surface and a second surface opposite to the first surface, has an annular convex portion on the outer periphery of the first surface, has a concave portion on the center side, and has an inclined portion connecting the annular convex portion and the concave portion; a step of forming a first conductive film on the first surface on the inner peripheral side of the first insulating film (fifth step); a step of forming a second insulating film on the first insulating film and on the first conductive film (sixth step); a step of forming a second conductive film on the second surface side (seventh step); a step of removing the second insulating film (eighth step); a step of setting a dicing tape on the semiconductor wafer on the first surface side (second step); a step of cutting the semiconductor wafer to separate the annular convex portion and the inclined portion from the concave portion (third step); and a step of separating the separated annular convex portion and the inclined portion from the dicing tape (fourth step).
[0123] The third embodiment relates to a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device of the third embodiment is a modified example of the method for manufacturing a semiconductor device of the first embodiment and / or the second embodiment. The method for manufacturing a semiconductor device of the third embodiment is a more specific method of the method for manufacturing a semiconductor device of the first embodiment. The description of the contents common to the first to third embodiments is omitted.
[0124] In the description of the method for manufacturing a semiconductor device according to the third embodiment, the flowchart and the schematic cross-sectional views of the process of the method for manufacturing a semiconductor device according to the second embodiment are partially referred to.
[0125] Reference Fig. 9 as well as Fig.13 The process schematic cross-sectional view illustrates a process (first process) of forming a first insulating film 2 on an annular convex portion C and an inclined portion B of a semiconductor wafer 1, wherein the semiconductor wafer 1 has a first surface X and a second surface Y which is opposite to the first surface X, an annular convex portion C on the outer periphery of the first surface X, a concave portion A on the center side, and an inclined portion B connecting the annular convex portion C and the concave portion A.
[0126] exist Fig. 9 The components shown in the schematic cross-sectional view of the process are formed by inkjet forming a first insulating film 2, and obtaining Fig.13 The process schematically shows the components in a cross-sectional view.
[0127] Reference Fig.14 as well as Fig.15 The step (fifth step) of forming the first conductive film on the first surface on the inner peripheral side of the first insulating film is described with reference to the schematic cross-sectional view of the step.
[0128] like Fig.14As shown in the schematic cross-sectional diagram of the process, Fig.13 The protective film 5 of the component of the schematic cross-sectional view is removed by peeling or the like. After removing the protective film 5, preferably furnace annealing is performed to bake (cure) the first insulating film 2.
[0129] Then, in Fig.14 The components shown in the schematic cross-sectional view of the process are formed into a first conductive film 7 by sputtering, and a Fig.15 The process schematically shows the components shown in the cross-sectional view.
[0130] Then, the sixth to eighth steps and the second to fourth steps and the like can be performed to appropriately manufacture the semiconductor device.
[0131] Here, refer to Fig.21 The schematic partial cross-sectional view of the semiconductor wafer 1 will explain the unevenness of the flat surface D or / and the substantially flat surface D of the annular convex portion C common to the first embodiment, the second embodiment, and the third embodiment. Fig.21 yes Figure 3 A schematic cross-sectional view of a portion of the b-b' cross section.
[0132] exist Fig.21 In the partial schematic cross-sectional view of the semiconductor wafer 1 and the first insulating film 2, H1 indicates the unevenness height (average value) of the flat surface D or / and the substantially flat surface D of the annular convex portion C of the semiconductor wafer 1 itself, and H2 indicates the unevenness height (average value) of the flat surface D or / and the substantially flat surface D of the annular convex portion C after the first insulating film 2 is formed. When the inclined portion B and the concave portion A are formed by wet etching, the unevenness height H1 becomes larger.
[0133] Compared with the concave-convex height H1, the concave-convex height H2 is reduced. This is because, even if the thickness of the first insulating film 2 formed on the inclined surface of the concave-convex is the same, regardless of the shape of the upper and lower ends of the concave-convex, the cross section is made arc-shaped in a way that the first insulating film 2 at the bottom of the concave portion becomes thicker (the center of the arc is in the direction from the semiconductor wafer 1 toward the first insulating film 2 compared to the arc), and the cross section is made arc-shaped in a way that the first insulating film 2 at the top of the convex portion becomes thinner (the center of the arc is in the direction from the first insulating film 2 toward the semiconductor wafer 1 compared to the arc). In the case where the dicing tape 3 is provided on the entire annular convex portion C of the semiconductor wafer 1, since H1 is high, the adhesion with the dicing tape 3 is increased, and cracks are easily generated in the semiconductor wafer 1 of the concave portion A during the separation in the fourth step.
[0134] After forming the first insulating film 2, even if a portion of the uneven surface of the annular protrusion C of the semiconductor wafer 1 is exposed, the uneven height H2 of the flat surface D or / and the substantially flat surface D of the annular protrusion C is smaller than the uneven height H1, so the adhesion with the cutting tape 3 is reduced, and during the separation in the fourth step, the cracks on the semiconductor wafer 1 of the recess A are reduced.
[0135] In the embodiment, the first insulating film 2 is preferably formed also at the boundary E between the annular convex portion C and the inclined portion B due to the inclined portion B. Therefore, the adhesion between the annular convex portion C and the inclined portion B and the dicing tape 3 can be reduced.
[0136] In the embodiment, since the inclined portion B is preferably provided, the first insulating film 2 is also formed at the boundary portion E between the annular convex portion C and the inclined portion B. Therefore, abnormal precipitation can be prevented in the seventh step.
[0137] Furthermore, it is preferred that the second insulating film 8 is formed on the flat surface D of the annular protrusion C or / and the surface whose unevenness is mitigated by the first insulating film 2 , thereby further mitigating the unevenness of the surface and reducing the adhesion with the dicing tape 3 .
[0138] It can also be considered that when the inclination angle R is reduced, due to the gentle inclination, even if the first insulating film 2 is not formed, the above-mentioned unevenness can be appropriately alleviated by the second insulating film 8. However, when the inclination angle R is reduced, the area of the inclined portion B of the semiconductor wafer 1 observed from the first surface X side increases. As a result, the effective element area of the semiconductor wafer 1 is reduced, which is not economically preferred. In this case, the effective element area of the semiconductor wafer 1 can be increased by reducing the area of the flat surface D or / and the substantially flat surface D of the annular convex portion C, but in this case, since the annular convex portion C becomes smaller and has a rim shape, the strength of the semiconductor wafer 1 is reduced, so it is not practically preferred.
[0139] From the above viewpoints, the inclination angle R is preferably 20[°] or more and 75[°] or less, and more preferably 30[°] or more and 60[°] or less.
[0140] By adopting the configuration of the embodiment, it is possible to achieve well-balanced strength of the semiconductor wafer 1 , a large effective device region of the semiconductor wafer 1 , and reduction of cracks in the semiconductor wafer 1 when peeled from the dicing tape 3 , which is preferable.
[0141] By adopting the configuration of the embodiment, it is possible to obtain the above-mentioned effects and reduce abnormal precipitation when forming the second conductive film 9 .
[0142] Below, the technical solution of the instruction manual is attached.
[0143] Technical Solution 1
[0144] A method for manufacturing a semiconductor device, comprising the following steps:
[0145] A step of forming a first insulating film on the annular convex portion and the inclined portion of a semiconductor wafer, wherein the semiconductor wafer has a first surface and a second surface opposite to the first surface, the annular convex portion is formed on the outer periphery of the first surface, has a concave portion on the center side, and has the inclined portion connecting the annular convex portion and the concave portion;
[0146] a step of providing a dicing tape on the semiconductor wafer on the first surface side;
[0147] a step of cutting the semiconductor wafer to separate the annular convex portion and the inclined portion from the concave portion; and
[0148] and separating the separated annular convex portion and the inclined portion from the dicing tape.
[0149] Technical Solution 2
[0150] The method for manufacturing a semiconductor device according to technical solution 1, wherein:
[0151] The first insulating film is an inorganic film.
[0152] Technical Solution 3
[0153] The method for manufacturing a semiconductor device according to technical solution 1 or 2, wherein:
[0154] The thickness of the first insulating film on the annular protrusion is greater than or equal to 10 [nm] and less than or equal to 3 [μm].
[0155] Technical Solution 4
[0156] The method for manufacturing a semiconductor device according to any one of technical solutions 1 to 3, wherein:
[0157] The thickness of the first insulating film on the inclined portion is greater than or equal to 10 [nm] and less than or equal to 3 [μm].
[0158] Technical Solution 5
[0159] The method for manufacturing a semiconductor device according to any one of technical solutions 1 to 4, wherein:
[0160] The annular convex portion on the first surface side of the semiconductor wafer has a flat surface or / and a substantially flat surface,
[0161] The first insulating film is formed on 50% or more and 100% or less of the area of the flat surface or / and the substantially flat surface.
[0162] Technical Solution 6
[0163] The method for manufacturing a semiconductor device according to any one of technical solutions 1 to 5, wherein:
[0164] The annular convex portion on the first surface side of the semiconductor wafer has a flat surface or / and a substantially flat surface,
[0165] The first insulating film is formed on 50% or more and 90% or less of the area of the flat surface or / and the substantially flat surface.
[0166] Technical Solution 7
[0167] The method for manufacturing a semiconductor device according to any one of technical solutions 1 to 6, wherein:
[0168] The thickness of the first insulating film on the annular convex portion is 1.2 times or more and 3 times or less of the thickness of the first insulating film on the inclined portion.
[0169] Technical Solution 8
[0170] The method for manufacturing a semiconductor device according to any one of technical solutions 1 to 7, wherein:
[0171] The first insulating film is formed on 1% to 100% of the area of the inclined portion.
[0172] Technical Solution 9
[0173] The method for manufacturing a semiconductor device according to any one of technical solutions 1 to 8, wherein:
[0174] The inclination angle of the inclined portion is greater than or equal to 20[°] and less than or equal to 75[°].
[0175] Technical Solution 10
[0176] The method for manufacturing a semiconductor device according to any one of technical solutions 1 to 9, wherein:
[0177] When the inclination angle of the inclined portion is 20° or more and less than 30°, the first insulating film is formed on 1% or more and 80% or less of the area of the inclined portion B.
[0178] Technical Solution 11
[0179] The method for manufacturing a semiconductor device according to any one of technical solutions 1 to 10, wherein:
[0180] When the inclination angle of the inclined portion is 30° or more and 75° or less, the first insulating film is formed on 1% or more and 100% or less of the area of the inclined portion B.
[0181] Technical Solution 12
[0182] The method for manufacturing a semiconductor device according to any one of technical solutions 1 to 11, wherein:
[0183] When the average concavo-convex height on the first surface side of the annular convex portion is 5 [nm] or more and 30 [nm] or less, the thickness of the first insulating film on the annular convex portion is 50 [nm] or more and 3 [μm] or less.
[0184] Technical Solution 13
[0185] The method for manufacturing a semiconductor device according to any one of technical solutions 1 to 12, wherein:
[0186] When the average concavo-convex height on the first surface side of the annular convex portion is 5 [nm] or more and 30 [nm] or less, the thickness of the first insulating film on the inclined portion is 50 [nm] or more and 3 [μm] or less.
[0187] Technical Solution 14
[0188] The method for manufacturing a semiconductor device according to any one of technical solutions 1 to 14, wherein:
[0189] When the average unevenness height on the first surface side of the annular protrusion is greater than 5 [nm] and less than 30 [nm], the thickness of the first insulating film on the annular protrusion is greater than 50 [nm] and less than 3 [μm], and the thickness of the first insulating film on the inclined portion is greater than 50 [nm] and less than 3 [μm].
[0190] Technical Solution 15
[0191] The method for manufacturing a semiconductor device according to any one of technical solutions 1 to 14, wherein:
[0192] The first insulating film is formed entirely on the semiconductor wafer on the first surface side by plasma CVD,
[0193] The temperature of the semiconductor wafer when the first insulating film is formed by the plasma CVD is 200 [° C.] or less,
[0194] The first insulating film formed entirely is processed by wet etching using a resist.
[0195] Technical Solution 16
[0196] The method for manufacturing a semiconductor device according to any one of technical solutions 1 to 15, wherein the following step is included between the step of forming the first insulating film and the step of providing the dicing tape:
[0197] forming a first conductive film on the first surface on the inner peripheral side of the first insulating film;
[0198] forming a second insulating film on the first insulating film and the first conductive film;
[0199] forming a second conductive film on the second surface; and
[0200] A step of removing the second insulating film.
[0201] Technical Solution 17
[0202] The method for manufacturing a semiconductor device according to technical solution 16, wherein:
[0203] The first conductive film is formed by a sputtering method so as not to be stacked on the first insulating film.
[0204] Technical Solution 18
[0205] The method for manufacturing a semiconductor device according to technical solution 16 or 17, wherein:
[0206] The second conductive film is formed by electroless plating.
[0207] Technical Solution 19
[0208] The method for manufacturing a semiconductor device according to any one of technical solutions 16 to 18, wherein:
[0209] A distance between the first insulating film and the first conductive film in a surface direction of the inclined portion is greater than or equal to 0.0 [mm] and less than or equal to 2.0 [mm].
[0210] Technical Solution 20
[0211] The method for manufacturing a semiconductor device according to any one of technical solutions 16 to 19, wherein:
[0212] A distance between the first insulating film and the first conductive film in a surface direction of the inclined portion is greater than or equal to 0.1 [mm] and less than or equal to 2.0 [mm].
[0213] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included in the invention described in the claims and their equivalents.
Claims
1. A method for manufacturing a semiconductor device, wherein: The process is as follows: A step of forming a first insulating film on the annular convex portion and the inclined portion of a semiconductor wafer, wherein the semiconductor wafer has a first surface and a second surface opposite to the first surface, the annular convex portion is provided on the outer periphery of the first surface, the concave portion is provided on the center side, and the inclined portion connects the annular convex portion and the concave portion; a step of providing a dicing tape on the semiconductor wafer on the first surface side; a step of cutting the semiconductor wafer to separate the annular convex portion and the inclined portion from the concave portion; as well as and separating the separated annular convex portion and the inclined portion from the dicing tape.
2. The method for manufacturing a semiconductor device according to claim 1, wherein: The first insulating film is an inorganic film.
3. The method for manufacturing a semiconductor device according to claim 1, wherein: The thickness of the first insulating film on the annular protrusion is greater than or equal to 10 nm and less than or equal to 3 μm.
4. The method for manufacturing a semiconductor device according to claim 1, wherein: The thickness of the first insulating film on the inclined portion is greater than or equal to 10 nm and less than or equal to 3 μm.
5. The method for manufacturing a semiconductor device according to claim 1, wherein: The annular convex portion on the first surface side of the semiconductor wafer has a flat surface or / and a substantially flat surface, The first insulating film is formed on 50% or more and 100% or less of the area of the flat surface or / and the substantially flat surface.
6. The method for manufacturing a semiconductor device according to claim 1, wherein: The annular convex portion on the first surface side of the semiconductor wafer has a flat surface or / and a substantially flat surface, The first insulating film is formed on 50% or more and 90% or less of the area of the flat surface or / and the substantially flat surface.
7. The method for manufacturing a semiconductor device according to claim 1, wherein: The thickness of the first insulating film on the annular convex portion is 1.2 times or more and 3 times or less of the thickness of the first insulating film on the inclined portion.
8. The method for manufacturing a semiconductor device according to claim 1, wherein: The first insulating film is formed on an area not less than 1% and not more than 100% of an area of the inclined portion.
9. The method for manufacturing a semiconductor device according to claim 1, wherein: The inclined portion has an inclination angle of not less than 20° and not more than 75°.
10. The method for manufacturing a semiconductor device according to claim 1, wherein: When the inclination angle of the inclined portion is greater than or equal to 20° and less than 30°, the first insulating film is formed in an area greater than or equal to 1% and less than or equal to 80% of the area of the inclined portion (B).
11. The method for manufacturing a semiconductor device according to claim 1, wherein: When the inclination angle of the inclined portion is greater than or equal to 30° and less than or equal to 75°, the first insulating film is formed in an area greater than or equal to 1% and less than or equal to 100% of the area of the inclined portion (B).
12. The method for manufacturing a semiconductor device according to claim 1, wherein: When the average concavo-convex height on the first surface side of the annular convex portion is 5 nm to 30 nm, the thickness of the first insulating film on the annular convex portion is 50 nm to 3 μm.
13. The method for manufacturing a semiconductor device according to claim 1, wherein: When the average concavo-convex height on the first surface side of the annular convex portion is 5 nm to 30 nm, the thickness of the first insulating film on the inclined portion is 50 nm to 3 μm.
14. The method for manufacturing a semiconductor device according to claim 1, wherein: When the average concavo-convex height on the first surface side of the annular convex portion is greater than 5 nm and less than 30 nm, the thickness of the first insulating film on the annular convex portion is greater than 50 nm and less than 3 μm, and the thickness of the first insulating film on the inclined portion is greater than 50 nm and less than 3 μm.
15. The method for manufacturing a semiconductor device according to claim 1, wherein: The first insulating film is formed entirely on the semiconductor wafer on the first surface side by plasma CVD, The temperature of the semiconductor wafer when the first insulating film is formed by the plasma CVD is 200° C. or less, The first insulating film formed entirely is processed by wet etching using a resist.
16. The method for manufacturing a semiconductor device according to any one of claims 1 to 15, wherein: The following steps are provided between the step of forming the first insulating film and the step of providing the dicing tape: forming a first conductive film on the first surface on the inner peripheral side of the first insulating film; forming a second insulating film on the first insulating film and the first conductive film; forming a second conductive film on the second surface; and A step of removing the second insulating film.
17. The method for manufacturing a semiconductor device according to claim 16, wherein: The first conductive film is formed by a sputtering method so as not to be stacked on the first insulating film.
18. The method for manufacturing a semiconductor device according to claim 16, wherein: The second conductive film is formed by electroless plating.
19. The method for manufacturing a semiconductor device according to claim 16, wherein: A distance between the first insulating film and the first conductive film in a surface direction of the inclined portion is greater than or equal to 0.0 mm and less than or equal to 2.0 mm.
20. The method for manufacturing a semiconductor device according to claim 16, wherein: A distance between the first insulating film and the first conductive film in a surface direction of the inclined portion is greater than or equal to 0.1 mm and less than or equal to 2.0 mm.
Citation Information
Patent Citations
Water management method, water management system, and composite dam
JP2023149072A