Semiconductor structure and method for manufacturing the same

Abstract

The present invention discloses a semiconductor package and a method for forming the semiconductor package. One of the methods includes the following steps. A first die is provided, wherein the first die includes a first substrate, a first interconnect structure, and a first pad, the first interconnect structure is located on the first substrate, and the first pad is disposed on the first interconnect structure and electrically connected to the first interconnect structure. A first bonding dielectric layer is formed on the first die to cover the first die. A first bonding through hole is formed through the first bonding dielectric layer using a single damascene process to electrically connect the first interconnect structure.

Description

Technical Field

[0001] The embodiments of the present invention relate to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] In recent years, the semiconductor industry has experienced rapid growth due to the continued improvement in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) In large part, this increase in integration density is attributed to the continuous reduction in minimum feature size, which enables more components to be integrated into a given area.

[0003] These smaller electronic components also require smaller packages that occupy a smaller area compared to previous packages. Some types of semiconductor packages include quad flat pack (QFP), pin grid array (PGA), ball grid array (BGA), flip chip (FC), three-dimensional integrated circuit (3DIC), wafer level package (WLP) and package on package (PoP) devices. Some 3DICs are prepared by placing chips on top of semiconductor wafer-level chips. 3DICs provide increased integration density and other advantages (e.g., faster speed and higher bandwidth) due to the reduced length of the internal connections between the stacked chips. However, there are many challenges to address for 3DIC technology. Summary of the invention

[0004] A method for manufacturing a semiconductor structure according to an embodiment of the present invention comprises the following steps. A first tube core is provided, wherein the first tube core comprises a first substrate, a first interconnect structure and a first pad, the first interconnect structure is located on the first substrate, and the first pad is arranged on the first interconnect structure and is electrically connected to the first interconnect structure. A first bonding dielectric layer is formed on the first tube core to cover the first tube core. A first bonding via is formed through the first bonding dielectric layer using a single damascene process to electrically connect the first interconnect structure.

[0005] A method for manufacturing a semiconductor structure according to an embodiment of the present invention comprises the following steps. A first tube core is formed, wherein the first tube core comprises a first substrate, a first interconnect structure and a first effective pad, wherein the first interconnect structure is located on the first substrate, and the first effective pad is arranged on the first interconnect structure and electrically connected to the first interconnect structure. A first bonding dielectric layer is formed on the first tube core to cover the first tube core. A via hole and at least one dummy via hole are formed respectively penetrating the bonding dielectric layer using a single removal process. A first effective bonding via and at least one first dummy bonding via are formed in the via hole and the at least one dummy via hole, respectively, wherein the first effective bonding via is electrically connected to the first interconnect structure, and the at least one first dummy bonding via is electrically floating.

[0006] A semiconductor structure according to an embodiment of the present invention includes a first tube core and a second tube core. The first tube core includes a first bonding dielectric layer located on the first tube core and a first effective bonding through hole located in the first bonding dielectric layer. The second tube core includes a second bonding dielectric layer located on the second tube core and a second effective bonding through hole located in the second bonding dielectric layer. The first tube core and the second tube core are bonded by bonding the first effective bonding through hole and the second effective bonding through hole together and bonding the first bonding dielectric layer and the second bonding dielectric layer together. The first effective bonding through hole penetrates the first bonding dielectric layer, and the first effective bonding through hole has a continuously inclined side wall from the top to the bottom of the first effective bonding through hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the critical dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1A to Figure 1E is a cross-sectional view of a method of forming a three-dimensional integrated circuit (3DIC) structure according to some embodiments of the present disclosure.

[0009] Figure 2 is a cross-sectional view of a 3DIC structure according to some embodiments of the present disclosure.

[0010] Figure 3 is a cross-sectional view of a 3DIC structure according to some embodiments of the present disclosure.

[0011] FIG. 4A to FIG. 4E is a cross-sectional view of a method of forming a 3DIC structure according to some embodiments of the present disclosure.

[0012] Figure 5 It is shown Figure 4D Top view of the structure shown.

[0013] Fig. 6A is a cross-sectional view of a 3DIC structure according to some embodiments of the present disclosure and Figure 6B It is a top view of a first bonding through hole, a first dummy bonding through hole, a first pad, and a first dummy pad in a 3DIC structure. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description in which a second feature is formed "above" or "on" a first feature may include an embodiment in which the second feature is formed to be in direct contact with the first feature, and may also include an embodiment in which an additional feature may be formed between the second feature and the first feature so that the second feature may not be in direct contact with the first feature. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than representing the relationship between the various embodiments and / or configurations discussed in itself.

[0015] In addition, for ease of description, spatially relative terms such as "beneath", "below", "lower", "on", "over", "overlying", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figures to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be in other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0016] In addition, for ease of description, terms such as "first", "second", "third", "fourth", etc. may be used herein to describe similar or different elements or features shown in the figures, and the terms may be used interchangeably according to the order or context of the description.

[0017] Other features and processes may also be included. For example, a test structure may be included to help perform verification testing on a three-dimensional package or 3DIC device. The test structure may, for example, include a test pad formed in a redistribution layer or on a substrate so that the three-dimensional package or 3DIC can be tested, a probe and / or a probe card can be used, etc. Verification testing can be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein can be used in combination with a test method that includes intermediate verification of known good dies to improve yield and reduce costs.

[0018] Figure 1A to Figure 1E is a cross-sectional view of a method of forming a three-dimensional integrated circuit (3DIC) structure according to some embodiments of the present disclosure.

[0019] Reference Figure 1A , providing a first die 101. For example, the first die 101 includes a first semiconductor substrate 102, a first device layer 104, a first interconnect structure 106, a first passivation layer 112, and a first effective pad 114. In some embodiments, the first die 101 can be a semiconductor die, a semiconductor chip, a die of a semiconductor wafer, or a combination thereof. For example, the first die 101 can be an application-specific integrated circuit (ASIC) chip, an analog chip, a sensor chip, a wireless and radio frequency chip, a voltage regulator chip, or a memory chip.

[0020] In some embodiments, the first semiconductor substrate 102 may include silicon or other semiconductor materials. Alternatively, or additionally, the first semiconductor substrate 102 may include other elemental semiconductor materials, such as germanium. In some embodiments, the first semiconductor substrate 102 is made of a compound semiconductor, such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. In some embodiments, the first semiconductor substrate 102 is made of an alloy semiconductor, such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. In some embodiments, the first semiconductor substrate 102 includes an epitaxial layer. For example, the first semiconductor substrate 102 has an epitaxial layer overlying a bulk semiconductor.

[0021] In some embodiments, the first device layer 104 is formed on the first semiconductor substrate 102 by a front-end-of-line (FEOL) process. The first device layer 104 includes a variety of devices. In some embodiments, the device includes active components, passive components, or a combination thereof. The functions of the device may include memory, processors, sensors, amplifiers, power distribution, input and / or output circuit systems, etc. In some embodiments, the device may include an integrated circuit device. For example, the device is a transistor, a capacitor, a resistor, a diode, a photodiode, a fuse device, or other similar devices. In some embodiments, the first device layer 104 includes a gate structure, a source and drain region, and an isolation structure (e.g., a shallow trench isolation (STI) structure (not shown in the figure)). In the first device layer 104, various N-type metal-oxide semiconductor (NMOS) devices and / or P-type metal-oxide semiconductor (PMOS) devices (e.g., transistors or memories, etc.) may be formed, and the devices may be connected together to perform one or more functions.

[0022] Reference Figure 1A, the first interconnect structure 106 is formed on the first device layer 104. In detail, the first interconnect structure 106 includes a first insulating material 108 and a plurality of first metal features 110. The first metal feature 110 is formed in the first insulating material 108 and electrically connected to the first device layer 104. A portion of the first metal feature 110 (e.g., the topmost first metal feature 110) is exposed by the first insulating material 108. In some embodiments, the first insulating material 108 includes an inner-layer dielectric (ILD) layer and at least one inter-metal dielectric (IMD) layer. The ILD layer is disposed on the first device layer 104 and the IMD is disposed on the ILD layer. In some embodiments, the first insulating material 108 includes silicon oxide, silicon oxynitride, silicon nitride, a low dielectric constant (low-k) material, or a combination thereof. In some embodiments, the first insulating material 108 may be a single layer or multiple layers. In some embodiments, the first metal feature 110 includes a plug and a metal line. The plug may include a contact formed in the ILD layer and a via formed in the IMD layer. A contact is formed between the first device layer 104 and the bottommost metal line, and is connected to the first device layer 104 and the bottommost metal line. A via is formed between two metal lines, and is connected to the two metal lines. The first metal feature 110 may be made of tungsten (W), copper (Cu), a copper alloy, aluminum (Al), an aluminum alloy, or a combination thereof. In some alternative embodiments, a barrier layer (not shown) may be formed between the first metal feature 110 and the first insulating material 108 to prevent the material of the first metal feature 110 from migrating or diffusing into the first device layer 104. For example, the material of the barrier layer includes tantalum, tantalum nitride, titanium, titanium nitride, cobalt-tungsten (CoW), or a combination thereof. In some embodiments, the thickness of the first metal feature 110 adjacent to the first interconnect structure 106 is less than that adjacent to the first bonding structure 115 (e.g., Figure 1D The thickness of the first metal feature 110 adjacent to the first device layer 104 is determined by comparing the thickness of the first metal feature 110 adjacent to the first device layer 104. For example, the thickness of the first metal feature 110 directly connected to the first device layer 104 is less than the thickness of the first metal feature 110 directly connected to the first active pad 114. However, the present invention is not limited thereto.

[0023] Reference Figure 1A, a first passivation layer 112 is formed on the first interconnect structure 106. In some embodiments, the material of the first passivation layer 112 includes silicon oxide, silicon nitride, benzocyclobutene (BCB) polymer, polyimide (PI), polybenzoxazole (PBO) or a combination thereof and can be formed by a suitable process (e.g., spin coating, chemical vapor deposition (CVD) etc.). In some embodiments, the first passivation layer 112 can be a single-layer structure, a double-layer structure or a multi-layer structure.

[0024] Reference Figure 1A , a first effective pad 114 is formed on the first interconnect structure 106 and is electrically connected to the first interconnect structure 106. In this document, when an element is described as "effective", the element is functional and electrically connected to other elements of the die. In some embodiments, the first effective pad 114 further extends into the first passivation layer 112, thereby electrically connecting to the first metal feature 110. The first effective pad 114 and the first metal feature 110 may have the same or different materials. In some embodiments, the material of the first effective pad 114 may include a metal material, such as aluminum, copper, nickel, gold, silver, tungsten, or a combination thereof. The first effective pad 114 may be formed by the following steps: forming a through hole to expose the first metal feature 110; depositing a metal material layer to fill the opening and cover the first passivation layer 112 by a suitable process (such as an electrochemical plating process, CVD, atomic layer deposition (ALD), PVD, etc.); and then patterning the metal material layer. In some embodiments, for example, the thickness of the first effective pad 114 may be in the range of 1 μm to 3 μm.

[0025] Reference Figure 1B , a first bonding dielectric layer 116 is formed on the front side of the first die 101. The first bonding dielectric layer 116 is disposed on the first passivation layer 112 to cover the first effective pad 114. In some embodiments, the first bonding dielectric layer 116 covers the top surface and sidewalls of the first effective pad 114. In some embodiments, the first bonding dielectric layer 116 includes silicon oxide, silicon nitride, a polymer, or a combination thereof. The first bonding dielectric layer 116 is formed by a suitable process (e.g., spin coating, CVD, etc.). In some embodiments, the thickness of the first bonding dielectric layer 116 may be in the range of 2 μm to 8 μm.

[0026] Reference Figure 1C and Figure 1D, a through hole 118 is formed in the first bonding dielectric layer 116, and a first effective bonding through hole 120 is formed in the through hole 118. In some embodiments, the first effective bonding through hole 120 is formed by a single damascene process. Figure 1C As shown, a mask layer M is formed on the first bonding dielectric layer 116, and the mask layer M has an opening OP to expose a portion of the first bonding dielectric layer 116. Then, using the mask layer M as a mask, some portions of the first bonding dielectric layer 116 and the first passivation layer 112 are removed by a single removal process (e.g., a dry etching process or a wet etching process), thereby exposing the first metal feature 110. In some embodiments, the first bonding dielectric layer 116 and the first passivation layer 112 may have similar etching selectivities relative to the etchant used in the single removal process. In addition, the etching selectivities of the first passivation layer 112 and the first bonding dielectric layer 116 are different from the etching selectivities of the first metal feature 110. Therefore, during the single removal process, the top surface of the first metal feature 110 can be used as an etching stop layer. Therefore, the through hole 118 penetrates the first passivation layer 112 and the first bonding dielectric layer 116 and stops on the top surface of the first metal feature 110. Then, the mask layer M is removed. In some embodiments, the via hole 118 is integrally formed by a single process and only requires one mask. Therefore, the cost of forming the via hole 118 can be reduced.

[0027] In some embodiments, the entire sidewall SW of the through hole 118 is continuously inclined and no turning point or step is formed. Therefore, the through hole 118 may have a substantially smooth sidewall SW. In some embodiments, for example, the sidewall SW may taper relative to the bottom of the through hole 118 and the top surface of the first insulating material 108. In some embodiments, for example, the angle θ between the sidewall SW and the top surface of the first insulating material 108 may be in the range of 85 degrees to 89.9 degrees. In some embodiments, for example, the difference between the top width TCD and the bottom width BCD of the through hole 118 may be less than 5% of the top width TCD. For example, the width TCD of the through hole 118 may be in the range of 2μm to 10μm. In some alternative embodiments, the sidewall SW is substantially perpendicular to the bottom of the through hole 118 and the top surface of the first insulating material 108, and thus the through hole 118 may have a substantially constant width from top to bottom.

[0028] Then, if Figure 1DAs shown, the first effective bonding via 120 is formed in the via hole 118 to electrically connect the first metal feature 110 of the first interconnect structure 106. In some embodiments, for example, the first effective bonding via 120 includes a barrier layer 122 and a metal layer 124. The barrier layer 122 is disposed on the sidewall SW and the bottom of the via hole 118, and the metal layer 124 is disposed on the barrier layer 122 and filled into the via hole 118. For example, the barrier layer 122 may include titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN) or a combination thereof, and the metal layer 124 may include tungsten (W), copper (Cu), copper alloy, aluminum (Al), aluminum alloy or a combination thereof. In some embodiments, the first effective bonding via 120 may be formed as follows. First, a barrier material is formed on the surface of the first bonding dielectric layer 116 and the sidewall SW and the bottom of the via hole 118. In some embodiments, the barrier material may be formed by a suitable process (e.g., a chemical vapor deposition method, a sputtering method, or a plating method). Next, a conductive material is formed on the barrier material and the conductive material is filled into the through hole 118 having the barrier material thereon. The conductive material may be formed by a suitable process (e.g., an electrochemical plating process, CVD, atomic layer deposition (ALD), PVD, etc.). Thereafter, the barrier material and the conductive material outside the through hole 118 are removed by a planarization process (e.g., a chemical mechanical polishing (CMP) process), and thus a first effective bonding through hole 120 is formed in the through hole 118.

[0029] In some embodiments, the first effective bonding via 120 is disposed beside and spaced apart from the first effective pad 114, and the first effective bonding via 120 is electrically isolated from the first effective pad 114. In some embodiments, the first effective bonding via 120 is formed as a through hole, and the first effective bonding via 120 penetrates the first passivation layer 112 and the first bonding dielectric layer 116 to electrically connect the first metal feature 110 of the first interconnect structure 106. In some embodiments, the first effective bonding via 120 is directly disposed on and contacts the topmost first metal feature 110 of the first interconnect structure 106. For example, the top surface of the first effective bonding via 120 is substantially flush with the top surface of the first bonding dielectric layer 116, and the bottom surface of the first effective bonding via 120 is substantially flush with the bottom surface of the first passivation layer 112 and the top surface of the first insulating material 108. In some embodiments, for example, the top surface of the barrier layer 122 and the top surface of the metal layer 124 are substantially coplanar with the top surface of the first bonding dielectric layer 116, and the bottom surface of the barrier layer 122 is substantially coplanar with the bottom surface of the first passivation layer 112 and the top surface of the first insulating material 108. The height of the first effective bonding via 120 may be substantially the same as the total thickness of the first passivation layer 112 and the first bonding dielectric layer 116 (e.g., 2 μm to 8 μm).

[0030] The first effective joint through hole 120 has substantially the same profile as the through hole 118. In detail, the entire sidewall SW of the first effective joint through hole 120 is continuously inclined and no turning point or step is formed. That is, the entire sidewall SW of the first effective joint through hole 120 is substantially smooth. In some embodiments, for example, the sidewall SW of the first effective joint through hole 120 may be tapered relative to the bottom of the first effective joint through hole 120 and the top surface of the first insulating material 108. In some embodiments, for example, the angle θ between the sidewall SW and the top surface of the first insulating material 108 may be in the range of 85 degrees to 89.9 degrees. In some embodiments, for example, the difference between the top width TCD and the bottom width BCD of the first effective joint through hole 120 may be less than 5% of the top width TCD. For example, the top width TCD of the first effective joint through hole 120 may be in the range of 2μm to 10μm. In some alternative embodiments, the sidewall SW is substantially perpendicular to the bottom of the first operative bonding via 120 and the top surface of the first insulating material 108 , and thus the first operative bonding via 120 may have a substantially constant width from top to top.

[0031] After forming the first effective bonding via 120 in the first bonding dielectric layer 116, the first bonding structure 115 is formed. Figure 1DAs shown, the first semiconductor structure 100 is completed. The first semiconductor structure 100 includes a first die 101 and a first bonding structure 115 on the first die 101 .

[0032] Reference Figure 1E , providing a second semiconductor structure 200. In detail, the second semiconductor structure 200 includes a second die 201 and a second bonding structure 215 disposed on the front surface of the second die 201. In some embodiments, the second semiconductor structure 200 may include a semiconductor die, a semiconductor chip, a semiconductor wafer, or a combination thereof. For example, the second die 201 may be an application-specific integrated circuit (ASIC) chip, an analog chip, a sensor chip, a wireless and radio frequency chip, a voltage regulator chip, or a memory chip. The second die 201 and the first die 101 may be the same type of die or different types of dies.

[0033] In some embodiments, the second die 201 is similar to the first die 101. That is, the second die 201 includes a second semiconductor substrate 202, a second device layer 204, a second interconnect structure 206, a second passivation layer 212, and a second active pad 214, and the second interconnect structure 206 includes a second insulating material 208 and a plurality of second metal features 210. The configuration, materials, and formation method of the second die 201 are similar to those of the first die 101. Therefore, the details are omitted here. Figure 1E The first die 101 and the second die 201 are shown to have the same size. The term "size" herein refers to width, length or area. For example, Figure 1E As shown, the width of the second die 201 is equal to the width of the first die 101. However, the embodiments of the present invention are not limited thereto. In other embodiments, the size of the first die 101 is different from the size of the second die 201. For example, the first die 101 may be a wafer, and the second die 201 may be a die and is disposed on the wafer as a chip-on-wafer (CoW) structure.

[0034] In some embodiments, the second bonding structure 215 is similar to the first bonding structure 115. That is, the second bonding structure 215 includes a second bonding dielectric layer 216 and a second effective bonding via 220 located in the second bonding dielectric layer 216, and the second effective bonding via 220 may have a barrier layer 222 and a metal layer 224. The configuration, material, and formation method of the second bonding structure 215 are similar to those of the first bonding structure 115. Therefore, the details thereof are omitted here. Figure 1E The first effective combination through hole 120 and the second effective combination through hole 220 are of the same size. Figure 1EAs shown, the width of the second effective combination through hole 220 is equal to the width of the first effective combination through hole 120. However, the embodiments of the present invention are not limited thereto. In other embodiments, the size of the first effective combination through hole 120 is different from the size of the second effective combination through hole 220. In addition, in some alternative embodiments, the second combination structure 215 may be different from the first combination structure 115.

[0035] Reference Figure 1E , the second semiconductor structure 200 is further turned upside down and mounted on the first semiconductor structure 100. That is, the first die 101 and the second die 201 are combined face to face through the first bonding structure 115 and the second bonding structure 215 to form a three-dimensional integrated circuit (3DIC) structure 10 (or referred to as a die stacking structure). However, the embodiments of the present invention are not limited to this. In other embodiments, the first die 101 and the second die 201 can be combined face to back.

[0036] In some embodiments, before bonding the first die 101 to the second die 201, the first bonding structure 115 is aligned with the second bonding structure 215 so that the first effective bonding via 120 can be bonded to the second effective bonding via 220, and the first bonding dielectric layer 116 can be bonded to the second bonding dielectric layer 216. In some embodiments, the alignment of the first bonding structure 115 and the second bonding structure 215 can be achieved using an optical sensing method. After the alignment is achieved, the first bonding structure 115 and the second bonding structure 215 are bonded together by hybrid bonding to form a hybrid bonding structure 15.

[0037] The first bonding structure 115 and the second bonding structure 215 are hybrid bonded together by applying pressure and heat. It should be noted that hybrid bonding involves at least two types of bonding, including metal-to-metal bonding and non-metal-to-non-metal bonding (e.g., dielectric-to-dielectric bonding or fusion bonding). Figure 1E As shown, the hybrid bonding structure 15 includes a first effective bonding via 120 and a second effective bonding via 220 bonded together by metal-to-metal bonding, and a first bonding dielectric layer 116 and a second bonding dielectric layer 216 bonded together by non-metal-to-non-metal bonding.

[0038] Figure 2 is a cross-sectional view of a 3DIC structure according to some embodiments of the present disclosure. Figure 2 The 3DIC structure shown is similar to Figure 1E The 3DIC structures shown are similar, and thus the same reference numerals are used to refer to the same and similar components, and a detailed description thereof will be omitted herein. Figure 1E and Figure 2The difference between the 3DIC structures shown is the location of the bonding vias. Figure 1E In the illustrated embodiment, the bonding vias (e.g., the first effective bonding via 120 and the second effective bonding via 220) are designed to be directly electrically connected to the interconnect structures (e.g., the first interconnect structure 106 and the second interconnect structure 206). Figure 2 In the illustrated embodiment, in the 3DIC structure 10A, the first effective bonding via 120 is disposed on the first effective pad 114 and electrically connected to the first effective pad 114, and is further electrically connected to the interconnect structure 106 through the first effective pad 114. In some embodiments, the first effective bonding via 120 penetrates the first bonding dielectric layer 116 above the first effective pad 114 and directly contacts the first effective pad 114. The height of the first effective bonding via 120 may be in the range of 1 μm to 5 μm. The first effective bonding via 120 may be formed by a single damascene method. For example, a through hole is formed in the first bonding dielectric layer 116 to expose a portion of the first effective pad 114. Then, a first effective bonding via 120 is formed in the through hole to electrically connect the first effective pad 114. In some embodiments, the second semiconductor structure 200 is similar to the first semiconductor structure 100. However, the present invention is not limited thereto.

[0039] In some alternative embodiments, such as Figure 3As shown, in the 3DIC structure 10B, the first bonding structure 115 may include a plurality of first effective bonding vias 120a, 120b located in the first bonding dielectric layer 116. The first effective bonding via 120a may be disposed on the first metal feature 110 of the first interconnect structure 106 and directly contact the first metal feature 110 of the first interconnect structure 106. The first effective bonding via 120b may be disposed on the first effective pad 114 and directly contact the first effective pad 114. In some embodiments, the height of the first effective bonding via 120a from top to bottom is greater than the height of the first effective bonding via 120b from top to bottom. The top surfaces of the first effective bonding vias 120a, 120b are substantially flush with the top surface of the first bonding dielectric layer 116. In some embodiments, the first effective bonding via 120a and the first effective bonding via 120b may be formed simultaneously using a single damascene method using the same mask. During the single damascene method, the first effective pad 114 and the first metal feature 110 are used as an etch stop layer. In some embodiments, the second bonding structure 215 may be similar to the first bonding structure 115. That is, the second bonding structure 215 may include a plurality of second effective bonding vias 220a, 220b located in the second bonding dielectric layer 216. For example, the second effective bonding via 220a may be disposed on the second metal feature 210 of the second interconnect structure 206 and directly contact the second metal feature 210 of the second interconnect structure 206, and the second effective bonding via 220b may be disposed on the second effective pad 214 and directly contact the second effective pad 214. After bonding, the first effective bonding vias 120a, 120b may be bonded to the second effective bonding vias 220a, 220b, respectively. However, the present invention is not limited thereto.

[0040] FIG. 4A to FIG. 4E is a cross-sectional view of a method of forming a 3DIC structure according to some embodiments of the present disclosure. Figure 5 It is shown Figure 4D A top view of the structure is shown, wherein the first bonding dielectric layer 116 is omitted. FIG. 4A to FIG. 4E The steps shown are Figure 1A to Figure 1E The steps shown are similar, and thus the same reference numerals are used to refer to the same and similar components, and a detailed description thereof will be omitted herein. FIG. 4A to FIG. 4E The steps shown are Figure 1A to Figure 1E The difference between the steps shown is the formation of the dummy elements and is explained below.

[0041] Reference Figure 4A, providing a first die 101. In some embodiments, for example, the first die 101 includes a first semiconductor substrate 102, a first device layer 104, a first interconnect structure 106, a plurality of first dummy features 130, a first passivation layer 112, and a first active pad 114. In some embodiments, the first dummy feature 130 is formed next to the first metal feature 110 of the first interconnect structure 106. In this document, when an element is described as "dummy", the element is electrically floating or electrically isolated from other elements. For example, as Figure 4A As shown, first dummy feature 130 is electrically floating.

[0042] In some embodiments, the first dummy feature 130 is at substantially the same level as the topmost first metal feature 110. That is, the top of the first dummy feature 130 and the top of the topmost first metal feature 110 are substantially coplanar with the top surface of the first insulating material 108. In some embodiments, the material of the first dummy feature 130 and the material of the first metal feature 110 may be the same. In some alternative embodiments, the material of the first dummy feature 130 may be different from the material of the first metal feature 110. In some embodiments, the first dummy feature 130 and the first metal feature 110 are formed simultaneously using the same mask. In some alternative embodiments, the first dummy feature 130 and the first metal feature 110 are formed successively. In some embodiments, for example, the width of the first dummy feature 130 may be less than the width of the topmost first metal feature 110. However, in some alternative embodiments, the width of the first dummy feature 130 may be substantially the same as or greater than the width of the topmost first metal feature 110.

[0043] In some embodiments, Figure 5 As shown, a plurality of first dummy features 130 and the topmost first metal feature 110 may form an array, and for example, a plurality of first dummy features 130 surround the topmost first metal feature 110. That is, the topmost first metal feature 110 may be disposed at the center of the array formed by arranging the plurality of first dummy features 130 and the topmost first metal feature 110. In some embodiments, in a direction (e.g., the x-direction or the y-direction), the distance D1 between the first dummy features 130 and the topmost first metal feature 110 may be smaller than the distance D2 between the first dummy features 130. However, the present invention is not limited thereto. In some embodiments, for example, the aforementioned distance D1 may be in the range of 3 μm to 10 μm.

[0044] Reference Figure 4B, a first bonding dielectric layer 116 is formed on the first die 101. Next, a mask layer M is formed on the first bonding dielectric layer 116, and the mask layer M includes a plurality of openings OP1 and OP2. The openings OP1 and OP2 expose the first bonding dielectric layer 116. In some embodiments, the opening OP1 is disposed corresponding to the topmost first metal feature 110, and the opening OP2 is disposed corresponding to the first dummy feature 130.

[0045] Reference Figure 4C , a through hole 118 and a plurality of dummy through holes 132 are formed in the first bonding dielectric layer 116 and the first passivation layer 112. In some embodiments, the mask layer M is used as a mask to remove some portions of the first bonding dielectric layer 116 and the first passivation layer 112 exposed by the openings OP1 and OP2, thereby forming the through hole 118 and the dummy through hole 132. In other words, the through hole 118 and the dummy through hole 132 can be formed simultaneously using the same mask and a single removal process. Since the etching selectivity of the topmost first metal feature 110 and the first dummy feature 130 is similar and different from the etching selectivity of the first bonding dielectric layer 116 and the first passivation layer 112, the removal process can stop at the top of the topmost first metal feature 110 and the first dummy feature 130. Then, the mask layer M is removed. In some embodiments, for example, the through hole 118 exposes the topmost first metal feature 110, and the dummy through hole 132 exposes the first dummy feature 130, respectively. In some embodiments, similar to the through hole 118 described in the aforementioned embodiments, the entire sidewall SW of the dummy through hole 132 is continuously inclined and no turning point or step is formed. Therefore, the dummy through hole 132 may have a substantially smooth sidewall SW. In some embodiments, for example, the sidewall SW of the dummy through hole 132 may be tapered relative to the bottom of the dummy through hole 132 and the bottom surface of the first passivation layer 112. In some embodiments, for example, the width of the dummy through hole 132 may be less than the width of the through hole 118. However, in some alternative embodiments, the width of the dummy through hole 132 may be substantially the same as or greater than the width of the through hole 118.

[0046] Reference Figure 4D, a first effective bonding via 120 and a plurality of first dummy bonding vias 134 are formed in the through hole 118 and the dummy through hole 132, respectively. In some embodiments, the first dummy bonding via 134 may be formed simultaneously with the first effective bonding via 120, and thus the first dummy bonding via 134 may have a configuration similar to, substantially the same as, or the same as that of the first effective bonding via 120. For example, in some embodiments, the first effective bonding via 120 may have a barrier layer 122 and a metal layer 124, and the first dummy bonding via 134 may have a barrier layer 136 and a metal layer 138. In some embodiments, the method of forming the first effective bonding via 120 and the first dummy bonding via 134 may include the following steps. First, a barrier material is formed on the exposed surfaces of the first bonding dielectric layer 116, the through hole 118, and the dummy through hole 132. Next, a metal material is formed on the top surface of the barrier material and the metal material is filled into the through hole 118 and the dummy through hole 132. Afterwards, the barrier material and the conductive material outside the through hole 118 and the dummy through hole 132 are removed by a planarization process (e.g., a CMP process), and the first effective bonding through hole 120 and the first dummy bonding through hole 134 are formed in the through hole 118 and the dummy through hole 132, respectively. In some embodiments, the first effective bonding through hole 120 and the first dummy bonding through hole 134 are formed by a single damascene process using the same mask. In some embodiments, similar to the first effective bonding through hole 120 described in the aforementioned embodiment, the entire sidewall SW of the first dummy bonding through hole 134 is continuously inclined and no turning point or step is formed. Therefore, the first dummy bonding through hole 134 may have a substantially smooth sidewall SW. In some embodiments, for example, the sidewall SW of the first dummy bonding via 134 may be tapered relative to the bottom of the via hole 118 and the bottom surface of the first passivation layer 112 .

[0047] In some embodiments, Figure 4D and Figure 5 As shown, the first effective bonding via 120 is disposed on the topmost first metal feature 110 of the first interconnect structure 106 and electrically connected to the topmost first metal feature 110 of the first interconnect structure 106, and the first dummy bonding vias 134 are respectively disposed on the first dummy features 130 and electrically isolated from the first interconnect structure 106. In some embodiments, the first dummy bonding vias 134 can be electrically connected to the electrically floating first dummy features 130. In some embodiments, for example, the width of the first dummy bonding via 134 can be less than the width of the first effective bonding via 120. However, in some alternative embodiments, the width of the first dummy bonding via 134 can be substantially the same as or greater than the width of the first effective bonding via 120.

[0048] In some embodiments, Figure 5As shown, a plurality of first dummy bonding through holes 134 and a first effective bonding through hole 120 may be arranged in an array, and for example, a plurality of first dummy bonding through holes 134 surround the first effective bonding through hole 120. That is, the first effective bonding through hole 120 may be disposed at the center of the array formed by arranging a plurality of first dummy bonding through holes 134 and the first effective bonding through hole 120. In some embodiments, in a direction (e.g., the x direction or the y direction), the distance D3 between the first dummy bonding through hole 134 and the first effective bonding through hole 120 may be less than the distance D4 between the first dummy bonding through holes 134. However, the present invention is not limited thereto. In some embodiments, for example, the aforementioned distance D3 may be in the range of 1 μm to 8 μm. In some embodiments, by designing the first dummy bonding through hole 134 next to the first effective bonding through hole 120, the load effect of the planarization process during the formation of the first effective bonding through hole 120 may be reduced.

[0049] After forming the first effective bonding via 120 and the first dummy bonding via 134 in the first bonding dielectric layer 116, the first bonding structure 115 is formed. Figure 4D As shown, the first semiconductor structure 100 is completed. The first semiconductor structure 100 includes a first die 101 and a first bonding structure 115 .

[0050] Reference Figure 4E , providing a second semiconductor structure 200 and bonding the second semiconductor structure 200 to Figure 4D The first semiconductor structure 100 is shown. In some embodiments, the second semiconductor structure 200 includes a second die 201 and a second bonding structure 215. In some embodiments, the second die 201 may be similar to the first die 101, and the second bonding structure 215 may be similar to the first bonding structure 115. For example, the second dummy bonding vias 234 are respectively disposed on the second dummy features 230 and electrically connected to the second dummy features 230, and the second effective bonding vias 220 are disposed on the top second metal feature 210 and electrically connected to the top second metal feature 210. In some embodiments, the second dummy bonding vias 234 may have a barrier layer 236 and a metal layer 238.

[0051] In some embodiments, the first die 101 and the second die 201 are combined together by hybrid bonding to form a 3DIC structure 10C. Figure 4E As shown, the hybrid bonding structure 15 includes the first effective bonding via 120 and the second effective bonding via 220 and the first dummy bonding via 134 and the second dummy bonding via 234 bonded together by metal-to-metal bonding, and the first bonding dielectric layer 116 and the second bonding dielectric layer 216 bonded together by non-metal-to-non-metal bonding.

[0052] Fig. 6A is a cross-sectional view of a 3DIC structure according to some embodiments of the present disclosure, and Figure 6B It is a top view of a first bonding through hole, a first dummy bonding through hole, a first pad, and a first dummy pad in a 3DIC structure. Fig. 6A and Figure 6B The 3DIC structure shown is similar to Figure 4E and Figure 5 The 3DIC structures shown are similar, and thus the same reference numerals are used to refer to the same and similar components, and a detailed description thereof will be omitted herein. Fig. 6A and Figure 6B The 3DIC structure shown is similar to Figure 4E and Figure 5 The difference between the 3DIC structures shown is the location of the bonding vias and the formation of dummy pads. Figure 4E and Figure 5 In the illustrated embodiment, the bonding vias (e.g., the first effective bonding via 120 and the second effective bonding via 220) and the dummy bonding vias (e.g., the first dummy bonding via 134 and the second dummy bonding via 234) are designed to be electrically connected to the interconnect structures (e.g., the first interconnect structures 106 and the second interconnect structures 206) and the dummy features (e.g., the first dummy features 130 and the second dummy features 230). However, in Fig. 6A and Figure 6B In the illustrated embodiment, in the 3DIC structure 10D, the first semiconductor structure 100 further includes a plurality of first dummy pads 140 located next to the first effective pads 114. The first effective pads 114 are electrically connected to the first interconnect structure 106, while the first dummy pads 140 are electrically floating and isolated from the first die 101. In some embodiments, the first dummy pads 140 are at substantially the same level as the first effective pads 114. In other words, the tops of the first dummy pads 140 and the tops of the first effective pads 114 are substantially coplanar with each other. In some alternative embodiments, the dummy features 130 may be omitted.

[0053] In some embodiments, the first effective bonding via 120 is disposed on the first effective pad 114 and electrically connected to the first effective pad 114, and the first dummy bonding vias 134 are respectively disposed on the first dummy pads 140 and electrically isolated from the first die 101. In some embodiments, the material of the first dummy pad 140 may include a metal material, such as aluminum, copper, nickel, gold, silver, tungsten, or a combination thereof. In some embodiments, the material of the first dummy pad 140 may have an etching selectivity similar to that of the material of the first effective pad 114 relative to the etchant used in the formation process of the through-hole holes of the first effective bonding via 120 and the first dummy bonding via 134. In some embodiments, the first dummy pad 140 is formed simultaneously with the first effective pad 114. In some alternative embodiments, the first dummy pad 140 is formed successively with the first effective pad 114. In some embodiments, for example, the width of the first dummy pad 140 may be less than the width of the first effective pad 114. However, in some alternative embodiments, the width of the first dummy pad 140 may be substantially the same as or greater than the width of the first effective pad 114 .

[0054] In some embodiments, Figure 6B As shown, a plurality of first dummy pads 140 and a first effective pad 114 may be configured into an array, and for example, a plurality of first dummy pads 140 surround the first effective pad 114. That is, the first effective pad 114 may be disposed in the center of the array formed by arranging a plurality of first dummy pads 140 and a first effective pad 114. In some embodiments, the distance between the first dummy pad 140 and the first effective pad 114 may be substantially smaller than the distance between the first dummy pads 140. However, the present invention is not limited thereto. In some embodiments, for example, the distance between the first dummy pad 140 and the first effective pad 114 may be in the range of 1 μm to 8 μm. In some embodiments, the second semiconductor structure 200 is similar to the first semiconductor structure 100. That is, the second semiconductor structure 200 has a plurality of second dummy pads 240 and a plurality of second dummy bonding vias 234. However, the present invention is not limited thereto. In some embodiments, as Fig. 6A As shown, the hybrid bonding structure 15 includes the first effective bonding via 120 and the second effective bonding via 220 and the first dummy bonding via 134 and the second dummy bonding via 234 bonded together by metal-to-metal bonding, and the first bonding dielectric layer 116 and the second bonding dielectric layer 216 bonded together by non-metal-to-non-metal bonding.

[0055] In some embodiments, the bonding vias penetrating the bonding dielectric layer are formed by a single damascene method. In other words, the through hole for the bonding via is formed by a single removal process using only one mask. Therefore, compared with the conventional conductive bonding structure including the bonding via and the bonding pad, no process and mask for forming the bonding pad are required. Therefore, the process of forming the bonding structure is simplified and the cost of forming the bonding structure is reduced. In addition, in some embodiments, in order to improve process control, a plurality of dummy bonding vias may be formed next to the bonding vias. In addition, a plurality of dummy elements (such as dummy features or dummy pads) may be formed below the dummy bonding vias, and the plurality of dummy elements may be used as an etch stop layer during the formation of the dummy bonding vias. In some embodiments, the dummy bonding vias may be formed simultaneously with the bonding vias using the same mask, and therefore time and cost will not be significantly increased.

[0056] According to some embodiments, a method for manufacturing a semiconductor structure includes the following steps: providing a first die, wherein the first die includes a first substrate, a first interconnect structure, and a first pad, wherein the first interconnect structure is located on the first substrate, and the first pad is disposed on the first interconnect structure and electrically connected to the first interconnect structure. forming a first bonding dielectric layer on the first die to cover the first die. forming a first bonding via penetrating the first bonding dielectric layer using a single damascene process to electrically connect the first interconnect structure.

[0057] According to some embodiments, forming the first bonding via includes: forming a mask layer above the first bonding dielectric layer, wherein the mask layer has an opening to expose a portion of the first bonding dielectric layer; using the mask layer as a mask to partially remove the first bonding dielectric layer to form a through-hole; removing the mask layer; forming a conductive material in the through-hole; and removing the conductive material outside the through-hole.

[0058] According to some embodiments, the first combining via directly contacts the first interconnect structure.

[0059] According to some embodiments, the first bonding via directly contacts the first pad.

[0060] According to some embodiments, the first combining through hole is not formed with a turning point.

[0061] According to some embodiments, it also includes: providing a second tube core, wherein the second tube core has a second bonding via and a second bonding dielectric layer; and bonding the first tube core and the second tube core by bonding the first bonding via and the second bonding via together and bonding the first bonding dielectric layer and the second bonding dielectric layer together.

[0062] According to some embodiments, a method for manufacturing a semiconductor structure includes the following steps. A first tube core is formed, wherein the first tube core includes a first substrate, a first interconnect structure and a first effective pad, the first interconnect structure is located on the first substrate, and the first effective pad is arranged on the first interconnect structure and is electrically connected to the first interconnect structure. A first bonding dielectric layer is formed on the first tube core to cover the first tube core. A through hole and at least one dummy through hole are formed using a single removal process to penetrate the bonding dielectric layer respectively. A first effective bonding via and at least one first dummy bonding via are formed in the through hole and the at least one dummy through hole, respectively, wherein the first effective bonding via is electrically connected to the first interconnect structure, and the at least one first dummy bonding via is electrically floating.

[0063] According to some embodiments, forming the through hole and the at least one dummy through hole also includes: forming a mask layer above the first combined dielectric layer, wherein the mask layer has a plurality of openings to expose portions of the first combined dielectric layer; and using the mask layer as a mask to partially remove the first combined dielectric layer through the single removal process to simultaneously form the through hole and the at least one dummy through hole.

[0064] According to some embodiments, the first effective coupling via and the at least one first dummy coupling via are formed simultaneously.

[0065] According to some embodiments, the through hole exposes the first interconnect structure.

[0066] According to some embodiments, the method further includes forming at least one first dummy feature, wherein the at least one first dummy feature is disposed beside the first interconnect structure and is electrically isolated from the first interconnect structure, wherein the at least one first dummy bonding via is connected to the at least one first dummy feature.

[0067] According to some embodiments, the through-hole exposes the first active pad.

[0068] According to some embodiments, the method further includes forming at least one first dummy pad, wherein the at least one first dummy pad is disposed beside the first effective pad and is electrically isolated from the first interconnect structure, wherein the at least one dummy through hole exposes the at least one first dummy pad.

[0069] According to some embodiments, it also includes: providing a second tube core; forming a second effective bonding via, at least one second dummy bonding via and a second bonding dielectric layer on the second tube core, wherein the second effective bonding via is electrically connected to the second tube core, and the at least one second dummy bonding via is electrically floating; and combining the first tube core and the second tube core by combining the first effective bonding via with the second effective bonding via, combining the at least one first dummy bonding via with the at least one second dummy bonding via, and combining the first bonding dielectric layer with the second bonding dielectric layer.

[0070] According to some embodiments, a semiconductor structure is provided and the semiconductor structure includes a first tube core and a second tube core. The first tube core includes a first bonding dielectric layer located on the first tube core and a first effective bonding through hole located in the first bonding dielectric layer. The second tube core includes a second bonding dielectric layer located on the second tube core and a second effective bonding through hole located in the second bonding dielectric layer. The first tube core and the second tube core are bonded by bonding the first effective bonding through hole and the second effective bonding through hole together and bonding the first bonding dielectric layer and the second bonding dielectric layer together. The first effective bonding through hole penetrates the first bonding dielectric layer, and the first effective bonding through hole has a continuously inclined side wall from the top to the bottom of the first effective bonding through hole.

[0071] According to some embodiments, the continuously inclined sidewall has no turning point.

[0072] According to some embodiments, the first effective bonding via is disposed on a first pad of the first die and contacts the first pad of the first die, and the first pad is disposed on a first interconnect structure of the first die and is electrically connected to the first interconnect structure of the first die.

[0073] According to some embodiments, the first active bonding via is disposed on a first interconnect structure of the first die and contacts the first interconnect structure of the first die.

[0074] According to some embodiments, at least one first dummy bonding via is located next to the first effective bonding via and at least one second dummy bonding via is located next to the second effective bonding via, wherein the at least one first dummy bonding via is arranged in the first bonding dielectric layer and is electrically floating, and the at least one second dummy bonding via is arranged in the second bonding dielectric layer and is electrically floating.

[0075] According to some embodiments, the at least one first dummy bonding via is coupled to the at least one second dummy bonding via.

[0076] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should know that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications to them without departing from the spirit and scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor structure, comprising: Providing a first tube core, wherein the first tube core comprises a first substrate, a first interconnect structure and a first effective pad, the first interconnect structure is located on the first substrate, and the first effective pad is disposed on the first interconnect structure and is electrically connected to the first interconnect structure; forming a first bonding dielectric layer over the first die to cover the first die; forming a first effective bonding via penetrating the first bonding dielectric layer to electrically connect the first interconnect structure; and A plurality of first dummy bonding vias are formed in the first bonding dielectric layer, wherein the first dummy bonding vias surround the first effective bonding vias and are electrically floating.

2. The method according to claim 1, wherein forming the first effective bonding via comprises: forming a mask layer over the first bonding dielectric layer, wherein the mask layer has an opening to expose a portion of the first bonding dielectric layer; partially removing the first bonding dielectric layer using the mask layer as a mask to form a via hole; removing the mask layer; forming a conductive material in the through hole; as well as The conductive material outside the through hole is removed. The method according to claim 1 , wherein the first active bonding via directly contacts the first interconnect structure. The method according to claim 1 , wherein the first active bonding via directly contacts the first active pad. The method according to claim 1 , wherein the first effective bonding via is formed without a turning point.

6. The method according to claim 1, further comprising: Providing a second tube core, wherein the second tube core has a second effective bonding via and a second bonding dielectric layer; as well as The first die is bonded to the second die by bonding the first active bonding via to the second active bonding via and bonding the first bonding dielectric layer to the second bonding dielectric layer.

7. The method according to claim 1, further comprising: A plurality of first dummy pads electrically connected to the first dummy bonding vias are formed, wherein the first dummy pads surround the first effective pads and are electrically floating.

8. The method according to claim 1, further comprising: A plurality of first dummy features electrically connected to the first dummy bonding vias are formed, wherein the first dummy features are electrically isolated from the first interconnect structure and the first dummy features and the first interconnect structure are formed simultaneously.

9. A method for manufacturing a semiconductor structure, comprising: Providing a first tube core, wherein the first tube core comprises a first substrate, a first interconnection structure and a first effective pad, the first interconnection structure is located on the first substrate, and the first effective pad is disposed on the first interconnection structure and is electrically connected to the first interconnection structure; Forming at least one first dummy pad next to the first effective pad, wherein the at least one first dummy pad is electrically isolated from the first interconnect structure; forming a first bonding dielectric layer over the first die to cover the first die; forming a through-hole and at least one dummy through-hole respectively penetrating the first bonding dielectric layer using a single removal process, wherein the through-hole exposes the first effective pad, and the at least one dummy through-hole exposes the at least one first dummy pad; as well as A first effective bonding via and at least one first dummy bonding via are formed in the via hole and the at least one dummy via hole, respectively, wherein the first effective bonding via is electrically connected to the first interconnect structure and the at least one first dummy bonding via is electrically floating.

10. The method of claim 9, wherein forming the via hole and the at least one dummy via hole further comprises: forming a mask layer over the first bonding dielectric layer, wherein the mask layer has a plurality of openings to expose portions of the first bonding dielectric layer; as well as The first bonding dielectric layer is partially removed through the single removal process using the mask layer as a mask to simultaneously form the via hole and the at least one dummy via hole. 11 . The method according to claim 9 , wherein the first effective bonding via and the at least one first dummy bonding via are formed simultaneously.

12. The method according to claim 9, further comprising: providing a second die; forming a second effective bonding via, at least one second dummy bonding via, and a second bonding dielectric layer over the second die, wherein the second effective bonding via is electrically connected to the second die, and the at least one second dummy bonding via is electrically floating; as well as The first die is bonded to the second die by bonding the first active bonding via to the second active bonding via, bonding the at least one first dummy bonding via to the at least one second dummy bonding via, and bonding the first bonding dielectric layer to the second bonding dielectric layer.

13. The method of claim 9, wherein the first active bonding via directly contacts the first interconnect structure. The method according to claim 9 , wherein the first active bonding via directly contacts the first active pad.

15. A method of manufacturing a semiconductor structure, comprising: Forming at least one first effective bonding via and a plurality of first dummy bonding vias on the first die, wherein the first dummy bonding via surrounds the at least one first effective bonding via and is electrically floating, and a width of the at least one first effective bonding via is greater than a width of the first dummy bonding via; Forming at least one second effective bonding via and a plurality of second dummy bonding vias on the second die, wherein the second dummy bonding via surrounds the at least one second effective bonding via and is electrically floating, and a width of the at least one second effective bonding via is greater than a width of the second dummy bonding via; as well as The first die is bonded to the second die by bonding the at least one first effective bonding via to the at least one second effective bonding via together and bonding the first dummy bonding via to the second dummy bonding via together.

16. The method according to claim 15, wherein the method of forming the at least one first effective bonding via and the first dummy bonding via comprises: forming at least one first via hole and a plurality of first dummy via holes in the first bonding dielectric layer by a single damascene process; forming a conductive material in the at least one first via hole and the first dummy via hole; as well as The conductive material outside the at least one first through hole and the first dummy through hole is removed to form the at least one first effective combination through hole and the first dummy combination through hole in the at least one first through hole and the first dummy through hole, respectively. 17 . The method of claim 15 , wherein a width of the at least one first effective bonding via is substantially equal to a width of the at least one second effective bonding via.

18. The method according to claim 15, wherein the first die further comprises at least one first conductive feature and a plurality of first dummy features electrically isolated from the at least one first conductive feature, the at least one first effective bonding via being directly formed on the at least one first conductive feature, and the first dummy bonding vias being respectively directly formed on the first dummy features. 19 . The method of claim 18 , wherein a width of the at least one first conductive feature is formed to be greater than a width of the first dummy feature.

20. The method of claim 15, further comprising forming a first effective pad on the first die, wherein the first dummy bonding via is located between the at least one first effective bonding via and the first effective pad.

21. A semiconductor structure comprising: A first die including a first interconnect structure and a first active pad electrically connected to the first interconnect structure; a first bonding dielectric layer, over the first die; a first effective bonding via in the first bonding dielectric layer and electrically connected to the first interconnect structure; and A plurality of first dummy bonding vias are provided in the first bonding dielectric layer, wherein the first dummy bonding vias surround the first effective bonding vias and are electrically floating.

22. The semiconductor structure of claim 21, wherein the first active bonding via is electrically connected to the first active pad.

23. The semiconductor structure of claim 21, wherein the first active bonding via is electrically isolated from the first active pad. 24 . The semiconductor structure of claim 21 , wherein at least one of the first dummy bonding vias is located between the first effective bonding via and the first effective pad. 25 . The semiconductor structure of claim 21 , wherein a width of the first effective bonding via is greater than a width of the first dummy bonding via.

26. The semiconductor structure according to claim 21, wherein a first surface of the first effective bonding via is substantially coplanar with a second surface of the first dummy bonding via, and a third surface of the first effective bonding via opposite to the first surface is substantially coplanar with a fourth surface of the first dummy bonding via opposite to the second surface.

27. A semiconductor structure comprising: A first die including a first interconnect structure and a first active pad electrically connected to the first interconnect structure; a first bonding dielectric layer, over the first die; A plurality of first dummy pads surrounding the first effective pad and located in the first bonding dielectric layer and electrically isolated from the first interconnect structure; and A first effective bonding via and at least one first dummy bonding via are provided in the first bonding dielectric layer, wherein the first effective bonding via is electrically connected to the first effective pad, and the at least one first dummy bonding via is electrically floating.

28. The semiconductor structure of claim 27, wherein the first active bonding via directly contacts the first active pad.

29. The semiconductor structure of claim 27, wherein the at least one first dummy bonding via directly contacts the first dummy pad.

30. The semiconductor structure of claim 27, wherein the at least one first dummy bonding via comprises a plurality of first dummy bonding vias, the first dummy bonding vias surrounding the first effective bonding via.

31. The semiconductor structure according to claim 27, wherein a first surface of the first effective bonding via is substantially coplanar with a second surface of the at least one first dummy bonding via, and a third surface of the first effective bonding via opposite to the first surface is substantially coplanar with a fourth surface of the at least one first dummy bonding via opposite to the second surface.

32. The semiconductor structure of claim 27, wherein a surface of the first effective pad is substantially coplanar with a surface of the first dummy pad.

33. A semiconductor structure comprising: A first tube die and a second tube die; at least one first effective bonding via and a plurality of first dummy bonding vias on the first die, wherein the first dummy bonding vias surround the at least one first effective bonding via and are electrically floating; as well as At least one second effective bonding through hole and a plurality of second dummy bonding through holes are located on the second tube core, wherein the at least one first effective bonding through hole is bonded with the at least one second effective bonding through hole and the first dummy bonding through holes are respectively bonded with the second dummy bonding through holes.

34. The semiconductor structure of claim 33, wherein a width of the at least one first effective bonding via is substantially equal to a width of the at least one second effective bonding via. 35 . The semiconductor structure of claim 33 , wherein a width of the at least one first effective bonding via is greater than a width of the first dummy bonding via. 36 . The semiconductor structure of claim 33 , wherein a width of the at least one second effective bonding via is greater than a width of the second dummy bonding via. 37 . The semiconductor structure of claim 33 , wherein a surface of the at least one first effective bonding via is substantially coplanar with a surface of the first dummy bonding via.

38. A semiconductor structure according to claim 33, wherein the first tube core also includes at least one first conductive feature and a plurality of first dummy features electrically isolated from the at least one first conductive feature, the at least one first effective bonding via directly contacts the at least one first conductive feature, and the first dummy bonding vias directly contact the first dummy features respectively.

39. The semiconductor structure of claim 38, wherein a width of the at least one first conductive feature is greater than a width of the first dummy feature.

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