Package and method of forming the same

Abstract

A semiconductor package and a method for forming the same. In an embodiment, a package includes: a substrate; a first die disposed in the substrate; a redistribution structure located on the substrate and the first die; and an encapsulated device located on the redistribution structure, the redistribution structure coupling the first die to the encapsulated device.

Description

Technical Field

[0001] The embodiments of the present invention relate to a package and a method for forming the same. Background Art

[0002] The semiconductor industry is continually improving the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously shrinking the minimum feature size so that more components (and thus more functionality) can be integrated into a given area. Integrated circuits with high functionality require many input / output pads. However, for applications where miniaturization is important, a small package may be required.

[0003] Integrated fan-out (InFO) packaging technology is becoming increasingly popular, especially when combined with wafer-level packaging (WLP) technology. An InFO package may include an integrated circuit encapsulated in a package, which typically includes a redistribution layer (RDL) or post-passivation post-interconnects for fanning out contact pads of the package so that electrical contacts can be made at a larger pitch than the contact pads of the integrated circuit. The resulting package structure provides high functional density at a relatively low cost and high-performance packaging. Summary of the invention

[0004] According to an embodiment of the present invention, a package includes a substrate, a first tube core, a rewiring structure and an encapsulated device. The first tube core is arranged in the substrate. The rewiring structure is located on the substrate and the first tube core. The encapsulated device is located on the rewiring structure, and the rewiring structure couples the first tube core to the encapsulated device.

[0005] According to an embodiment of the present invention, a method for forming a package includes: forming a cavity in a substrate; bonding a first tube core to the substrate, the first tube core being arranged in the cavity; forming a rewiring structure on a first side of the substrate and above the first tube core; and bonding a semiconductor device to the rewiring structure, the semiconductor device including a second tube core encapsulated by the encapsulation body.

[0006] According to an embodiment of the present invention, a method for forming a package includes: forming a cavity in a substrate; mounting the substrate on a carrier; bonding a first device to the substrate and the cavity; and coupling a second device to the first device, the second device being encapsulated by the encapsulation body, the second device being arranged above the first device in a direction perpendicular to the main surface of the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 A core substrate is shown in accordance with some embodiments.

[0009] Figure 2 The formation of openings in a core substrate is shown in accordance with some embodiments.

[0010] Figure 3 The formation of conductive traces and conductive plugs in a core substrate is shown in accordance with some embodiments.

[0011] Figure 4 A dielectric layer and a protective layer are shown formed over a core substrate in accordance with some embodiments.

[0012] Figure 5 The formation of a cavity in a core substrate is shown in accordance with some embodiments.

[0013] Figure 6 Bonding of a substrate to a carrier is shown in accordance with some embodiments.

[0014] Fig. 7A A first die is shown attached within the cavity in accordance with some embodiments.

[0015] Figure 7B A multilayer ceramic capacitor according to some embodiments is shown.

[0016] Figure 8 An underfill formed around passive devices is shown in accordance with some embodiments.

[0017] Figures 9 to 15 A front side rewiring structure is shown formed over a substrate and passive devices according to some embodiments.

[0018] Fig.16 The formation of openings in a front side redistribution structure is shown in accordance with some embodiments.

[0019] Fig.17A The formation of conductive connections on a front side redistribution structure is shown in accordance with some embodiments.

[0020] Fig. 17B and Fig. 17C A first package formed over a carrier is shown in accordance with some embodiments.

[0021] Fig.18 The carrier is shown being peeled away according to some embodiments.

[0022] Fig.19Bonding of a packaged semiconductor device is shown in accordance with some embodiments.

[0023] Fig. 20 The conformation of an annular structure is shown according to some embodiments.

[0024] Fig.21 Formation of conductive connections on the back side of a substrate is shown in accordance with some embodiments.

[0025] [Explanation of Symbols]

[0026] 100, 154, 164: insulation layer;

[0027] 101: a first package body;

[0028] 102: conductive layer;

[0029] 104: substrate;

[0030] 106, 172: opening;

[0031] 108: a first conductive trace;

[0032] 110: conductive plug;

[0033] 112: second conductive trace;

[0034] 114, 134, 138, 144, 148, 158, 170: dielectric layer;

[0035] 116: protective layer;

[0036] 118: cavity;

[0037] 120: cavity substrate;

[0038] 122: carrier substrate;

[0039] 124: release layer;

[0040] 126: first tube core;

[0041] 128, 196: adhesive;

[0042] 130, 222: connection terminals;

[0043] 132: bottom filling glue;

[0044] 136, 142, 146, 150: metallization pattern;

[0045] 140: Front side heavy wiring structure;

[0046] 152, 162: conductive columns;

[0047] 156, 160, 166: conductive traces;

[0048] 168: Under Bump Metal;

[0049] 174, 198: conductive connectors;

[0050] 180: Packaged semiconductor devices;

[0051] 182: processor die;

[0052] 184: tube core;

[0053] 186: Encapsulation material;

[0054] 188: Integrated fan-out structure;

[0055] 190: external contact;

[0056] 192: bottom filling material;

[0057] 194: Ring structure;

[0058] 200: System Integrated Substrate (SoIS);

[0059] 220:MLCC;

[0060] 224: Ceramics;

[0061] 226: Electrode;

[0062] T1: Thickness. DETAILED DESCRIPTION

[0063] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0064] Additionally, for ease of description, spatially relative terms such as "below," "lower," "above," and "upper" may be used herein to describe the relationship of one element or feature to another (other) element or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative terms used herein should be interpreted accordingly.

[0065] Various embodiments relate to packaged semiconductor devices and methods of forming the same. The packaged semiconductor device may be a system on integrated substrate (SoIP) package, a system-in-package (SiP), or the like. A cavity may be formed in a core substrate, and electronic components such as a multilayer ceramic capacitor (MLCC), an integrated passive device (IPD), an integrated voltage regulator (IVR), a static random access memory (SRAM), etc. may be bonded to the core substrate in the cavity. A redistribution layer (RDL) may be formed over the core substrate and the electronic components, and electronic devices such as a chip-on-wafer (CoW), an integrated fan-out (InFO) package, a die, or another package may be bonded to the redistribution layer. Embedding the electronic components in the core substrate shortens the distance between the electronic components and the electronic devices, which reduces the voltage drop between the electronic components and the electronic devices, and improves the power integrity and overall performance of the packaged semiconductor device.

[0066] First refer to Figure 1 , Figure 1A substrate 104 is shown according to some embodiments, the substrate 104 including an insulating layer 100 and a conductive layer 102 located on both sides of the insulating layer 100. The substrate 104 may be a core substrate. In some embodiments, the substrate 104 is a double-sided copper clad laminate (CCL). The insulating layer 100 may be an organic substrate, a ceramic substrate, a pre-impregnated composite fiber (prepreg), Ajinomoto Build-up Film (ABF), paper, fiberglass, non-woven glass fabric, other insulating materials, or a combination thereof. The conductive layer 102 may be one or more layers of copper, nickel, aluminum, other conductive materials, or a combination thereof laminated or formed on opposite sides of the insulating layer 100.

[0067] Reference Figure 2 , a plurality of openings 106 are formed in the substrate 104. In some embodiments, the openings 106 are formed by laser drilling. Other processes, such as mechanical drilling, etching, etc., may also be used. In a top view, the openings 106 may have a rectangular, circular, or other shape.

[0068] Reference Figure 3 According to some embodiments, the filling opening 106 (see Figure 2 ) to form a plurality of conductive plugs 110, a plurality of first conductive traces 108, and a plurality of second conductive traces 112. The conductive traces (e.g., the first conductive traces 108 and the second conductive traces 112) may be used to form routing lines to reroute electrical signals, or as die connector pads to which die connectors may be attached. Prior to depositing the conductive material within the opening 106, a surface preparation process may be performed. The surface preparation process may include cleaning the exposed surfaces of the substrate 104 (e.g., the surface of the conductive layer 102 and the surface of the insulating layer 100 in the opening 106) with one or more cleaning solutions (e.g., sulfuric acid, chromic acid, neutralized alkaline solutions, water rinses, etc.) to remove or reduce dirt, oil, and / or natural oxide films. A desmear process may be performed to clean areas near the opening 106 that may have been contaminated by the material of the insulating layer 100 that has been removed to form the opening 106. Desmear can be achieved mechanically (e.g., sandblasting with fine abrasives in a wet slurry), chemically (e.g., washing with a combination of organic solvents, permanganates, etc.), or by a combination of mechanical and chemical desmearing. After cleaning, a chemical conditioner can be used for treatment, which is conducive to adsorption of activators used during subsequent electroless plating. In some embodiments, the conductive layer 102 can be micro-etched after the conditioning step to micro-roughen the conductive surface of the conductive layer 102, thereby providing better bonding between the conductive layer 102 and the conductive material deposited later.

[0069] Forming the conductive plug 110, the first conductive trace 108, and the second conductive trace 112 may include: forming a patterned mask layer, and selectively depositing a conductive material (e.g., copper, other metals, metal alloys, etc.) in openings of the patterned mask layer using a metal electroless plating technique. The patterned mask layer may be formed by coating a surface with a photoresist layer, exposing the photoresist layer to an optical pattern, and developing the exposed photoresist layer to form openings in the photoresist layer, the openings defining a pattern of regions where the conductive material may be selectively deposited.

[0070] After forming the first conductive trace 108 and the second conductive trace 112, the patterned mask layer (e.g., photoresist) may be stripped. A suitable etching process may be used to remove portions of the conductive layer 102 that were once covered by the patterned mask layer. Removing unwanted portions of the conductive layer 102 may prevent unwanted electrical shorts between conductive features formed in areas exposed by the patterned mask layer. The conductive plug 110, the first conductive trace 108, and the second conductive trace 112 may be formed on both sides of the substrate 104 in the manner described above. Figure 3 The cross-sectional view shows the state of the substrate 104 after the conductive layer 102 is etched as described above.

[0071] As discussed in more detail below, substrate 104 will serve as a core substrate (cavity substrate 120) that forms a cavity containing Figure 3 shown in Figure 5 ) is shown in the substrate. Figure 3 In the embodiment, a first conductive trace 108 is formed on one side of an insulating layer 100, in which a cavity 118 (not shown) is formed during subsequent processing steps. Figure 3 shown in Figure 5 ). According to some embodiments, the first conductive trace 108 may be omitted from areas where a cavity may be subsequently formed (eg, areas between the innermost conductive plugs 110 in this example).

[0072] Although not shown in this example, it is understood that the method of using a metal-clad laminate, forming openings extending through the metal-clad laminate, forming patterned conductive trace layers (e.g., using electroless deposition or plating, etc.), and removing unwanted metal cladding layers can be repeatedly performed to vertically stack multiple alternating layers of insulating material and conductive traces and conductive plugs to vertically connect adjacent layers of conductive traces.

[0073] Reference Figure 4, a dielectric layer 114 and a protective layer 116 are formed on the substrate 104 and on the first conductive trace 108 and the second conductive trace 112, respectively. In some embodiments, the dielectric layer 114 is formed of a polymer that can be patterned using a lithography mask, and the polymer can be a photosensitive material such as polybenzoxazole (PBO), polyimide, benzocyclobuten (BCB), etc. The dielectric layer 114 can be formed by spin coating, lamination, chemical vapor deposition (CVD), the like, or a combination thereof. The dielectric layer 114 is patterned to form an opening that exposes a portion of the first conductive trace 108. When the dielectric layer 114 is a photosensitive material, the patterning can be achieved by exposing the dielectric layer 114 to light and developing the dielectric layer 114. The dielectric layer 114 may also be formed of a material that is not photosensitive, such as silicon nitride, silicon oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), etc. In the embodiment where the dielectric layer 114 is formed of a non-photosensitive material, the dielectric layer 114 may be patterned by etching through a patterned photoresist mask using a suitable etching process (e.g., anisotropic reactive ion etching).

[0074] In various embodiments, the protective layer 116 may be a solder resist or the like formed over the second conductive trace 112 to protect an area of ​​the insulating layer 100 from external damage. The protective layer 116 may be patterned to form an opening exposing a portion of the second conductive trace 112. In an embodiment where the protective layer 116 is formed of a photosensitive material, the patterning may be achieved by exposing the protective layer 116 to light and developing the protective layer 116. In an embodiment where the protective layer 116 is formed of a non-photosensitive material, the protective layer 116 may be patterned by etching through a patterned photoresist mask using a suitable etching process (e.g., anisotropic reactive ion etching). The opening exposing the second conductive trace 112 may be used as a die connector pad, and the conductive connector 198 (not shown) may be patterned. Figure 4 shown in Fig.21 ) can then be bonded to the die connector pads.

[0075] exist Figure 5 In some embodiments, the cavity 118 is formed by removing a portion of the insulating layer 100. Removing the portion of the insulating layer 100 does not affect the first conductive trace 108 located on the same side of the insulating layer 100 that is recessed by the removal process. Figure 3As described above, the patterned mask used to form the first conductive trace 108 may be designed to exclude the first conductive trace 108 from being formed over a portion of the insulating layer 100 where the cavity 118 is formed. Removing material to form the cavity 118 may be performed by a computer numerical control (CNC) machining process, in which material is removed by mechanical drilling. Figure 5 As shown, the resulting structure is a cavity substrate 120. The insulating layer 100 of the cavity substrate 120 may have a thickness T1 from about 25 μm to about 2,000 μm (e.g., about 250 μm or about 500 μm). The cavity 118 may have a depth from about 10 μm to about 1,000 μm (e.g., about 70 μm or about 400 μm). The cavity 118 may have an area from about 1 mm by 1 mm to about 20 mm by 20 mm (e.g., about 1.5 mm by 1.5 mm or about 5.0 mm by 4.0 mm). In some embodiments, a portion of the insulating layer 100 may remain along the bottom of the cavity 118 and may have a thickness from about 20 μm to about 1600 μm (e.g., about 30 μm or about 800 μm). Other processes may also be used to form the cavity 118, such as laser drilling, etching, and / or the like.

[0076] exist Figure 6 In some embodiments, the cavity substrate 120 is bonded to the carrier substrate 122 using a release layer 124. Figure 6 As shown, the cavity substrate 120 can be attached to the carrier substrate 122 using a release layer 124 so that the cavity 118 is opposite to the release layer 124. The carrier substrate 122 can be a glass carrier substrate, a ceramic carrier substrate, etc. The release layer 124 can be a polymer-based material, an epoxy-based thermal release material (such as a light-to-heat-conversion (LTHC) release coating) or an ultraviolet (UV) glue (for example, a glue that loses its adhesive properties when exposed to ultraviolet light). The release layer 124 can help remove the carrier substrate 122 during subsequent processing. The release layer 124 can be removed together with the carrier substrate 122 during subsequent processing.

[0077] exist Fig. 7A In some embodiments, the first die 126 is placed in the cavity 118 (shown in Figure 6). The first die 126 can be placed in the cavity 118 using a pick-and-place (PnP) tool. The first die 126 can be a passive device, such as a multilayer ceramic chip (MLCC) capacitor; an integrated passive device (IPD); an integrated voltage regulator (IVR), etc. or a combination thereof; or an active device, such as a memory die (e.g., a static random access memory (SRAM) die, a dynamic random access memory (DRAM) die, a high bandwidth memory (HBM) die, etc.), a logic chip, an analog chip, a microelectromechanical system (MEMS) chip, a radio frequency (RF) chip, a similar chip or a combination thereof. In some embodiments, the first die 126 is bonded to the insulating layer 100 by an adhesive 128. Although Fig. 7A A first die 126 is shown placed in the cavity 118, however it should be understood that multiple dies or devices may also be placed in the cavity 118 of the cavity substrate 120. For example, in some embodiments, the first die 126 may be a plurality of devices placed laterally adjacent to each other and / or stacked on each other, wherein the plurality of devices may have the same or different sizes. Before the first die 126 is placed on the cavity substrate 120, the first die 126 may be processed according to an applicable manufacturing process to form a corresponding device structure. The first die 126 may include a connection terminal 130 (e.g., an aluminum pad, a copper pad, etc.) for external connection. The first die 126 may have a height from about 30 μm to about 350 μm, a length from about 0.5 mm to about 0.8 mm, and a width from about 0.5 mm to about 0.8 mm.

[0078] Adhesive 128 may be attached to the back side of first die 126, and first die 126 may be attached to insulating layer 100. Adhesive 128 may be any suitable adhesive, epoxy, die attach film (DAF), etc. Adhesive 128 may be applied to the back side of first die 126 before singulation of first die 126. First die 126 may be singulated, for example, by sawing or dicing, and first die 126 may be attached to insulating layer 100 through adhesive 128 using, for example, a PnP tool. In some embodiments, adhesive 128 may be attached to cavity substrate 120 before first die 126 is placed in cavity 118.

[0079] Figure 7B MLCC 220 is shown that can be used as the first die 126. Figure 7B As shown, the MLCC 220 includes a plurality of electrodes 226 sandwiched between layers of ceramic 224. The MLCC 220 also includes a plurality of connection terminals 222 for external connection.

[0080] exist Figure 8 In some embodiments, an underfill 132 is formed between the plurality of sidewalls of the first die 126 and the cavity substrate 120. The underfill 132 may be formed by a capillary flow process after the first die 126 is bonded, or may be formed by a suitable deposition method before the first die 126 is bonded. The underfill 132 may be a material such as a molding compound, an epoxy, an underfill, a molding underfill (MUF), a resin, or the like. The underfill 132 may reduce stress between the first die 126 and the cavity substrate 120, and may help secure the first die 126 in the cavity 118. Figure 8 As shown, the upper surface of the underfill 132 may be concave; however, in some embodiments, the upper surface of the underfill 132 may be convex or flat.

[0081] Figures 9 to 15 A front side rewiring structure 140 (shown in FIG. 1 ) is formed over the connection terminals 130 of the first die 126 and the first conductive traces 108 of the cavity substrate 120 according to some embodiments. Fig.15 ). The front side rewiring structure 140 includes a vertical stack of alternating layers of dielectric and conductive traces. Each layer of conductive traces is separated from the vertically adjacent conductive trace layer by a dielectric layer. The conductive traces extend through the underlying dielectric layer to form vias for interconnecting vertically adjacent conductive traces. The front side rewiring structure 140 and the cavity substrate 120 together form the first package body 101 (shown in FIG. Fig.15 middle).

[0082] exist Fig. 9In the embodiment of the present invention, a dielectric layer 134 is formed on the cavity substrate 120, the bottom fill 132 and the first tube core 126. In some embodiments, the dielectric layer 134 is formed of a polymer that can be patterned using a photolithography mask, and the polymer can be a photosensitive material such as PBO, polyimide, BCB, etc. The dielectric layer 134 can be formed by spin coating, lamination, chemical vapor deposition (CVD), similar processes or combinations thereof. The dielectric layer 134 is patterned to form a plurality of openings that expose a plurality of connection terminals 130 and a plurality of first conductive traces 108. When the dielectric layer 134 is a photosensitive material, the patterning can be achieved by exposing the dielectric layer 134 to light. The dielectric layer 134 can also be formed of the following materials that are not photosensitive, such as silicon nitride, silicon oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), etc. In embodiments where the dielectric layer 134 is formed of a non-photosensitive material, the dielectric layer 134 may be patterned by etching through a patterned photoresist mask using a suitable etching process (eg, anisotropic reactive ion etching).

[0083] exist Fig.10, a metallization pattern 136 is formed on the dielectric layer 134 and the metallization pattern 136 extends through the dielectric layer 134. As an example of forming the metallization pattern 136, a seed layer (not shown separately) is formed on the dielectric layer 134. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer including multiple sublayers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer located on the titanium layer. The seed layer may be formed using, for example, physical vapor deposition (PVD), CVD, etc. A photoresist (not shown separately) is then formed on the seed layer and the photoresist is patterned. The photoresist may be formed by spin coating, etc., may be exposed to patterned light or another patterned energy source, and may be exposed to a developer to remove the exposed or unexposed portions of the photoresist. The pattern of the photoresist corresponds to the metallization pattern 136. The patterning forms an opening through the photoresist to expose the seed layer. A conductive material (not shown separately) is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating such as electroplating, electroless plating, etc. The conductive material can include metals such as copper, titanium, tungsten, aluminum, etc. Then, the photoresist and the portion of the seed layer where the conductive material is not formed are removed. The photoresist can be removed, for example, using oxygen plasma, by an acceptable ashing process or stripping process. Once the photoresist is removed, an acceptable etching process (such as wet etching or dry etching) is used to remove the exposed portion of the seed layer. The remaining portion of the seed layer and the conductive material will form a metallization pattern 136. The metallization pattern 136 includes conductive traces formed along the top surface of the dielectric layer 134 and a via hole passing through the dielectric layer 134. The via hole electrically connects the conductive traces of the metallization pattern 136 and physically connects to the metal pattern (e.g., the first conductive trace 108 and the connection terminal 130) directly below the dielectric layer 134.

[0084] Forming a dielectric layer 134 (see Fig. 9 Discussion) and the conductive traces and vias of the metallization pattern 136 (see Fig.10 The method of forming the dielectric layer 134 and the metallization pattern 136 is described only as an example. It should be understood that the process of forming the dielectric layer 134 and the metallization pattern 136 can vary based on the design specifications (e.g., the desired minimum size of the pattern). For example, in some embodiments, a damascene process (e.g., a single damascene process or a dual damascene process) can be utilized. The front side rewiring structure 140 can be constructed by vertically stacking additional dielectric layers and metallization patterns.

[0085] Fig.11 Additional dielectric layers 138 , 144 , and 148 are shown formed over the top surfaces of dielectric layer 134 and metallization pattern 136 . Fig.11Also shown are metallization patterns 142, 146, and 150. The metallization patterns 142, 146, and 150 include conductive traces formed along the top surfaces of the respective dielectric layers 138, 144, and 148 and vias extending through the respective dielectric layers 138, 144, and 148. The vias of the metallization patterns 142, 146, and 150 electrically and physically connect the conductive traces of the metallization patterns 142, 146, and 150 to the respective metallization patterns (e.g., the respective metallization patterns 136, 142, and 146) directly below the respective dielectric layers 138, 144, and 148. Similar processes, techniques, and materials as described above with respect to the dielectric layer 134 and the metallization pattern 136 may be repeated to form the dielectric layers 138 , 144 , and 148 and the metallization patterns 142 , 146 , and 150 .

[0086] exist Fig.12 In the embodiment of the present invention, a plurality of conductive pillars 152 are formed on the metallization pattern 150. As an example of forming the conductive pillars 152, a seed layer (not shown separately) is formed on the dielectric layer 148 and the metallization pattern 150. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer including multiple sublayers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer located on the titanium layer. The seed layer may be formed using, for example, PVD, CVD, etc. A photoresist (not shown separately) is then formed on the seed layer and the photoresist is patterned. The photoresist may be formed by spin coating, etc., may be exposed to patterned light or another patterned energy source, and may be exposed to a developer to remove the exposed or unexposed portion of the photoresist. The pattern of the photoresist corresponds to the conductive pillars 152. The patterning forms an opening through the photoresist to expose the seed layer. A conductive material (not shown separately) is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating such as electroplating, electroless plating, etc. The conductive material can include metals such as copper, titanium, tungsten, aluminum, etc. Then, remove the photoresist and the portion of the seed layer that is not formed with the conductive material. The photoresist can be removed, for example, using oxygen plasma, by an acceptable ashing process or a stripping process. Once the photoresist is removed, an acceptable etching process (such as wet etching or dry etching) is used to remove the exposed portion of the seed layer. The remaining portion of the seed layer and the conductive material will form a conductive column 152. The conductive column 152 is electrically connected and physically connected to the metallization pattern 150.

[0087] Now refer to Fig.13, the conductive pillars 152 may be embedded in the insulating layer 154 by, for example, laminating a build-up film such as ABF or prepreg, and using an etch-back or planarization process (e.g., chemical-mechanical polishing (CMP), grinding, etc.) to expose the top surface of the conductive pillars 152. In some embodiments, the insulating layer 154 may be deposited as a liquid molding compound molded onto the dielectric layer 148 and the metallization pattern 150 and surrounding the conductive pillars 152.

[0088] exist Fig.14 In the embodiment, a plurality of conductive traces 156 are formed on the conductive pillars 152 and the insulating layer 154. The conductive traces 156 may be formed using the same method as described above. Fig.10 The metallization pattern 136 shown is formed using processes, techniques, and materials similar to those described above, wherein a seed layer is deposited, a patterned mask is formed over the seed layer, a plating process is performed to form a metallization pattern, the patterned mask is removed, and unused portions of the seed layer are removed.

[0089] exist Fig.15 In the embodiment, a dielectric layer 158, a plurality of conductive traces 160, a plurality of conductive pillars 162, an insulating layer 164, a plurality of conductive traces 166, and a plurality of under-bump metallization (UBM) 168 are formed over the conductive traces 156 and the insulating layer 154. The dielectric layer 158 may be formed using the same method as described above with respect to Fig. 9 The conductive traces 160 and 166 and the conductive posts 162 may be formed using processes, techniques, and materials similar to those described above for forming the dielectric layer 134. Fig.10 The metallization pattern 136 is formed by processes, techniques, and materials similar to those described above, wherein a seed layer is deposited, a patterned mask is formed over the seed layer, a plating process is performed to form a metallization pattern, the patterned mask is removed, and unused portions of the seed layer are removed. Fig.15 Although not shown in the drawings, vias may be formed that extend through dielectric layer 158 and electrically connect conductive trace 160 to conductive trace 156. Insulating layer 164 may be formed using the same techniques as described above with respect to Fig.13 The insulating layer 154 shown is formed using processes, techniques, and materials similar to those described above for forming the insulating layer 154 .

[0090] UBM 168 may be formed over insulating layer 164 and conductive pillars 162. UBM 168 includes a solderable metal surface that may be used as a solder bump for subsequently formed solder bumps (eg, Fig.17A The interface between the conductive connector 174) and the front side redistribution structure 140 is shown. Fig.15As shown, UBM 168 can be electrically and physically connected to conductive pillar 162. UBM 168 can be used with Fig.10 The metallization pattern 136 may be formed using processes, techniques, and materials similar to those described above. Fig. 9 Dielectric layer 170 is formed over insulating layer 164 , conductive traces 166 , and UBM 168 using processes, techniques, and materials similar to those described for forming dielectric layer 134 .

[0091] More or fewer dielectric layers, insulating layers, metallization patterns, conductive traces, and conductive pillars may be formed in the front side rewiring structure 140. In some embodiments, the front side rewiring structure 140 may include 1 to 10 dielectric layers / insulating layers; however, the front side rewiring structure 140 may be optional, and in some embodiments, the front side rewiring structure 140 may not be included. If fewer dielectric layers and metallization patterns are to be formed, the steps and processes discussed above may be omitted. If more dielectric layers and metallization patterns are to be formed, the steps and processes discussed above may be repeated. Each of the dielectric layer 134, the dielectric layer 138, the dielectric layer 144, the dielectric layer 148, the dielectric layer 158, and the dielectric layer 170, and each of the insulating layer 154 and the insulating layer 164 may have a thickness from about 5 μm to about 100 μm (e.g., about 30 μm).

[0092] In the above-described embodiment, two insulating layers (insulating layer 154 and insulating layer 164) are included in the front side rewiring structure 140. The insulating layer 154 and the insulating layer 164 may be formed of a mold compound material having a lower impedance than the dielectric material used to form the dielectric layer 134, the dielectric layer 138, the dielectric layer 144, the dielectric layer 148, the dielectric layer 158, and the dielectric layer 170. As such, the insulating layer 154 and the insulating layer 164 may be included in the front side rewiring structure 140 to control the impedance of the front side rewiring structure 140 and match the impedance of the front side rewiring structure to a desired value. For example, the impedance of the front side rewiring structure 140 including the insulating layer 154 and the insulating layer 164 may be between about 90Ω and about 100Ω, for example, about 100Ω.

[0093] exist Fig.16 In the embodiment, the dielectric layer 170 is patterned to form a plurality of openings 172 that expose portions of the plurality of UBMs 168. When the dielectric layer 170 is a photosensitive material, the patterning may be achieved by exposing the dielectric layer 170 to light. In embodiments where the dielectric layer 170 is formed of a non-photosensitive material, the dielectric layer 170 may be patterned by etching through a patterned photoresist mask using a suitable etching process (e.g., anisotropic reactive ion etching).

[0094] exist Fig.17AIn the embodiment, a plurality of conductive connectors 174 are formed on the plurality of UBMs 168. The conductive connectors 174 may be ball grid array (BGA) connectors, solder balls, conductive pillars, controlled collapse chip connection (C4) bumps, micro bumps, bumps formed by electroless nickel-electroless palladium-immersion gold technique (ENEPIG), etc. The conductive connectors 174 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, similar materials, or combinations thereof. In some embodiments, the conductive connectors 174 are formed on the substrate by utilizing processes such as evaporation, electroplating, printing, solder transfer, ball placement, etc. Fig.16 The conductive connector 174 is formed by initially forming a solder layer on the structure shown. Once the solder layer has been formed, reflow can be performed to shape the solder material into a desired bump shape. In another embodiment, the conductive connector 174 is a conductive column (e.g., a copper column) formed by sputtering, printing, electroplating, electroless plating, CVD, etc. The conductive connector 174 may be solder-free and may have a substantially vertical sidewall. In some embodiments, a metal cap layer (not shown separately) is formed on the top of the conductive column. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, similar materials or combinations thereof, and may be formed by a plating process.

[0095] A plurality of first packages 101 may be formed on a single carrier substrate 122. Fig. 17B As shown, the first package body 101 may have a rectangular shape, the carrier substrate 122 may have a round shape (eg, a circular shape), and the carrier substrate 122 may be referred to as a wafer. Fig. 17C As shown, the first package 101 may have a rectangular shape, the carrier substrate 122 may have a rectangular shape, and the carrier substrate 122 may be referred to as a panel. The first package 101 may be singulated from each other, for example, by sawing, cutting, etc. The first package 101 may be singulated before removing the carrier substrate 122. Fig. 17B Four first packages 101 are shown in FIG. Fig. 17C Nine first packages 101 are shown in FIG. 1 , however any number of first packages 101 may be formed on the carrier substrate 122 , for example, from a single first package 101 to thousands of first packages 101 .

[0096] exist Fig.18In some embodiments, a carrier substrate de-bonding process is performed to detach (peel off) the carrier substrate 122 from the protective layer 116 of the cavity substrate 120. In embodiments where the release layer 124 is a photosensitive adhesive, the de-bonding may be performed by projecting light, such as laser or ultraviolet light, onto the release layer 124 so that the release layer 124 decomposes and the carrier substrate 122 may be removed. A cleaning process may be performed to remove residues of the release layer 124 from the protective layer 116. Peeling off the carrier substrate 122 exposes the protective layer 116 and the plurality of openings therein.

[0097] exist Fig.19 , the packaged semiconductor device 180 is bonded to the conductive connector 174. According to an embodiment, the packaged semiconductor device 180 may be arranged over the front side redistribution structure 140, for example, by a pick and place machine (not separately shown). However, any other alternative method of arranging the packaged semiconductor device 180 on the front side redistribution structure 140 may be utilized.

[0098] In an embodiment, the packaged semiconductor device 180 may include a processor die 182 (e.g., a Xilinx processing unit (xPU)), such as a central processing unit (CPU), a micro control unit (MCU), a graphics processing unit (GPU), an application processor (AP), etc. The packaged semiconductor device 180 may also include additional die 184, such as memory die (e.g., dynamic random access memory (DRAM) die, wide input / output (I / O) die, magnetic random access memory (MRAM) die, resistive random access memory (RRAM) die, NAND die, static random access memory (SRAM) die, etc.), memory cubes (e.g., high bandwidth memory (HBM), hybrid memory cube (HMC), etc.), high data rate transceiver die, I / O interface die, integrated passive device (IPD) die, power management die (e.g., power management integrated circuit (PMIC) die), radio frequency (RF) die, sensor die, microelectromechanical system (MEMS) die, signal processing die (e.g., digital signal processing (DSP) die), front-end die (e.g., analog front end (AFE) die), etc.), etc. The processor die 182 and the additional die 184 may be linked together by a combination of HMC links, through-silicon vias (TSVs) and microbumps, and may be embedded in an encapsulation material 186. In some embodiments, the packaged semiconductor device 180 may be a single chip-on-wafer (CoW) device, a system on chip (SoC) device, an integrated fan-out (InFO) device, a single die, or a package including one or more dies. The external contacts of the packaged semiconductor device 180 may be disposed on a first surface of the packaged semiconductor device 180, which is opposite to a thinned backside second surface of the packaged semiconductor device 180.

[0099] In addition, the packaged semiconductor device 180 may include an integrated fan-out (InFO) structure 188 having a plurality of external contacts 190. The InFO structure 188 may include a plurality of dielectric layers and a redistribution layer (RDL) for internally connecting the external contacts of the packaged semiconductor device 180 disposed on a first side of the InFO structure 188 to the external contacts 190 disposed on a second side of the InFO structure 188 opposite to the first side of the InFO structure 188.

[0100] In an embodiment, the external contact 190 may be, for example, a conductive pillar, such as a copper pillar or a copper support. In some embodiments, the external contact 190 may be a solder bump, a copper bump, or other suitable external contact 190, which may be fabricated to provide electrical connection from the packaged semiconductor device 180 to other external devices through, for example, the conductive connector 174 and the front side redistribution structure 140. All such external contacts are intended to be included within the scope of the embodiments.

[0101] like Fig.19 As further shown, in an embodiment, the packaged semiconductor device 180 may be arranged over the front side redistribution structure 140 such that the external contacts 190 of the packaged semiconductor device 180 are aligned with and placed in contact with the conductive connectors 174 on the front side redistribution structure 140. Once arranged, a bonding step may be performed to bond the packaged semiconductor device 180 to the front side redistribution structure 140. The external contacts may be bonded to the conductive connectors 174 using metal-to-metal bonding, solder bonding, or the like.

[0102] An underfill material 192 may be formed in the opening between the InFO structure 188 and the front side redistribution structure 140 and around the conductive connectors 174 and the external contacts 190. The underfill material 192 may be formed by a capillary underfill process after the packaged semiconductor device 180 has been attached. In another embodiment, the underfill material 192 may be provided by a suitable deposition process before the packaged semiconductor device 180 has been attached.

[0103] Fig.19The packaged semiconductor device 180 is shown connected to the first tube core 126 through the front side rewiring structure 140, the conductive connector 174 and the InFO structure 188. Disposing the first tube core 126 in the cavity 118 of the cavity substrate 120 can reduce the distance between the first tube core 126 and the packaged semiconductor device 180. For example, the distance between the first tube core 126 and the packaged semiconductor device 180 can be less than about 0.3mm or from about 0.1mm to about 0.5mm. In contrast, the alternative packaging structure may have a distance between the first tube core 126 and the packaged semiconductor device 180 that is greater than about 10mm. Reducing this distance reduces the voltage drop between the first tube core 126 and the packaged semiconductor device 180, which can improve the packaged semiconductor device (for example, referred to below) including the first tube core 126 and the packaged semiconductor device 180. Fig.21 The power integrity of the SoIS 200 discussed above.

[0104] exist Fig. 20 , the annular structure 194 is attached to the front side rewiring structure 140 and surrounds the packaged semiconductor device 180. The annular structure 194 can be attached to protect the packaged semiconductor device 180, increase the stability of the first package body 101, and dissipate heat from the packaged semiconductor device 180 and the first package body 101. The annular structure 194 can be formed of the following materials with high thermal conductivity, such as steel, stainless steel, copper, aluminum, combinations thereof, etc. In some embodiments, the annular structure 194 can be a metal coated with another metal (such as gold). In various embodiments, the annular structure 194 can be a cover covering the upper surface of the packaged semiconductor device 180. An adhesive 196 can be used to fix the annular structure 194 to the front side rewiring structure 140.

[0105] exist Fig.21 In the embodiment, a plurality of conductive connectors 198 are formed on the second conductive traces 112 to form a system integrated substrate (SoIS) 200. The conductive connectors 198 may be BGA connectors, solder balls, conductive pillars, C4 bumps, micro bumps, bumps formed by ENEPIG, etc. The conductive connectors 198 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, similar materials, or combinations thereof. In some embodiments, the conductive connectors 198 are formed on the substrate by processes such as evaporation, electroplating, printing, solder transfer, ball planting, etc. Fig. 20The conductive connector 198 is formed by initially forming a solder layer on the structure shown. Once the solder layer has been formed, reflow can be performed to shape the solder material into a desired bump shape. In another embodiment, the conductive connector 198 is a conductive column (e.g., a copper column) formed by sputtering, printing, electroplating, electroless plating, CVD, etc. The conductive connector 198 may be solder-free and may have a substantially vertical sidewall. In some embodiments, a metal cap layer (not shown separately) is formed on the top of the conductive column. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, similar materials or combinations thereof, and may be formed by a plating process.

[0106] Attaching the first die 126 in the cavity 118 of the cavity substrate 120 and then connecting the packaged semiconductor device 180 to the first die 126 through the front side redistribution structure 140, the conductive connectors 174, and the InFO structure 188 minimizes the distance between the first die 126 and the packaged semiconductor device 180. This reduces the voltage drop between the first die 126 and the packaged semiconductor device 180, thereby improving the power integrity and overall performance of the SoIS 200.

[0107] According to an embodiment, a package includes: a substrate; a first die disposed within the substrate; a rewiring structure located above the substrate and the first die; and an encapsulated device located above the rewiring structure, the rewiring structure coupling the first die to the encapsulated device. In an embodiment, the first die includes a multilayer ceramic capacitor (MLCC). In an embodiment, the first die includes an integrated passive device (IPD). In an embodiment, the first die includes an integrated voltage regulator (IVR). In an embodiment, the first die includes a static random access memory (SRAM) die. In an embodiment, a distance between the encapsulated device and the first die is less than 0.3 mm. In an embodiment, the rewiring structure includes one or more molding compound layers. In an embodiment, each of the one or more molding compound layers has a thickness from 5 μm to 100 μm. In an embodiment, the package also includes an annular structure attached to the rewiring structure, the annular structure surrounding the encapsulated device. In an embodiment, the package also includes an underfill material surrounding a plurality of sidewalls of the first die.

[0108] According to another embodiment, a method includes: forming a cavity in a substrate; attaching a first die to the substrate, the first die being disposed in the cavity; forming a redistribution structure on a first side of the substrate and on the first die; and attaching a semiconductor device to the redistribution structure, the semiconductor device including a second die encapsulated by an encapsulant. In an embodiment, the method further includes filling the cavity with an underfill after attaching the first die to the substrate. In an embodiment, the first die is attached to the substrate using an adhesive. In an embodiment, forming the redistribution structure includes forming a through hole on the first side of the substrate and on the first die, and forming a molding compound surrounding the through hole, the molding compound being laterally coterminous with the substrate.

[0109] According to yet another embodiment, a method comprises: forming a cavity in a substrate; mounting the substrate on a carrier; attaching a first device to the substrate and the cavity; and coupling a second device to the first device, the second device being encapsulated by an encapsulant, the second device being disposed above the first device in a direction perpendicular to a major surface of the substrate. In an embodiment, the method further comprises depositing an underfill surrounding the first device. In an embodiment, the method further comprises forming a front side rewiring structure on a front side of the substrate and above the first device, the front side rewiring structure comprising one or more molding compound layers, the second device being coupled to the first device through the front side rewiring structure. In an embodiment, the carrier is peeled off from the substrate before coupling the second device to the first device. In an embodiment, the method further comprises forming a plurality of electrical connections on a back side of the substrate after peeling off the carrier. In an embodiment, the cavity is formed using mechanical drilling.

[0110] The above content summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications to them without departing from the spirit and scope of the present disclosure.

Claims

1. A package, comprising: substrate; A first tube core is arranged in the substrate; a redistribution structure, located on the substrate and the first die; as well as an encapsulated device over the rewiring structure, the rewiring structure coupling the first die to the encapsulated device, wherein The redistribution structure includes one or more dielectric layers and one or more molding compound layers, the dielectric layers include a dielectric material, the molding compound layers include a molding compound material, and the molding compound material has a lower resistance than the dielectric material. 2 . The package of claim 1 , wherein the first die comprises a multilayer ceramic capacitor. 3 . The package of claim 1 , wherein the first die comprises integrated passive devices. The package of claim 1 , wherein the first die comprises an integrated voltage regulator.

5. The package of claim 1 wherein the first die comprises a static random access memory die. The package of claim 1 , wherein a distance between the encapsulated device and the first die is less than 0.3 mm. 7 . The package of claim 1 , wherein each of the one or more molding compound layers has a thickness from 5 μm to 100 μm. 8 . The package of claim 1 , further comprising an annular structure attached to the redistribution structure, the annular structure surrounding the encapsulated device. 9 . The package of claim 1 , further comprising an underfill material surrounding a plurality of sidewalls of the first die.

10. A method of forming a package, comprising: forming a cavity in the substrate; attaching a first tube die to the substrate, wherein the first tube die is disposed in the cavity; forming a redistribution structure on the first side of the substrate and over the first die; as well as A semiconductor device is attached to the rewiring structure, wherein the semiconductor device includes a second die encapsulated by an encapsulation body, wherein The redistribution structure includes one or more dielectric layers and one or more molding compound layers, the dielectric layers include a dielectric material, the molding compound layers include a molding compound material, and the molding compound material has a lower resistance than the dielectric material. 11 . The method of forming a package according to claim 10 , further comprising filling the cavity with an underfill after attaching the first die to the substrate. 12 . The method of forming a package according to claim 10 , wherein the first die is attached to the substrate using an adhesive.

13. The method of forming a package according to claim 10, wherein forming the redistribution structure comprises forming a through hole over the first side of the substrate and the first die, and forming a molding compound surrounding the through hole, wherein the molding compound is laterally coterminal with the substrate.

14. A method of forming a package, the method comprising: forming a cavity in the substrate; mounting the substrate on a carrier; attaching a first device to the substrate and the cavity, forming a front side redistribution structure on the front side of the substrate and over the first device, the front side redistribution structure comprising one or more dielectric layers and one or more molding compound layers; as well as A second device is coupled to the first device through the front side rewiring structure, the second device is encapsulated by an encapsulation body, and the second device is arranged above the first device in a direction perpendicular to the main surface of the substrate, wherein The dielectric layer includes a dielectric material, the mold compound layer includes a mold compound material, and the mold compound material has a lower impedance than the dielectric material. 15 . The method of forming a package according to claim 14 , further comprising depositing an underfill surrounding the first device. 16 . The method of forming a package according to claim 14 , wherein the carrier is peeled off from the substrate before coupling the second device to the first device. 17 . The method of forming a package of claim 16 , further comprising forming a plurality of electrical connectors over the back side of the substrate after stripping the carrier.

18. The method of forming a package according to claim 14, wherein the cavity is formed using mechanical drilling.

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