Time synchronization distribution input interface circuit and method for compensating for delay thereof

Abstract

A time synchronization distribution input interface circuit and a delay compensation method, control module and computer readable storage medium thereof, wherein the time synchronization distribution input interface circuit comprises a level converter, a phase-locked loop (PPL) module and a control module, and further comprises a first selector and a second selector; the first selector is configured to input a reference measurement clock signal output by the PPL module to the level converter in a delay measurement phase and input a second pulse (1PPS) signal to the level converter in a working phase according to control of the control module; and the second selector is configured to output a signal output by the level converter to a second measurement end of the PPL module in the delay measurement phase and output the signal output by the level converter to a working end of the PPL module in the working phase according to control of the control module.

Description

Technical Field

[0001] This article relates to, but is not limited to, a time synchronization allocation input interface circuit and its delay compensation method, control module, and computer-readable storage medium. Background Technology

[0002] Next-generation mobile communication, namely 5G, places higher demands on high-precision time synchronization networks. At certain network nodes, such as backhaul and fronthaul networks, the synchronization requirements of a single node device relative to the time source reach nanoseconds (ns) or even sub-ns levels. For node devices in the synchronization network, the devices include traditional 1PPS (1 Pulse Per Second) and TOD (Time of Day) RS-422 level interface time synchronization distribution circuits.

[0003] This interface circuit is clearly defined in standards such as G.703 and G.8271. A block diagram of the device connection circuit can be found in [reference needed]. Figure 1 The 422 level converter is connected to the PLL (Phase Locked Loop) module, and the control module is also connected to the PLL module. The 422 level converter converts 422 levels to LVCMOS levels to adapt to the PLL module. A rising edge of 1PPS is typically used to represent an integer second of alignment.

[0004] In this solution, the delay fluctuation of the 422-level converter is relatively large, reaching approximately 7ns. The delay of this type of converter is often calculated using typical values ​​from the datasheet, without considering variations in actual device batches, leading to inaccurate delay compensation and significant errors. This severely compromises the end-to-end time synchronization accuracy of 5G. Furthermore, the device delay also fluctuates by approximately 2ns depending on temperature, failing to meet the requirements for high-precision time synchronization. Summary of the Invention

[0005] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0006] This application provides a time synchronization allocation input interface circuit and its delay compensation method, control module, and computer-readable storage medium to reduce delay errors.

[0007] This application provides a time synchronization distribution input interface circuit, including a level converter, a phase-locked loop (PLL) module, and a control module. It further includes a first selector and a second selector, wherein the first selector, the level converter, the second selector, and the PLL module are sequentially connected, the PLL module is connected to the first selector, and the control module is connected to the first selector, the second selector, and the PLL module, wherein:

[0008] The first selector is used to input the reference measurement clock signal output by the PLL module to the level converter during the delay measurement phase, and to input the second pulse 1PPS signal to the level converter during the working phase, according to the control of the control module.

[0009] The level converter is used to convert the level of the signal output by the first selector;

[0010] The second selector is used to output the signal output by the level converter to the second measurement terminal of the PLL module during the delay measurement phase, and to output the signal output by the level converter to the working terminal of the PLL module during the working phase, according to the control of the control module.

[0011] The PLL module is used to output a system clock signal and a reference measurement clock signal, and the reference measurement clock signal is looped back to the first measurement terminal of the PLL module.

[0012] The control module is used to control the first selector, the second selector, and the PLL module to perform delay measurement and delay compensation based on the delay data obtained from the delay measurement.

[0013] This application also provides a method for delay compensation of a time synchronization allocation input interface circuit, including:

[0014] The delay data is determined by comparing the first input signal and the second input signal of the PLL module to perform delay measurement. The first input signal is the reference measurement clock signal output by the PLL module, which loops back into the PLL module. The second input signal is the reference measurement clock signal output by the PLL module, which passes through the first selector, the level shifter, and the second selector in sequence before being input into the PLL module.

[0015] Delay compensation is performed based on the delay data.

[0016] This application embodiment also provides a control module, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the method for delay compensation of the time synchronization allocation input interface circuit.

[0017] This application also provides a computer-readable storage medium storing computer-executable instructions for performing the delay compensation method for the time synchronization allocation input interface circuit.

[0018] The time synchronization allocation input interface circuit of this application embodiment includes a level converter, a PLL module, and a control module, and further includes: a first selector and a second selector. The first selector, the level converter, the second selector, and the PLL module are sequentially connected. The PLL module is connected to the first selector, and the control module is connected to the first selector, the second selector, and the PLL module. The first selector, according to the control of the control module, inputs the reference measurement clock signal output by the PLL module to the level converter during the delay measurement phase, and inputs a 1PPS signal to the level converter during the operation phase. A level converter is used to convert the signal output by the first selector; the second selector, under the control of the control module, outputs the signal output by the level converter to the second measurement terminal of the PLL module during the delay measurement phase, and outputs the signal output by the level converter to the working terminal of the PLL module during the operation phase; the PLL module outputs a system clock signal and a reference measurement clock signal, the reference measurement clock signal being looped back to the first measurement terminal of the PLL module; the control module controls the first selector, the second selector, and the PLL module to perform delay measurement and delay compensation based on the delay data obtained from the delay measurement. Through this embodiment, delay measurement and delay compensation can be performed on the time synchronization allocation input interface circuit in real time, reducing the delay error of the traditional 1PPS time synchronization interface circuit by approximately two orders of magnitude; thus, the delay error of the external synchronization time interface allocation circuit no longer becomes a bottleneck for the overall device synchronization performance.

[0019] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of a traditional time-synchronized input interface circuit;

[0021] Figure 2 This is a schematic diagram of the time synchronization allocation input interface circuit according to an embodiment of this application;

[0022] Figure 3 This is a flowchart of a method for delay compensation of the time synchronization allocation input interface circuit according to an embodiment of this application. Detailed Implementation

[0023] The embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0024] The steps illustrated in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases the steps shown or described may be performed in a different order than that presented here.

[0025] This application embodiment relates to a time synchronization distribution input interface circuit (1PPS level conversion) and its automatic delay measurement (error less than 100ps) and delay compensation in a time synchronization distribution network node device, for a system node device, to eliminate errors in the level converter caused by batch, voltage, temperature, etc., including but not limited to communication, industrial, Internet of Things and other fields.

[0026] The embodiments of this application can be applied to environments with stringent time synchronization requirements, such as the fronthaul network of mobile 5G and the Internet of Things (IoT) which is sensitive to latency synchronization.

[0027] like Figure 2 As shown, the time synchronization allocation input interface circuit of this application embodiment includes: a first selector 11, a level converter 12, a second selector 13, a PLL module 14, and a control module 15. The first selector 11, the level converter 12, the second selector 13, and the PLL module 14 are connected in sequence. The PLL module 14 is connected to the first selector 11, and the control module 15 is connected to the first selector 11, the second selector 13, and the PLL module 14.

[0028] The first selector 11 is used to input the reference measurement clock signal output by the PLL module 14 to the level converter 12 during the delay measurement phase, and to input the 1PPS signal (1PPS_422) to the level converter 12 during the working phase, according to the control of the control module 15.

[0029] The first selector 11 can be a two-to-one input selector, which selects different inputs according to the control of the control module 15.

[0030] The level converter 12 is used to perform level conversion on the signal (Clka) output by the first selector 11.

[0031] The level converter 12 is usually located on the main control card and converts the 422 level to the LVCMOS level in order to adapt to the PLL module 14.

[0032] The second selector 13 is used to output the signal (Clkb) output by the level converter 12 to the second measurement terminal of the PLL module 14 during the delay measurement phase, and to output the signal output by the level converter 12 to the working terminal of the PLL module 14 during the working phase, according to the control of the control module 15.

[0033] The second selector 13 can be a two-to-one output selector, which selects the output to different ports of the PLL module 14 according to the control of the control module 15.

[0034] To make the delay measurement more accurate, the line from the second selector 13 that outputs the signal from the level converter 12 to the second measurement terminal of the PLL module 14 is the same length as the line from the second selector 13 that outputs the signal from the level converter 12 to the working terminal of the PLL module 14, that is, the PCB (Printed Circuit Board) traces of 1PPS_LVCMOS,Ref_Clk2_b are the same length.

[0035] The first selector 11 and the second selector 13 work together to complete the delay measurement switching function for the reference clock.

[0036] The transmission delay of the first selector 11 and the second selector 13 is small, and the delay due to changes in the environment is also small enough to be negligible.

[0037] In this embodiment, the first selector 11 and the second selector 13 can be relay switches, whose delay is a short-run delay of less than 0.01ps, which can be ignored.

[0038] The PLL module 14 is used to output a system clock signal (Sys_Clock) and a reference measurement clock signal, and the reference measurement clock signal is looped back to the first measurement terminal of the PLL module 14.

[0039] The reference measurement clock signal may include Ref_Clk1 and Ref_Clk2, which are the same signal.

[0040] To make the delay measurement more accurate, the line from the reference measurement clock signal loopback input to the first measurement terminal of the PLL module is the same length as the line from the reference measurement clock signal input to the first selector, that is, the PCB traces of Ref_Clk1 and Ref_Clk2 are the same length.

[0041] The PLL module 14 can also output a noise-filtered signal (1PPS_Filter), as well as a reference clock signal (Ref_Clk3) and a second pulse reference signal (1PPS_Ref) to the control module 15. Ref_Clk3 can be used by the control module 15 to measure the high-level pulse width and low-level pulse width of 1PPS.

[0042] The PLL module 14 is the main module of the system clock unit. It can be used to select the input reference clock, track the reference clock, perform noise filtering, and perform frequency conversion and synthesis.

[0043] In addition, the PLL module 14 may have a zero-delay function, that is, the input and output are edge-aligned when the input and output clock frequencies are integer multiples of each other and the input is noise-free.

[0044] The output of the PLL module 14 can be such that multiple channels are aligned, i.e., the skew (clock offset) value is below 0.03ns.

[0045] The PLL module 14 can also have the function of testing the phase difference between any two inputs; this difference can be read from the internal register of the PLL module 14.

[0046] The control module 15 is used to control the first selector 11, the second selector 13 and the PLL module 14 to perform delay measurement and delay compensation based on the delay data obtained from the delay measurement.

[0047] The control module 15 can be used to configure and initialize the PLL module 14, as well as to select and control the first selector 11 and the second selector 13, and to control and read the phase difference test.

[0048] The control module 15 can select the wider pulse period of the high-level pulse width and the low-level pulse width for delay measurement based on the 1PPS high and low level pulse widths, as well as the rising or falling edge. A reference clock signal generated by the PLL module 14, such as ref_clk3, can be used, with a frequency controllable to 125MHz. This provides a measurement accuracy of approximately 8ns for the edge and pulse width, which meets the requirements.

[0049] A typical 1PPS input uses the rising edge to represent an integer second, while most of this 1-second period is at a 0 level.

[0050] Therefore, the control module 15 can be selected to perform the measurement during the 0 level of the 1PPS input.

[0051] In addition, there are usually parameter specifications for the high and low pulse widths of the input 1PPS, which can be used to select an appropriate pulse period for delay measurement.

[0052] Because the measurement time and accuracy of the phase difference are affected by the frequency of the clock being tested, a suitable frequency for the reference measurement clock signals (Ref_Clk1 and Ref_Clk2) must be selected. Since the PCB trace delay of the reference measurement clock signals is in the range of nanoseconds (ns) to tens of nanoseconds, the frequency of this reference measurement signal can be controlled, for example, at 1 MHz. With a reference measurement clock of 1 MHz, the phase difference measurement accuracy can reach the order of ps within a 10 ms period.

[0053] Through the embodiments of this application, delay measurement and compensation can be performed on the time synchronization allocation input interface circuit in real time, reducing the delay error of the traditional 1PPS time synchronization interface circuit by approximately two orders of magnitude; thus, the delay error of the external synchronization time interface allocation circuit no longer becomes a bottleneck for the overall device synchronization performance. After delay measurement and compensation through the level converter, the delay error of the input synchronization time interface circuit can be reduced to less than 0.1ns; this represents an improvement of nearly two orders of magnitude compared to the traditional solution (7ns).

[0054] like Figure 3 As shown, the method for delay compensation of the time synchronization allocation input interface circuit in this application embodiment includes:

[0055] Step 201: Determine the delay data by comparing the first input signal and the second input signal of the PLL module to perform delay measurement.

[0056] Wherein, the first input signal (Ref_Clk1) is the reference measurement clock signal output by the PLL module looping back into the PLL module, and the second input signal (Ref_Clk2_b) is the reference measurement clock signal output by the PLL module passing through the first selector, the level shifter, and the second selector in sequence before being input into the PLL module.

[0057] In one embodiment, prior to step 201, the method further includes:

[0058] The control module initializes and configures the PLL module.

[0059] The configuration of the PLL module may include the following:

[0060] 1. Configure the PLL module to 0-delay mode.

[0061] Specifically, the PLL module is configured in 0-delay mode, locking the external synchronization time interface input at 1PPS, and aligning the rising edges of the input and output.

[0062] The output clocks 1PPS_Filter, Sys_Clk, Ref_Clk1, Ref_clk3, 1PPS_Ref, etc., have edge alignment (the clock frequencies have multiple relationships).

[0063] 2. Measure the pulse width of the high level and the pulse width of the low level of 1PPS, and select the wider pulse period of the high level and the low level pulse width for delay measurement.

[0064] Based on the input 1PPS high and low pulse width parameters, write specific values ​​to the designated control module register;

[0065] The control module selects a wider pulse period for the delay test of the input circuit, and the test needs to be completed before the pulse width transition.

[0066] 3. Select the period of the reference measurement clock signal based on the estimated delay value and measurement window.

[0067] Wherein, the period of the reference measurement clock signal is greater than the estimated delay value, and the measurement window is smaller than the wider pulse period of the high-level pulse width and the low-level pulse width.

[0068] Before testing the input interface circuit, the delay of the input interface circuit can be roughly evaluated, mainly the delay of the level converter; the period of the reference measurement clock is greater than the delay of the input interface circuit, while the test window time for testing the input interface circuit is less than the larger pulse width period of 1PPS.

[0069] Based on the actual device and the PCB trace delay inside the equipment, a 1MHz reference measurement clock is more appropriate.

[0070] In one embodiment, step 201 includes:

[0071] The delay data is obtained by comparing the phase difference between the first input signal and the second input signal of the PLL module.

[0072] This delay data represents an input delay of 1 PPS.

[0073] During the delay measurement phase, the first selector, under the control of the control module, inputs the reference measurement clock signal output by the PLL module to the level converter, and the second selector, under the control of the control module, outputs the signal output by the level converter to the second measurement terminal of the PLL module.

[0074] The controller reads the relevant data register interface inside the PLL module to obtain measurement data.

[0075] Step 202: Perform delay compensation based on the delay data.

[0076] In one embodiment, the delay data includes a delay value, and step 202 includes:

[0077] Add the aforementioned delay value to the TOD value.

[0078] In this step, the edge value of 1PPS is corrected based on the actual test delay value. In fact, the delay value of the PCB line and the converter is added to the TOD value obtained from the input interface.

[0079] In one embodiment, the method further includes:

[0080] Delayed measurements are performed according to preset measurement time intervals or triggered by temperature changes.

[0081] The control module can modify the measurement time interval. Since environmental factors do not change drastically in a short period of time, the time interval can be set to a large value, or the test can be triggered again based on the temperature change.

[0082] The following are some application examples to illustrate this.

[0083] Application Example 1

[0084] The implementation of the technical solution in a single-frame communication device will be described in further detail below with reference to the accompanying drawings:

[0085] Reference Figure 2 :

[0086] The PCB traces of Ref_Clk1 and Ref_Clk2 are of equal length.

[0087] The PCB traces of 1PPS_LVCMOS and Ref_Clk2_b are of equal length.

[0088] Step 1: Configure the PLL module to 0-delay mode

[0089] Configure the PLL module to 0-delay mode, lock the external synchronization time interface input to 1PPS, and align the rising edges of the input and output.

[0090] The output clocks 1PPS_Filter, Sys_Clk, Ref_Clk1, Ref_clk3, 1PPS_Ref, etc., have edge alignment (the clock frequencies have multiple relationships).

[0091] Step 2, 1PPS high and low pulse width configuration

[0092] Based on the input 1PPS high and low pulse width parameters, write specific values ​​to the designated control module register;

[0093] The control module selects a wider pulse period for the delay test of the input circuit, and the test is completed before the pulse width transition.

[0094] Step 3: Frequency selection of input circuit delay measurement reference clocks Ref_Clk2 and Ref_Clk3

[0095] Before testing the input interface circuit, roughly assess the delay of the input interface circuit, mainly the delay of the level converter; the period of the reference measurement clock is greater than the delay of the input interface circuit, while the test window time for testing the input interface circuit is less than the larger pulse width period of 1PPS.

[0096] Based on the actual device and the PCB trace delay inside the equipment, a 1MHz reference measurement clock is more appropriate.

[0097] Step 4, Selection control of the first selector and the second selector

[0098] The control module selects different inputs and outputs for the first and second selectors based on whether the current time is within a delay measurement cycle.

[0099] Step 5: Delay Measurement and Compensation Algorithm

[0100] Configure the PLL module to measure the phase difference between the two input clocks, Ref_Clk2_b and Ref_Clk1, using the edge of the input from Ref_Clk1 to the input port of the PLL module as a reference. Obtain the measurement data by reading the relevant data registers within the PLL module.

[0101] Before measurement, the control module controls the switches of the first and second selectors, so that during the test, the first selector selects the Ref_Clk2 output and the second selector selects the Clkb input to Ref_Clk2_b.

[0102] Since the PCB trace delays of Ref_Clk1 and Ref_Clk2 are equal, the actual phase difference data tested is the delay of the 1PPS synchronization time allocation input interface circuit within the device.

[0103] The control module can modify the test interval. Since environmental factors do not change drastically in a short period of time, the time interval can be set to a large value, or the test can be triggered again based on the temperature change.

[0104] Application Example 2

[0105] For time allocation between chassis of trunking communication equipment, the traditional solution also adopts 1PPS, TOD; the input interface circuit of 1PPS also has the same situation as single chassis.

[0106] The implementation steps are the same as in Application Example 1.

[0107] Application Example 3

[0108] In addition to the communication bearer equipment, the data server center also uses the 1PPS, TOD time synchronization input interface circuit; for high-precision synchronization requirements, it is also necessary to eliminate and compensate for the delay error of the input interface circuit.

[0109] The implementation steps are the same as in Application Example 1.

[0110] In summary, the embodiments of this application modify the traditional 1PPS time synchronization allocation input interface circuit, so that the delay fluctuations of the 422 level converter in the input interface circuit caused by batch, environmental and other factors can be automatically measured and compensated, reducing the delay error of the input interface circuit from 7ns to 0.1ns, and eliminating the input time allocation bottleneck for the high-precision synchronization time requirements of devices in 5G applications.

[0111] This application embodiment also provides a control module, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the method for delay compensation of the time synchronization allocation input interface circuit.

[0112] This application also provides a computer-readable storage medium storing computer-executable instructions for performing the delay compensation method for the time synchronization allocation input interface circuit.

[0113] In this embodiment, the storage medium may include, but is not limited to, various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0114] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

Claims

1. A time synchronization distribution input interface circuit comprising a level shifter, a phase-locked loop (PLL) module, and a control module, characterized in that, Also include: The first selector, the level converter, the second selector and the PLL module are connected in turn, the PLL module is connected with the first selector, the control module is connected with the first selector, the second selector and the PLL module, wherein: The first selector is used for inputting the reference measurement clock signal output by the PLL module to the level converter in the delay measurement stage and inputting the second pulse 1PPS signal to the level converter in the working stage according to the control of the control module; The level converter is used for carrying out level conversion on the signal output by the first selector; The second selector is used for outputting the signal output by the level converter to the second measurement end of the PLL module in the delay measurement stage and outputting the signal output by the level converter to the working end of the PLL module in the working stage according to the control of the control module; The PLL module is used for outputting the system clock signal and the reference measurement clock signal, and the reference measurement clock signal is looped back to the first measurement end of the PLL module; The control module is used for controlling the first selector, the second selector and the PLL module to carry out delay measurement and delay compensation according to the delay data obtained by delay measurement.

2. The time synchronization distribution input interface circuit of claim 1, wherein, The first selector and the second selector are relay switches.

3. The time synchronization distribution input interface circuit of claim 1, wherein, The line for looped back inputting the reference measurement clock signal to the first measurement end of the PLL module is equal in length to the line for inputting the reference measurement clock signal to the first selector; The line for outputting the signal output by the level converter to the second measurement end of the PLL module by the second selector is equal in length to the line for outputting the signal output by the level converter to the working end of the PLL module by the second selector.

4. A method for delay compensation of a time synchronization distribution input interface circuit, applied to a time synchronization distribution input interface circuit, the time synchronization distribution input interface circuit comprising a level converter, a phase-locked loop (PLL) module, a first selector and a second selector, the first selector, the level converter, the second selector and the PLL module being connected in turn, the PLL module being connected with the first selector, the method comprising: Carrying out delay measurement by comparing a first input signal and a second input signal of the PLL module to determine delay data, wherein the first input signal is a signal for looped back inputting a reference measurement clock signal output by the PLL module to the PLL module, and the second input signal is a signal for inputting the reference measurement clock signal output by the PLL module to the PLL module in turn through the first selector, the level converter and the second selector; Carrying out delay compensation according to the delay data.

5. The method of claim 4, wherein, Before the delay measurement by comparing the first input signal and the second input signal of the PLL module, the method further comprises: Configuring the PLL module to be in 0 delay mode.

6. The method of claim 4, wherein, Before the delay measurement by comparing the first input signal and the second input signal of the PLL module, the method further comprises: measuring the pulse width of the high level and the pulse width of the low level of the 1PPS, and selecting the wider pulse period of the pulse width of the high level and the pulse width of the low level for the delay measurement.

7. The method of claim 6, wherein, After the selecting the wider pulse period of the pulse width of the high level and the pulse width of the low level for the delay measurement, the method further comprises: selecting the period of the reference measurement clock signal according to the estimated delay value and a measurement window, wherein the period of the reference measurement clock signal is greater than the estimated delay value, and the measurement window is less than the wider pulse period of the pulse width of the high level and the pulse width of the low level.

8. The method of claim 4, wherein, The delay measurement by comparing the first input signal and the second input signal of the PLL module, and determining the delay data, comprises: comparing the phase difference of the first input signal and the second input signal of the PLL module to obtain the delay data.

9. The method of claim 4, wherein, The delay data comprises a delay value, and the delay compensation according to the delay data comprises: adding the delay value to a time of day (TOD) value.

10. The method of claim 4, wherein, The method further comprises: triggering the delay measurement according to a preset measurement time interval or according to temperature change.

11. A control module comprising: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method of any one of claims 4-10 when executing the program.

12. A computer readable storage medium storing computer executable instructions for performing the method of any one of claims 4-10.

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