System and method for eliminating offset mismatch in ADC

Abstract

Embodiments of the present disclosure relate to an interleaved analog-to-digital converter ("ADC") system and a method of operating an interleaved analog-to-digital converter ("ADC") system. The interleaved analog-to-digital converter ("ADC") system includes: a first ADC having an input for sampling an analog signal during a first time period, an output for providing a digital signal, and a power supply terminal for receiving a first power supply voltage; a second ADC having an input for sampling an analog signal during a second time period, an output for providing a digital signal, and a power supply terminal for receiving a second power supply voltage; a first deviation estimator for estimating a deviation value of the first ADC; a second deviation estimator for estimating a deviation value of the second ADC; and a comparator for comparing the deviation values, adjusting the first power supply voltage in response to a first output value of the comparator, and adjusting the second power supply voltage in response to a second output value of the comparator.

Description

Technical Field

[0001] The present invention generally relates to systems and methods for eliminating skew mismatch in analog-to-digital converters (ADCs). Background Art

[0002] Time interleaving is a technique that allows the use of multiple ADCs to process analog input signals into digital output signals at a faster rate than the operating sampling rate of each individual data converter. Time interleaving involves time division multiplexing of a parallel array of M identical ADCs (e.g. Figure 1 ), to achieve a higher net sampling rate of 102 (f s , where the sampling period is T s =1 / f s ), even though each ADC in the array actually operates at f s Thus, for example, a 10-bit / 400MSPS ADC can be implemented by interleaving four 10-bit / 100MSPS (million samples per second) ADCs.

[0003] Figure 1 An interleaved ADC 100 includes a plurality of ADCs, including ADC1, ADC2, . . . ADC M ADC 100 may include any number of ADCs. The inputs of the ADCs are coupled together to selectively receive an input voltage V via an analog switch front end circuit device 104. IN The outputs of the ADCs are selectively coupled together correspondingly through the digital output multiplexer circuit device 106 to generate a digital output multiplexer circuit device 106 representing the input analog signal V IN The composite output digital signal D OUT The interleaved ADC 100 has an effective sampling rate 102 of fs, while each individual ADC has an effective sampling rate of f s / M sampling rate.

[0004] exist Figure 1 In the analog input V IN (t) is sampled by "M" ADCs and generates a combined digital output data series D OUT ADC1 first checks V IN (t0) samples and then starts converting them into n-bit digital representation. s After a few seconds, ADC2 will respond to V IN (t0+T s ) is sampled and begins to convert it into an n-bit digital representation. Then, T s After seconds, ADC3 will IN (t0+2T s) for sampling, and so on. In the ADC M V IN (t0+(M-1)×T s ) is sampled, the next sampling cycle will start from ADC1 to V IN (t0+M×T s ) Sampling starts.

[0005] When the n-bit output of the ADC is available sequentially in the same order as the sampling operation, these digital n-bit words are composed of Figure 1 The demultiplexer shown on the right collects the reassembled data output sequence D OUT (t0+L), D OUT (t0+L+T s )、D OUT (t0+L+2T s ).... "L" represents the fixed conversion time of each single ADC, and the recombined data sequence is a sequence with a sampling rate f s Therefore, although each ADC (often referred to as a "channel") is based on f s / M sampling n-bit ADC, but the interleaved ADC 100 is equivalent to f s The input analog signal V IN are processed separately by the ADCs in the interleaved ADC 100 and then reassembled at the output to form the input V IN The high data rate indicates D OUT .

[0006] Figure 2 An example of a clock scheme with a single clock signal for the case of M=4 is shown. The sampling rate of each single ADC in the interleaved ADC is f s / M, the resulting time-interleaved ADC sampling rate 102 is f s .

[0007] As shown, although the sampling rate of the interleaved ADC can be increased relative to the sampling rate of a single ADC in the interleaved ADC, the accuracy of the digital output signal may be reduced due to the relative differences in performance between the individual ADCs. For example, relative differences in offset, gain, and skew (sampling time deviation occurs when some of the channels are sampled earlier or later than a specified time interval) between the individual ADCs may reduce the accuracy of the overall reassembled digital output signal of the interleaved ADC. Summary of the invention

[0008] According to one embodiment, an interleaved analog-to-digital converter ("ADC") system includes: a first ADC having an input configured to sample an analog signal during a first time period, an output configured to provide a digital signal representing the analog signal during the first time period, and a power supply terminal configured to receive a first power supply voltage; a second ADC having an input configured to sample the analog signal during a second time period different from the first time period, an output configured to provide a digital signal representing the analog signal during the second time period, and a power supply terminal configured to receive a second power supply voltage; a first deviation estimator configured to estimate a deviation value of the first ADC; a second deviation estimator configured to estimate a deviation value of the second ADC; and a comparator circuit configured to compare the deviation value of the first ADC with the deviation value of the second ADC, adjust the first power supply voltage in response to a first output value of the comparator circuit, and adjust the second power supply voltage in response to a second output value of the comparator circuit.

[0009] According to another embodiment, an interleaved analog-to-digital converter (“ADC”) system includes: a plurality of ADCs having inputs, outputs, and power supply terminals, the inputs being configured to sample analog signals during dedicated time periods, the outputs being configured to provide digital signals representing the analog signals during dedicated time periods, and the power supply terminals being configured to receive a power supply voltage; a plurality of deviation estimators being configured to estimate deviation values ​​for each of the plurality of ADCs; and a comparator circuit being configured to compare at least two of the deviation values ​​of the plurality of ADCs and to adjust a power supply voltage for at least one of the ADCs in response to an output signal of the comparator circuit.

[0010] According to another embodiment, a method for operating an interleaved analog-to-digital converter (“ADC”) system includes: estimating an offset value of a first ADC in the ADC system, wherein the first ADC converts an analog input signal into a digital output signal during a first time period; estimating an offset value of a second ADC in the ADC system, wherein the second ADC converts the analog input signal into a digital output signal during a second time period different from the first time period; comparing the offset value of the first ADC with the offset value of the second ADC; generating a comparison signal after comparing the offset values; adjusting a power supply voltage of the first ADC in response to a first value of the comparison signal; and adjusting a power supply voltage of the second ADC in response to a second value of the comparison signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a schematic diagram of an exemplary interleaved ADC system;

[0012] Figure 2 yes Figure 1 A timing diagram of an exemplary interleaved ADC system;

[0013] Figure 3 is a schematic diagram of an exemplary interleaved ADC system including a digital calibration circuit arrangement;

[0014] Figure 4 is a schematic diagram of an interleaved ADC system including a digital calibration circuit arrangement according to one embodiment;

[0015] Figure 5 is with Figure 4 A schematic diagram of a digital signal processing circuit device associated with an interleaved ADC system;

[0016] Figure 6 According to one embodiment Figure 4 Timing diagram associated with the interleaved ADC system;

[0017] Figure 7 According to another embodiment Figure 4 Timing diagram associated with the interleaved ADC system;

[0018] Figure 8 is a flow chart of an embodiment method for an interleaved ADC system including two interleaved ADCs;

[0019] Fig. 9 is a flow chart of an embodiment method for an interleaved ADC system including a plurality of interleaved ADCs; and

[0020] Fig. 10A and Fig. 10B Together they form the ratio Figure 8 The flowchart illustrated in FIG. 1 is a more detailed flowchart for an embodiment interleaved ADC system.

[0021] Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated.The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale. DETAILED DESCRIPTION

[0022] Embodiment methods and circuits estimate relative deviations between individual ADCs in an interleaved ADC, and adjust supply voltages associated with the individual ADCs based on the relative deviation estimates to balance the relative deviations. For example, in an interleaved ADC including two ADCs, if the deviation of a first ADC is greater than the deviation of a second ADC, the supply voltage of the first ADC is increased. Alternatively, if the deviation of the second ADC is greater than the deviation of the first ADC, the supply voltage of the second ADC is increased.

[0023] Figure 33 is a schematic diagram of an exemplary interleaved ADC system 300 including a digital calibration circuit arrangement. The interleaved ADC includes an analog section 302 including a plurality of individual converters ADC including ADC1 and ADC2. Converter ADC1 has an input for receiving a first analog input signal and an output for providing a first digital output signal. Converter ADC2 has an input for receiving a second analog input signal and an output for providing a second digital output signal. The digital output signals are combined to provide a composite digital output signal D IN The supply voltage for ADC1 is provided by a low dropout (LDO) voltage regulator LDO1, and the supply voltage for ADC2 is provided by a low dropout voltage regulator LDO2. In the interleaved ADC system 300, the supply voltages for ADC1 and ADC2 are not regulated. The converters ADC1 and ADC2 receive a clock signal CLK DIG , the clock signal CLK DIG is the non-inverting clock signal or the inverting clock signal 306 from the multiplexer 308. Figure 3 The analog switch front end circuitry and the digital output multiplexer circuitry are not shown in the analog portion 302 and have been omitted for clarity.

[0024] Each converter ADC1 and ADC2 may also include Figure 1 The multiple interleaved ADC system shown in FIG. 1 similarly has one or more sub-ADCs arranged in parallel.

[0025] The interleaved ADC 300 also includes a digital portion 304, which includes: a digital calibration circuit device 310; a formatting block 312 for providing a final digital output signal at a digital output 316; and a storage block 314 for providing analytical data about the digital output signal. The digital calibration block may include digital estimation and correction circuit devices for each individual ADC in the interleaved ADC. For example, the digital calibration circuit device 310 may include offset estimation and correction, gain estimation and correction, and bias estimation and correction. Many digital estimation and correction methods are known in the art and are therefore not described in detail. The bias estimation circuit may be implemented in software, digital circuits, or analog circuits, or a combination of these embodiments.

[0026] Figure 4 and Figure 5 Further described are features for adjusting the offset of individual ADCs (and / or sub-ADCs) in an interleaved ADC system by adjusting the supply voltage of the individual ADCs (and / or sub-ADCs). Figure 4 A mechanism is included for adjusting the voltage of the power supply by adjusting the power register used to provide the power supply voltage (this is in Figure 3 is not possible in a circuit of the present invention), and by adjusting a deviation estimation register used to estimate the deviation of each ADC in each ADC (and / or sub-ADC). Figure 4 The digital calibration circuit arrangement shown in FIG. 1 includes at least a deviation estimator circuit, but in some embodiments may also include Figure 3 Some or all of the digital calibration features shown in FIG. Figure 3 and Figure 4 There are some similarities between the aspects of Figure 4 and Figure 5 The circuit shown in provides an adjustable power supply deviation balancing function. Figure 5 A digital processing circuit including a microprocessor according to an embodiment is shown, wherein the microprocessor is used to compare the deviation estimation register with the Figure 4 The power control registers of the MOSFET are linked to provide a bias balancing function.

[0027] therefore, Figure 4 FIG. 4 is a schematic diagram of an interleaved ADC system 400 including a digital calibration circuit device according to one embodiment, the interleaved ADC system 400 including an analog portion 402 and a digital portion 404. The analog portion 402 includes a plurality of individual ADCs including ADC1 and ADC2. Figure 4 The analog switch front end circuitry and the digital output multiplexer circuitry are not shown in the analog portion 402 and have been omitted for clarity.

[0028] The digital portion 404 includes a digital calibration circuit device 410 , a formatting block 412 for providing a final digital output signal 416 , and a storage block 414 .

[0029] In one embodiment, the analog portion 402 includes an LDO1 control register 418 for adjusting the supply voltage of ADC1, and the LDO1 control register 418 may include multiple sub-registers for adjusting the supply voltage of each sub-ADC associated with the converter ADC1. In one embodiment, the analog portion 402 also includes an LDO2 control register 420 for controlling the deviation of ADC2, and the LDO2 control register 420 may also include multiple sub-registers for adjusting the supply voltage of each sub-ADC associated with the converter ADC2.

[0030] In one embodiment, the digital calibration circuit device 410 includes a deviation estimator register 422 for estimating the deviation of ADC1, and the deviation estimator register 422 may include a plurality of sub-registers for estimating the deviation of each sub-ADC associated with the converter ADC1. In one embodiment, the digital calibration circuit device 410 also includes a deviation estimator register 424 for estimating the deviation of ADC2, and the deviation estimator register 424 may also include a plurality of sub-registers for estimating the deviation of each sub-ADC associated with the converter ADC2.

[0031] Figure 5 is with Figure 4 Schematic diagram of a digital signal processing circuit device 500 associated with an interleaved ADC system of FIG. The digital processing circuit device includes the previously described ADC1 deviation estimator register 422 and the ADC2 deviation estimator register 424, the microprocessor 502, and the previously described LDO1 control register 418 and the previously described LDO2 control register 420. The microprocessor receives register data from the deviation estimator registers 422 and 424 and compares the relative deviation data. If the deviation data associated with the ADC1 deviation estimator register 422 (the deviation of ADC1) is greater than the deviation data associated with the ADC2 deviation estimator register 424 (the deviation of ADC2), the digital value of the LDO1 control register 418 (the voltage of LDO1) is increased. If the deviation data associated with the ADC2 deviation estimator register 424 (the deviation of ADC2) is greater than the deviation data associated with the ADC1 deviation estimator register 422 (the deviation of ADC1), the digital value of the LDO2 control register 420 (the voltage of LDO2) is increased. In this way, the relative deviations between ADC1 and ADC2 can be balanced, thereby minimizing errors in the digital output signals of the interleaved ADCs.

[0032] "Deviation" can be defined as leading or lagging the reference sampling time. Figure 6 and Figure 7 Lead and lag deviations associated with a reference sampling time, and adjustment of the supply voltage for balancing the relative deviations in an interleaved ADC system are described. In one embodiment, "deviations" without the qualifiers "lead" or "lag" are considered hysteresis deviations, which can be rebalanced by increasing the power supply to the corresponding ADC. "Adjusting" the supply voltage can therefore include increasing or decreasing the supply voltage as needed to balance the relative deviations of the individual ADCs in the interleaved ADC system.

[0033] Figure 6 Shows Figure 4602 shows a timing diagram of an interleaved ADC system including two ADCs. Timing diagram 602 shows: a first converter ADC1 with an advanced sampling time at time t1, a reference sampling time at time t2, and a second converter ADC2 with a delayed sampling time at time t3. In order to rebalance the deviation of the interleaved ADC system, the power supply of ADC1 is adjusted so that the sampling time of ADC1 coincides with the sampling time of ADC2. A power reduction 604 is performed on ADC1 so that its sampling time now occurs at time t3. Note that in timing diagram 602, the deviation performance is improved, but the sampling time of converter ADC1 and the sampling time of ADC2 are not necessarily consistent with the designed sampling time t2. Timing diagram 606 shows two identical converter sampling times, but different techniques are used to adjust the power supply voltage. In contrast, in order to rebalance the deviation of the interleaved ADC system, the power supply of ADC2 is adjusted so that the sampling time of ADC2 coincides with the sampling time of ADC1. A power increase 608 is performed on ADC2 so that its sampling time now occurs at time t1. It should also be noted that in timing diagram 606, the deviation performance is improved, but the sampling time of converter ADC1 and the sampling time of ADC2 are not necessarily consistent with the designed sampling time t2. Finally, timing diagram 610 shows two identical converter sampling times, but another technique is used to adjust the power supply voltage. In order to rebalance the deviation of the interleaved ADC system, the power supplies of ADC1 and ADC2 are adjusted so that the sampling time of ADC1 and the sampling time of ADC2 are consistent with the reference sampling time t2. A power reduction 612 is performed on ADC1 so that its sampling time now occurs at time t2, and a power increase 614 is performed on ADC2 so that its sampling time now also occurs at time t2. It should also be noted that in timing diagram 610, the deviation performance is improved, and the sampling time of converter ADC1 and the sampling time of ADC2 are consistent with the designed sampling time t2.

[0034] Figure 7 Shows Figure 4702 shows a timing diagram of an interleaved ADC system including three ADCs. Timing diagram 702 shows: a first converter ADC1 with an advanced sampling time at time t1, a reference sampling time at time t2, a second converter ADC2 with a delayed sampling time at time t3, and a third converter ADC3 with a delayed sampling time at time t4. In order to rebalance the deviation of the interleaved ADC system, the power supply of ADC1 is adjusted so that the sampling time of ADC1 is consistent with the sampling time of ADC2. A power reduction 704 is performed on ADC1 so that its sampling time now occurs at time t3. A power increase 706 is also performed on ADC3 so that its sampling time now also occurs at time t3. Note that in timing diagram 702, the deviation performance is improved, but the sampling times of converters ADC1, ADC2 and ADC3 are not necessarily consistent with the designed sampling time t2. Timing diagram 708 shows three identical converter sampling times, but different techniques are used to adjust the power supply voltage. In order to rebalance the deviation of the interleaved ADC system, the power supply of ADC2 is adjusted so that the sampling time of ADC2 is consistent with the sampling time of ADC1. A power increase 710 is performed on ADC2 so that its sampling time now occurs at time t1. A power increase 712 is also performed on ADC3 so that its sampling time now also occurs at time t1. It should also be noted that in timing diagram 708, the deviation performance is improved, but the sampling times of converters ADC1, ADC2 and ADC3 are not necessarily consistent with the designed sampling time t2. Finally, timing diagram 714 shows the same three converter sampling times, but another different technique is used to adjust the power supply voltage. In order to rebalance the deviation of the interleaved ADC system, the power supplies of ADC1, ADC2 and ADC3 are all adjusted so that the sampling times of ADC1 and ADC2, ADC3 are consistent with the reference sampling time t2. A power reduction 716 is performed on ADC1 so that its sampling time now occurs at time t2, a power increase 718 is performed on ADC2 so that its sampling time now also occurs at time t2, and a power increase 720 is performed on ADC3 so that its sampling time now also occurs at time t2. It should also be noted that in timing diagram 714, the deviation performance is improved and the sampling times of converters ADC1, ADC2, and ADC3 are all consistent with the designed sampling time t2.

[0035] Figure 6 and Figure 7 The timing diagram of can be extended to include any number of ADCs and / or sub-ADCs, and include any corresponding number of sampling times. Figure 4For an ADC system of this type, if all 32 sub-ADCs are used (16 sub-ADCs for each converter ADC1 and ADC2), there will be 32 separate sampling times, which result in 32 separate offset estimates that can be balanced using 32 separate power supply adjustments.

[0036] Figure 8 8 is a flow chart of an embodiment method 800 for an interleaved ADC system including two interleaved ADCs. The method begins at step 802, where the deviation of ADC1 is estimated. After estimating the deviation of ADC1, at step 804, the deviation of ADC2 is estimated. At step 806, if the deviation of ADC1 is greater than the deviation of ADC2, the power supply voltage of ADC1 is increased at step 808. At step 810, if the deviation of ADC2 is greater than the deviation of ADC1, the power supply voltage of ADC2 is increased at step 812. In this way, the deviation between converters ADC1 and ADC2 can be more balanced, because the increased power will increase the operating speed and reduce the deviation of the corresponding ADC. Method 800 can be performed only once during an initialization or calibration mode of operation. However, for example, if a change in environmental conditions is detected, method 800 can be performed again. Therefore, at step 814, the state of the environmental operating conditions is monitored. If the environmental operating conditions have not changed, the end of the deviation calibration is reached at step 816. If there is a change in ambient operating conditions, method 800 may be repeated by returning to step 802 .

[0037] Fig. 9 9 is a flow chart of an embodiment method 900 for an interleaved ADC system including a plurality of interleaved ADCs. The method begins at step 902, where the deviation of each ADC in the interleaved ADC system is estimated. After estimating the relative deviations of the ADCs in the interleaved ADC system, all ADCs having deviations different from the baseline deviation are determined at step 904. At step 906, the power supply of each ADC in the selected ADC is adjusted. For example, an ADC with a larger deviation will have its power supply increased, and an ADC with a smaller deviation will have its power supply reduced. All power supply voltages are appropriately adjusted at step 908, and the relative deviations are balanced. Method 900 may be performed only once during an initialization or calibration mode of operation. However, for example, if a change in environmental conditions is detected, method 900 may be performed again. Therefore, at step 910, the state of the environmental operating conditions is monitored. If the environmental operating conditions have not changed, the end of the deviation calibration is reached at step 912. If there is a change in environmental operating conditions, method 900 may be repeated by returning to step 902.

[0038] and Figure 8Compared with the flowchart shown in the figure, Fig. 10A and Fig. 10B Together, they constitute a more detailed flow chart of an embodiment method for operating an interleaved ADC system. Fig. 10A and Fig. 10B Especially for systems with two ADCs, but Fig. 10A and Fig. 10B The embodiment concept illustrated in FIG. 4 can be extended to include an ADC system having more than two ADCs.

[0039] Fig. 10A A first portion 1000A of a detailed flow chart of a system for interleaving two ADCs is shown. At step 1002, the LDO1 and LDO2 registers are set to default values. At step 1004, the deviation of ADC1 (Skew1) and the deviation of ADC2 (Skew2) are measured. At step 1006, a "bias balance (Skew_balance)" is calculated, which is defined as the absolute value of the difference between Skew1 and Skew2 (abs(Skew1-Skew2)). At step 1008, the maximum deviation balance (Skew_balance_max) is set to 0.1 picoseconds. At step 1010, it is determined whether the value of LDO1 is not equal to the maximum value (max) of LDO1, or whether the value of LDO2 is not equal to the maximum value of LDO2, and whether the deviation balance is greater than the maximum deviation balance and whether the deviation balance is less than 0.5 picoseconds. If not, the method continues at path 1028 to Fig. 10B If yes, the method proceeds to step 1012. At step 1012, LDO1 and LDO2 are again set to default values ​​and the deviations of ADC1 and ADC2 are again measured. The deviation balance is again calculated as the absolute value of the difference between Skew1 and Skew2. Fig. 10B The detailed flow chart shown in FIG. 1 is continued in the second part 100B. Fig. 10A It also shows the Fig. 10B Return path 1026.

[0040] therefore, Fig. 10B A second portion 1000B of the detailed flow chart of a system for interleaving two ADCs is shown. At step 1026, it is determined whether the deviation balance is greater than the maximum deviation balance, and whether LDO1 is less than the maximum value and whether LDO2 is less than the maximum value. If not, the method returns along path 1026 to Fig. 10AIf yes, the method proceeds to step 1016. At step 1016, if Skew1 is greater than Skew2, then LDO1 is increased at step 1020. If Skew1 is not greater than Skew2, then LDO2 is increased at step 1018. After step 1018 or step 1020, the method proceeds to step 1022 to calculate a new deviation balance value, and the method continues at step 1014. Fig. 10A Path 1028 is also shown as ending the method at step 1024.

[0041] Despite Figure 8 , Fig. 9 , Fig. 10A and Fig. 10B An embodiment method is shown in the flowchart of , but those skilled in the art will recognize that many other such flowcharts can be constructed to adjust the power supply (increase or decrease the power supply value, or increment or decrement the control register) of at least one ADC or sub-ADC in the interleaved ADC system so as to balance the deviations of these ADCs and so as to provide a more accurate composite digital output signal corresponding to the analog input signal.

[0042] Example embodiments of the invention are summarized here. Other embodiments may also be understood from the entire specification and claims submitted herein.

[0043] Example 1. According to one embodiment, an interleaved analog-to-digital converter ("ADC") system includes: a first ADC having an input configured to sample an analog signal during a first time period, an output configured to provide a digital signal representing the analog signal during the first time period, and a power supply terminal configured to receive a first power supply voltage; a second ADC having an input configured to sample the analog signal during a second time period different from the first time period, an output configured to provide a digital signal representing the analog signal during the second time period, and a power supply terminal configured to receive a second power supply voltage; a first deviation estimator configured to estimate a deviation value of the first ADC; a second deviation estimator configured to estimate a deviation value of the second ADC; and a comparator circuit configured to compare the deviation value of the first ADC with the deviation value of the second ADC, adjust the first power supply voltage in response to a first output value of the comparator circuit, and adjust the second power supply voltage in response to a second output value of the comparator circuit.

[0044] Example 2. An ADC system according to Example 1, wherein the first bias estimator includes a first bias estimator register associated with the first ADC, and wherein the second bias estimator includes a second bias estimator register associated with the second ADC.

[0045] Example 3. The ADC system according to any of the preceding examples further includes: a first voltage regulator configured to provide the first power supply voltage to the first ADC; and a second voltage regulator configured to provide the second power supply voltage to the second ADC.

[0046] Example 4. An ADC system according to any of the preceding examples, wherein the first voltage regulator comprises a low dropout (LDO) voltage regulator having an LDO control register, and wherein the second voltage regulator comprises a low dropout (LDO) voltage regulator having an LDO control register.

[0047] Example 5. An ADC system according to any of the preceding examples, wherein the comparator circuit comprises a digital processor.

[0048] Example 6. The ADC system of any of the preceding examples, wherein the comparator circuit is configured to adjust at least one of the first supply voltage or the second supply voltage during an initial operating mode of the ADC system.

[0049] Example 7. The ADC system of any of the preceding examples, wherein the comparator circuit is configured to readjust at least one of the first supply voltage or the second supply voltage upon detecting a change in an environmental condition of the ADC system.

[0050] Example 8. According to one embodiment, an interleaved analog-to-digital converter ("ADC") system includes: a plurality of ADCs having inputs configured to sample analog signals during dedicated time periods, outputs configured to provide digital signals representing the analog signals during the dedicated time periods, and power supply terminals configured to receive a power supply voltage; a plurality of deviation estimators configured to estimate deviation values ​​for each of the plurality of ADCs; and a comparator circuit configured to compare at least two of the deviation values ​​of the plurality of ADCs and adjust the power supply voltage of at least one of the ADCs in response to an output signal of the comparator circuit.

[0051] Example 9. The ADC system of Example 8, wherein each of the plurality of bias estimators comprises a bias estimator register associated with a corresponding one of the plurality of ADCs.

[0052] Example 10. The ADC system of any of the preceding examples further comprises a plurality of voltage regulators configured to provide a supply voltage to the plurality of ADCs.

[0053] Example 11. The ADC system of any of the preceding examples, wherein each of the plurality of voltage regulators comprises a low dropout (LDO) voltage regulator having an LDO control register.

[0054] Example 12. An ADC system according to any of the preceding examples, wherein the comparator circuit comprises a digital processor.

[0055] Example 13. An ADC system according to any of the preceding examples, wherein the comparator circuit is configured to adjust at least one of the supply voltages during an initial operating mode of the ADC system.

[0056] Example 14. The ADC system of any of the preceding examples, wherein the comparator circuit is configured to readjust at least one of the supply voltages upon detecting a change in an environmental condition of the ADC system.

[0057] Example 15. According to one embodiment, a method of operating an interleaved analog-to-digital converter ("ADC") system, the method comprising: estimating an offset value of a first ADC in the ADC system, wherein the first ADC converts an analog input signal into a digital output signal during a first time period; estimating an offset value of a second ADC in the ADC system, wherein the second ADC converts the analog input signal into a digital output signal during a second time period different from the first time period; comparing the offset value of the first ADC with the offset value of the second ADC; generating a comparison signal after comparing the offset values; adjusting a power supply voltage of the first ADC in response to a first value of the comparison signal; and adjusting the power supply voltage of the second ADC in response to a second value of the comparison signal.

[0058] Example 16. The method of Example 15, wherein estimating the offset value of a first ADC in the ADC system comprises generating a first offset estimator register value, and wherein estimating the offset value of a second ADC in the ADC system comprises generating a second offset estimator register value.

[0059] Example 17. The method of any of the preceding examples further comprises: providing a first power supply voltage to the first ADC using a first voltage regulator; and providing a second power supply voltage to the second ADC using a second voltage regulator.

[0060] Example 18. A method according to any of the preceding examples, wherein adjusting the supply voltage of the first ADC in response to a first value of the comparison signal includes: adjusting a register of the first voltage regulator, and wherein adjusting the supply voltage of the second ADC in response to a second value of the comparison signal includes: adjusting a register of the second voltage regulator.

[0061] Example 19. The method of any of the preceding examples, wherein comparing the offset value of the first ADC and the offset value of the second ADC and generating a comparison signal after comparing the offset values ​​are performed by a digital processor.

[0062] Example 20. A method according to any one of the preceding examples, wherein the following operation is performed once during an initial operating mode of the ADC system: adjusting the supply voltage of the first ADC in response to a first value of the comparison signal, or adjusting the supply voltage of the second ADC in response to a second value of the comparison signal.

[0063] Although embodiments have been illustrated and described for adjusting the power supply of a single ADC in an interleaved ADC system in response to estimating the deviation of the single ADC, those skilled in the art will appreciate that the power supply of all or at least some of the sub-ADCs in the individual sub-ADCs may also be adjusted in a manner similar to that described herein, particularly in embodiments where access to the individual sub-ADC deviation estimator registers is possible.

[0064] Simulations show that, relative to an interleaved ADC system not including the embodiment concepts, the embodiment concepts provide significantly increased performance in the composite digital output signal with respect to the following specifications: SFDR (spurious free dynamic range), SNR (signal-to-noise ratio), and ENOB (effective number of bits).

[0065] One advantage of the embodiments described herein is that they save power consumed in performing digital calibration. Another advantage is that the embodiments described herein do not interact with sensitive internal nodes of analog circuit devices that may cause other system problems. Finally, one advantage is that the embodiments described herein can be used instead of or in conjunction with previous offset rebalancing solutions and correction solutions as needed.

[0066] Although the present invention has been described with reference to illustrative embodiments, this description is not intended to be interpreted in a limiting sense. Various modifications and combinations of the illustrative embodiments and other embodiments of the present invention will be apparent to those skilled in the art with reference to this description. Therefore, it is intended that the appended claims cover any such modifications or embodiments.

Claims

1. An interleaved analog-to-digital converter (ADC) system, comprising: a first ADC having an input configured to sample an analog signal during a first time period; an output configured to provide a digital signal representative of the analog signal during the first time period; and a power terminal configured to receive a first power voltage; a second ADC having an input configured to sample the analog signal during a second time period different from the first time period; an output configured to provide a digital signal representative of the analog signal during the second time period; and a power terminal configured to receive a second power voltage; A first bias estimator configured to estimate a bias value of the first ADC; a second deviation estimator configured to estimate a deviation value of the second ADC; as well as A comparator circuit is configured to compare the offset value of the first ADC with the offset value of the second ADC, adjust the first supply voltage in response to a first output value of the comparator circuit, and adjust the second supply voltage in response to a second output value of the comparator circuit.

2. The ADC system of claim 1, wherein the first offset estimator comprises a first offset estimator register associated with the first ADC, and wherein the second offset estimator comprises a second offset estimator register associated with the second ADC.

3. The ADC system according to claim 1, further comprising: a first voltage regulator configured to provide the first supply voltage to the first ADC; as well as The second voltage regulator is configured to provide the second power supply voltage to the second ADC.

4. The ADC system of claim 3, wherein the first voltage regulator comprises a low dropout (LDO) voltage regulator having an LDO control register, and wherein the second voltage regulator comprises a low dropout (LDO) voltage regulator having an LDO control register.

5. The ADC system of claim 1, wherein the comparator circuit comprises a digital processor. 6 . The ADC system of claim 1 , wherein the comparator circuit is configured to adjust at least one of the first supply voltage or the second supply voltage during an initial operation mode of the ADC system. 7 . The ADC system of claim 6 , wherein the comparator circuit is configured to readjust at least one of the first supply voltage or the second supply voltage upon detecting a change in an environmental condition of the ADC system.

8. An interleaved analog-to-digital converter (ADC) system comprising: a plurality of ADCs having inputs, outputs, and power supply terminals, the inputs being configured to sample analog signals during dedicated time periods, the outputs being configured to provide digital signals representative of the analog signals during the dedicated time periods, and the power supply terminals being configured to receive a power supply voltage; a plurality of bias estimators configured to estimate a bias value of each ADC of the plurality of ADCs; as well as A comparator circuit is configured to compare at least two of the deviation values ​​of the plurality of ADCs and adjust the supply voltage of at least one of the ADCs in response to an output signal of the comparator circuit. 9 . The ADC system of claim 8 , wherein each of the plurality of deviation estimators comprises a deviation estimator register associated with a corresponding one of the plurality of ADCs. 10 . The ADC system of claim 8 , further comprising a plurality of voltage regulators configured to provide a supply voltage to the plurality of ADCs.

11. The ADC system of claim 10, wherein each of the plurality of voltage regulators comprises a low dropout (LDO) voltage regulator having an LDO control register.

12. The ADC system of claim 8, wherein the comparator circuit comprises a digital processor.

13. The ADC system of claim 8, wherein the comparator circuit is configured to adjust at least one of the supply voltages during an initial operating mode of the ADC system.

14. The ADC system of claim 13, wherein the comparator circuit is configured to readjust at least one of the supply voltages upon detecting a change in an environmental condition of the ADC system.

15. A method of operating an interleaved analog-to-digital converter (ADC) system, the method comprising: estimating an offset value of a first ADC in the ADC system, wherein the first ADC converts an analog input signal into a digital output signal during a first time period; estimating an offset value of a second ADC in the ADC system, wherein the second ADC converts the analog input signal into a digital output signal during a second time period different from the first time period; comparing the deviation value of the first ADC with the deviation value of the second ADC; generating a comparison signal after comparing the deviation value; adjusting a supply voltage of the first ADC in response to a first value of the comparison signal; and A supply voltage of the second ADC is adjusted in response to a second value of the comparison signal.

16. The method of claim 15, wherein estimating an offset value of a first ADC in the ADC system comprises: A first bias estimator register value is generated, and wherein estimating a bias value for a second ADC in the ADC system includes generating a second bias estimator register value.

17. The method according to claim 15, further comprising: Providing a first power supply voltage to the first ADC using a first voltage regulator; as well as A second supply voltage is provided to the second ADC using a second voltage regulator.

18. The method of claim 17, wherein adjusting the supply voltage of the first ADC in response to the first value of the comparison signal comprises: A register of the first voltage regulator is adjusted, and wherein adjusting the supply voltage of the second ADC in response to the second value of the comparison signal comprises adjusting a register of the second voltage regulator.

19. The method of claim 15, wherein comparing the offset value of the first ADC and the offset value of the second ADC, and generating a comparison signal after comparing the offset values ​​are performed by a digital processor.

20. The method of claim 15, wherein the following operation is performed once during an initial operation mode of the ADC system: adjusting the supply voltage of the first ADC in response to a first value of the comparison signal, or adjusting the supply voltage of the second ADC in response to a second value of the comparison signal.

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