Device, system and method for data processing

Abstract

The present application relates to apparatus, systems and methods for data processing. According to one general aspect, an apparatus may include a graphics processing engine including a pipeline having a plurality of substantially sequential circuit stages, the pipeline including a front-end output logic circuit configured to substantially separate positional information into positional information pipeline portions and non-positional information into non-positional information pipeline portions. The pipeline is configured to perform multi-stage culling of data.

Description

Technical Field

[0001] The present description relates to computer architecture, or more particularly, to apparatus and methods for optimized pixel shader attribute management. Background Art

[0002] A graphics processing unit (GPU) is typically a specialized electronic circuit designed to quickly manipulate and change memory to speed up the creation of images in a frame buffer for output to a display device. GPUs are used in embedded systems, mobile phones, personal computers, workstations, and game consoles. Modern GPUs are very efficient at manipulating computer graphics and image processing. Their highly parallel structure makes them more efficient than general-purpose central processing units (CPUs) for algorithms that process large blocks of data in parallel. In personal computers, GPUs can be present on a graphics card or embedded on the motherboard. In some processors, they are embedded on the same chip.

[0003] GPUs can be used to accelerate the memory-intensive work of texture mapping and rendering polygons, or to accelerate geometric calculations such as vertex rotations and translations to different coordinate systems. GPU development includes support for programmable shaders (which can manipulate vertices and textures using many of the same operations supported by the CPU), oversampling and interpolation techniques to reduce aliasing, and very high-precision color spaces.

[0004] In computer graphics, a computer graphics pipeline, rendering pipeline, or simply graphics pipeline is a conceptual model that describes what steps a graphics system needs to perform to render a three-dimensional (3D) scene to a two-dimensional (2D) screen. Once a 3D model is created, such as in a video game or any other 3D computer animation, the graphics pipeline is the process of converting the 3D model into what the computer displays. Summary of the invention

[0005] According to one general aspect, an apparatus may include a graphics processing engine including a pipeline having a plurality of substantially sequential circuit stages, the pipeline including front-end output logic configured to substantially separate positional information into a positional information pipeline portion and to separate non-positional information into a non-positional information pipeline portion, wherein the pipeline is configured to perform multi-stage culling of data.

[0006] According to another general aspect, a system may include a processor core configured to process instructions. The system may include a graphics core configured to render graphics data, wherein the graphics core includes a graphics processing pipeline, the graphics processing pipeline including a plurality of circuit stages substantially sequentially arranged to at least partially process data as the data flows through the graphics processing pipeline. The circuit stages may include front-end output logic circuitry configured to provide non-culled data to one or more subsequent circuit stages. The circuit stages may include a multi-stage culling portion of the circuit stages configured to indicate to the front-end output logic circuitry which data is culled data.

[0007] According to another general aspect, a method may include receiving graphics data from one or more front-end output buffers. The method may include determining which graphics data may be removed via multi-stage culling involving multiple graphics pipeline circuit stages, wherein the determining includes converting a triangle into a triangle fan. The method may include preventing subsequent graphics pipeline circuit stages from accessing the culled data.

[0008] The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features will be apparent from the description and drawings, and from the claims.

[0009] A system and / or method for computer architecture, or more specifically, an apparatus and method for optimized pixel shader attribute management is shown in and / or described in conjunction with at least one of the accompanying drawings, substantially as more fully set forth in the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a block diagram of an example embodiment of a system in accordance with the disclosed subject matter.

[0011] Figure 2 is a block diagram of an example embodiment of a system in accordance with the disclosed subject matter.

[0012] Figure 3 is a schematic block diagram of an information processing system that may include devices formed according to the principles of the disclosed subject matter.

[0013] Similar reference symbols in different drawings identify similar elements. DETAILED DESCRIPTION

[0014] Various example embodiments will be described more fully below with reference to the accompanying drawings, some of which are shown in the accompanying drawings. However, the subject matter of the present disclosure can be implemented in many different forms and should not be construed as being limited to the example embodiments set forth herein. On the contrary, these example embodiments are provided to make the present disclosure thorough and complete, and will fully convey the scope of the subject matter of the present disclosure to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity.

[0015] It should be understood that when an element or layer is referred to as being "on another element or layer," "connected to another element or layer," or "coupled to another element or layer," it may be directly on, directly connected to, or coupled to another element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to another element or layer," there are no intermediate elements or layers. Throughout the text, like numbers refer to like elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0016] It will be understood that although the term first, second, third, etc. can be used to describe various elements, components, regions, layers, and / or partitions in this article, these elements, components, regions, layers, and / or partitions should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer, or partition from another region, layer, or partition. Therefore, the first element, component, region, layer, or partition discussed below can be referred to as the second element, component, region, layer, or partition, without departing from the teaching of the subject matter of the present disclosure.

[0017] For ease of description, spatial relative terms (such as "below", "below", "below", "on", "above", etc.) may be used herein to describe the relationship between an element or feature as shown in the figure and another one or more elements or features. It should be understood that spatial relative terms are intended to include different orientations of the device in use or in operation, in addition to the orientation depicted in the figure. For example, if the device in the figure is flipped, the element described as being below or below other elements or features will be oriented above the other elements or features. Therefore, the exemplary term "below" can include both above and below orientations. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein are interpreted accordingly.

[0018] Similarly, for ease of description, electrical terms (such as "high", "low", "pullup", "pull down", "1", "0", etc.) may be used herein to describe voltage levels or currents relative to other voltage levels or relative to another one or more elements or features as shown. It should be understood that electrical-related terms are intended to include different reference voltages for the device in use or operation in addition to the voltages or currents depicted in the figures. For example, if the device or signal in the figure is reversed or uses other reference voltages, currents, or charges, the elements described as "high" or "pull up" will be "low" or "pull down" compared to the new reference voltage or current. Therefore, the exemplary term "high" can include relatively low or high voltages or currents. The device can be based on different electrical reference frameworks, and the electrical-related descriptors used herein can be interpreted accordingly.

[0019] The terms used herein are only for describing specific example embodiments and are not intended to limit the subject matter of the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are intended to include the plural forms as well. It will also be understood that when the terms "include" and / or "comprise" are used in this specification, the presence of the stated features, wholes, steps, operations, elements, and / or components is specified, but the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof is not excluded.

[0020] Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized example embodiments (and intermediate structures). As such, variations in the shapes of the illustrations are to be expected due to, for example, manufacturing techniques and / or tolerances. Thus, the example embodiments should not be construed as limited to regions of specific shapes shown herein, but rather include deviations in shapes that are caused, for example, by manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of a region of the device, and are not intended to limit the scope of the subject matter of the present disclosure.

[0021] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the subject matter of the present disclosure belongs. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and will not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0022] Hereinafter, example embodiments will be explained in detail with reference to the accompanying drawings.

[0023] Figure 1 1 is a block diagram of an example embodiment of a system 100 according to the disclosed subject matter. In various embodiments, the system 100 may be part of a graphics processing unit (GPU), either separate or integrated into a chipset or processor (e.g., a system on a chip (SoC)). In various embodiments, the system 100 may include a graphics processing pipeline. A portion of the high-level pipeline 100 is shown for purposes of illustration. Figure 2 A more detailed section of the pipeline is shown to provide context.

[0024] In the illustrated embodiment, system 100 may include multiple stages or separate circuits in which data is processed and then conventionally passed from pipeline stage to pipeline stage. Conventionally, such passing of data results in increased power usage (and excess heat) and wastes computing resources. In the illustrated embodiment, and with reference to Figure 2 Described in more detail, the system 100 can discard or remove data when it is determined that the data is no longer needed. Therefore, the illustrated embodiment can achieve lower power usage, heat, and less waste of computing resources.

[0025] In the illustrated embodiment, the graphics pipeline 100 typically processes data including vertices (one or more), where a vertex is a point in a three-dimensional world. Many points or vertices in the world are used to connect the surfaces of objects. Vertices typically form primitives or basic shapes. A triangle is the most common geometric primitive in computer graphics. It is defined by three vertices and a normal vector. In various embodiments, one or three normal vectors are sometimes used. They are typically derived from vertex positions and order. For example, the front face is defined by the vertex order and relative position. Signed triangle areas are typically calculated, and the sign specifies the front or back face. The normal vector is used to indicate the front face of a triangle and is a vector perpendicular to the surface. Triangle vertices can have many attributes. For example, attributes such as color or texture position (a texture is an image "glued" on top of a triangle). Attributes can be considered to include data that specifies a position (positional; for example, x / y coordinates) or data about things other than position (non-positional; for example, color, brightness, etc.).

[0026] In the illustrated embodiment, the system 100 may include an input attribute fetching unit or circuit 102. In such an embodiment, the input attribute fetching circuit 102 may be configured to receive vertex attribute data (eg, in the form of an array).

[0027] In the illustrated embodiment, the system 100 may include one or more shader units or circuits 104, such as, for example, a vertex shader (VS) or a pixel shader (PS). In various embodiments, the vertex shader may be configured to convert the 3D position of each vertex in some modeling or object 3D space to 2D coordinates that appear on the screen, and convert the depth value for the Z buffer to a 3D space called "clip space", in which clipping can be performed on the primitives formed by these vertices. Clipping removes non-visible primitives and subdivides partially visible primitives.

[0028] In the illustrated embodiment, the system 100 may include one or more front-end (FE) stages or circuits 106, such as, for example, optional stages or required front-end stages, such as primitive assemblies (PAs). In various embodiments, these FE stages 106 may include zero or more optional processing units or circuits (not shown separately) that may be added to or removed from the pipeline based on the desired processing tasks. Example FE stages 106 may include tessellation shaders, geometry shaders, hull shaders, domain shaders, unified shaders, and the like. It should be understood that the above are merely some illustrative examples and the disclosed subject matter is not limited thereto.

[0029] In the illustrated embodiment, the input attribute acquisition circuit 102, the vertex shader 104, and any front-end stage 106 can be conceptually grouped into a front-end pipeline portion 150 of the system 100. These front-end units or circuits can be configured to pre-process or prepare vertex data for final processing and rendering. This can include forming vertices into primitives and then passing vertex positions and attributes to the back end 152 for use by the pixel shader.

[0030] In the illustrated embodiment, stages 108, 110, 112, 114, 115, 116, and 118 may be considered part of a back-end pipeline portion 152. In such an embodiment, back-end 152 may be configured to perform final graphics processing before an image is displayed on a screen or display (not shown).

[0031] In the illustrated embodiment, the system 100 may include a clipping, culling, and viewport manipulation (CCV) unit or circuit 108. In various embodiments, the CCV unit 108 may be configured to determine which primitives need to be changed or clipped and any changes that need to be made to the virtual viewport or camera, and then cull data as needed. In conventional systems, the CCV unit 108 may be the only or primary culling operation in the system. However, as described below with reference to Figure 2 As described, the illustrated system 100 may employ multiple stages of culling operations.

[0032] In the illustrated embodiment, system 100 may include a rasterization engine, unit, or circuit 110. In such an embodiment, rasterization circuit 110 may be configured to use primitive outlines to calculate which pixels are covered by primitives.

[0033] In the illustrated embodiment, the system 100 may include an early depth test unit or circuit 112. The early depth test unit or circuit 112 may be configured to interpolate attributes to pixels or sampling locations for use by pixel shaders. In various embodiments, this may be done in dedicated interpolation hardware, by pixel shaders, or by some combination of these pixel shaders.

[0034] In the illustrated embodiment, the system 100 may include one or more pixel shader (PS) units or circuits 114. In various embodiments, the PS unit 114 may be configured to calculate pixel color and other pixel data, which is typically derived using texture image data. In various embodiments, the texture image data may be provided by a texture unit or circuit 115.

[0035] In the illustrated embodiment, system 100 may include a post depth test unit or circuit 116. In such an embodiment, post depth test unit or circuit 116 may be configured to perform pixel depth testing and update depth and stencil buffers. In various embodiments, depth units 112 and 116 may perform additional culling.

[0036] In the illustrated embodiment, the system 100 may also include a color mixing and output unit or circuit 118. The color mixing and output unit 118 may be configured to perform pixel blending calculations and write the final pixel color to a color buffer (not shown). The pixel may then be displayed on a screen (not shown).

[0037] Figure 2 is a block diagram of an example embodiment of a system or pipeline 200 according to the disclosed subject matter. In the illustrated embodiment, Figure 1 A more detailed version of a subset of the graphics pipeline is shown.

[0038] In the illustrated embodiment, the pipeline 200 may include a plurality of front-end (FE) shader units or circuits 202. These FE shaders 202 may calculate pixel shader attributes and other data. Each shader 202 may include a front-end output buffer (FOB) 203. In another embodiment, the FOB 203 may be separate and may be filled by the last shader 202 in the image processing. In another embodiment, the FOB 203 may be included as part of a front-end output logic (FOL) unit 204, as described below. The FOB 203 may be configured to store shader attributes.

[0039] In the illustrated embodiment, the system 200 may include a FE output logic (FOL) unit or circuit 204. In various embodiments, the FOL unit or circuit 204 may read vertex data (including attributes) and pass the data to subsequent pipeline stages. In the illustrated embodiment, the FOL unit 204 may help cull or remove unneeded or unwanted data so that the various pipeline stages do not have to process it or the system 200 does not need to move the data. Likewise, processing and moving data involves higher power usage and heat generation, both of which are desired to be reduced.

[0040] In the illustrated embodiment, the FOL unit or circuit 204 can be configured to separate the data path into two parts, a positional path (stages 206, 208, and 210) and a non-positional path (stages 222 and 224). As described below, attributes 250 including positional information can be processed and used to make a rejection determination. Attributes 252 including non-positional information can be maintained (as described below) until a positional rejection determination has been made, and then rejected separately. In such an embodiment, the FOL unit 204 can facilitate a multi-stage rejection process that removes unwanted information before it is processed by subsequent stages.

[0041] In such an embodiment, the FOL unit or circuit 204 can be configured to read vertex position information and primitive connectivity from the FOB(s) 203 and form primitives. The FOL unit 204 can be configured to send the position information and associated connectivity from these vertices to the CCV stage 206. In turn, the FOL unit 204 can receive information from the CCV stage 206 about which primitives survived or did not survive the CCV primitive and vertex culling. The FOL unit 204 can be configured to read the surviving non-position vertex attributes from the FOB 203 after culling and pass those required by the primitives to the following stages (e.g., stages 222 and 224, etc.).

[0042] The system 200 may include a clipping, culling, viewport (CCV) unit or circuit 206. The CCV unit 206 may be configured to perform primitive clipping and vertex culling. It may also eliminate small primitives that cannot render any pixels or samples. It may also perform viewport transformation operations.

[0043] In such an embodiment, CCV unit 206 may be configured to inform FOL unit 204 which vertices or primitives' vertices need to be passed down pipeline 200 , and which primitives or vertices are to be discarded, as described above and shown by signal 254 .

[0044] In one embodiment, CCV unit 206 can also perform clipping. In various embodiments, CCV unit 206 can be configured to perform primitive clipping, but does not perform attribute calculation. All primitives generated by clipping a single input primitive can be referred to as "sub-primitives". For example, a clipped triangle (triangle) can be converted into a triangle fan (trianglefan), because triangle clipping usually produces multiple output triangles. These sub-primitives may only need to be unique during rasterization. In such an embodiment, CCV unit 206 may be configured to calculate a set of barycentric factors for all clipped primitives. In various embodiments, attribute setting unit 222 can use these barycentric factors to calculate the vertex attribute values ​​of clipping. All sub-primitives of input primitives can use the same attribute setting output (for example, the same plane equation or barycentric setting).

[0045] In the illustrated embodiment, the system 200 may include a rasterization setup unit or circuit 208. In such an embodiment, the rasterization setup unit 208 may be configured to calculate setup information for the rasterization and depth testing stage 210.

[0046] In such an embodiment, the rasterization setup unit 208 may be configured to determine which information is useful for attribute setting and which information is needed for control purposes, or neither. In one embodiment, this information may be stored in a buffer until needed. Primitives may be tested to see if any coverage survived culling, such as from scissor regions, tiled regions, etc. Primitives (and their attributes) that do not survive all tests may be culled at this level.

[0047] In the illustrated embodiment, the system 200 may include a rasterization and early depth testing unit or circuit 210. As described above, in various embodiments, these may be multiple units or circuits. In the illustrated embodiment, the rasterization unit 210 may be configured to generate pixel or sample coverage information for each primitive. Also, the early depth testing portion of the unit 210 may be configured to perform a depth test before executing the pixel shader 212. In such an embodiment, primitives that are not covered or not visible on the screen may be culled after rasterization, early depth, and / or stencil testing.

[0048] In various embodiments, additional units or circuits (not shown) may be part of system 200. In such embodiments, additional culling may occur or be performed by those units. In various embodiments, these culling operations may include redundant coverage discard (RDC) and / or quadruple merging. It should be understood that the above are merely a few illustrative examples and the disclosed subject matter is not limited thereto.

[0049] In the illustrated embodiment, the system 200 may include an attribute setting unit or circuit 222. As described above, the attribute setting unit 222 may receive non-position information 252 associated with the position information 250. In such an embodiment, the attribute setting unit 222 may be configured to cull various non-position information 252 based on information and culling activities of the position portion of the pipeline (e.g., units 206, 208, and 210). In various embodiments and in the system 200 as a whole, attribute culling may be performed on a per-vertex basis. In such an embodiment, attributes of vertices that are no longer needed because the surviving primitives no longer need the vertices may be culled.

[0050] For example, in response to feedback 254 provided by CCV unit 206, a first culling may occur not through attribute setup unit 222, but through FOL unit 204. FOL unit 204 may simply avoid sending any culled attributes to attribute setup unit 222. A second culling may occur when rasterization setup unit 208 provides position information culling results (via position information queue 220). A third culling may occur when feedback is received from rasterization unit 210 (via signal 256). In another embodiment, feedback via 220 and 256 may be sent back to FOL unit 204 so that culled non-position information is never sent to attribute setup unit 222.

[0051] In such an embodiment, non-position attribute processing may be delayed until all culling information has been received from the multi-stage culling portion (units 206, 208, and 210). If a particular vertex does not have "real-time" coverage or has already been culled, the non-position information associated with it may also be culled or discarded. Thus, the amount of information passed to the next stage 224 and 212 may be reduced not only by the position level, but also by the non-position level. Likewise, splitting the attributes into two pipelines means that less information travels or is transmitted through the two pipelines. In various embodiments, all attribute calculations may be performed by the attribute setting unit 222, including applying the center of gravity factors from clipping and perspective correction.

[0052] Furthermore, attribute information required for interpolation (such as a plane equation or a centroid factor) may be stored in an attribute storage memory included in the attribute setting unit 222 (or as a separate memory, not shown) for use.

[0053] In various embodiments, system 200 may include a hardware interpolation unit or circuit 224. Interpolation unit 224 may be configured to interpolate data.

[0054] In various embodiments, system 200 may include a pixel shader (PS) unit or circuit 212. Pixel shader unit 212 may be configured to receive non-culled or surviving position information and non-culled or surviving non-position information and calculate color and other attributes of each "fragment" or unit of rendering work that affects at most a single output pixel.

[0055] In the illustrated embodiment, power usage is reduced by reducing the amount of data movement along pipeline 200, reducing computation (because less data is involved after each culling), and reducing storage (e.g., storage in buffers between each pipeline stage). As for data, each time a particular primitive is culled, its vertices and associated attributes may no longer be needed and may be discarded. In addition to the computational savings along each culling stage, savings also exist in not performing attribute setup calculations and interpolations for culled attributes. It should be understood that the above are merely a few illustrative examples and the disclosed subject matter is not limited thereto.

[0056] Figure 3 is a schematic block diagram of an information processing system 300 that may include a semiconductor device formed according to the principles of the disclosed subject matter.

[0057] refer to Figure 3 , information processing system 300 may include one or more devices constructed according to the principles of the disclosed subject matter. In another embodiment, information processing system 300 may employ or perform one or more techniques according to the principles of the disclosed subject matter.

[0058] In various embodiments, information handling system 300 may include a computing device, such as, for example, a laptop, desktop, workstation, server, blade server, personal digital assistant, smart phone, tablet computer, and other appropriate computers or virtual machines or virtual computing devices thereof. In various embodiments, information handling system 300 may be used by a user (not shown).

[0059] The information processing system 300 according to the disclosed subject matter may also include a central processing unit (CPU), logic, or processor 310. In some embodiments, the processor 310 may include one or more functional unit blocks (FUB) or combinatorial logic blocks (CLB) 315. In such embodiments, the combinatorial logic block may include various Boolean logic operations (e.g., "NAND", "NOR", "NOR", "XOR"), stable logic devices (e.g., flip-flops, latches), other logic devices, or combinations thereof. These combinatorial logic operation devices may be configured in a simple or complex manner to process input signals to obtain desired results. It should be understood that although several illustrative examples of synchronous combinatorial logic operation devices are described, the disclosed subject matter is not limited thereto and may include asynchronous operation devices or a mixture thereof. In one embodiment, the combinatorial logic operation device may include a plurality of complementary metal oxide semiconductors (CMOS) transistors. In various embodiments, these CMOS transistors may be arranged as gates to perform logic operations; however, it should be understood that other technologies may be used and are also within the scope of the disclosed subject matter.

[0060] The information processing system 300 according to the disclosed subject matter may also include volatile memory 320 (e.g., random access memory (RAM)). The information processing system 300 according to the disclosed subject matter may also include non-volatile memory 330 (e.g., a hard disk drive, optical storage, NAND gates, or flash memory). In some embodiments, the volatile memory 320, the non-volatile memory 330, or a combination or portion thereof may be referred to as a "storage medium". In various embodiments, the volatile memory 320 and / or the non-volatile memory 330 may be configured to store data in a semi-permanent or substantially permanent form.

[0061] In various embodiments, the information processing system 300 may include one or more network interfaces 340 configured to allow the information processing system 300 to become part of a communication network and communicate via the communication network. Examples of Wi-Fi protocols may include, but are not limited to, Institute of Electrical and Electronics Engineers (IEEE) 802.11g, IEEE 802.11n. Examples of cellular protocols may include, but are not limited to: IEEE 802.16m (also known as wireless metropolitan area network (MAN) advanced, long term evolution (LTE) advanced, enhanced data rates for GSM Evolution (EDGE), evolved high-speed packet access (HSPA+). Examples of wired protocols may include, but are not limited to, IEEE 802.3 (also known as Ethernet), fiber channel, power line communication (e.g., home plug, IEEE 1901). It should be understood that the above are just a few illustrative examples, and the disclosed subject matter is not limited thereto.

[0062] The information processing system 300 according to the disclosed subject matter may also include a user interface unit 350 (e.g., a display adapter, a tactile interface, a human-machine interface device). In various embodiments, the user interface unit 350 may be configured to receive input from a user and / or provide output to a user. Other types of devices may also be used to provide interaction with a user; for example, the feedback provided to the user may be any form of sensory feedback, such as visual feedback, auditory feedback, or tactile feedback; and input from the user may be received in any form, including sound, voice, or tactile input.

[0063] In various embodiments, information handling system 300 may include one or more other devices or hardware components 360 (e.g., display or monitor, keyboard, mouse, camera, fingerprint reader, video processor). It should be understood that the above are just a few illustrative examples and the disclosed subject matter is not limited thereto.

[0064] The information processing system 300 according to the disclosed subject matter may also include one or more system buses 305. In such an embodiment, the system bus 305 may be configured to communicatively couple the processor 310, the volatile memory 320, the nonvolatile memory 330, the network interface 340, the user interface unit 350, and one or more hardware components 360. Data processed by the processor 310 or data input from outside the nonvolatile memory 330 may be stored in the nonvolatile memory 330 or the volatile memory 320.

[0065] In various embodiments, the information processing system 300 may include or execute one or more software components 370. In some embodiments, the software component 370 may include an operating system (OS) and / or an application. In some embodiments, the OS may be configured to provide one or more services to the application and manage or act as an intermediary between the application and various hardware components (e.g., processor 310, network interface 340) of the information processing system 300. In such an embodiment, the information processing system 300 may include one or more local applications, which may be installed locally (e.g., in non-volatile memory 330) and configured to be directly executed by the processor 310 and directly interact with the OS. In such an embodiment, the local application may include precompiled machine executable code. In some embodiments, the local application may include a script interpreter (e.g., C shell (C shell, csh), AppleScript, AutoHotkey) or a virtual execution machine (virtual executionmachine, VM) (e.g., Java virtual machine, Microsoft common language runtime) configured to translate source code or object code into executable code that is then executed by the processor 310.

[0066] Various packaging techniques may be used to package the above-mentioned semiconductor devices. For example, a semiconductor device constructed according to the principles of the disclosed subject matter may use at least one of the following: package on package (POP) technology, ball grid array (BGA) technology, chip scale package (CSP) technology, plastic leaded chip carrier (PLCC) technology, plastic dual in-line package (PDIP) technology, bare die in waffle pack, bare die in wafer form, chip on board (COB) technology, ceramic dual in-line package (CERDIP) technology, plastic metric quad flat package (PMQFP) technology, plastic quad flat package (PQFP) technology, small outline package (SOIC) technology, shrink small outline package (SSOP) technology, thin small outline package (TSOP) technology, thin quad flat package (TSOP) technology. The present invention may be a process for manufacturing a multi-chip package (MCP) or a wafer-level fabricated package (WFP) or a wafer-level processed stack package (WSP) or other technologies known to those skilled in the art.

[0067] The method steps may be performed by one or more programmable processors executing a computer program to perform functions by operating on input data and generating outputs. The method steps may also be performed by a dedicated logic circuit (e.g., a field programmable gate array (FPGA) or an application-specific integrated circuit (ASIC)), and the apparatus may be implemented as a dedicated logic circuit.

[0068] In various embodiments, the computer-readable medium may include instructions that, when executed, cause a device to perform at least a portion of the method steps. In some embodiments, the computer-readable medium may be included in magnetic media, optical media, other media, or a combination thereof (e.g., a CD-ROM, a hard drive, a read-only memory, a flash drive). In such embodiments, the computer-readable medium may be a tangible and non-transitory implemented article of manufacture.

[0069] Although the principles of the disclosed subject matter have been described with reference to example embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of these disclosed concepts. Therefore, it should be understood that the above-described embodiments are not restrictive, but merely illustrative. Therefore, the scope of the disclosed concepts will be determined by the broadest permissible interpretation of the appended claims and their equivalents, and should not be limited by the foregoing description. Therefore, it should be understood that the appended claims are intended to cover all such modifications and changes that fall within the scope of the embodiments.

Claims

1. A device for data processing, comprising: A graphics processing engine comprising a pipeline having a plurality of sequential circuit stages, the pipeline comprising: a front-end output logic circuit, the front-end output logic circuit being configured to receive attribute data of the graphics data, the attribute data comprising position data and non-position data, the front-end output logic circuit being further configured to output the position data to a position data path of the pipeline, and to output the non-position data to a non-position data path of the pipeline, Wherein, the position data path of the pipeline is configured as: performing multi-level culling of the position data, and Based on feeding back the culling information to the front-end output logic circuit to remove the non-position data, the non-position data corresponding to the culled position data is removed from the non-position data path of the pipeline.

2. The device according to claim 1, wherein: The front-end output logic circuit is configured as: Non-position data corresponding to the discarded position data is discarded to prevent the non-position data corresponding to the discarded position data from being received by the subsequent pipeline circuit stage.

3. The device according to claim 1, wherein: The pipeline includes a cull circuit configured to: Eliminating primitive data based at least in part on primitive characteristics; and Preventing non-positional data corresponding to the culled primitive data from being processed by subsequent pipeline circuit stages.

4. The device according to claim 1, wherein: The pipeline includes a rasterization circuit configured to: culling metadata based at least in part on the visibility determination; and Preventing non-positional data corresponding to the culled primitive data from being processed by subsequent pipeline circuit stages.

5. The device according to claim 1, wherein: The pipeline includes a culling circuit and a rasterization circuit, wherein the front-end output logic circuit, the culling circuit, and the rasterization circuit are placed in series and each performs a culling operation to reduce the amount of data passed to subsequent pipeline stages, wherein at least the front-end output logic circuit, the culling circuit, and the rasterization circuit form a multi-stage culling portion of the pipeline.

6. The device according to claim 1, wherein: The pipeline includes an attribute setting circuit and a culling circuit; and wherein the non-position data is routed from the front-end output logic circuit to the attribute setting circuit, and Wherein, the position data is routed from the front-end output logic circuit to the reject circuit.

7. The device according to claim 6, wherein: The attribute setting circuit is configured to delay setting of primitive attribute interpolation until after primitive data has been culled.

8. The device according to claim 1, wherein: The pipeline is configured to perform multi-stage culling of data by culling attribute data prior to culling primitive data.

9. The device according to claim 1, wherein: The pipeline includes a cull circuit and at least one subsequent processing circuit stage architecturally subsequent to the cull circuit; Wherein, the front-end output logic circuit is configured as: receiving an indication from the culling circuit as to which data to cull, Read the surviving data from the front-end output buffer, and The surviving data or a portion thereof is passed to the at least one subsequent processing circuit stage for processing as needed.

10. A system for data processing, comprising: a processor core, configured to process instructions; and a graphics core configured to render graphics data, wherein the graphics core comprises a graphics processing pipeline, the graphics processing pipeline comprising a plurality of circuit stages, the plurality of circuit stages being sequentially arranged to at least partially process the graphics data as the graphics data flows through the graphics processing pipeline, the graphics data comprising positional data and non-positional data, in, The circuit level comprises: a front-end output logic circuit configured to receive the graphics data and provide non-culled graphics data to one or more subsequent circuit stages and remove culled graphics data from the graphics processing pipeline; and The multi-stage elimination part of the circuit-level position information part is after the front-end output logic circuit and is configured to feed back to the front-end output logic circuit which non-position data is to be eliminated from the graphic data received by the front-end output logic circuit.

11. The system according to claim 10, wherein: The front-end output logic circuit is configured as: determining unrequired position data that is not required by subsequent pipeline circuit stages; and The graphic data corresponding to the unnecessary position data is discarded to prevent the graphic data corresponding to the unnecessary position data from being processed by the subsequent pipeline circuit stage.

12. The system according to claim 10, wherein: The pipeline includes a cull circuit configured to: culling primitive data based at least in part on primitive characteristics; and Graphics data corresponding to the culled metadata is prevented from being processed by subsequent pipeline circuit stages.

13. The system according to claim 10, wherein: The pipeline includes a rasterization circuit configured to: culling metadata based at least in part on the visibility determination; and Graphics data corresponding to the culled metadata is prevented from being processed by subsequent pipeline circuit stages.

14. The system according to claim 10, wherein: The multi-stage culling section includes a culling circuit and a rasterizing circuit, and The front-end output logic circuit, the culling circuit and the rasterization circuit are placed in series, and each circuit performs a culling operation to reduce the amount of data passed to the next pipeline stage.

15. The system according to claim 10, wherein: The pipeline includes an attribute setting circuit and a culling circuit; and wherein non-position information is routed from the front-end output logic circuit to the attribute setting circuit, and Wherein, position information is routed from the front-end output logic circuit to the reject circuit.

16. The system of claim 15, wherein: The attribute setting circuit is configured to delay setting of primitive attribute interpolation until after primitive data has been culled.

17. The system according to claim 10, wherein: The pipeline is configured to perform multi-stage culling of data by culling attribute data prior to culling primitive data.

18. The system of claim 10, wherein: The pipeline includes a cull circuit and at least one subsequent processing circuit stage architecturally subsequent to the cull circuit; Wherein, the front-end output logic circuit is configured as: receiving an indication from the culling circuit as to which graphics data to cull, reading un-culled graphics data from the front-end output buffer, and The unculled graphics data or a portion thereof is passed to the at least one subsequent processing circuit stage for processing as needed.

19. A method for data processing, comprising: receiving graphics data from one or more front-end output buffers at a front-end output logic circuit of a graphics pipeline, the graphics data including positional data and non-positional data; At a culling circuit after a front-end output logic circuit in the graphics pipeline, determining which graphics data can be removed based on the position data; removing the position data determined to be removed by the rejection circuit; as well as Information is fed back from the culling circuit to the front end output logic circuit to remove non-position data corresponding to the position data determined to be removed.

20. The method according to claim 19, wherein: The determination includes: determining, by the front-end output logic circuit, unneeded attribute data that is not needed by a subsequent pipeline circuit stage based on the information received from the culling circuit; culling primitive data based at least in part on primitive features by the culling circuit; as well as The metadata is culled by the rasterization circuitry based at least in part on the visibility determination.

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