Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, wherein the method comprises: providing a substrate, wherein the substrate comprises a first region and a second region adjacent to each other, and the first region and the second region are arranged along a first direction; forming a plurality of mutually discrete pseudo gate structures on the surface of the substrate, and the plurality of pseudo gate structures are arranged in parallel along a second direction, and the second direction is perpendicular to the first direction; forming a protective layer on the side wall surface of the pseudo gate structure on the second region; forming a second sidewall on the side wall surface of the protective layer on the second region, and forming a first sidewall on the side wall surface of the pseudo gate structure on the first region. The semiconductor structure formed by the method has good performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] With the rapid development of integrated circuit manufacturing technology, the size of semiconductor devices in integrated circuits has been continuously reduced, which effectively improves the operating speed of the entire integrated circuit. However, when the size of the components is further reduced, it will bring corresponding challenges to the existing process.

[0003] Currently, device performance can be improved by forming a semiconductor structure with a gate structure having two critical dimensions.

[0004] However, the performance of the semiconductor structure having the gate structure of the two critical dimensions formed by the prior art is still poor. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the formed semiconductor structure.

[0006] In order to solve the above technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first region and a second region adjacent to each other, and the first region and the second region are arranged along a first direction; forming a plurality of mutually discrete pseudo gate structures on the surface of the substrate, and the plurality of the pseudo gate structures are arranged in parallel along a second direction, and the second direction is perpendicular to the first direction; forming a protective layer on the side wall surface of the pseudo gate structure in the second region; forming a second side wall on the side wall surface of the protective layer in the second region, and forming a first side wall on the side wall surface of the pseudo gate structure in the first region.

[0007] Optionally, along the second direction, a size range of the dummy gate structure is 5 nanometers to 30 nanometers.

[0008] Optionally, along the second direction, a size range of the protective layer is 1 nanometer to 10 nanometers.

[0009] Optionally, the material of the protective layer includes silicon oxide, silicon nitride, or silicon oxynitride.

[0010] Optionally, the method for forming the protective layer includes: forming a mask layer on the first region, and the mask layer exposes the surface of the second region and the side wall surface and top surface of the pseudo gate structure located on the surface of the second region; using the mask layer as a mask, and adopting an atomic layer deposition process to form a protective material film on the surface of the second region and the side wall surface and top surface of the pseudo gate structure located on the surface of the second region; etching back the protective material film until the top surface of the pseudo gate structure and the substrate surface are exposed to form the protective layer; after the protective layer is formed, removing the mask layer.

[0011] Optionally, the temperature range of the quasi-atomic layer deposition process is 0 degrees Celsius to 100 degrees Celsius.

[0012] Optionally, materials of the first spacer and the second spacer include silicon oxide, silicon nitride, silicon carbide nitride, silicon boron nitride, silicon carbon nitride oxide or silicon nitride oxide.

[0013] Optionally, the method for forming the first and second side walls includes: forming a side wall material film on the substrate surface, the top and side wall surfaces of the protective layer, and the surface exposed by the pseudo gate structure; etching back the side wall material film until the top surface of the pseudo gate structure, the top surface of the protective layer, and the substrate surface are exposed, forming the second side wall on the side wall surface of the protective layer in the second area, and forming the first side wall on the side wall surface of the pseudo gate structure in the first area.

[0014] Optionally, the dummy gate structure includes: a dummy gate dielectric layer located on a portion of the substrate surface and a dummy gate electrode layer located on the surface of the dummy gate dielectric layer; the material of the dummy gate dielectric layer includes: silicon oxide; the material of the dummy gate electrode layer includes: polysilicon.

[0015] Optionally, after forming the first side wall and the second side wall, it also includes: forming a dielectric layer on the substrate; removing the pseudo gate structure on the second area and the protective layer located on the side wall surface of the pseudo gate structure, forming a second opening in the dielectric layer on the second area, removing the pseudo gate structure on the first area, and forming a first opening in the dielectric layer on the first area; forming a first gate structure in the first opening, and forming a second gate structure in the second opening.

[0016] Optionally, the first region is used to form an NMOS transistor, and the second region is used to form a PMOS transistor.

[0017] Optionally, the method further includes: after forming the protective layer and before forming the first sidewall spacer and the second sidewall spacer, performing a cleaning process on the surface of the substrate, the surface of the protective layer, and the surface of the dummy gate structure.

[0018] Optionally, the cleaning process includes: a wet etching process; parameters of the wet etching process include: an etching solution used includes one or both of sulfuric acid or hydrogen peroxide.

[0019] Optionally, it also includes: after forming the first side wall and the second side wall, before forming the first gate structure and the second gate structure, forming a first source and drain doped region in the substrate on both sides of the protective layer, and forming a second source and drain doped region in the substrate on both sides of the dummy gate structure.

[0020] Optionally, the substrate includes: a base and a first fin and a second fin located on a surface of the base, the first fin is located in a first region, the second fin is located in a second region, and the dummy gate structure spans the first fin and the second fin.

[0021] Correspondingly, an embodiment of the present invention also provides a semiconductor structure formed by any of the methods described above, comprising: a substrate, the substrate comprising an adjacent first region and a second region, and the first region and the second region are arranged along a first direction; a plurality of mutually discrete pseudo gate structures located on the surface of the substrate, and the plurality of pseudo gate structures are arranged in parallel along a second direction, and the second direction is perpendicular to the first direction; a protective layer located on the side wall surface of the pseudo gate structure on the second region; a second side wall located on the side wall surface of the protective layer on the second region, and a first side wall located on the side wall surface of the pseudo gate structure on the first region.

[0022] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0023] In the method for forming a semiconductor structure provided by the technical solution of the present invention, a protective layer is formed on the side wall surface of the dummy gate structure on the second region, so that along the second direction, the common size of the dummy gate structure and the protective layer on the second region is larger than the size of the dummy gate structure on the first region. Since the dummy gate structure and the protective layer on the second region jointly determine the size of the second gate structure to be formed subsequently, and the dummy gate structure on the first region determines the size of the first gate structure to be formed subsequently, the size of the second gate structure is larger than the size of the first gate structure, thereby meeting the process requirements. At the same time, the uniformity of the protective layer is good, so that the surface of the protective layer is smooth and the morphology is good, thereby making the performance of the semiconductor structure with the first gate structure and the second gate structure of two sizes formed subsequently better.

[0024] Furthermore, the quasi-atomic layer deposition process, on the one hand, can make the thickness of the formed protective material film uniform, which is beneficial to the subsequently formed side wall surface uniformity and good morphology, thereby making the formed semiconductor performance better; on the other hand, because the quasi-atomic layer deposition process can deposit materials at a relatively low temperature, in the case of a mask layer on the first region, a protective material film can be formed on the surface of the second region and on the top surface and side wall surface of the pseudo gate structure located on the surface of the second region, thereby meeting the process requirements.

[0025] Furthermore, after forming the protective layer and before forming the first side wall and the second side wall, a cleaning process is performed on the substrate surface, the protective layer surface, and the pseudo gate structure surface to remove impurities attached to the substrate surface, the protective layer surface, and the pseudo gate structure surface, which is beneficial to improving the performance of the formed semiconductor structure.

[0026] Furthermore, the cleaning process is a wet etching process, and the etching solution used includes: sulfuric acid or hydrogen peroxide, which can avoid the etching solution from causing etching loss to the material of the protective layer, thereby ensuring that the size of the protective layer is not affected, which is beneficial to the subsequent formation of the second gate structure in the second opening. The size is larger and can meet the process requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figures 1 to 3 It is a structural schematic diagram of each step of a method for forming a semiconductor structure;

[0028] Figures 4 to 19 It is a cross-sectional schematic diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention. DETAILED DESCRIPTION

[0029] As described in the background art, the performance of the semiconductor structure formed by the existing method is poor.

[0030] The following is a detailed description of the reasons for the poor performance of the semiconductor structure with reference to the accompanying drawings. Figures 1 to 3 The present invention is a structural schematic diagram of each step of a semiconductor structure forming method.

[0031] Please refer to Figure 1 , providing a substrate 100, the substrate 100 comprising a first region A and a second region B adjacent to each other, the first region A and the second region B being arranged along a first direction X, the surface of the substrate 200 having a plurality of mutually discrete dummy gate structures 110, and the plurality of dummy gate structures 110 being arranged in parallel along a second direction, the second direction Y being perpendicular to the first direction X;

[0032] Please refer to Figure 2A mask layer 120 is formed on the surface of the second region B, and the mask layer 120 exposes the first region A and the top and sidewall surfaces of the dummy gate structure 110 located on the surface of the first region A.

[0033] Please refer to Figure 3 , using the mask layer 120 as a mask, etching the exposed dummy gate structure 110 located on the surface of the first area A, forming a first dummy gate structure 111 on the surface of the first area A, and forming a second dummy gate structure 112 on the surface of the second area B, and along the second direction Y, the size of the first dummy gate structure 111 is smaller than the size of the second dummy gate structure 112; after forming the first dummy gate structure 111 and the second dummy gate structure 112, removing the mask layer 120.

[0034] The first region A is used to form a PMOS transistor, and the second region B is used to form an NMOS transistor. Since the carrier types in the PMOS transistor and the NMOS transistor are different, that is, the carrier migration efficiency in the channel of the PMOS transistor is different from the carrier migration efficiency in the channel of the NMOS transistor. Therefore, in order to ensure that the performance difference between the PMOS transistor and the NMO transistor is small, the channel length of the PMOS transistor and the channel length of the NMOS transistor need to be different, so as to make up for the difference in carrier mobility. Since the length of the gate structure determines the size of the channel located below the gate structure, and the size of the pseudo-gate structure determines the size of the gate structure, in order to meet the process requirements, the size of the pseudo-gate structure used to form the PMOS transistor is larger than the size of the pseudo-gate structure used to form the NMOS transistor.

[0035] In the above method, the dummy gate structure 110 exposed on the surface of the first region A is etched by masking with the mask layer 120, so that the size of the first dummy gate structure 111 formed on the surface of the first region A is smaller than the size of the second dummy gate structure 112 on the surface of the second region B.

[0036] However, when a portion of the dummy gate structure 110 is removed, due to the low accuracy of the existing etching process, the side wall surface of the formed first dummy gate structure 111 is uneven, resulting in a rough side wall surface of the formed first dummy gate structure 111, that is, the size uniformity of the first dummy gate structure 111 along the second direction Y is poor, thereby resulting in poor performance of the formed semiconductor structure.

[0037] To solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor device, comprising: providing a substrate, the substrate comprising a first region and a second region adjacent to each other, and the first region and the second region are arranged along a first direction; forming a plurality of mutually discrete pseudo gate structures on the surface of the substrate, and the plurality of pseudo gate structures are arranged in parallel along a second direction, and the second direction is perpendicular to the first direction; forming a protective layer on the side wall surface of the pseudo gate structure in the second region; forming a first side wall on the side wall surface of the protective layer in the second region, and forming a second side wall on the side wall surface of the pseudo gate structure in the first region.

[0038] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0039] Figures 4 to 19 It is a cross-sectional schematic diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention.

[0040] Please refer to Figure 4 , providing a substrate 200, wherein the substrate 200 includes adjacent first regions I and second regions II, and the first regions I and second regions II are arranged along a first direction X.

[0041] In this embodiment, the substrate 200 includes a base 201 and a first fin 202 and a second fin 203 located on a surface of the base 201 . The first fin 202 is located in a first region I, and the second fin 203 is located in a second region II.

[0042] In other embodiments, when the semiconductor structure is a planar MOS transistor, the substrate is a planar semiconductor substrate.

[0043] The method for forming the substrate 200 includes: providing an initial substrate (not shown in the figure), forming a first patterned layer (not shown in the figure) on the initial substrate; etching the initial substrate using the first patterned layer as a mask to form the substrate 201 and the first fin 202 and the second fin 203 located on the surface of the substrate 201.

[0044] In this embodiment, the material of the initial substrate is silicon. Accordingly, the material of the substrate 201 , the first fin 202 , and the second fin 203 are silicon.

[0045] In other embodiments, the material of the initial substrate includes germanium, silicon germanium, silicon on insulator or germanium on insulator. Correspondingly, the material of the substrate includes germanium, silicon germanium, silicon on insulator or germanium on insulator, and the material of the first fin and the second fin includes germanium, silicon germanium, silicon on insulator or germanium on insulator.

[0046] The surface of the substrate 200 also has an isolation structure (not shown in the figure) covering the first fin 202 and the second fin 203 , and the top surface of the isolation structure is lower than the top surfaces of the first fin 202 and the second fin 203 .

[0047] The isolation structure is used to achieve electrical insulation between different devices.

[0048] In this embodiment, one first fin 202 and one second fin 203 are used as an example for description. In other embodiments, the number of the first fins may be greater than 1, and the number of the second fins may be greater than 1.

[0049] In this embodiment, the first region I is used to form an NMOS transistor, and the second region II is used to form a PMOS transistor.

[0050] In other embodiments, both the first region and the second region are used to form a PMOS transistor; or, both the first region and the second region are used to form an NMOS transistor.

[0051] Please refer to Figures 5 to 7 , Figure 5 For Figure 4 Based on the schematic diagram, Figure 6 for Figure 5 Schematic diagram of the cross section along the M1-N1 tangent line. Figure 7 for Figure 5 Schematic diagram along the tangent line of MN, Figure 5 for Figure 6 and Figure 7 In the top view, a plurality of separate dummy gate structures 210 are formed on the surface of the substrate 200, and the plurality of dummy gate structures 210 are arranged in parallel along a second direction Y, and the second direction Y is perpendicular to the first direction X.

[0052] In this embodiment, the dummy gate structure 210 spans across the first fin 202 and the second fin 203 .

[0053] The dummy gate structure 210 is also located on the surface of a portion of the isolation structure.

[0054] The method for forming the pseudo gate structure 210 includes: forming a pseudo gate dielectric material film (not shown in the figure) on the surface of the substrate 200; forming a pseudo gate electrode material film (not shown in the figure) on the surface of the pseudo gate dielectric material film; forming a second patterned layer (not shown in the figure) on the surface of the pseudo gate electrode material film, wherein the second patterned layer exposes a portion of the surface of the pseudo gate electrode material film; using the second patterned layer as a mask, etching the pseudo gate dielectric material film and the pseudo gate electrode material film located on the surface of the pseudo gate dielectric material film until the surface of the substrate 200 is exposed to form the pseudo gate structure 210.

[0055] The dummy gate structure 210 includes: a dummy gate dielectric layer (not shown in the figure) located on the surface of a portion of the substrate 200 and a dummy gate electrode layer (not shown in the figure) located on the surface of the dummy gate dielectric layer.

[0056] The material of the dummy gate dielectric layer includes silicon oxide; the material of the dummy gate electrode layer includes polysilicon.

[0057] In this embodiment, the dummy gate dielectric layer is located on a portion of the top and sidewall surfaces of the first fin 202 , the top and sidewall surfaces of the second fin 203 , and the surface of the isolation structure.

[0058] The size of the dummy gate structure 210 is in the range of 5 nanometers to 30 nanometers along the second direction Y. In this embodiment, the size of the dummy gate structure 210 is 18 nanometers.

[0059] The size of the dummy gate structure 210 determines the size of the first gate structure subsequently formed on the first region I.

[0060] In this embodiment, the top surface of the dummy gate structure 210 further has a first hard mask layer (not marked in the figure) and a second hard mask layer (not marked in the figure) located on the surface of the first hard mask layer.

[0061] The first hard mask layer and the second hard mask layer are both used to protect the dummy gate structure 210 to prevent the surface of the dummy gate structure from being damaged by etching.

[0062] Next, a protective layer is formed on the sidewall surface of the pseudo gate structure on the second region. For details on the process of forming the protective layer, please refer to Figures 8 to 16 .

[0063] Please refer to Figures 8 to 10 , Figure 8 For Figure 5 Based on the schematic diagram, Fig. 9 For Figure 6 Based on the schematic diagram, Fig.10 For Figure 7 Based on the schematic diagram, a mask layer 220 is formed on the first region I, and the mask layer 220 exposes the surface of the second region II and the sidewall surface and the top surface of the dummy gate structure 210 located on the surface of the second region II.

[0064] The mask layer 220 is used as a mask for subsequently forming a protection layer on the sidewall surface of the dummy gate structure 210 on the second region II.

[0065] In this embodiment, the material of the mask layer 220 is photoresist.

[0066] The method for forming the mask layer 220 includes: forming a mask material layer (not shown in the figure) on the substrate 200; exposing and developing the mask material layer to form a mask layer 220, and the mask layer 220 exposes the surface of the second region II and the side wall surface and top surface of the pseudo gate structure 210 located on the surface of the second region II.

[0067] In other embodiments, the material of the mask layer may also be an organic material with relatively high fluidity, such as SOC (spin-on-carbon).

[0068] Please refer to Figures 11 to 13 , Fig.11 For Figure 8 Based on the schematic diagram, Fig.12 For Fig. 9 Based on the schematic diagram, Fig.13 For Fig.10 Based on the schematic diagram, the mask layer 220 is used as a mask and an atomic layer deposition process is adopted to form a protective material film (shown in the figure) on the surface of the second region II and the side wall surface and top surface of the pseudo gate structure 210 located on the surface of the second region II; the protective material film is etched back until the top surface of the pseudo gate structure 210 and the surface of the substrate 200 are exposed to form the protective layer 230.

[0069] The protective material film is used to form the protective layer 230 .

[0070] The material of the protective material film includes silicon oxide, silicon nitride, or silicon oxynitride. Accordingly, the material of the formed protective layer 230 includes silicon oxide, silicon nitride, or silicon oxynitride.

[0071] In this embodiment, the material of the protective material film is silicon oxide, and therefore, the material of the protective layer 230 is silicon oxide.

[0072] The temperature range of the quasi-atomic layer deposition process is 0 degrees Celsius to 100 degrees Celsius.

[0073] Usually, the material of the mask layer 220 is an organic material with high fluidity, which is easy to fill in a small space and easy to form a flat surface. However, organic materials have poor high temperature resistance and are easy to volatilize under high temperature conditions, resulting in pollution to the equipment and affecting the accuracy of related processes. Since the temperature range of the atomic layer deposition process is 0 degrees Celsius to 100 degrees Celsius, the process temperature is relatively low, which can avoid the high temperature effect on the mask layer 220, and ensure that the mask layer 220 formed on the first area I is relatively stable. The protective material film is formed on the side wall surface and top surface of the second area II surface and the pseudo gate structure 210 located on the second area II surface, which is beneficial to improve the performance of the formed semiconductor structure.

[0074] On the one hand, the quasi-atomic layer deposition process can make the thickness of the formed protective material film uniform, which is beneficial to the subsequently formed protective layer 230 having better uniformity and morphology of the side wall surface, thereby making the formed semiconductor have better performance; on the other hand, since the quasi-atomic layer deposition process can deposit materials at a relatively low temperature, when there is a mask layer 220 on the first region I, a protective material film can be formed on the surface of the second region II and on the top surface and side wall surface of the pseudo gate structure located on the surface of the second region II, thereby meeting the process requirements.

[0075] The size of the protective layer 230 is in the range of 1 nanometer to 10 nanometers along the second direction Y. In this embodiment, the size of the protective layer 230 is 4 nanometers.

[0076] The significance of selecting the size range is that: if the size is less than 1 nanometer, the protective layer 230 is too thin, so that the effect of the size of the subsequently formed second gate structure being larger than the size of the first gate structure is not obvious, and thus the effect of improving the performance of the semiconductor structure is not obvious; if the size is greater than 10 nanometers, since the sizes of the protective layer 230 and the dummy gate structure 210 jointly determine the size of the subsequently formed second gate structure, the thickness of the protective layer 230 is too thick. On the one hand, the size of the formed second gate structure is too large, which is not conducive to improving the integration of the semiconductor structure. On the other hand, it leads to a large difference between the first gate structure and the second gate structure, which easily increases the difficulty of subsequently forming conductive plugs on the surfaces of the first gate structure and the second gate structure, and has poor compatibility with subsequent processes, which is not conducive to improving the performance of the semiconductor structure.

[0077] By forming a protective layer 230 on the sidewall surface of the dummy gate structure 210 in the second region II, the common size of the dummy gate structure 210 and the protective layer 230 in the second region II is larger than the size of the dummy gate structure 210 in the first region I along the second direction Y. Since the dummy gate structure 210 and the protective layer 230 in the second region II jointly determine the size of the first gate structure to be formed subsequently, the dummy gate structure in the first region I determines the size of the second gate structure to be formed subsequently, so that the size of the first gate structure is larger than the size of the second gate structure, thereby meeting the process requirements. At the same time, the protective layer 230 has good uniformity, so that the surface of the protective layer 230 is smooth and the morphology is good, thereby making the performance of the semiconductor structure with the first dummy gate structure and the second dummy gate structure of two sizes formed subsequently better.

[0078] The process of etching back the protective material film includes: one of a dry etching process and a wet etching process or a combination of the two.

[0079] In this embodiment, the process of etching back the protective material film is anisotropic dry etching.

[0080] Please refer to Figures 14 to 16 , Fig.14 For Fig.11 Based on the schematic diagram, Fig.15 For Fig.12 Based on the schematic diagram, Fig.16 For Fig.13 Based on the schematic diagram, after the protection layer 230 is formed, the mask layer 220 is removed.

[0081] The process of removing the mask layer 220 includes: a dry etching process, a wet etching process or an ashing process.

[0082] In this embodiment, the material of the mask layer 220 is photoresist, and the mask layer 220 is removed by an ashing process, which is simple and easy to operate.

[0083] In this embodiment, after the protection layer 230 is formed, the process further includes: performing a cleaning process on the surface of the substrate 200 , the surface of the protection layer 230 , and the surface of the dummy gate structure 210 .

[0084] The surface of the substrate 200, the surface of the protective layer 230, and the surface of the dummy gate structure 210 are cleaned to remove impurities attached to the surface of the substrate 200, the surface of the protective layer 230, and the surface of the dummy gate structure 210, which is beneficial to improving the performance of the formed semiconductor structure.

[0085] The cleaning process includes: a wet etching process.

[0086] In this embodiment, the parameters of the wet etching process include: the etching solution used includes: sulfuric acid or hydrogen peroxide.

[0087] Since the material of the protective layer 230 is silicon oxide, when the etching solution used includes one or both of sulfuric acid and hydrogen peroxide, the etching solution can etch and remove impurities without reacting with the protective layer 230, thereby avoiding the etching loss of the material of the protective layer 230 by the etching solution used, thereby ensuring that the size of the protective layer 230 is not affected, which is beneficial for the size of the second gate structure subsequently formed in the second opening to be larger and meet the process requirements.

[0088] In other embodiments, after forming the protection layer, the cleaning process is not performed.

[0089] Next, a second sidewall is formed on the sidewall surface of the protective layer in the second region, and a first sidewall is formed on the sidewall surface of the dummy gate structure in the first region. For details on the process of forming the first sidewall and the second sidewall, please refer to Figures 17 to 19 .

[0090] Please refer to Figures 17 to 19 , Fig.17 For Fig.14 Based on the schematic diagram, Fig.18 For Fig.15 Based on the schematic diagram, Fig.19 For Fig.16 Based on the schematic diagram, a sidewall material film (not shown in the figure) is formed on the surface of the substrate 200, the top and sidewall surfaces of the protective layer 230, and the exposed surface of the pseudo gate structure 210; the sidewall material film is etched back until the top surface of the pseudo gate structure 210, the top surface of the protective layer 230 and the surface of the substrate 200 are exposed, and the second sidewall 242 is formed on the sidewall surface of the protective layer 230 in the second area II, and the first sidewall 241 is formed on the sidewall surface of the pseudo gate structure 210 in the first area I.

[0091] The spacer material film is used to form the first spacer 241 and the second spacer 242 .

[0092] The material of the side wall material film includes: silicon oxide, silicon nitride, silicon carbide nitride, silicon boronitride, silicon carbon nitride or silicon oxynitride. Correspondingly, the materials formed of the first side wall 241 and the second side wall 242 include: silicon oxide, silicon nitride, silicon carbide nitride, silicon boronitride, silicon carbon nitride or silicon oxynitride.

[0093] In this embodiment, the material of the spacer material film is silicon nitride. Therefore, the material of the first spacer 241 and the second spacer 242 is silicon nitride.

[0094] The process of etching back the sidewall material film includes: one of a dry etching process and a wet etching process or a combination of the two.

[0095] In this embodiment, the process of etching back the sidewall material film is anisotropic dry etching.

[0096] The functions of the first side wall 241 and the second side wall 242 are that, on the one hand, the first side wall 241 covers the side wall surface of the first gate structure formed subsequently, and the second side wall 242 covers the side wall surface of the second gate structure formed subsequently, thereby protecting the side wall surfaces of the first gate structure and the second gate structure from being affected by subsequent processes; on the other hand, the first side wall 241 and the second side wall 242 are subsequently used as masks to form a first source-drain doping region and a second source-drain doping region in the substrate 200 on both sides of the pseudo gate structure, thereby avoiding the distance between the first source-drain doping region and the second source-drain doping region being too close, which may lead to leakage, thereby making the formed semiconductor structure have better performance.

[0097] In this embodiment, after forming the first sidewall 241 and the second sidewall 242 , the method further includes: forming a first source-drain doped region in the substrate 200 on both sides of the protective layer 230 , and forming a second source-drain doped region in the substrate on both sides of the dummy gate structure.

[0098] In this embodiment, after forming the first source-drain doped region and the second source-drain doped region, it also includes: forming a dielectric layer on the substrate; removing the dummy gate structure on the second region and the protective layer located on the side wall surface of the dummy gate structure, forming a second opening in the dielectric layer on the second region, removing the dummy gate structure on the second region, and forming a first opening in the dielectric layer on the first region; forming a first gate structure in the first opening, and forming a second gate structure in the second opening.

[0099] Since the dummy gate structure 210 and the protective layer 230 on the second region II jointly determine the size of the second gate structure, the dummy gate structure 210 on the first region I determines the size of the first gate structure, so that the size of the second gate structure is larger than the size of the first gate structure, thereby meeting the process requirements.

[0100] Accordingly, the embodiment of the present invention further provides a semiconductor structure formed by the above method, please continue to refer to Fig.17, comprising: a substrate 200, wherein the substrate 200 comprises a first region I and a second region II adjacent to each other, and the first region I and the second region II are arranged along a first direction X; a plurality of mutually discrete dummy gate structures 210 located on the surface of the substrate 200, and the plurality of dummy gate structures 210 are arranged in parallel along a second direction Y, and the second direction Y is perpendicular to the first direction X; a protective layer 230 located on the side wall surface of the dummy gate structure 210 on the second region II; a second sidewall 242 located on the side wall surface of the protective layer 230 on the second region II, and a first sidewall 241 located on the side wall surface of the dummy gate structure 210 on the first region I.

[0101] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a first region and a second region adjacent to each other, wherein the first region and the second region are arranged along a first direction; Forming a plurality of mutually discrete dummy gate structures on the surface of the substrate, and the plurality of dummy gate structures are arranged in parallel along a second direction, wherein the second direction is perpendicular to the first direction; Forming a protective layer on the sidewall surface of the dummy gate structure on the second region; the protective layer is formed by using an atomic layer deposition-like process; A second spacer is formed on the sidewall surface of the protection layer on the second region, and a first spacer is formed on the sidewall surface of the dummy gate structure on the first region; A dielectric layer is formed on the substrate; the pseudo gate structure on the second area and the protective layer located on the side wall surface of the pseudo gate structure are removed, a second opening is formed in the dielectric layer on the second area, the pseudo gate structure on the first area is removed, and a first opening is formed in the dielectric layer on the first area; a first gate structure is formed in the first opening, and a second gate structure is formed in the second opening.

2. The method for forming a semiconductor structure according to claim 1, wherein: Along the second direction, the size of the dummy gate structure ranges from 5 nanometers to 30 nanometers.

3. The method for forming a semiconductor structure according to claim 1, wherein: Along the second direction, the size of the protective layer ranges from 1 nanometer to 10 nanometers.

4. The method for forming a semiconductor structure according to claim 1, wherein: The material of the protection layer includes silicon oxide, silicon nitride, or silicon oxynitride.

5. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the protective layer comprises: forming a mask layer on the first region, wherein the mask layer exposes the surface of the second region and the side wall surface and the top surface of the pseudo gate structure located on the surface of the second region; using the mask layer as a mask, and adopting an atomic layer deposition process, forming a protective material film on the surface of the second region and the side wall surface and the top surface of the pseudo gate structure located on the surface of the second region; etching back the protective material film until the top surface of the pseudo gate structure and the substrate surface are exposed to form the protective layer; after forming the protective layer, removing the mask layer.

6. The method for forming a semiconductor structure according to claim 5, wherein: The temperature range of the atomic layer deposition process is 0 degrees Celsius to 100 degrees Celsius.

7. The method for forming a semiconductor structure according to claim 1, wherein: The materials of the first spacer and the second spacer include silicon oxide, silicon nitride, silicon carbide nitride, silicon boron nitride, silicon carbon nitride oxide or silicon nitride oxide.

8. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the first side wall and the second side wall comprises: forming a side wall material film on the surface of the substrate, the top and side wall surfaces of the protective layer, and the surface exposed by the pseudo gate structure; etching back the side wall material film until the top surface of the pseudo gate structure, the top surface of the protective layer and the substrate surface are exposed, forming the second side wall on the side wall surface of the protective layer in the second area, and forming the first side wall on the side wall surface of the pseudo gate structure in the first area.

9. The method for forming a semiconductor structure according to claim 1, wherein: The dummy gate structure comprises: a dummy gate dielectric layer located on a portion of the substrate surface and a dummy gate electrode layer located on the surface of the dummy gate dielectric layer; the material of the dummy gate dielectric layer comprises: silicon oxide; the material of the dummy gate electrode layer comprises: polysilicon.

10. The method for forming a semiconductor structure according to claim 1, wherein: The first region is used to form an NMOS transistor, and the second region is used to form a PMOS transistor.

11. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: After forming the protection layer and before forming the first sidewall spacer and the second sidewall spacer, a cleaning process is performed on the surface of the substrate, the surface of the protection layer, and the surface of the dummy gate structure.

12. The method for forming a semiconductor structure according to claim 11, wherein: The cleaning process includes: a wet etching process; the parameters of the wet etching process include: the etching solution used includes one or both of sulfuric acid and hydrogen peroxide.

13. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: After forming the first sidewall and the second sidewall, and before forming the first gate structure and the second gate structure, a first source-drain doped region is formed in the substrate on both sides of the protective layer, and a second source-drain doped region is formed in the substrate on both sides of the dummy gate structure.

14. The method for forming a semiconductor structure according to claim 1, wherein: The substrate comprises: a base and a first fin and a second fin located on a surface of the base, the first fin being located in a first region, the second fin being located in a second region, and the dummy gate structure spanning the first fin and the second fin.

15. A semiconductor structure formed by the method according to any one of claims 1 to 14, characterized in that: include: A substrate, the substrate comprising a first region and a second region adjacent to each other, wherein the first region and the second region are arranged along a first direction; A plurality of gate structures separated from each other are located on the surface of the substrate, and the plurality of gate structures are arranged in parallel along a second direction, and the second direction is perpendicular to the first direction; The gate structure comprises: a first gate structure located on the first region and a second gate structure located on the second region; A second spacer is located on the sidewall surface of the second gate structure on the second region, and a first spacer is located on the sidewall surface of the first gate structure on the first region.

Images