Vertical memory devices

Abstract

A vertical memory device is provided. The vertical memory device includes gate electrodes disposed on a substrate and spaced apart from each other in a vertical direction. A channel extends in a vertical direction and is positioned adjacent to the gate electrodes. A tunnel insulating pattern is disposed on the outer wall of the channel in a portion adjacent to each of the gate electrodes. A charge trapping pattern structure is disposed between the tunnel insulating pattern and each of the gate electrodes. Each of the charge trapping pattern structures includes an upper charge trapping pattern and a lower charge trapping pattern spaced apart from each other in a vertical direction. A blocking pattern structure is located between the charge trapping pattern structure and each of the gate electrodes. A first portion of the channel adjacent to the tunnel insulating pattern has a thickness in the horizontal direction that is smaller than the thickness of the other portions of the channel.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0073588, filed on June 20, 2019, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to a vertical memory device. More specifically, this invention relates to a non-volatile memory device having vertical channels. Background Technology

[0003] The size of each vertically stacked layer of a vertical memory device can be reduced to improve integration. However, there are limitations to reducing the size of each layer of a vertical memory device beyond a certain level. Summary of the Invention

[0004] Exemplary embodiments of the present invention provide a vertical memory device with improved electrical characteristics.

[0005] According to an exemplary embodiment of the present invention, a vertical memory device includes gate electrodes disposed on a substrate and spaced apart from each other in a vertical direction substantially perpendicular to the upper surface of the substrate. A channel extends in the vertical direction and is positioned adjacent to the gate electrodes. A tunnel insulating pattern is disposed on a portion of the outer wall of the channel. The portion of the outer wall of the channel is adjacent to each of the gate electrodes. A charge trapping pattern structure is disposed between the tunnel insulating pattern and each of the gate electrodes. Each of the charge trapping pattern structures includes an upper charge trapping pattern and a lower charge trapping pattern spaced apart from each other in the vertical direction. A blocking pattern structure is disposed between the charge trapping pattern structure and each of the gate electrodes. A first portion of the channel adjacent to the tunnel insulating pattern has a thickness less than the thickness of other portions of the channel in a horizontal direction substantially parallel to the upper surface of the substrate.

[0006] According to an exemplary embodiment of the present invention, a vertical memory device includes gate electrodes disposed on a substrate and spaced apart from each other in a vertical direction substantially perpendicular to the upper surface of the substrate. A channel extends in the vertical direction and is positioned adjacent to the gate electrodes. The channel includes a protrusion that protrudes toward each of the gate electrodes in a horizontal direction substantially parallel to the upper surface of the substrate. A tunneling insulating pattern is disposed on a portion of the outer sidewall of the channel adjacent in the horizontal direction to each of the gate electrodes and the protrusion of the channel. A charge-trapping pattern structure is disposed between the tunneling insulating pattern and each of the gate electrodes. Each of the charge-trapping pattern structures includes an upper charge-trapping pattern and a lower charge-trapping pattern spaced apart from each other in the vertical direction. A blocking pattern structure is disposed between the charge-trapping pattern structure and each of the gate electrodes. The sidewall of each of the gate electrodes adjacent to the channel is recessed in the horizontal direction.

[0007] According to an exemplary embodiment of the present invention, a vertical memory device includes gate electrodes disposed on a substrate and spaced apart from each other in a vertical direction substantially perpendicular to the upper surface of the substrate. Channels extend in the vertical direction and are positioned adjacent to the gate electrodes. The channels include recesses formed on the outer walls of the channels on adjacent portions of each of the gate electrodes. The recesses are spaced apart from each other in the vertical direction. A tunnel insulating pattern fills each of the recesses and protrudes toward each of the gate electrodes in a horizontal direction substantially parallel to the upper surface of the substrate. A charge trapping pattern structure is disposed between the tunnel insulating pattern and each of the gate electrodes. Each of the charge trapping pattern structures includes an upper charge trapping pattern and a lower charge trapping pattern spaced apart from each other in the vertical direction. A blocking pattern structure is disposed between the charge trapping pattern structure and each of the gate electrodes.

[0008] According to an exemplary embodiment of the present invention, a method for manufacturing a vertical memory device includes forming gate electrodes on a substrate. The gate electrodes are spaced apart from each other in a vertical direction substantially perpendicular to the upper surface of the substrate. Channels extending in the vertical direction are formed, and the channels are positioned adjacent to the gate electrodes. A tunnel insulating pattern is formed on a portion of the outer sidewall of the channel. The portion of the outer sidewall of the channel is adjacent to each of the gate electrodes. The tunnel insulating pattern includes a protrusion that protrudes further toward the adjacent gate electrode in a horizontal direction substantially parallel to the upper surface of the substrate compared to any other portion of the tunnel insulating pattern. A charge trapping pattern structure is formed between the tunnel insulating pattern and each of the gate electrodes. Each of the charge trapping pattern structures includes an upper charge trapping pattern and a lower charge trapping pattern spaced apart from each other in the vertical direction through the protrusion of the tunnel insulating pattern. A blocking pattern structure is formed between the charge trapping pattern structure and each of the gate electrodes.

[0009] A vertical memory device according to an exemplary embodiment of the present invention may include a tunnel insulating pattern, a charge trapping pattern structure and a blocking pattern structure formed on the outer wall of a channel extending through a gate electrode and an insulating pattern alternately and repeatedly formed in a vertical direction substantially perpendicular to the upper surface of the substrate, and the charge trapping pattern structure may include an upper charge trapping pattern and a lower charge trapping pattern spaced apart from each other in a vertical direction.

[0010] Therefore, multiple charge-trapping patterns can be arranged in a single transistor, thereby improving the integration density of the vertical memory device including the transistor. Furthermore, electrons can be efficiently injected through multiple charge-trapping patterns, thereby improving the electrical characteristics of the vertical memory device. Attached Figure Description

[0011] Figure 1This is a top plan view illustrating an exemplary embodiment of a vertical memory device according to the present invention.

[0012] Figure 2A It is along the exemplary embodiment of the concept of the present invention. Figure 1 A sectional view taken by line A-A'.

[0013] Figure 2B This is an exemplary embodiment of the concept of the present invention. Figure 2A An enlarged view of region X shown in the image.

[0014] Figures 3 to 9A , Figures 10 to 15 It is along Figure 1 The section cut by line A-A' shows a stage of a method for manufacturing a vertical memory device according to an exemplary embodiment of the present invention.

[0015] Figure 9B This is an exemplary embodiment of the concept of the present invention. Figure 9A An enlarged view of region X' shown in the image.

[0016] Figure 16 It is along Figure 1 The section cut by line A-A' shows a cross-sectional view of an exemplary embodiment of a vertical memory device according to the present invention.

[0017] Figure 17 and Figure 18 It is along Figure 1 The section cut by line A-A' shows a cross-sectional view of an exemplary embodiment of a vertical memory device according to the present invention.

[0018] Figure 19 It is along Figure 1 The section cut by line A-A' shows a cross-sectional view of an exemplary embodiment of a vertical memory device according to the present invention.

[0019] Figures 20 to 22A and Figure 23 It is along Figure 1 The section cut by line A-A' shows a stage of a method for manufacturing a vertical memory device according to an exemplary embodiment of the present invention.

[0020] Figure 22B This is an exemplary embodiment of the concept of the present invention. Figure 22A An enlarged view of region X'' shown in the image. Detailed Implementation

[0021] A vertical memory device and a method of manufacturing the same, according to exemplary embodiments of the present invention, will be described more fully below with reference to the accompanying drawings.

[0022] Figure 1 This is a top plan view showing a vertical memory device according to an exemplary embodiment. Figure 2A It is along the exemplary embodiment of the concept of the present invention. Figure 1 A sectional view taken by line A-A'. Figure 2B This is an exemplary embodiment of the concept of the present invention. Figure 2A An enlarged view of region X shown in the image.

[0023] In the following description, a vertical direction substantially perpendicular to the upper surface of the substrate is defined as a first direction, and two intersecting directions among the horizontal directions substantially parallel to the upper surface of the substrate are defined as a second direction and a third direction, respectively. In an exemplary embodiment, the second direction and the third direction may be orthogonal to each other. However, the exemplary embodiments of the inventive concept are not limited thereto.

[0024] Reference Figure 1 , Figure 2A and Figure 2B The vertical memory device may include an insulating pattern 115, a gate electrode, a channel 165, a tunnel insulating pattern 220, a charge trapping pattern structure 235, and a barrier pattern structure 245 on a substrate 100. Furthermore, the vertical memory device may also include a buried pattern 175, a pad 180, a second barrier pattern 255, a spacer 270, a common source line (CSL) 280, a first insulating intermediate layer 130, a second insulating intermediate layer 190, a third insulating intermediate layer 290, and a fourth insulating intermediate layer 310, a contact plug 300, and a bit line 320.

[0025] In exemplary embodiments, substrate 100 may include silicon, germanium, silicon-germanium, or III-V compounds such as GaP, GaAs, GaSb, etc. In some exemplary embodiments, substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0026] The insulating pattern 115 can be formed on multiple levels (horizontal planes) along a first direction and can be spaced apart from each other. The term "level (horizontal plane)" refers to different distances from the substrate 100 in the first direction. The insulating pattern 115 can have different thicknesses along the first direction depending on the level of the insulating pattern. For example, the lowermost insulating pattern 115 formed on the first level from the upper surface of the substrate 100 (e.g., the insulating pattern closest to the substrate in the first direction) can have a smaller thickness than the insulating patterns 115 on other levels. For example, in Figure 2A In the exemplary embodiment shown, each of the insulating patterns 115 other than the insulating pattern 115 at the first level has substantially the same thickness as each other, and such thickness is greater than the thickness of the insulating pattern at the first level.

[0027] Each of the gate electrodes can be formed between insulating patterns 115, and thus can be (e.g., in the first direction) formed on multiple horizontal (horizontal planes) spaced apart from each other. For example, in Figure 2A In the exemplary embodiment shown, insulating patterns 115 and gate electrodes are alternately and repeatedly stacked on the substrate 100 in a first direction. Each of the gate electrodes may extend in a second direction, and multiple gate electrodes may be arranged in a third direction. For example, as Figure 2A In the exemplary embodiment shown, each of the gate electrodes extending in the second direction can be formed in the opening 200 (in Figure 8 The spacers 270 and CSL 280 (shown in the diagram) are spaced apart from each other in the third direction.

[0028] The gate electrode may include a first gate electrode 263, a second gate electrode 265, and a third gate electrode 267 formed sequentially along a first direction. In an exemplary embodiment, the first gate electrode 263 may serve as a ground select line (GSL), the second gate electrode 265 may serve as a word line, and the third gate electrode 267 may serve as a serial select line (SSL). Each of the first gate electrode 263, the second gate electrode 265, and the third gate electrode 267 may be formed at one or more levels. Furthermore, in an exemplary embodiment, at least one dummy word line may also be formed between the first gate electrode 263 and the second gate electrode 265 and / or between the second gate electrode 265 and the third gate electrode 267.

[0029] like Figure 2A In an exemplary embodiment, the first gate electrode 263 may be formed on the lowest level (horizontal plane) of the electrode closest to the substrate 100 in a first direction. The third gate electrode 267 may be formed on the highest level of the electrode furthest from the substrate 100 in the first direction and on a level below it. The second gate electrode 265 may be formed on multiple levels between the first gate electrode 263 and the third gate electrode 267. For example, in Figure 2A In the exemplary embodiment shown, the second gate electrode 265 may be formed on four levels between the first gate electrode 263 and the lowermost third gate electrode 267. However, the exemplary embodiments of the inventive concept are not limited thereto. Each of the first gate electrode 263, the second gate electrode 265, and the third gate electrode 267 may be formed adjacent to the channel 165 (e.g., in the third direction).

[0030] The first gate electrode 263 may include a first gate conductive pattern and a first gate blocking pattern covering a portion of the upper and lower surfaces (e.g., in a first direction) and sidewalls of the first gate conductive pattern. The second gate electrode 265 may include a second gate conductive pattern and a second gate blocking pattern covering a portion of the upper and lower surfaces (e.g., in a first direction) and sidewalls of the second gate conductive pattern. The third gate electrode 267 may include a third gate conductive pattern and a third gate blocking pattern covering a portion of the upper and lower surfaces (e.g., in a first direction) and sidewalls of the third gate conductive pattern.

[0031] The upper and lower surfaces of each of the gate electrodes, as well as the sidewalls (e.g., inner sidewalls) adjacent to the channel 165, may be covered by the second barrier pattern 255. The second barrier pattern 255 may also cover a portion of the sidewalls of each of the insulating patterns 115, the sidewalls of each of the first insulating intermediate layer 130 and the second insulating intermediate layer 190, and a portion of the upper surface of the substrate 100. Furthermore, the second barrier pattern 255 may cover a portion of the upper surface of the oxide layer 103 formed on the substrate 100.

[0032] In an exemplary embodiment, the sidewall of each of the gate electrodes adjacent to the channel 165 may have a shape that is concave upward in the third direction.

[0033] like Figure 2A In an exemplary embodiment, the channel 165 may extend along a first direction on the upper surface of the substrate 100 and may extend through the alternating and repeating stacked insulating pattern 115 and gate electrode.

[0034] The buried pattern 175 can be formed to fill the interior space of the channel 165.

[0035] In an exemplary embodiment, the channel 165 may be formed in a cup shape, and the interior space of the cup shape may be filled with a cylindrical burial pattern 175. However, exemplary embodiments of the inventive concept are not limited thereto. For example, in an alternative embodiment, the channel 165 may have a cylindrical shape and may not have a burial pattern 175 formed.

[0036] Multiple channels 165 can be formed along a second direction and a third direction, thus defining a channel array.

[0037] The tunnel insulating pattern 220 may be formed on the outer wall of the trench 165 and may include an oxide such as silicon oxide. However, exemplary embodiments of the inventive concept are not limited thereto. The tunnel insulating pattern 220 may include a protrusion that projects horizontally (e.g., in the third direction) toward the gate electrode relative to the upper surface of the substrate 100.

[0038] In an exemplary embodiment of the present invention, the tunnel insulation pattern 220 may include a first portion 220a, a second portion 220b, and a third portion 220c, which are stacked sequentially from the outer sidewall of the trench 165 along a third direction and have a first width W1, a second width W2, and a third width W3, respectively, in a first direction.

[0039] The first portion 220a of the tunnel insulating pattern may fill the second recess 167, which may be formed on the outermost sidewall of the channel 165 in the third direction adjacent to each of the gate electrodes. The upper surface of the first portion 220a of the tunnel insulating pattern may (e.g., in the first direction) be higher than the lower surface of the insulating pattern 115 formed on each of the gate electrodes adjacent to the first portion 220a, and the lower surface of the first portion 220a of the tunnel insulating pattern may (e.g., in the first direction) be lower than the upper surface of the insulating pattern 115 formed below each of the gate electrodes adjacent to the first portion 220a.

[0040] A second portion 220b of the tunnel insulation pattern may be formed on the outer wall of the first portion 220a (e.g., the sidewall furthest from the trench 165) to cover the first portion 220a. The second portion 220b of the tunnel insulation pattern may extend (e.g., in a third-order direction) toward each of the gate electrodes adjacent to the second portion 220b. The upper surface of the second portion 220b of the tunnel insulation pattern may contact the lower surface of the insulation pattern 115 formed on each of the gate electrodes adjacent to the second portion 220b, and the lower surface of the second portion 220b of the tunnel insulation pattern may contact the upper surface of the insulation pattern 115 formed below each of the gate electrodes adjacent to the second portion 220b.

[0041] The third portion 220c of the tunnel insulating pattern may be formed on the outer wall of the second portion 220b (e.g., the sidewall furthest from the channel) and may protrude in a third direction toward each of the gate electrodes to form a protrusion. The upper surface of the third portion 220c of the tunnel insulating pattern may not contact the lower surface of the insulating pattern 115 formed on each of the gate electrodes adjacent to the third portion 220c, and the lower surface of the third portion 220c of the tunnel insulating pattern may not contact the upper surface of the insulating pattern 115 formed below each of the gate electrodes adjacent to the third portion 220c. In an exemplary embodiment, the third portion 220c of the tunnel insulating pattern may be formed on the central portion of the second portion 220b (e.g., in a first direction). However, exemplary embodiments of the inventive concept are not limited thereto.

[0042] In an exemplary embodiment of the present invention, the first width W1 of the first portion 220a (e.g., its length in the first direction) may be larger than the second width W2 of the second portion 220b. The second width W2 of the second portion 220b may be larger than the third width W3 of the third portion 220c. For example, the first width W1 of the first portion 220a, the second width W2 of the second portion 220b, and the third width W3 of the third portion 220c may gradually decrease in this order.

[0043] In an exemplary embodiment of the present invention, the third portion 220c of the tunnel insulation pattern may be surrounded (e.g., on the inner sidewall) by the second portion 220b of the tunnel insulation pattern, (e.g., on portions of the upper and lower surfaces) by the charge trapping pattern structure 235, (e.g., on portions of the upper and lower surfaces) by the blocking pattern structure 245, and (e.g., on portions of the upper and lower surfaces and on the outer sidewall) by the second blocking pattern 255.

[0044] In an exemplary embodiment, the tunnel insulation pattern 220 may include an oxide such as silicon oxide, and a plurality of tunnel insulation patterns 220 may be formed to be spaced apart from each other along the outer sidewall of the trench 165 in a first direction.

[0045] In an exemplary embodiment, the charge trapping pattern structure 235 may include a nitride such as silicon nitride. A plurality of charge trapping pattern structures 235 may be formed to be spaced apart from each other in a first direction, and each of the charge trapping pattern structures 235 may include an upper charge trapping pattern 235a and a lower charge trapping pattern 235b spaced apart from each other in the first direction via a third portion 220c (e.g., a protrusion) of the tunnel insulating pattern 220.

[0046] In an exemplary embodiment of the present invention, the uppermost surface of the tunnel insulation pattern 220 (e.g., the top surface of the first portion 220a of the tunnel insulation pattern) may be higher than the top surface of the upper charge trapping pattern 235a. The lowermost surface of the tunnel insulation pattern 220 (e.g., the bottom surface of the first portion 220a of the tunnel insulation pattern) may be lower than the bottom surface of the lower charge trapping pattern 235b.

[0047] In an exemplary embodiment, each of the upper charge trapping pattern 235a and the lower charge trapping pattern 235b may have an outer sidewall that is recessed along a third direction (e.g., the sidewall furthest from the channel 165). However, exemplary embodiments of the inventive concept are not limited thereto. For example, each of the upper charge trapping pattern 235a and the lower charge trapping pattern 235b may include an outer sidewall having a vertical outer sidewall relative to the upper surface of the substrate 100 (e.g., extending in a first direction).

[0048] In an exemplary embodiment, the barrier pattern structure 245 may include an oxide such as silicon oxide. A plurality of barrier pattern structures 245 may be formed to be spaced apart from each other in a first direction, and each of the barrier pattern structures 245 includes an upper first barrier pattern 245a and a lower first barrier pattern 245b spaced apart from each other in the first direction by a third portion 220c (e.g., a protrusion) of the tunnel insulating pattern 220. In an exemplary embodiment of the inventive concept, the barrier pattern structure 245 may be disposed between the charge trapping pattern structure 235 and the gate electrode (e.g., 267). A second barrier pattern 255 may be in direct contact with the tunnel insulating pattern 220 and the barrier pattern structure 245. The upper first barrier pattern 245a and the lower first barrier pattern 245b may be surrounded by the tunnel insulating pattern 220, the charge trapping pattern structure 235, and the second barrier pattern 255.

[0049] In an exemplary embodiment of the present invention, the top surface of the first portion 220a of the tunnel insulation pattern may (e.g., in a first direction) be higher than the top surface of the upper first barrier pattern 245a. The bottom surface of the first portion 220a of the tunnel insulation pattern may (e.g., in a first direction) be lower than the bottom surface of the lower first barrier pattern 245b.

[0050] like Figure 2B In the exemplary embodiment shown, the top surface of the upper first blocking pattern 245a and the top surface of the upper charge trapping pattern 235a may be formed at the same height (e.g., at the same distance from the upper surface of the substrate 100 in the first direction) to contact the insulating pattern 115 formed thereon, and the bottom surface of the lower first blocking pattern 245b and the bottom surface of the lower charge trapping pattern 235b may also be formed at the same height to contact the insulating pattern 115 formed thereunder.

[0051] A first insulating interlayer 130 may be formed on the channel 165 and the uppermost insulating pattern 115, and a pad 180 may extend through the first insulating interlayer 130 to contact the upper surface of the channel 165. A second insulating interlayer 190 may be formed on the first insulating interlayer 130 and the pad 180. For example, the bottom surface of the second insulating interlayer 190 may (e.g., in the first direction) be directly disposed on the top surface of the first insulating interlayer 130 and the top surface of the pad 180.

[0052] Spacer 270 may be formed in opening 200 extending through insulating pattern 115 and gate electrode and exposing upper surface of substrate 100. Figure 8 On the side wall (as shown in the diagram). CSL 280 can fill the remaining portion of opening 200.

[0053] The third insulating interlayer 290 can be formed on the second insulating interlayer 190, CSL 280, spacer 270, and second barrier pattern 255. For example, as Figure 2A In the exemplary embodiment shown, the bottom surface of the third insulating intermediate layer 290 may (e.g., in the first direction) be formed on the top surface of the second insulating intermediate layer 190, the top surface of the CSL 280, the top surface of the spacer 270, and the top surface of the second blocking pattern 255.

[0054] The contact plug 300 can extend through the second insulating intermediate layer 190 and the third insulating intermediate layer 290 to contact the upper surface of the pad 180.

[0055] Bit line 320 may extend through the fourth insulating interlayer 310 to contact the upper surface of contact plug 300. For example, in an exemplary embodiment, bit line 320 may extend upward in a third direction, and multiple bit lines may be arranged in a second direction.

[0056] As described above, the charge trapping pattern structure 235 formed between the gate electrode and the channel 165 (specifically, between each of the gate electrodes and the tunnel insulating pattern 220) may include an upper charge trapping pattern 235a and a lower charge trapping pattern 235b spaced apart from each other along a first direction, such that electrons can be effectively injected through each of the upper charge trapping pattern 235a and the lower charge trapping pattern 235b, thereby improving the electrical characteristics of the vertical memory device.

[0057] Furthermore, the multiple charge trapping pattern structures 235 can be formed to be spaced apart from each other along the first direction, and each of the charge trapping pattern structures 235 can be separated by each of the insulating patterns 115. Therefore, interference between adjacent gate electrodes can be minimized, and coupling between gate electrodes can be reduced.

[0058] Figures 3 to 15 This is a cross-sectional view illustrating stages of a method for manufacturing a vertical memory device according to an exemplary embodiment of the present invention. In particular, Figures 3 to 9A and Figures 10 to 15 It is along Figure 1 A sectional view taken by line A-A'. Figure 9B yes Figure 9A An enlarged sectional view of region X'.

[0059] Reference Figure 3 The insulating layer 110 and the sacrificial layer structure 120 can be stacked alternately and repeatedly on the substrate 100 (e.g., in the first direction). Therefore, multiple insulating layers 110 and multiple sacrificial layer structures 120 can be stacked alternately in the first direction. Figure 3In the exemplary embodiment shown, eight horizontal (horizontal) insulating layers 110 and seven horizontal (horizontal) sacrificial layer structures 120 are alternately formed on the substrate 100. However, the number of insulating layers 110 and sacrificial layer structures 120 is not limited thereto, and each of the insulating layers 110 and sacrificial layer structures 120 may be formed in a larger or smaller number.

[0060] The sacrificial layer structure 120 may have a second sacrificial layer 120b formed between two first sacrificial layers 120a. For example, the first sacrificial layer 120a, the second sacrificial layer 120b, and the first sacrificial layer 120a may be stacked sequentially to form a sacrificial layer structure 120. The top surface of the second sacrificial layer 120b may contact the bottom surface of the upper first sacrificial layer (i.e., the upper first sacrificial layer), and the bottom surface of the second sacrificial layer may contact the top surface of the lower first sacrificial layer (i.e., the lower first sacrificial layer). In an exemplary embodiment, the thickness of the second sacrificial layer 120b (e.g., its length in a first direction) may be smaller than the thickness of the first sacrificial layer 120a.

[0061] In an exemplary embodiment, the insulating layer 110 and the sacrificial layer structure 120 can be formed by chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or the like. Alternatively, the insulating layer 110 can be formed directly on the upper surface of the substrate 100 by a thermal oxidation process.

[0062] The insulating layer 110 may include silicon oxide, such as PE-TEOS, HDP oxide, PEOX, etc. The sacrificial layer structure 120 may include a material such as silicon nitride that has etch selectivity relative to the insulating layer 110.

[0063] In an exemplary embodiment, each of the first sacrificial layer 120a and the second sacrificial layer 120b of the sacrificial layer structure 120 may have etch selectivity relative to each other.

[0064] For example, the first sacrificial layer 120a and the second sacrificial layer 120b may comprise silicon nitride, and for a particular etch solution or a particular etch gas, the second sacrificial layer 120b may have a higher etch rate than the first sacrificial layer 120a. Therefore, when performing an etch process using an etch solution or etch gas, the first sacrificial layer 120a can be etched to a less extent than the second sacrificial layer 120b.

[0065] Alternatively, in another exemplary embodiment, the first sacrificial layer 120a and the second sacrificial layer 120b may have different materials from each other. For example, the first sacrificial layer 120a and the second sacrificial layer 120b may respectively comprise silicon nitride and silicon oxynitride. In another exemplary embodiment, the first sacrificial layer 120a and the second sacrificial layer 120b may also respectively comprise silicon oxynitride and silicon nitride. Therefore, when an etching process for removing the second sacrificial layer 120b is performed, the first sacrificial layer 120a can be etched to a lesser extent.

[0066] In an exemplary embodiment, the lowermost insulating layer 110 formed at a first level (first horizontal plane) on the upper surface of the substrate 100 in a first direction may have a smaller thickness compared to the insulating layers 110 at other levels. In an exemplary embodiment, the insulating layers 110 other than the lowermost insulating layer 110 may have substantially the same thickness as each other.

[0067] Reference Figure 4 A first insulating intermediate layer 130 is formed on the uppermost insulating layer 110. For example, as... Figure 4 In the exemplary embodiment shown, the bottom surface of the first insulating intermediate layer 130 can be formed directly on the top surface of the uppermost insulating layer 110. Subsequently, an etching process is performed using an etching mask to etch the underlying first insulating intermediate layer 130, insulating layer 110, and sacrificial layer structure 120, and a channel hole 140 extending through the first insulating intermediate layer 130, insulating layer 110, and sacrificial layer structure 120 can be formed to expose the upper surface of the substrate 100.

[0068] In an exemplary embodiment, the channel hole 140 may also extend partially through the upper portion of the substrate 100.

[0069] Reference Figure 5 The sidewalls of the second sacrificial layer 120b of each of the sacrificial layer structures 120 exposed by the channel hole 140 can be partially removed to form (e.g., an upwardly extending third portion) a first recess 150.

[0070] In an exemplary embodiment, each of the first recesses 150 can be formed by partially removing each of the second sacrificial layers 120b, and the recesses can have a constant depth in the third direction. Thus, the alternating and repetitively stacked insulating layers 110 and sacrificial layer structures 120 can generally have an uneven shape along the first direction.

[0071] The first sacrificial layer 120a and the second sacrificial layer 120b may have etch selectivity relative to each other, such that the first sacrificial layer 120a is not removed when the first recess 150 is formed.

[0072] In an exemplary embodiment, the first recess 150 may be formed by a dry etching process or a wet etching process. However, exemplary embodiments of the present invention are not limited thereto.

[0073] Reference Figure 6 A channel layer 160 may be formed on the exposed upper surface of the substrate 100, the sidewalls of the insulating layer 110 and the sidewalls of the sacrificial layer structure 120, the first recess 150 and the upper surface of the first insulating intermediate layer 130.

[0074] The channel layer 160 can be formed to fill each of the first recesses 150, and the portion of the outer wall of the channel layer 160 adjacent to each of the second sacrificial layers 120b can protrude further in the horizontal direction (e.g., in the third direction) than other portions of its outer wall to form a protrusion. Thus, the outer wall of the channel layer 160 can generally have an uneven shape along the first direction.

[0075] In an exemplary embodiment, the channel layer 160 may include amorphous silicon or polycrystalline silicon that is doped or undoped. In an exemplary embodiment where the channel layer 160 includes amorphous silicon, a laser epitaxial growth (LEG) process or a solid-state epitaxy (SPE) process may be further performed to convert the amorphous silicon into crystalline silicon.

[0076] Reference Figure 7 A buried layer can be formed on the trench layer 160 to effectively fill the remaining portion of the trench aperture 140. The buried layer and trench layer 160 can then be planarized until the upper surface of the first insulating intermediate layer 130 can be exposed, and the buried pattern 175 and trench 165 can be formed to fill the trench aperture 140. In an exemplary embodiment, the trench 165 may have a cup-shaped shape, and the buried pattern 175 may have a columnar shape.

[0077] Multiple channels 165 can be formed along the second and third directions to form a channel array.

[0078] In an exemplary embodiment, the buried pattern 175 may include oxides such as silicon oxide.

[0079] The upper portion of each of the burial pattern 175 and the trench 165 can be removed to form a trench and a pad 180 can be formed to fill the trench.

[0080] For example, after removing the upper portions of each of the buried pattern 175 and the trench 165 to form a trench, a pad layer filling the trench can be formed on the buried pattern 175, the trench 165, and the first insulating intermediate layer 130. The upper portion of the pad layer can then be planarized until the upper surface of the first insulating intermediate layer 130 can be exposed to form the pad 180. In an exemplary embodiment, the pad layer may comprise amorphous silicon or polycrystalline silicon doped with impurities. However, exemplary embodiments of the inventive concept are not limited thereto. In an exemplary embodiment where the pad layer comprises amorphous silicon, processes for crystallizing the pad layer may be further performed.

[0081] Reference Figure 8 A second insulating interlayer 190 is formed on the first insulating interlayer 130 and the pad 180. For example, as... Figure 8 In the exemplary embodiment, the bottom surface of the second insulating intermediate layer 190 can directly contact the top surface of the first insulating intermediate layer 130. An opening 200 extending through the first insulating intermediate layer 130 and the second insulating intermediate layer 190, the insulating layer 110 and the sacrificial layer structure 120 can then be formed by performing an etching process using an etching mask to expose the upper surface of the substrate 100.

[0082] In an exemplary embodiment, the opening 200 may extend in a second direction and may form a plurality of openings 200 along a third direction.

[0083] Because of the opening 200, the insulating layer 110 can be converted into the insulating pattern 115, and the sacrificial layer structure 120 can be converted into the sacrificial pattern structure.

[0084] The sacrificial pattern structure exposed by the opening 200 can be removed to form a gap 210 between each horizontal insulating pattern 115, and a portion of the outer wall of the channel 165 can be exposed by the gap 210. In an exemplary embodiment, the sacrificial pattern structure exposed by the opening 200 can be removed by a wet etching process using an etchant comprising phosphoric acid or sulfuric acid.

[0085] The portion of the outer wall of the channel 165 exposed by the gap 210 may include a protrusion projecting upward in a third direction.

[0086] Reference Figure 9A An oxidation process can be performed on the portion of the outer wall of the trench 165 exposed by the gap 210 to form a tunnel insulation pattern 220 on the outer wall of the trench 165.

[0087] The tunnel insulation pattern 220 can be formed by oxidation of the portion of the outer wall of the trench exposed by the gap 210, and thus the tunnel insulation pattern 220 may include a protruding portion projecting upward in a third direction.

[0088] Furthermore, during the oxidation process, a portion of the channel 165 is converted into a tunnel insulation pattern 220. The portion of the channel adjacent to the tunnel insulation pattern 220 in the third direction may have a smaller thickness than the other portions of the channel 165 (e.g., its length in the third direction). Therefore, the channel 165 may have a thickness (e.g., its length in the third direction) that is not constant along the first direction.

[0089] In an exemplary embodiment, the tunnel insulation pattern 220 may include an oxide such as silicon oxide, and a plurality of tunnel insulation patterns 220 may be formed to be spaced apart from each other along the outer sidewall of the trench 165 in a first direction.

[0090] In an exemplary embodiment, the tunnel insulation pattern 220 may have a flat upper surface and a flat lower surface, and may have an inner wall that is substantially perpendicular (e.g., extending in a first direction) to the upper surface of the substrate 100.

[0091] Alternatively, an oxidation process can be used to oxidize the portion of the upper surface of the substrate 100 exposed by the opening 200 to form an oxide layer 103. In an exemplary embodiment, the oxide layer 103 may include an oxide such as silicon oxide.

[0092] Reference Figure 9B The tunnel insulation pattern 220 may include a first portion 220a, a second portion 220b, and a third portion 220c, which are sequentially stacked along a third direction from the outer wall of the trench 165 and have a first width W1, a second width W2, and a third width W3 in the respective first direction. For example, the inner wall of the first portion 220a (e.g., the sidewall closest to the trench 165) may directly contact the outer wall of the trench and extend along the first direction. The outer wall of the first portion 220a may directly contact the inner wall of the second portion 220b. The outer wall of the second portion may directly contact the inner wall of the third portion 220c.

[0093] The first portion 220a of the tunnel insulation pattern may fill the second recess 167, which may be formed on the outer sidewall of the channel 165 adjacent to the gap 210 in the third direction. The upper surface of the first portion 220a of the tunnel insulation pattern (e.g., in the first direction) may be higher than the lower surface of the insulation pattern 115 formed below the gap 210 (e.g., in the first direction).

[0094] The second portion 220b of the tunnel insulation pattern may be formed on the outer wall of the first portion 220a to cover the first portion 220a, and may extend upward toward the gap 210. The upper surface of the second portion 220b of the tunnel insulation pattern may contact the lower surface of the insulation pattern 115 formed above the gap 210. The lower surface of the second portion 220b of the tunnel insulation pattern may contact the upper surface of the insulation pattern 115 formed below the gap 210.

[0095] The third portion 220c of the tunnel insulation pattern may be formed on the outer wall of the second portion 220b (e.g., the sidewall furthest from the trench 165) and may protrude within the gap 210 to form a protrusion. However, the upper surface of the third portion 220c of the tunnel insulation pattern may not contact the lower surface of the insulation pattern 115 formed above the gap 210, and the lower surface of the third portion 220c of the tunnel insulation pattern may not contact the upper surface of the insulation pattern 115 formed below the gap 210. In an exemplary embodiment, the third portion 220c of the tunnel insulation pattern may be formed on the central portion of the second portion 220b (e.g., in the first direction).

[0096] exist Figure 9B In the exemplary embodiment shown, the first width W1 of the first portion 220a (e.g., its length in the first direction) may be larger than the second width W2 of the second portion 220b, and the second width W2 of the second portion 220b may be larger than the third width W3 of the third portion 220c. Therefore, the first width W1 of the first portion 220a, the second width W2 of the second portion 220b, and the third width W3 of the third portion 220c may gradually decrease in this order.

[0097] In an exemplary embodiment, the first portion 220a may have a thickness greater than that of the second portion 220b (e.g., in length in the third direction) but less than that of the third portion 220c. For example, the third portion 220c may have the maximum thickness in the third direction, and the second portion 220b may have the minimum thickness in the third direction.

[0098] Reference Figure 10 A charge trapping layer 230 is conformally formed on the outer wall of the tunnel insulation pattern 220, the upper surface, lower surface, and sidewall of each of the insulation patterns 115, the oxide layer 103, and the surface of each of the first insulating intermediate layer 130 and the second insulating intermediate layer 190. The charge trapping layer 230 can then be partially removed to form a structure as described above. Figure 11 The charge trapping pattern structure 235 is shown. In an exemplary embodiment, the charge trapping layer 230 may include a nitride such as silicon nitride.

[0099] In an exemplary embodiment, the charge trapping layer 230 can be formed using chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or the like. The charge trapping layer 230 can have a uniform thickness overall. However, since the outer wall of the tunnel insulation pattern 220 may include a protruding portion projecting upwards in a third direction, the portion of the charge trapping layer 230 formed between the third portion 220c of the tunnel insulation pattern and each of the insulation patterns 115 can have a greater thickness than the other portions of the charge trapping layer 230.

[0100] Reference Figure 11 In an exemplary embodiment, a wet etching process may be performed on the charge trapping layer 230.

[0101] The charge trapping layer 230 can have a uniform thickness overall, and most of the charge trapping layer 230 can be removed. However, the portion of the charge trapping layer 230 with a larger thickness formed between the third portion 220c of the tunnel insulating pattern and each insulating pattern 115 is not completely removed even after the etching process and can be retained to form the charge trapping pattern structure 235.

[0102] Multiple charge trapping pattern structures 235 may be formed to be spaced apart from each other in a first direction, and each of the charge trapping pattern structures 235 may include an upper charge trapping pattern 235a and a lower charge trapping pattern 235b spaced apart from each other in the first direction through a third portion 220c (e.g., a protrusion) of the tunnel insulating pattern 220.

[0103] In an exemplary embodiment, the top surface of the first portion 220a of the tunnel insulation pattern 220 (e.g., the uppermost surface of the tunnel insulation pattern) may be higher than the upper surface of the upper charge trapping pattern 235a, and the bottom surface of the first portion 220a of the tunnel insulation pattern (e.g., the lowermost surface of the tunnel insulation pattern) may be lower than the bottom surface of the lower charge trapping pattern 235b.

[0104] In an exemplary embodiment, each of the upper charge trapping pattern 235a and the lower charge trapping pattern 235b may have an outer sidewall with a recessed shape along a third direction (e.g., the sidewall furthest from the channel 165). However, exemplary embodiments of the inventive concept are not limited thereto. For example, each of the upper charge trapping pattern 235a and the lower charge trapping pattern 235b may have an outer sidewall with a recessed shape along a third direction, or may have a vertical outer sidewall relative to the upper surface of the substrate 100.

[0105] Reference Figure 12A first barrier layer 240 may be conformally formed on the outer wall of the tunnel insulation pattern 220, the outer wall of the charge trapping pattern structure 235, the upper surface, lower surface and sidewall of each of the insulation patterns 115, the oxide layer 103, and the surfaces of the first insulation intermediate layer 130 and the second insulation intermediate layer 190 exposed by the opening 200 and the gap 210.

[0106] In an exemplary embodiment, the first barrier layer 240 may include an oxide such as silicon oxide. However, exemplary embodiments of the present invention are not limited thereto.

[0107] Reference Figure 13 An etching process, such as a wet etching process, can be performed on the first barrier layer 240 to form a barrier pattern structure 245.

[0108] Multiple barrier pattern structures 245 may be formed to be spaced apart from each other in a first direction, and each of the barrier pattern structures 245 may include an upper first barrier pattern 245a and a lower first barrier pattern 245b spaced apart from each other in the first direction by a third portion 220c (e.g., a protrusion) of a tunnel insulation pattern.

[0109] In an exemplary embodiment, the top surface of the first portion 220a of the tunnel insulation pattern may (e.g., in a first direction) be higher than the top surface of the upper first barrier pattern 245a, and the bottom surface of the first portion 220a of the tunnel insulation pattern may (e.g., in a first direction) be lower than the bottom surface of the lower first barrier pattern 245b.

[0110] In an exemplary embodiment, the upper surfaces of the upper first blocking pattern 245a and the upper charge trapping pattern 235a may be formed at the same height (e.g., at the same distance from the upper surface of the substrate 100 in a first direction) to contact the insulating pattern 115 formed thereon. The lower surfaces of the lower first blocking pattern 245b and the lower charge trapping pattern 235b may also be formed at the same height to contact the insulating pattern 115 formed below thereon.

[0111] like Figure 13 In the exemplary embodiment shown, each of the upper first blocking pattern 245a and the lower first blocking pattern 245b may have an outer wall with a recessed shape along a third direction.

[0112] Reference Figure 14A second barrier layer 250 can be conformally formed on the outer walls of the tunnel insulating pattern 220, the outer walls of the barrier pattern structure 245, the outer walls of the charge trapping pattern structure 235, the upper surface, lower surface, and sidewalls of each insulating pattern 115, the oxide layer 103, and the surfaces of the first insulating intermediate layer 130 and the second insulating intermediate layer 190 exposed by the opening 200 and the gap 210. A gate electrode layer can then be formed on the second barrier layer 250 to effectively fill the remaining portion of the gap 210.

[0113] In an exemplary embodiment, the second barrier layer 250 may include a metal oxide such as aluminum oxide, hafnium oxide, zirconium oxide, etc. However, exemplary embodiments of the present invention are not limited thereto.

[0114] The gate electrode layer may include a gate barrier layer and a gate conductive layer stacked sequentially. In an exemplary embodiment, the gate conductive layer may include a metal with low resistance (such as tungsten, titanium, tantalum, platinum, etc.). The gate barrier layer may include a metal nitride such as titanium nitride, tantalum nitride, etc.

[0115] The gate electrode layer can be partially removed to form a gate conductive pattern and a gate blocking pattern in the gap 210, and the gate conductive pattern and the gate blocking pattern can be formed together to form the gate electrode. In an exemplary embodiment, the gate conductive pattern and the gate blocking pattern can be removed by a wet etching process.

[0116] The gate electrode can extend in a second direction, and multiple gate electrodes can be formed along a third direction. Each of the gate electrodes extending in the second direction can be spaced apart from each other in the third direction through an opening 200.

[0117] The gate electrode may include a first gate electrode 263, a second gate electrode 265, and a third gate electrode 267 formed sequentially along a first direction. The first gate electrode 263 may be used as a ground select line (GSL), the second gate electrode 265 may be used as a word line, and the third gate electrode 267 may be used as a serial select line (SSL). Each of the first gate electrode 263, the second gate electrode 265, and the third gate electrode 267 may be formed on one or more horizontal planes. Furthermore, at least one dummy word line may be formed between the first gate electrode 263 and the second gate electrode 265 and / or between the second gate electrode 265 and the third gate electrode 267.

[0118] In an exemplary embodiment, a first gate electrode 263 may be formed on a first level (e.g., the lowest level in a first direction), a third gate electrode 267 may be formed on the highest level and one level below it, and a second gate electrode 265 may be formed on multiple levels between the first gate electrode 263 and the third gate electrode 267.

[0119] The first gate electrode 263 may include a first gate conductive pattern and a first gate blocking pattern covering a portion of the upper and lower surfaces and sidewalls of the first gate conductive pattern; the second gate electrode 265 may include a second gate conductive pattern and a second gate blocking pattern covering a portion of the upper and lower surfaces and sidewalls of the second gate conductive pattern; and the third gate electrode 267 may include a third gate conductive pattern and a third gate blocking pattern covering a portion of the upper and lower surfaces and sidewalls of the third gate conductive pattern.

[0120] The top surface of the first portion 220a of the tunnel insulating pattern may be higher than the bottom surface of the insulating pattern 115 formed on each gate electrode adjacent to the first portion 220a, and the bottom surface of the first portion 220a of the tunnel insulating pattern may be lower than the top surface of the insulating pattern 115 formed below each gate electrode adjacent to the first portion 220a. The top surface of the second portion 220b of the tunnel insulating pattern may contact the bottom surface of the insulating pattern 115 formed on each gate electrode adjacent to the second portion 220b, and the bottom surface of the second portion 220b of the tunnel insulating pattern may contact the top surface of the insulating pattern 115 formed below each gate electrode adjacent to the second portion 220b. The upper surface of the third portion 220c of the tunnel insulating pattern may not contact the lower surface of the insulating pattern 115 formed on each gate electrode adjacent to the third portion 220c, and the bottom surface of the third portion 220c of the tunnel insulating pattern may not contact the top surface of the insulating pattern 115 formed below each gate electrode adjacent to the third portion 220c.

[0121] In an exemplary embodiment, the inner sidewall of each gate electrode adjacent to the channel 165 may have a recessed shape along a third direction.

[0122] Reference Figure 15 Impurities can be implanted into the exposed upper portion of the substrate 100 formed beneath the oxide layer 103 to form impurity regions 105. Spacer layers can be formed on the upper surface of the impurity regions 105, the sidewalls of the opening 200, and the upper surface of the second insulating intermediate layer 190. The spacer layers can be anisotropically etched to form spacers 270 on the sidewalls of the opening 200. Therefore, the impurity regions 105 on the upper portion of the substrate 100 can be partially exposed.

[0123] In an exemplary embodiment, the impurities may include n-type impurities such as phosphorus and arsenic, and the second spacer layer may include an oxide such as silicon oxide. However, exemplary embodiments of the present invention are not limited thereto.

[0124] A common source pole line (CSL) 280 can be formed on the exposed impurity region 105 to fill the remaining portion of the opening 200.

[0125] In an exemplary embodiment, the CSL 280 can be formed by forming a conductive layer on the exposed impurity region 105, spacer 270, and second insulating intermediate layer 190 to fill the opening 200. The upper portion of the conductive layer is then planarized until the upper surface of the second insulating intermediate layer 190 is exposed. Alternatively, a portion of the second barrier layer 250 formed on the upper surface of the second insulating intermediate layer 190 can be removed; the second barrier layer 250 can be converted into a second barrier pattern 255. The conductive layer may include a metal, a metal nitride, and / or a metal silicide.

[0126] Refer again Figure 1 , Figure 2A and Figure 2B After the third insulating intermediate layer 290 is formed on the second insulating intermediate layer 190, CSL 280, spacer 270 and the second blocking pattern 255, a contact plug 300 can be formed extending through the third insulating intermediate layer 290 and the second insulating intermediate layer 190 and contacting the upper surface of the pad 180.

[0127] After the fourth insulating intermediate layer 310 is formed on the third insulating intermediate layer 290 and the contact plug 300, a bit line 320 extending through the fourth insulating intermediate layer 310 and contacting the upper surface of the contact plug 300 can be formed, thereby completing the manufacturing of the vertical memory device.

[0128] In an exemplary embodiment, the third insulating intermediate layer 290 and the fourth insulating intermediate layer 310 may include oxides such as silicon oxide, and the contact plug 300 and bit line 320 may include metals (such as copper, aluminum, tungsten, titanium, tantalum, etc.) and / or metal nitrides (e.g., titanium nitride, tantalum nitride, tungsten nitride, etc.). However, exemplary embodiments of the inventive concept are not limited thereto.

[0129] In an exemplary embodiment, bit lines 320 may extend upward in a third direction, and multiple bit lines 320 may be formed along a second direction.

[0130] As described above, (e.g., in the third direction) the charge trapping pattern structure 235 formed between the gate electrode and the channel 165 may include an upper charge trapping pattern 235a and a lower charge trapping pattern 235b spaced apart from each other along a first direction by a third portion 220c of the tunnel insulating pattern, so that electrons can be effectively injected through each of the upper charge trapping pattern 235a and the lower charge trapping pattern 235b, thereby improving the electrical characteristics of the vertical memory device.

[0131] Furthermore, multiple charge trapping pattern structures 235 can be formed to be spaced apart from each other along a first direction, and each of the charge trapping pattern structures 235 can be separated by each of the insulating patterns 115. Therefore, interference between adjacent gate electrodes can be minimized, and coupling between gate electrodes can be reduced.

[0132] Figure 16 It is along Figure 1 The section cut by line A-A' shows a cross-sectional view of an exemplary embodiment of a vertical memory device according to the present invention.

[0133] In addition to the shape of the inner wall of the tunnel insulation pattern, Figure 16 The vertical memory device shown in the exemplary embodiment and Figure 1 , Figure 2A and Figure 2B The vertical memory devices described herein are substantially the same or similar. Therefore, the same reference numerals denote the same elements, and detailed descriptions thereof are omitted here.

[0134] Reference Figure 16 The inner sidewall of the tunnel insulation pattern 220 that contacts the trench 165 may have a varying slope and is not perpendicular to the upper surface of the substrate 100 (e.g., does not extend in the first direction).

[0135] In an exemplary embodiment, the upper portion of the inner sidewall of the tunnel insulation pattern 220 may have a slope that decreases in absolute value towards the top. The lower portion of the inner sidewall of the tunnel insulation pattern 220 may have a slope that increases in absolute value towards the bottom, and the remaining portion of the inner sidewall of the tunnel insulation pattern 220 is substantially perpendicular to the upper surface of the substrate 100. For example, the inner sidewall of the tunnel insulation pattern 220 may bulge significantly towards the trench 165 in a third-order upward direction.

[0136] Figure 17 and Figure 18 This is a cross-sectional view illustrating an exemplary embodiment of a vertical memory device according to the present invention. Figure 17 and Figure 18 It is along Figure 1 A sectional view taken by line A-A'.

[0137] In addition to the shape of each of the charge-trapping pattern structure and the blocking pattern structure Figure 17 and Figure 18 The vertical memory device shown is with Figure 1 , Figure 2A and Figure 2B The vertical memory devices described herein are substantially the same or similar. Therefore, the same reference numerals denote the same elements, and detailed descriptions thereof are omitted here.

[0138] Reference Figure 17 Each of the upper charge trapping pattern 235a and the lower charge trapping pattern 235b may have an outer sidewall that is substantially perpendicular to the upper surface of the substrate 100 (e.g., extending in a first direction), and each of the upper first blocking pattern 245a and the lower first blocking pattern 245b may also have an outer sidewall that is substantially perpendicular to the upper surface of the substrate 100.

[0139] Therefore, the portion of the second blocking pattern 255 that contacts the outer sidewall of the blocking pattern structure 245 may have a sidewall that is substantially perpendicular (e.g., extending in a first direction) to the upper surface of the substrate 100.

[0140] Reference Figure 18 Each of the upper charge trapping pattern 235a and the lower charge trapping pattern 235b may have an outer wall with a raised shape along a third direction, and each of the upper first blocking pattern 245a and the lower first blocking pattern 245b may also have an outer wall with a raised shape along a third direction (e.g., extending toward the channel 165).

[0141] Therefore, the portion of the second blocking pattern 255 that contacts the outer wall of the blocking pattern structure 245 may have a concave sidewall.

[0142] Figure 19 It is along Figure 1 The section cut by line A-A' shows a cross-sectional view of an exemplary embodiment of a vertical memory device according to the present invention.

[0143] In addition to the shape of the obstructing pattern structure Figure 19 Vertical memory devices and Figure 1 , Figure 2A and Figure 2B The vertical memory devices described herein are substantially the same or similar. Therefore, the same reference numerals denote the same elements, and detailed descriptions thereof are omitted here.

[0144] Reference Figure 19 The vertical memory device can be in Figures 3 to 15 as well as Figure 1 , Figure 2A and Figure 2B The process described in the document is not implemented. Figure 13 It was manufactured using the process described in the paper, in which the first barrier layer 240 is partially removed.

[0145] For example, after the first barrier layer 240 is formed, the first barrier layer 240 may not be partially removed, and a second barrier layer 250 may be formed on the first barrier layer 240. Therefore, the barrier pattern structure 245 may be formed not to be spaced apart from each other in the first direction, and may be referred to as the first barrier pattern 245.

[0146] For example, in execution and Figures 3 to 15 Following a process substantially identical or similar to that described herein, a first barrier layer 240 and a second barrier layer 250 may be sequentially formed on the outer walls of the tunnel insulating pattern 220, the outer walls of the charge trapping pattern structure 235, the upper surface, lower surface, and sidewalls of each insulating pattern 115, the oxide layer 103, and the surfaces of the first insulating intermediate layer 130 and the second insulating intermediate layer 190 exposed by the opening 200 and the gap 210. A gate electrode layer may then be formed to effectively fill the remaining portion of the gap 210. The gate electrode layer may be partially removed to form a gate electrode in the gap 210, and a process similar to that described herein may be performed. Figure 14 and Figure 15 as well as Figure 1 , Figure 2A and Figure 2B The processes described in the text are basically the same or similar, thus completing the manufacturing of vertical memory devices.

[0147] In an exemplary embodiment of the present invention, the first blocking pattern 245 may cover the upper surface, lower surface and sidewalls of the protruding portion of the tunnel insulating pattern 220 adjacent to each gate electrode, and may contact the outer sidewall of the charge trapping pattern structure 235.

[0148] Figures 20 to 22A and Figure 23 It is along Figure 1 The section along line A-A' shows a cross-sectional view of various stages of a method for manufacturing a vertical memory device according to an exemplary embodiment of the present invention. Figure 22B This is an exemplary embodiment of the concept of the present invention. Figure 22A An enlarged view of region X'' shown in the image.

[0149] The method includes with Figures 3 to 15 as well as Figure 1 , Figure 2A and Figure 2B The processes described herein are essentially the same or similar. Therefore, a detailed description thereof is omitted here.

[0150] Reference Figure 20 The oxidation process can be omitted from the outer wall of the channel 165 exposed by the gap 210, and the exposed outer wall of the channel 165 can be partially removed.

[0151] An etching process can be performed to reduce the size of only the protruding portion of the outer wall of the channel 165 without completely removing the protrusion, so that the channel 165 can still have an uneven shape even after the etching process. However, after the etching process, the thickness (e.g., the length in the third direction) of the portion of the channel 165 exposed by the gap 210 can be smaller than that of the other portions of the channel 165.

[0152] In an exemplary embodiment, the etching process may include a process for selectively removing polycrystalline silicon or amorphous silicon.

[0153] Reference Figure 21 The exemplary embodiment shown can conformally form the tunnel insulation layer 223.

[0154] Therefore, it is not necessary to form an oxide layer 103 on the upper surface of the substrate 100 exposed by the opening 200.

[0155] In an exemplary embodiment, the tunnel insulation layer 223 may include an oxide such as silicon oxide and may be integrally formed along a first direction and a third direction. However, exemplary embodiments of the inventive concept are not limited thereto.

[0156] Since the tunnel insulation layer 223 can be formed as a protruding portion with a reduced size covering the outer wall of the trench 165, the tunnel insulation layer 223 can have a shape that protrudes upward in the third direction in the internal space of the gap between adjacent insulation patterns 115.

[0157] In an exemplary embodiment, the tunnel insulation layer 223 may have a uniform thickness overall. However, the tunnel insulation layer 223 may have a relatively large thickness on the portion of the outer wall of the trench 165 exposed by the gap 210. (Refer to...) Figure 22A and Figure 22B It can execute with Figures 10 to 13 The processes described in the text are basically the same or similar.

[0158] After a charge trapping layer 230 is conformally formed on the outer wall of the tunnel insulating layer 223, the charge trapping layer 230 can be partially removed to form a charge trapping pattern structure 235. A first barrier layer 240 can then be conformally formed on both the outer wall of the tunnel insulating layer 223 and the outer wall of the charge trapping pattern structure 235. The first barrier layer 240 can then be partially etched to form the barrier pattern structure 245.

[0159] When the first barrier layer 240 is partially etched, the tunnel insulation layer 223 can also be partially removed, thus forming the tunnel insulation pattern 225.

[0160] In an exemplary embodiment, the uppermost surface of the tunnel insulation pattern 225 may (e.g., in a first direction) be higher than the bottom surface of the insulation pattern 115 formed on the tunnel insulation pattern 225, and the lowermost surface of the tunnel insulation pattern 225 may (e.g., in a first direction) be lower than the top surface of the insulation pattern 115 formed below the tunnel insulation pattern 225.

[0161] In an exemplary embodiment, the upper surface, lower surface, and inner sidewall adjacent to the channel 165 of the upper charge trapping pattern 235a may be covered by the tunnel insulating pattern 225. The upper surface and lower surface of the upper first blocking pattern 245a may be covered by the tunnel insulating pattern 225. The upper surface, lower surface, and inner sidewall adjacent to the channel 165 of the lower charge trapping pattern 235b may be covered by the tunnel insulating pattern 225. The upper surface and lower surface of the lower first blocking pattern 245b may be covered by the tunnel insulating pattern 225.

[0162] In an exemplary embodiment, the upper and lower surfaces of the upper charge trapping pattern 235a may be formed at substantially the same height as the upper and lower surfaces of the upper first blocking pattern 245a, and the upper and lower surfaces of the lower charge trapping pattern 235b may be formed at substantially the same height as the upper and lower surfaces of the lower first blocking pattern 245b.

[0163] In an exemplary embodiment, a first distance D1, which is the shortest distance (e.g., in the third direction) between the channel 165 through which the tunnel insulating pattern 225 is interposed and the insulating pattern 115, can be larger than a second distance D2, which is the shortest distance between the channel 165 through which the tunnel insulating pattern 225 is interposed and the charge trapping pattern structure 235. However, exemplary embodiments of the inventive concept are not limited thereto; the first distance D1 may be smaller than the second distance D2, or the first distance D1 and the second distance D2 may be substantially the same as each other.

[0164] In an exemplary embodiment of the present invention, the outer wall of the tunnel insulation pattern 225 and the outer wall of the barrier pattern structure 245 exposed by the gap 210 may together have an uneven shape.

[0165] Reference Figure 23 It can execute with Figure 14 and Figure 15 as well as Figure 1 , Figure 2A and Figure 2B The processes described in the text are essentially the same or similar, thus completing the fabrication of the vertical memory device.

[0166] Since the outer sidewalls of the tunnel insulation pattern 225 and the outer sidewalls of the barrier pattern structure 245 exposed by the gap 210 can together have an uneven shape, the sidewalls of each gate electrode adjacent to them can also have an uneven shape.

[0167] As described above, although the inventive concept has been described with reference to exemplary embodiments, it will be readily understood by those skilled in the art that many modifications can be made in the exemplary embodiments without substantially departing from the novel teachings and advantages of the inventive concept.

Claims

1. A vertical memory device, the vertical memory device comprising: Gate electrodes are disposed on the substrate and spaced apart from each other in a vertical direction substantially perpendicular to the upper surface of the substrate; The channel extends vertically and is positioned adjacent to the gate electrode; A tunnel insulation pattern is disposed on a portion of the outer wall of the trench, said portion of the outer wall of the trench being adjacent to each of the gate electrodes; A charge trapping pattern structure is disposed between each of the gate electrodes and the tunnel insulating pattern, each of the charge trapping pattern structures including an upper charge trapping pattern and a lower charge trapping pattern spaced apart from each other in the vertical direction; as well as A blocking pattern structure is disposed between each charge-trapping pattern structure in the gate electrode. The first portion of the trench adjacent to the tunnel insulation pattern in a horizontal direction that is substantially parallel to the upper surface of the substrate has a thickness in the horizontal direction that is smaller than the thickness of the other portions of the trench that are not adjacent to the tunnel insulation pattern in the horizontal direction.

2. The vertical memory device according to claim 1, wherein, The tunnel insulation pattern includes a protruding portion that protrudes more horizontally toward the adjacent gate electrode than any other portion of the tunnel insulation pattern.

3. The vertical memory device according to claim 2, wherein: The protruding portion of the tunnel insulation pattern is formed on the central portion of the tunnel insulation pattern in the vertical direction, and The upper charge trapping pattern and the lower charge trapping pattern are separated from each other in the vertical direction by protrusions.

4. The vertical memory device according to claim 2, wherein: Each of the blocking pattern structures includes an upper first blocking pattern and a lower first blocking pattern that are spaced apart from each other in the vertical direction; and The upper first blocking pattern and the lower first blocking pattern are spaced apart from each other in the vertical direction by the protrusion.

5. The vertical memory device according to claim 4, wherein, The outer sidewall of each of the upper and lower first blocking patterns has a recessed shape along the horizontal direction.

6. The vertical memory device according to claim 1, wherein: The tunnel insulation pattern comprises a first portion to a third portion sequentially stacked horizontally from the outer wall of the trench, the first portion having a first width in the vertical direction, the second portion having a second width in the vertical direction, and the third portion having a third width in the vertical direction; and The first width is larger than the second width, and the second width is larger than the third width.

7. The vertical memory device according to claim 6, wherein: The inner wall of the first part of the tunnel insulation pattern contacts the trench and extends in the vertical direction; and The third part of the tunnel insulation pattern protrudes horizontally from the second part toward the adjacent gate electrode.

8. The vertical memory device according to claim 1, wherein, The outer walls of each of the upper and lower charge trapping patterns have a recessed shape along the horizontal direction.

9. The vertical memory device according to claim 1, wherein, The tunnel insulation pattern comprises multiple tunnel insulation patterns spaced apart from each other in the vertical direction.

10. The vertical memory device according to claim 9, wherein: The uppermost surface of the tunnel insulation pattern is higher than the uppermost surface of the charge trapping pattern structure and the uppermost surface of the blocking pattern structure corresponding to the tunnel insulation pattern. and The lowest surface of the tunnel insulation pattern is lower than the lowest surface of the charge trapping pattern structure and the blocking pattern structure corresponding to the tunnel insulation pattern.

11. The vertical memory device of claim 1, further comprising: A second blocking pattern covers the upper surface, lower surface, and a sidewall of each of the gate electrodes, wherein the sidewall of the gate electrode is adjacent to the channel. The second blocking pattern is in direct contact with the tunnel insulation pattern and the blocking pattern structure.

12. The vertical memory device according to claim 1, wherein, Each of the gate electrodes has a sidewall adjacent to the channel that is recessed in the horizontal direction.

13. A vertical memory device, the vertical memory device comprising: Gate electrodes are disposed on the substrate and spaced apart from each other in a vertical direction substantially perpendicular to the upper surface of the substrate; The channel extends vertically and is positioned adjacent to the gate electrode. The channel includes a protrusion that protrudes toward each of the gate electrodes in a horizontal direction that is substantially parallel to the upper surface of the substrate. The tunnel insulation pattern is set on the portion of the outer wall of the trench that is horizontally adjacent to each of the grid electrodes and the protrusion of the trench; A charge trapping pattern structure is disposed between each of the gate electrodes and the tunnel insulating pattern, each of the charge trapping pattern structures including an upper charge trapping pattern and a lower charge trapping pattern spaced apart from each other in the vertical direction; as well as A blocking pattern structure is disposed between each charge-trapping pattern structure in the gate electrode. Each of the gate electrodes has a recessed portion along the horizontal direction on its sidewall adjacent to the channel. Each of the blocking pattern structures includes an upper first blocking pattern and a lower first blocking pattern that are spaced apart from each other in the vertical direction.

14. The vertical memory device of claim 13, further comprising: A second blocking pattern covers the upper surface, lower surface, and a sidewall of each of the gate electrodes, wherein the sidewall of the gate electrode is adjacent to the channel. The second blocking pattern is in direct contact with the tunnel insulation pattern and the blocking pattern structure.

15. The vertical memory device according to claim 14, wherein: The upper and lower first blocking patterns are surrounded by a tunnel insulation pattern, a charge trapping pattern structure, and a second blocking pattern.

16. A vertical memory device, the vertical memory device comprising: Gate electrodes are disposed on the substrate and spaced apart from each other in a vertical direction substantially perpendicular to the upper surface of the substrate; The channel extends vertically and is positioned adjacent to the gate electrode. The channel has recesses formed on the outer wall of the channel on each adjacent portion of the gate electrode, the recesses being spaced apart from each other in the vertical direction. The tunnel insulation pattern fills each of the recesses and protrudes toward each of the gate electrodes in a horizontal direction that is substantially parallel to the upper surface of the substrate; A charge trapping pattern structure is disposed between each of the gate electrodes and the tunnel insulating pattern, each of the charge trapping pattern structures including an upper charge trapping pattern and a lower charge trapping pattern spaced apart from each other in the vertical direction; as well as A blocking pattern structure is disposed between each charge-trapping pattern structure in the gate electrode. The first portion of the trench adjacent to the tunnel insulation pattern in a horizontal direction that is substantially parallel to the upper surface of the substrate has a thickness in the horizontal direction that is smaller than the thickness of the other portions of the trench that are not adjacent to the tunnel insulation pattern in the horizontal direction.

17. The vertical memory device according to claim 16, wherein, Tunnel insulation patterns include: The first part is to fill each of the recesses in the channel; The second part is disposed on the first part, and the second part has a second width in the horizontal direction, the second width being smaller than the first width of the first part in the horizontal direction; and The third part is set on top of the second part, and the third part has a third width that is smaller than the second width in the horizontal direction.

18. The vertical memory device according to claim 17, wherein, The upper charge trapping pattern and the lower charge trapping pattern are vertically spaced apart from each other through the third part of the tunnel insulation pattern.

19. The vertical memory device according to claim 16, wherein: The blocking pattern structure includes an upper first blocking pattern and a lower first blocking pattern that are spaced apart from each other in the vertical direction; and The upper first blocking pattern and the lower first blocking pattern are separated from each other by the tunnel insulation pattern.

20. The vertical memory device of claim 16, further comprising: A second blocking pattern covers the upper surface, lower surface, and a sidewall of each of the gate electrodes, wherein the sidewall of the gate electrode is adjacent to the channel. The second blocking pattern is in direct contact with the tunnel insulation pattern and the blocking pattern structure.

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