image sensor

Abstract

An image sensor is provided. The image sensor includes a substrate, a grid structure, and a color filter. The substrate includes a pixel separation structure defining a pixel region and a sub-pixel region for each pixel region. The grid structure is disposed on the substrate and includes a first fence portion disposed between the sub-pixel regions and a second fence portion disposed between adjacent pixel regions. The grid structure defines openings corresponding to the sub-pixel regions, respectively. The color filter is disposed in the openings defined by the grid structure. Each color filter has a planar top surface, the planar top surface of each color filter being parallel to its bottom surface.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0074388, filed on June 21, 2019, with the Korean Intellectual Property Office, and U.S. Patent Application No. 16 / 775,937, filed on January 29, 2020, with the United States Patent and Trademark Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to image sensors and methods of manufacturing the same, and more specifically, to image sensors and methods of manufacturing the same having improved electrical and optical properties. Background Technology

[0003] Image sensors convert photonic images into electrical signals. Recent advancements in the computer and communications industries have created a strong demand for high-performance image sensors in various consumer electronics devices, such as digital cameras, mobile phones, camcorders, personal communication systems (PCS), game controllers, security cameras, and medical miniature cameras. Summary of the Invention

[0004] On the one hand, an image sensor with improved electrical and optical properties is provided.

[0005] The aspects are not limited to those mentioned above, and other aspects not mentioned above will be clearly understood by those skilled in the art from the following description.

[0006] According to one aspect of some example embodiments, an image sensor is provided, the image sensor comprising: a substrate including a pixel separation structure defining a plurality of pixel regions and a plurality of sub-pixel regions for each of the plurality of pixel regions; a mesh structure disposed on the substrate and including a first fence portion disposed between the sub-pixel regions and a second fence portion disposed between adjacent pixel regions, the mesh structure defining a plurality of openings corresponding to the plurality of sub-pixel regions respectively; and a plurality of color filters disposed in the openings defined by the mesh structure, each color filter having a flat top surface parallel to its bottom surface.

[0007] According to another aspect of some example embodiments, an image sensor is provided, the image sensor comprising: a substrate having a first surface and a second surface facing away from the first surface, the substrate including a pixel separation structure defining a plurality of pixel regions; a device isolation layer disposed adjacent to the first surface of the substrate on each of the plurality of pixel regions, the device isolation layer defining an active region in the plurality of pixel regions; a plurality of interlayer dielectric layers stacked on the first surface of the substrate and including contact plugs and interconnects; a fixed charge layer disposed on the second surface of the substrate; a planar dielectric layer disposed on the fixed charge layer; a mesh structure disposed on the planar dielectric layer to be superimposed on the pixel separation structure in a planar view, the mesh structure including fence portions disposed between adjacent pixel regions, the mesh structure defining a plurality of openings respectively corresponding to the plurality of pixel regions; a plurality of color filters disposed in the openings defined by the mesh structure; a sacrificial planarization layer located between adjacent color filters among the plurality of color filters, the sacrificial planarization layer having a top surface coplanar with the uppermost surface of each color filter; and a microlens array disposed on the plurality of color filters.

[0008] According to another aspect of some example embodiments, a method for manufacturing an image sensor is provided, the method comprising the steps of: providing a substrate having a plurality of pixel regions and a plurality of sub-pixel regions for each pixel region; forming a mesh structure on the substrate, the mesh structure including a first fence portion disposed between the sub-pixel regions and a second fence portion disposed between adjacent pixel regions; forming an initial color filter on the pixel regions, the initial color filter filling a space defined by the mesh structure, wherein, in each pixel region, a corresponding initial color filter covers the first fence portion of the mesh structure in the pixel region; forming a sacrificial planarization layer to cover the top surface of the initial color filter; and performing a planarization process on the sacrificial planarization layer to form a color filter on the pixel regions, the color filter having a flat top surface parallel to its bottom surface after the planarization process. Attached Figure Description

[0009] Figure 1 A simplified plan view of an image sensor according to some example embodiments is shown;

[0010] Figure 2A and Figure 2B A circuit diagram showing an active pixel sensor array of an image sensor according to some example embodiments is shown;

[0011] Figure 3 A simplified plan view is shown, illustrating an active pixel sensor array of an image sensor according to some example embodiments;

[0012] Figure 4A A plan view showing an image sensor according to some example embodiments is shown;

[0013] Figure 4B It shows along Figure 4A The image sensor cut off by line I-I' is shown as a cross-sectional view according to some example embodiments;

[0014] Figures 5A to 5C The display shows Figure 4B An enlarged view of section A;

[0015] Figure 6 It shows along Figure 4A The image sensor cut off by line I-I' is shown as a cross-sectional view according to some example embodiments;

[0016] Figure 7A and Figure 7B The display shows Figure 6 An enlarged view of section B;

[0017] Figure 8 It shows along Figure 4A The image sensor cut off by line I-I' is shown as a cross-sectional view according to some example embodiments;

[0018] Figure 9A and Figure 9B The display shows Figure 8 An enlarged view of section C;

[0019] Figure 10A It shows along Figure 4A The image sensor cut off by line I-I' is shown as a cross-sectional view according to some example embodiments;

[0020] Figure 10B The display shows Figure 10A An enlarged view of section D;

[0021] Figure 11 A cross-sectional view showing an image sensor according to some example embodiments is shown;

[0022] Figure 12A A plan view showing an image sensor according to some example embodiments is shown;

[0023] Figure 12B It shows along Figure 12A The image sensor cut off by line II-II' is shown as a cross-sectional view according to some example embodiments;

[0024] Figure 13 A circuit diagram showing an active pixel sensor array of an image sensor according to some example embodiments is shown;

[0025] Figure 14 A block diagram illustrating an image sensor according to some example embodiments is shown;

[0026] Figure 15 A cross-sectional view showing an image sensor according to some example embodiments is shown;

[0027] Figures 16A to 16H It shows along Figure 4A A cross-sectional view showing a method of manufacturing an image sensor according to some example embodiments, taken by line I-I'; and

[0028] Figures 17A to 17D It shows along Figure 4A The line I-I' cuts out a cross-sectional view of a method for manufacturing an image sensor according to some example embodiments. Detailed Implementation

[0029] An image sensor and its manufacturing method according to some example embodiments will be discussed in conjunction with the accompanying drawings.

[0030] Figure 1 A simplified plan view of an image sensor according to some example embodiments is shown.

[0031] Reference Figure 1 An image sensor may include a pixel array area R1 and a pad (also known as a solder pad) area R2.

[0032] Multiple unit pixels P can be arranged two-dimensionally along the row and column directions on the pixel array region R1. Each unit pixel P in the pixel array region R1 can output an electrical signal converted from the incident light. The pixel array region R1 may include a central region (see...). Figure 11 The CR) and the peripheral regions surrounding the central region CR (see Figure 11 (ER). For example, when viewed in a plane, the edge region ER can be positioned on the top, bottom, left, and right sides of the central region CR. The pad region R2 can include multiple conductive pads CP for input and output control signals and photoelectric conversion signals. For easy connection to external devices, when viewed in a plane, the pad region R2 can surround the pixel array region R1.

[0033] Figure 2A and Figure 2B A circuit diagram showing an active pixel sensor array of an image sensor according to some example embodiments is shown.

[0034] Reference Figure 2AAn active pixel sensor array may include multiple unit pixels P. Each unit pixel P may include a first photoelectric conversion element PD1 and a second photoelectric conversion element PD2, a first transmission transistor TX1 and a second transmission transistor TX2, and logic transistors RX, SX, and AX. Logic transistors RX, SX, and AX may include a reset transistor RX, a select transistor SX, and an amplifier transistor AX. The gate electrodes of the first transmission transistor TX1, the second transmission transistor TX2, the reset transistor RX, and the select transistor SX may be respectively connected to drive signal lines TG1, TG2, RG, and SG.

[0035] The first transmission transistor TX1 may include a first transmission gate electrode connected to the drive signal line TG1. The first transmission transistor TX1 may be connected to the first photoelectric conversion element PD1. The second transmission transistor TX2 may include a second transmission gate electrode connected to the drive signal line TG2. The second transmission transistor TX2 may be connected to the second photoelectric conversion element PD2. The first transmission transistor TX1 and the second transmission transistor TX2 may share a charge detection node FD (i.e., the floating diffusion region).

[0036] The first photoelectric conversion element PD1 and the second photoelectric conversion element PD2 can generate and accumulate photocharge proportional to the amount of externally incident light on them. The first and second transfer gate electrodes can transfer the charge accumulated in the first and second photoelectric conversion elements PD1 and PD2 to the charge detection node FD (i.e., the floating diffusion region). The first and second transfer gate electrodes can receive complementary signals. For example, charge can be transferred from one of the first and second photoelectric conversion elements PD1 and PD2 to the charge detection node FD. At a later time, charge can be transferred from the other of the first and second photoelectric conversion elements PD1 and PD2 to the charge detection node FD.

[0037] The charge detection node FD can receive and accumulate the charge generated from the first photoelectric conversion element PD1 and the second photoelectric conversion element PD2. The amplifier transistor AX can be controlled by the amount of photocharge accumulated in the charge detection node FD.

[0038] The reset transistor RX can periodically reset the accumulated charge in the charge detection node FD. For example, the reset transistor RX can have a drain electrode connected to the charge detection node FD and a power supply voltage V. DD The source electrode of the reset transistor RX. When the reset transistor RX is turned on, the charge detection node FD can receive the power supply voltage V connected to the source electrode of the reset transistor RX. DDTherefore, when the reset transistor RX is turned on, the charge accumulated in the charge detection node FD will be depleted, and thus the charge detection node FD can be reset.

[0039] The amplifier transistor AX amplifies the potential change at the charge detection node FD, and the amplified signal or pixel signal can be output to the output line V by selecting the transistor SX. OUT The amplifier transistor AX can be a source follower buffer amplifier, configured to generate a source-drain current proportional to the amount of photocharge applied to the gate electrode. The amplifier transistor AX can have a gate electrode connected to the charge detection node FD and connected to the supply voltage V. DD The drain electrode and the source electrode connected to the drain electrode of the select transistor SX.

[0040] The selector transistor SX selects the unit pixel P of each row to be read. When the selector transistor SX is turned on, the power supply voltage V connected to the drain electrode of the amplifier transistor AX is... DD It can be transferred to the drain electrode of the select transistor SX.

[0041] Reference Figure 2B An active pixel sensor array can include multiple unit pixels P, and each unit pixel P can include four photoelectric conversion elements PD1, PD2, PD3, and PD4, and four transmission transistors TX1, TX2, TX3, and TX4. The four transmission transistors TX1, TX2, TX3, and TX4 can share a charge detection node FD and logic transistors RX, SX, and AX. Figure 2B In the example embodiment shown, charge can be transferred from one of the four photoelectric conversion elements PD1, PD2, PD3 and PD4 to the charge detection node FD based on the signals applied to the four transmission transistors TX1, TX2, TX3 and TX4.

[0042] Figure 3 A simplified plan view is shown, illustrating an active pixel sensor array of an image sensor according to some example embodiments.

[0043] Reference Figure 3 The active pixel sensor array may include a plurality of pixel regions P1, P2, and P3 arranged in a matrix shape along a first direction D1 and a second direction D2. The plurality of pixel regions P1, P2, and P3 may include a first pixel region P1, a second pixel region P2, and a third pixel region P3. Each of the first pixel region P1, the second pixel region P2, and the third pixel region P3 can receive light whose wavelength is different from the wavelength of light incident on the other pixel regions in the first pixel region P1, the second pixel region P2, and the third pixel region P3.

[0044] In some example embodiments, the number of first pixel regions P1 can be twice the number of second pixel regions P2 or the number of third pixel regions P3. The first pixel regions P1 can be arranged diagonally, and the second and third pixel regions P2 can also be arranged diagonally. Figure 3 As shown, each first pixel region P1 can be disposed between second pixel regions P2 in the first direction D1 (or in the second direction D2) and between third pixel regions P3 in the second direction D2 (or in the first direction D1).

[0045] Each of the first pixel region P1, the second pixel region P2, and the third pixel region P3 may include multiple sub-pixel regions PG1 / PG2, PB, or PR. For example, each of the first pixel region P1, the second pixel region P2, and the third pixel region P3 may include multiple sub-pixel regions PG1 / PG2, PB, or PR arranged in a 2×2 quadruple matrix shape. Specifically, in some example embodiments, each first pixel region P1 may include multiple first sub-pixel regions PG1 or PG2, each second pixel region P2 may include multiple second sub-pixel regions PR, and each third pixel region P3 may include multiple third sub-pixel regions PB.

[0046] The first sub-pixel region PG1 / PG2 can receive light with a first wavelength, the second sub-pixel region PR can receive light with a second wavelength, which is longer than the first wavelength. The third sub-pixel region PB can receive light with a third wavelength, which is shorter than the first wavelength. For example, green light can be incident on the first sub-pixel region PG1 / PG2, red light can be incident on the second sub-pixel region PR, and blue light can be incident on the third sub-pixel region PB.

[0047] In some example embodiments, each of the first sub-pixel region PG1 / PG2, the second sub-pixel region PR, and the third sub-pixel region PB may include the above reference. Figure 2A or Figure 2B The photoelectric conversion element and transmission transistor discussed. For example, each of the first sub-pixel regions PG1 / PG2, the second sub-pixel region PR, and the third sub-pixel region PB may include a reference. Figure 2A or Figure 2B The unit of discussion is pixels.

[0048] Figure 4A A plan view showing an image sensor according to some example embodiments is shown. Figure 4B It shows along Figure 4A The line I-I' shows a cross-sectional view of an image sensor according to some example embodiments. Figures 5A to 5C The display shows Figure 4B An enlarged view of section A.

[0049] Reference Figure 4A and Figure 4B An image sensor according to some example embodiments may include a semiconductor substrate 100. The semiconductor substrate 100 may have a first surface 100a and a second surface 100b facing away from each other. A photoelectric conversion region 110 may be disposed on the semiconductor substrate 100. A readout circuit layer may be disposed on the first surface 100a (or front surface) of the semiconductor substrate 100, and a light-transmitting layer may be disposed on the second surface 100b (or rear surface) of the semiconductor substrate 100.

[0050] The semiconductor substrate 100 may be a first conductivity type (e.g., p-type) bulk silicon substrate on which an epitaxial layer having a first conductivity type is formed. Optionally, the semiconductor substrate 100 may be a p-type epitaxial layer retained after the bulk silicon substrate is removed in a manufacturing process for an image sensor. Optionally, the semiconductor substrate 100 may be a bulk semiconductor substrate including a first conductivity type well.

[0051] As mentioned above, refer to... Figure 3 The semiconductor substrate 100 discussed may include a first pixel region P1, a second pixel region P2, and a third pixel region P3 arranged in a quaternion matrix, and each of the first pixel region P1, the second pixel region P2, and the third pixel region P3 may receive light whose wavelength is different from that of light incident on the other pixel regions in the first pixel region P1, the second pixel region P2, and the third pixel region P3.

[0052] As discussed above, the first pixel region P1, the second pixel region P2, and the third pixel region P3 can each include multiple corresponding sub-pixel regions PG1 / PG2, PR, and PB. Each first pixel region P1 may include multiple first sub-pixel regions PG1 or PG2, and each second pixel region P2 may include multiple second sub-pixel regions PR. Each third pixel region P3 may include multiple third sub-pixel regions PB. The respective sub-pixel regions PG1 / PG2, PR, and PB of the first pixel region P1, the second pixel region P2, and the third pixel region P3 can have the same size and can be defined by the pixel separation structure 103. For example, as Figure 4A and Figure 4B As shown, at least two first sub-pixel regions PG1 can be set between adjacent second sub-pixel regions PR.

[0053] The pixel separation structure 103 can extend vertically from the first surface 100a of the semiconductor substrate 100 to the second surface 100b. The pixel separation structure 103 can penetrate the semiconductor substrate 100. In this case, the pixel separation structure 103 can have a vertical thickness substantially the same as the vertical thickness of the semiconductor substrate 100. Optionally, in some example embodiments, the pixel separation structure 103 can extend vertically from the first surface 100a of the semiconductor substrate 100 toward but not to the second surface 100b.

[0054] In some example embodiments, such as Figure 4B As shown, the pixel separation structure 103 may have a first width adjacent to a first surface 100a of the semiconductor substrate 100 and a second width smaller than the first width adjacent to a second surface 100b of the semiconductor substrate 100. The pixel separation structure 103 may have a width that gradually decreases from the first surface 100a to the second surface 100b of the semiconductor substrate 100. Optionally, in some example embodiments, the pixel separation structure 103 may have a uniform width and may penetrate the semiconductor substrate 100.

[0055] When viewed in a two-dimensional plane, such as Figure 4A As shown, the pixel separation structure 103 may surround each of the first sub-pixel regions PG1 / PG2, the second sub-pixel region PR, and the third sub-pixel region PB. For example, the pixel separation structure 103 may include a first portion 103a that extends parallel to each other along a first direction D1 and is spaced apart from each other in a second direction D2, and a second portion 103b that extends parallel to each other along the second direction D2, intersects the first portion 103a, and is spaced apart from each other in the first direction D1.

[0056] In some example embodiments, each of the first sub-pixel regions PG1 / PG2, the second sub-pixel region PR, and the third sub-pixel region PB may have a width corresponding to the spacing between adjacent first portions 103a and / or the spacing between adjacent second portions 103b. The first portions 103a of the pixel separation structure 103 may have a spacing, for example, in the range of approximately 50 μm to approximately 100 μm. For example, the first portions 103a of the pixel separation structure 103 may have a spacing of approximately 70 μm.

[0057] The pixel separation structure 103 can be formed of a dielectric material with a refractive index lower than that of the semiconductor substrate 100, and can include a single dielectric layer or multiple dielectric layers. For example, the semiconductor substrate 100 can be silicon. For example, the pixel separation structure 103 can be formed of a silicon oxide layer, a silicon nitride layer, an undoped polysilicon layer, air, or a combination thereof. The pixel separation structure 103 can prevent crosstalk between adjacent sub-pixel regions in the first sub-pixel region PG1 / PG2, the second sub-pixel region PR, and the third sub-pixel region PB.

[0058] The photoelectric conversion region 110 can be correspondingly disposed on the first sub-pixel region PG1 / PG2, the second sub-pixel region PR, and the third sub-pixel region PB. The photoelectric conversion region 110 can be formed by implanting an impurity with a second conductivity type opposite to that of the semiconductor substrate 100 into the semiconductor substrate 100. A photodiode can be formed at the junction between the semiconductor substrate 100 having the first conductivity type and the photoelectric conversion region 110 having the second conductivity type. The photoelectric conversion region 110 can generate photocharge proportional to the amplitude of the incident light.

[0059] In some example embodiments, each photoelectric conversion region 110 may have a difference in impurity concentration between the portion adjacent to the first surface 100a and the portion adjacent to the second surface 100b, such that a potential slope can be provided between the first surface 100a and the second surface 100b of the semiconductor substrate 100. For example, each photoelectric conversion region 110 may include a plurality of vertically stacked impurity portions.

[0060] The device isolation layer 101 can be configured to be adjacent to the first surface 100a of the semiconductor substrate 100 on each of the first sub-pixel regions PG1 / PG2, the second sub-pixel region PR, and the third sub-pixel region PB. The device isolation layer 101 can define an active region of the semiconductor substrate 100.

[0061] The readout circuit may be disposed on a first surface 100a of the semiconductor substrate 100. The readout circuit may include a reference... Figure 2A and Figure 2B The MOS transistor under discussion. On each of the sub-pixel regions PG1 / PG2, PR, and PB, a transfer gate electrode TG can be disposed on the first surface 100a of the semiconductor substrate 100, and refer to... Figure 2A and Figure 2B The readout circuit discussed can also be disposed on the first surface 100a of the semiconductor substrate 100.

[0062] When viewed in a plane, the transfer gate electrode TG can be disposed on the central portion of each of the sub-pixel regions PG1 / PG2, PR, and PB. A portion of the transfer gate electrode TG can be disposed within the semiconductor substrate 100, and a gate dielectric layer can be interposed between the transfer gate electrode TG and the semiconductor substrate 100. A floating diffusion region FD can be disposed on one side of the transfer gate electrode TG within the semiconductor substrate 100. The floating diffusion region FD can be formed by implanting an impurity into the semiconductor substrate 100 using an impurity of a conductivity type opposite to that of the semiconductor substrate 100. For example, the floating diffusion region FD can be an n-type impurity region.

[0063] Interlayer dielectric layers 211, 213, and 215 may be stacked on the first surface 100a of the semiconductor substrate 100, and may cover the transfer gate electrode TG and MOS transistor constituting the readout circuit. Interlayer dielectric layers 211, 213, and 215 may include one or more of, for example, silicon oxide, silicon nitride, and silicon oxynitride. Connection lines CL may be disposed on each interlayer dielectric layer 211, 213, and 215, and may be electrically connected to the readout circuit via contact plugs CT.

[0064] A fixed charge layer 300 may be disposed on a second surface 100b of a semiconductor substrate 100. The fixed charge layer 300 prevents the photoelectric conversion region 110 from receiving charges (e.g., electrons or holes) generated from defects present on the second surface 100b of the semiconductor substrate 100. The fixed charge layer 300 may comprise a single layer or multiple layers. For example, the fixed charge layer 300 may comprise a metal oxide or a metal fluoride, the metal oxide or metal fluoride comprising at least one metal selected from the group consisting of hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), yttrium (Y), and lanthanides (Ln). For example, the fixed charge layer 300 may comprise one or more layers of aluminum oxide and hafnium oxide. The fixed charge layer 300 may have a thickness in the range of about 1 nm to about 50 nm.

[0065] A planar dielectric layer 310 may be disposed on the fixed charge layer 300. The planar dielectric layer 310 may include a first planar layer 311, a second planar layer 313, and a third planar layer 315 stacked in sequence (see...). Figure 5AThe first planarization layer 311, the second planarization layer 313, and the third planarization layer 315 may comprise a transparent dielectric material. The first planarization layer 311, the second planarization layer 313, and the third planarization layer 315 may have different refractive indices than each other. The first planarization layer 311, the second planarization layer 313, and the third planarization layer 315 may be combined with each other to have an appropriate thickness, resulting in a high refractive index. For example, the first planarization layer 311 may be thicker than the fixed charge layer 300. The second planarization layer 313 may be thicker than the first planarization layer 311. The third planarization layer 315 may be thinner than the second planarization layer 313.

[0066] The first planarization layer 311 and the third planarization layer 315 may have the same refractive index, while the second planarization layer 313 may have a different refractive index than the first planarization layer 311 and the third planarization layer 315. For example, the first planarization layer 311 and the third planarization layer 315 may comprise metal oxides, while the second planarization layer 313 may comprise silicon oxide.

[0067] The mesh structure 320 can be disposed on the planar dielectric layer 310. Similar to the pixel separation structure 103, the mesh structure 320 can have a mesh shape when viewed in a plane. When viewed in a plane, the mesh structure 320 can be superimposed on the pixel separation structure 103. For example, the mesh structure 320 may include a first portion extending in a first direction D1 and a second portion extending in a second direction D2 and intersecting the first portion. The mesh structure 320 can be disposed between the photoelectric conversion regions 110 of the sub-pixel regions PG1 / PG2, PR, and PB. Figure 4B As shown, the grid structure 320 may have a width that is substantially the same as the minimum width of the pixel separation structure 103, or it may have a width that is smaller than the minimum width of the pixel separation structure 103.

[0068] The mesh structure 320 can refract light incident obliquely through the microlens 353, and then allow the refracted light to enter the photoelectric conversion regions 110 of the sub-pixel regions PG1 / PG2, PR, and PB. The mesh structure 320 can have an aspect ratio in the range of approximately 2:1 to approximately 5:1. up to approximately The height is within a certain range. The width of the mesh structure 320 can be in the range of approximately 50 nm to approximately 150 nm.

[0069] The mesh structure 320 may include a light-shielding pattern 322 and a low-refractive-index pattern 324 sequentially stacked on the flat dielectric layer 310. The light-shielding pattern 322 may be disposed between the low-refractive-index pattern 324 and the flat dielectric layer 310. The light-shielding pattern 322 may include a metallic material, such as titanium, tantalum, or tungsten.

[0070] The low-refractive-index pattern 324 may comprise a material whose refractive index is lower than that of the color filters 345a and 345b. The low-refractive-index pattern 324 may comprise an organic material and may have a refractive index in the range of approximately 1.1 to approximately 1.3. For example, the mesh structure 320 may be a polymer layer comprising silica nanoparticles. Because the low-refractive-index pattern 324 has a low refractive index, it is possible to increase the amount of light incident on the photoelectric conversion region 110 and reduce crosstalk between sub-pixel regions PG1 / PG2, PR, and PB. In this configuration, each photoelectric conversion region 110 can improve light receiving efficiency and enhance the signal-to-noise ratio (SNR).

[0071] A protective layer 330 may be disposed on the planar dielectric layer 310, thereby covering the planar dielectric layer 310 and the surface of the grid structure 320 located on the planar dielectric layer 310 with a substantially uniform thickness. For example, the protective layer 330 may extend from the space between the sidewall of any of the color filters 345a and 345b and the sidewall of the grid structure 320 toward the space between the planar dielectric layer 310 and the bottom surface of any of the color filters 345a and 345b.

[0072] The protective layer 330 may be a single layer or multiple layers comprising one or more of, for example, alumina and silicon carbide. In some example embodiments, the protective layer 330 may have a depth of approximately [missing information]. up to approximately The thickness is within a certain range. The protective layer 330 can protect the color filters 345a and 345b and can also be used to absorb moisture. In some example embodiments, the protective layer 330 can be formed to have a thickness of approximately... up to approximately The thickness is such that it will not affect the path of light incident on the sub-pixel regions PG1 / PG2, PR and PB.

[0073] In some example embodiments, the mesh structure 320 may have openings O, each opening O being defined by a pair of first portions of the mesh structure 320 extending in a first direction D1 and by a pair of second portions of the mesh structure 320 extending in a second direction D2, and the openings O may be superimposed with the photoelectric conversion regions 110 of the sub-pixel regions PG1 / PG2, PR and PB.

[0074] Color filters 345a and 345b can be disposed within the opening defined by the grid structure 320. For example, the first color filter 345a can be disposed on the corresponding first sub-pixel region PG1 / PG2 of the first pixel region P1, and the second color filter 345b can be disposed on the corresponding second sub-pixel region PR of the second pixel region P2. Similarly, the third color filter ( Figure 4B (Not shown in the image) can be set in the third pixel area (see...) Figure 3The first color filter 345a, the second color filter 345b, and the third color filter may each include a green color filter, a red color filter, and a blue color filter, respectively. Optionally, the first color filter 345a, the second color filter 345b, and the third color filter may each include a magenta color filter, a yellow color filter, and a cyan color filter, respectively. Although three types of color filters are provided as mentioned above, in some example embodiments, four types of color filters may be provided.

[0075] In some example embodiments, such as Figure 4B As shown, at least two first color filters 345a can be disposed between adjacent second color filters 345b. The grid structure 320 may include a first fence portion FS1 disposed between sub-pixel regions PG1 / PG2, PR, and PB of pixel regions P1, P2, and P3, and may also include a second fence portion FS2 disposed between different pixel regions P1, P2, and P3. For example, the first fence portion FS1 of the grid structure 320 may be disposed between color filters 345a or 345b whose colors are the same as each other, while the second fence portion FS2 of the grid structure 320 may be disposed between color filters 345a and 345b whose colors are different from each other.

[0076] Each of the color filters 345a and 345b may have a first sidewall S1 adjacent to the first fence portion FS1 of the grid structure 320 and a second sidewall S2 adjacent to the second fence portion FS2 of the grid structure 320. The first sidewall S1 may have a height H1 that is substantially the same as the height H2 of the second sidewall S2. For example, the difference between the first height H1 of the first sidewall S1 and the second height H2 of the second sidewall S2 may be approximately up to approximately Within the range. Each of the color filters 345a and 345b may have a substantially flat top surface, and the top surfaces of the color filters 345a and 345b may be parallel to the bottom surfaces of the color filters 345a and 345b.

[0077] Reference Figure 4B and Figure 5A The protective layer 330 may cover the top surface of the grid structure 320, and the top surfaces of the color filters 345a and 345b may be substantially coplanar with the top surface of the protective layer 330 located on the top surface of the grid structure 320. For example, the top surface of the grid structure 320 may be positioned at a level substantially the same as the level of the top surface of the protective layer 330. (Refer to...) Figure 5B The top surfaces of color filters 345a and 345b can be positioned at a level lower than the top surface of the grid structure 320. (Refer to...) Figure 5CThe protective pattern 331 can directly cover the sidewalls of the grid structure 320 and the bottom surfaces of the color filters 345a and 345b. That is, unlike the protective pattern 330, in some example embodiments, the protective pattern 331 may not be positioned along the top surface of the grid structure 320. The top surface of the protective pattern 331 can be positioned at a level substantially the same as the top surface of the grid structure 320, while the top surfaces of the color filters 345a and 345b can be positioned at a level lower than the top surface of the grid structure 320.

[0078] Return to reference Figure 4A and Figure 4B The microlens array 350 can be disposed on a color filter array including a first color filter 345a, a second color filter 345b, and a third color filter. The microlens array 350 may include a flat portion 351 adjacent to the color filters 345a and 345b, and may also include microlenses 353 located on the flat portion 351 corresponding to the sub-pixel regions PG1 / PG2, PR, and PB.

[0079] Because the first color filter 345a, the second color filter 345b, and the third color filter have substantially flat top surfaces, the flat portion 351 can have a substantially uniform thickness on the top surfaces of the first color filter 345a, the second color filter 345b, and the third color filter. For example, the flat portion 351 can have substantially the same thickness on the first sidewall S1 and the second sidewall S2 of each of the color filters 345a and 345b. Microlenses 353 can be correspondingly disposed on the sub-pixel regions PG1 / PG2, PR, and PB, and can all have an upwardly convex shape. In some example embodiments, because the flat portion 351 has a reduced thickness distribution with respect to the microlens array 350, it is possible to improve light collection efficiency through the microlenses 353.

[0080] The passivation layer 360 can conformally cover the top surface of the microlens array 350. The passivation layer 360 can be formed of, for example, inorganic oxides.

[0081] In the following description, for the sake of brevity, features that are the same as those of the image sensors discussed above may be omitted in some cases.

[0082] Figure 6 It shows along Figure 4A The line I-I' shows a cross-sectional view of an image sensor according to some example embodiments. Figure 7A and Figure 7B The display shows Figure 6 An enlarged view of section B.

[0083] Reference Figure 6 , Figure 7A and Figure 7BAs discussed above, each of the color filters 345a and 345b can have a substantially flat top surface. Furthermore, as... Figure 6 As shown, the top surfaces of color filters 345a and 345b can be positioned at a level higher than the level of the top surface of the mesh structure 320. The mesh structure 320 can have a height smaller than the thickness of the color filters 345a and 345b. The thickness of each of the color filters 345a and 345b located on the flat dielectric layer 310 can be different from the thickness of each of the color filters 345a and 345b located on the mesh structure 320.

[0084] A first color filter 345a may be disposed on a first pixel region P1 and on a plurality of first sub-pixel regions PG1. The first color filter 345a may be connected or continuous on a first fence portion FS1 of the grid structure 320, which is disposed between the first sub-pixel regions PG1. For example, on each first sub-pixel region PG1, the first color filter 345a may cover the grid structure 320 (e.g., see...). Figure 6 The top surface of the first fence portion FS1 of the intermediate grid structure 320. Even if each of the color filters 345a and 345b covers the first fence portion FS1 of the grid structure 320, the height difference between the first sidewall S1 adjacent to the first fence portion FS1 of the grid structure 320 and the second sidewall S2 adjacent to the second fence portion FS2 of the grid structure 320 can be approximately up to approximately The range.

[0085] Reference Figure 7A The grid structure 320 may include sequentially stacked light-shielding patterns 322 and low-refractive-index patterns 324. The low-refractive-index pattern 324 may have a refractive index of approximately... up to approximately Within a range (e.g., in approximately) up to approximately The height of the color filters 345a and 345b can be within a range of approximately [missing information]. up to approximately Thickness within the specified range. (Refer to...) Figure 7B In some exemplary embodiments, the mesh structure 320 may include a metallic material and has approximately up to approximately The height within the range.

[0086] Figure 8 It shows along Figure 4A The line I-I' shows a cross-sectional view of an image sensor according to some example embodiments. Figure 9A and Figure 9B The display shows Figure 8An enlarged view of section C.

[0087] Reference Figure 8 Each of the color filters 345a and 345b may have different thicknesses at portions adjacent to the first fence portion FS1 and the second fence portion FS2 of the grid structure 320, respectively. In other words, as Figure 8 As shown, the thickness t1 of each of the color filters 345a and 345b adjacent to the first fence portion FS1 can be greater than the thickness t2 of each of the color filters 345a and 345b adjacent to the second fence portion FS2. A sacrificial planarization layer 355 can be partially retained between the adjacent first color filters 345a and second color filters 345b. The sacrificial planarization layer 355 can have a top surface substantially coplanar with the uppermost surfaces of the first color filters 345a and second color filters 345b.

[0088] Reference Figure 9A In some example embodiments, each of the color filters 345a and 345b may have a minimum thickness and a maximum thickness both greater than the height of the grid structure 320. Each of the color filters 345a and 345b may have a maximum thickness at a portion adjacent to the first fence portion FS1 of the grid structure 320a, and a minimum thickness at a portion adjacent to the second fence portion FS2 of the grid structure 320b. The difference between the maximum thickness and the minimum thickness of each of the color filters 345a and 345b may be approximately... up to approximately Within the range.

[0089] Reference Figure 9B In some example embodiments, each of the color filters 345a and 345b may have an uppermost surface at a level substantially the same as the top surface of the protective layer 330 covering the top surfaces of the mesh structures 320a and 320b. In this configuration, the minimum thickness of each of the color filters 345a and 345b may be less than the height of the mesh structures 320a and 320b.

[0090] Figure 10A It shows along Figure 4A The line I-I' shows a cross-sectional view of an image sensor according to some example embodiments. Figure 10B The display shows Figure 10A An enlarged view of section D.

[0091] Reference Figure 10A and Figure 10B The planar dielectric layer 310 may be disposed on the second surface 100b of the semiconductor substrate 100, and the mesh structure 320 may have a lower portion located within the planar dielectric layer 310. For example, the lower portion of the mesh structure 320 may penetrate the planar dielectric layer 310.

[0092] A fixed charge layer 300 may be disposed between the planar dielectric layer 310 and the second surface 100b of the semiconductor substrate 100, and the mesh structure 320 may have a bottom surface in contact with the fixed charge layer 300. Optionally, in some example embodiments, the bottom surface of the mesh structure 320 may be in contact with the pixel separation structure 103. The planar dielectric layer 310 may include a first planar layer 311 and a second planar layer 313 stacked in sequence. The first planar layer 311 and the second planar layer 313 may have different refractive indices and different thicknesses.

[0093] The mesh structure 320 may include a material whose refractive index is lower than that of the semiconductor substrate 100. For example, the semiconductor substrate 100 may be, for example, silicon. For example, the mesh structure 320 may be formed of a low refractive index material whose refractive index is about 1.3 or less. For example, the mesh structure 320 may be a polymer layer comprising silicon dioxide nanoparticles.

[0094] Figure 11 A cross-sectional view showing an image sensor according to some example embodiments is shown.

[0095] Reference Figure 11 As shown above Figure 1 The semiconductor substrate 100 discussed may include a pixel array region R1 and a pad region R2 surrounding the pixel array region R1, and the pixel array region R1 may include a central region CR and an edge region ER surrounding the central region CR and adjacent to the pad region R2.

[0096] Color filters 345a and 345b can have a substantially flat top surface in the central region CR and the edge region ER. For example... Figure 11 As shown, color filters 345a and 345b can have a relatively small thickness in the edge region ER and a relatively large thickness in the central region CR. For example, in the central region CR, the top surfaces of color filters 345a and 345b can be positioned at a level substantially the same as the top surface of the protective layer 330, and in the edge region ER, the top surfaces of color filters 345a and 345b can be positioned at a level lower than the top surface of the mesh structure 320.

[0097] In pad region R2, a through-hole plug TPLG can be configured to penetrate the semiconductor substrate 100, and a sidewall dielectric layer SS can surround the sidewall of the through-hole plug TPLG. In pad region R2, a connection line CL can be disposed on a first surface 100a of the semiconductor substrate 100, and a conductive pad CP can be disposed on a second surface 100b of the semiconductor substrate 100. The connection line CL in pad region R2 can be connected to the connection line CL in pixel array region R1. The through-hole plug TPLG can electrically connect the connection line CL to the conductive pad CP.

[0098] Figure 12A A plan view showing an image sensor according to some example embodiments is shown. Figure 12B It shows along Figure 12A The line II-II' cuts out a cross-sectional view of an image sensor according to some example embodiments.

[0099] Reference Figure 12A and Figure 12B The above reference Figure 3 Each of the first pixel region P1, the second pixel region P2, and the third pixel region P3 discussed may include corresponding sub-pixel regions in sub-pixel regions PG1 / PG2, PR, and PB, which are arranged in a 3×3 matrix shape. For example, at least three first sub-pixel regions PG1 / PG2 may be set between adjacent second sub-pixel regions PR.

[0100] The grid structure 320 may include a first fence portion FS1 disposed between sub-pixel regions PG1 / PG2, PR, and PB, and may also include a second fence portion FS2 disposed between pixel regions P1, P2, and P3. In this configuration, at least two first fence portions FS1 may be disposed between the second fence portions FS2 that are spaced apart from each other.

[0101] As discussed above, color filters 345a and 345b can fill the opening defined by the grid structure 320, and each of the color filters 345a and 345b can have a substantially flat surface.

[0102] Figure 13 A circuit diagram showing an active pixel sensor array of an image sensor according to some example embodiments is shown.

[0103] Reference Figure 13 Each unit pixel P may include a photoelectric conversion element PD1, an organic photoelectric conversion element OPD, a first transmission transistor TX1 and a second transmission transistor TX2, and readout transistors RX, SX, and AX. (See reference...) Figure 2A The readout transistors discussed may include a reset transistor RX, an amplifier transistor AX, and a select transistor SX.

[0104] The first transfer transistor TX1 can be connected to the photoelectric conversion element PD1, and the second transfer transistor TX2 can be connected to the organic photoelectric conversion element OPD. The first transfer transistor TX1 and the second transfer transistor TX2 can share the charge detection node FD (i.e., the floating diffusion region).

[0105] Photoelectric conversion element PD1 and organic photoelectric conversion element OPD can generate and accumulate photocharge proportional to the amount of externally incident light. In some example embodiments, photoelectric conversion element PD1 can be a photodiode, phototransistor, grating, pinned photodiode (PPD), and combinations thereof. Organic photoelectric conversion element OPD can include an organic photoelectric conversion layer. The organic photoelectric conversion layer can generate photocharge (electron-hole pairs) proportional to incident light having a specific wavelength band. A voltage difference applied to opposite ends of organic photoelectric conversion element OPD can cause charge detection node FD to store photocharge generated from the organic photoelectric conversion layer.

[0106] The first transfer transistor TX1 and the second transfer transistor TX2 can transfer the charge accumulated in the photoelectric conversion element PD1 and the organic photoelectric conversion element OPD to the charge detection node FD. The first transfer transistor TX1 and the second transfer transistor TX2 can be controlled by a charge transfer signal provided through the first charge transfer line TG1 and the second charge transfer line TG2, and according to the charge transfer signal applied to the first transfer transistor TX1 and the second transfer transistor TX2, charge can be transferred from either the photoelectric conversion element PD1 or the organic photoelectric conversion element OPD to the charge detection node FD. Specifically, when the voltage V... PIX When an electron or hole is applied to one of the terminals of an organic photoelectric conversion element (OPD) and a charge transfer signal is applied to a second transfer transistor (TX2), the generated electrons or holes can be transferred to the charge detection node (FD) and accumulated in the charge detection node (FD).

[0107] Figure 14 A block diagram showing an image sensor according to some example embodiments is shown.

[0108] Reference Figure 14The image sensor may include a plurality of unit pixels P arranged two-dimensionally along a first direction D1 and a second direction D2 intersecting the first direction D1. Each unit pixel P of the image sensor may have a structure in which at least two photoelectric conversion elements are stacked on a third direction D3 perpendicular to the first direction D1 and the second direction D2. Each unit pixel P may include one of a first photoelectric conversion element PD1 and a second photoelectric conversion element PD2, one of a first color filter CF1 and a second color filter CF2, and an organic photoelectric conversion element OPD. For example, a unit pixel P may include a first photoelectric conversion element PD1, a first color filter CF1, and an organic photoelectric conversion element OPD, while another unit pixel P may include a second photoelectric conversion element PD2, a second color filter CF2, and an organic photoelectric conversion element OPD, and so on.

[0109] The first photoelectric conversion element PD1 and the second photoelectric conversion element PD2 can be disposed in a semiconductor substrate and can be arranged in a matrix shape. The first photoelectric conversion element PD1 and the second photoelectric conversion element PD2 can be arranged in a zigzag pattern.

[0110] like Figure 14 As shown, the organic photoelectric conversion element (OPD) can be stacked correspondingly on the first photoelectric conversion element (PD1) and the second photoelectric conversion element (PD2). For example, when viewed in a plane, the organic photoelectric conversion element (OPD) can be stacked with a corresponding one of the first photoelectric conversion element (PD1) and the second photoelectric conversion element (PD2). A first color filter (CF1) can be correspondingly disposed between the first photoelectric conversion element (PD1) and the organic photoelectric conversion element (OPD), and a second color filter (CF2) can be correspondingly disposed between the second photoelectric conversion element (PD2) and the organic photoelectric conversion element (OPD).

[0111] In some example embodiments, the organic photoelectric conversion element (OPD) of a unit pixel P can receive corresponding incident light from a first incident light L1, a second incident light L2, and a third incident light L3, which respectively have a first band, a second band, and a third band. The first photoelectric conversion element PD1, the second photoelectric conversion element PD2, and the organic photoelectric conversion element OPD can each receive incident light having a band different from the band of any other incident light, and can each generate photocharge proportional to the amount of incident light.

[0112] For example, a first photoelectric conversion element PD1 can generate a first photocharge corresponding to a first incident light L1 having a first wavelength band. A second photoelectric conversion element PD2 can generate a second photocharge corresponding to a second incident light L2 having a second wavelength band. An organic photoelectric conversion element OPD can generate a third photocharge corresponding to a third incident light L3 having a third wavelength band. The first wavelength band can be longer than the third wavelength band, and the second wavelength band can be shorter than the third wavelength band. For example, the first incident light L1 having the first wavelength band can appear red, the second incident light L2 having the second wavelength band can appear blue, and the third incident light L3 having the third wavelength band can appear green.

[0113] The first incident light L1, having a first wavelength band, can pass through the organic photoelectric conversion element OPD and the first color filter CF1, and then enter the first photoelectric conversion element PD1. The second incident light L2, having a second wavelength band, can pass through the organic photoelectric conversion element OPD and the second color filter CF2, and then enter the second photoelectric conversion element PD2. The third incident light L3, having a third wavelength band, can enter the organic photoelectric conversion element OPD.

[0114] At a unit pixel P including a first photoelectric conversion element PD1, a first pixel signal S1 corresponding to a first incident light L1 having a first wavelength band can be output, and at a unit pixel P including a second photoelectric conversion element PD2, a second pixel signal S2 corresponding to a second incident light L2 having a second wavelength band can be output. Furthermore, an organic photoelectric conversion element OPD at unit pixel P can output a third pixel signal S3 corresponding to a third incident light L3 having a third wavelength band. For example, the first photoelectric conversion element PD1 can generate photocharge corresponding to red light. The second photoelectric conversion element PD2 can generate photocharge corresponding to blue light. The organic photoelectric conversion element OPD can generate photocharge corresponding to green light.

[0115] Figure 15 A cross-sectional view showing an image sensor according to some example embodiments is shown.

[0116] Reference Figure 15 As discussed above, the semiconductor substrate 100 can include a pixel separation structure comprising a photoelectric conversion region 110 and defining pixel regions P1 and P2 (see...). Figure 4A and Figure 4B (103).

[0117] In each of the pixel regions P1 and P2, a transfer gate electrode TG may be disposed on a first surface 100a of the semiconductor substrate 100, and a first floating diffusion region FD1 may be disposed in the semiconductor substrate 100 on one side of the transfer gate electrode TG. A second floating diffusion region FD2 may be disposed in the semiconductor substrate 100 and spaced apart from the first floating diffusion region FD1.

[0118] The first floating diffusion region FD1 and the second floating diffusion region FD2 can be formed by implanting impurities into the semiconductor substrate 100 with an impurity whose conductivity type is opposite to that of the semiconductor substrate 100. For example, the first floating diffusion region FD1 and the second floating diffusion region FD2 can be n-type impurity regions.

[0119] Pixel regions P1 and P2 may have a through electrode structure 130 between them that penetrates a portion of the pixel separation structure 103.

[0120] The through-electrode structure 130 may include: a through-electrode 134 vertically penetrating the semiconductor substrate 100; and a through-dielectric pattern 132 surrounding the sidewalls of the through-electrode 134. The through-electrode 134 may include a conductive material. The through-electrode 134 may include polycrystalline silicon or a metal doped with n-type or p-type impurities. The through-electrode 134 may have a width that gradually decreases from a first surface 100a to a second surface 100b of the semiconductor substrate 100. The through-dielectric pattern 132 may include, for example, one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0121] Interlayer dielectric layers 211, 213, and 215 may be disposed on the first surface 100a of the semiconductor substrate 100 and may cover the transfer gate electrode TG and the MOS transistor constituting the first and second readout circuits. A plurality of bottom contact plugs BCP1 to BCP3 may be disposed within the interlayer dielectric layers 211, 213, and 215. For example, the first bottom contact plug BCP1 may be bonded to the first floating diffusion region FD1, and the second bottom contact plug BCP2 may be bonded to the second floating diffusion region FD2. The third bottom contact plug BCP3 may be bonded to the through electrode 134.

[0122] The first bottom contact plug BCP1 can be electrically connected to the reset transistor via the first connection line CL1 (see...). Figure 13 (RX) and amplifier transistors (see Figure 13 (AX). The second bottom contact plug BCP2 can be connected to the third bottom contact plug BCP3 via the second connecting line CL2. For example, the through electrode 134 can be electrically connected to the second floating diffusion region FD2 via the second bottom contact plug BCP2, the third bottom contact plug BCP3, and the second connecting line CL2.

[0123] A planar dielectric layer 310 may be disposed on a second surface 100b of the semiconductor substrate 100. As discussed above, the planar dielectric layer 310 may comprise a single layer or multiple layers. The planar dielectric layer 310 may comprise a metal oxide such as aluminum oxide and / or hafnium oxide.

[0124] Color filters 345a and 345b can be disposed on the flat dielectric layer 310 at corresponding pixel regions P1 and P2. Color filters 345a and 345b may include a first color filter 345a located on the first pixel region P1 and a second color filter 345b located on the second pixel region P2.

[0125] Color filters 345a and 345b can be disposed in an opening defined by a mesh structure 320 disposed on a flat dielectric layer 310. A first color filter 345a can be disposed on a first pixel region P1, and a second color filter 345b can be disposed on a second pixel region P2. As discussed above, in some example embodiments, each of the color filters 345a and 345b can have a substantially flat top surface parallel to its bottom surface. The top surfaces of the color filters 345a and 345b can be positioned at a level lower than the level of the top surface of the mesh structure 320, or they can be positioned at a level substantially the same as the level of the top surface of the mesh structure 320.

[0126] The first upper planarization layer (BPL) can cover the top surfaces of color filters 345a and 345b. The first upper planarization layer (BPL) is formed on the flat top surfaces of color filters 345a and 345b and can have substantially flat top surfaces.

[0127] The top contact plug TCP can penetrate the first upper planarization layer BPL, a portion of the mesh structure 320, and the planar dielectric layer 310 to bond to the corresponding through electrode 134. Each top contact plug TCP may include a barrier metal layer formed of a metal nitride such as titanium nitride, tantalum nitride, or tungsten nitride, and may also include a metal layer formed of a metal such as tungsten or copper.

[0128] An organic photoelectric conversion element (OPD) can be disposed on a first upper planarization layer (BPL) disposed on a second surface 100b of a semiconductor substrate 100. The organic photoelectric conversion element (OPD) may include a bottom electrode (BE), a top electrode (TE), and an organic photoelectric conversion layer (OPL) located between the bottom electrode (BE) and the top electrode (TE).

[0129] The bottom electrode BE can be disposed on a first upper planarization layer BPL having a flat top surface. When viewed in a plane, the bottom electrode BE can be positioned to correspond to pixel regions P1 and P2 and can be spaced apart from each other. Each bottom electrode BE can be electrically connected to the second floating diffusion region FD2 via a corresponding top contact plug TCP, through electrode 134, second bottom contact plug BCP2 and third bottom contact plug BCP3, and second connecting line CL2.

[0130] The bottom electrode BE can include a transparent conductive material. For example, the bottom electrode BE can include one or more of ITO (indium tin oxide), IZO (indium zinc oxide), ZnO (zinc oxide), SnO2, ATO (antimony-doped tin oxide), AZO (aluminum-doped zinc oxide), GZO (gallium-doped zinc oxide), TiO2, and FTO (fluorine-doped tin oxide).

[0131] An organic photoelectric conversion layer (OPL) can be disposed on the bottom electrode (BE). The OPL can selectively absorb light of a specific wavelength band, thus inducing photoelectric conversion. The OPL may comprise p-type and n-type organic semiconductor materials, which form a pn junction. In other embodiments, the OPL may comprise quantum dots or chalcogenides.

[0132] The top electrode TE can be disposed on the organic photoelectric conversion layer OPL. The top electrode TE can include a transparent conductive material and can completely cover pixel areas P1 and P2.

[0133] The encapsulation layer TFE can be disposed on the top electrode TE. The encapsulation layer TFE can be formed of a single layer or multiple layers. The encapsulation layer TFE may include, for example, an aluminum layer and a silicon oxynitride layer. A second upper planarization layer TPL can be disposed on the encapsulation layer TFE, and a microlens array 350 can be disposed on the second upper planarization layer TPL. The second upper planarization layer TPL may include a transparent dielectric material, such as a metal oxide or silicon oxide. The microlens array 350 may include microlenses corresponding to pixel regions P1 and P2.

[0134] Figures 16A to 16H It shows along Figure 4A The line I-I' cuts out a cross-sectional view of a method for manufacturing an image sensor according to some example embodiments.

[0135] Reference Figure 4A and Figure 16A A semiconductor substrate 100 having a first conductivity type (e.g., p-type) may be provided. The semiconductor substrate 100 may have a first surface 100a and a second surface 100b facing each other.

[0136] In some example embodiments, the semiconductor substrate 100 may include a first pixel region, a second pixel region, and a third pixel region (see Figure 3 P1, P2, and P3), each of the pixel regions P1, P2, and P3 may include multiple sub-pixel regions (see P1, P2, and P3). Figure 3 (PG1 / PG2, PR and PB).

[0137] Photoelectric conversion regions 110 can be formed in semiconductor substrate 100. On each of the sub-pixel regions PG1 / PG2, PR and PB, photoelectric conversion regions 110 can be formed by implanting impurities with a second conductivity type (e.g., n-type) that is different from the first conductivity type into semiconductor substrate 100.

[0138] A device isolation layer 101 can be formed, thereby being adjacent to the first surface 100a on each of the sub-pixel regions PG1 / PG2, PR, and PB and defining an active region on the semiconductor substrate 100. The device isolation layer 101 can be formed by forming shallow trenches on the first surface 100a of the semiconductor substrate 100 through patterning, and then depositing dielectric material in the shallow trenches. The formation of the device isolation layer 101 can be performed before or after the formation of the photoelectric conversion region 110.

[0139] A pixel separation structure 103 can be formed on the semiconductor substrate 100 to define sub-pixel regions PG1 / PG2, PR, and PB. The pixel separation structure 103 can be formed by forming a deep trench by patterning a first surface 100a and / or a second surface 100b of the semiconductor substrate 100, and then filling the deep trench with a dielectric material.

[0140] Reference Figure 4A and Figure 16B Metal-oxide-semiconductor (MOS) transistors can be formed on the first surface 100a of the semiconductor substrate 100 to form a readout circuit. For example, a transfer gate electrode TG can be formed on the first surface 100a of the semiconductor substrate 100, and a gate dielectric layer can be disposed between the semiconductor substrate 100 and each transfer gate electrode TG. The gate electrode (not shown) of the MOS transistor can also be formed together with the transfer gate electrode TG.

[0141] After forming the transfer gate electrode TG, a floating diffusion region FD can be formed in the semiconductor substrate 100 on one side of the transfer gate electrode TG. The floating diffusion region FD can be formed by implanting impurities having a second conductivity type. In addition, the source / drain impurity regions (not shown) of the MOS transistor can also be formed together with the floating diffusion region FD.

[0142] Reference Figure 4A and Figure 16C Interlayer dielectric layers 211, 213, and 215, contact plugs CT, and interconnects CL can be formed on the first surface 100a of the semiconductor substrate 100. Interlayer dielectric layers 211, 213, and 215 can cover the first and second transmission transistors and the logic transistors. Interlayer dielectric layers 211, 213, and 215 can be formed of a material with excellent gap-filling properties and can have planarized upper portions.

[0143] Contact plugs (CTs) can be formed in the interlayer dielectric layers 211, 213, and 215 to connect to the floating diffusion region FD or MOS transistor. Connector lines (CLs) can be formed between the interlayer dielectric layers 211, 213, and 215. The contact plugs (CTs) and connector lines (CLs) can be formed from, for example, copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), molybdenum (Mo), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), zirconium nitride (ZrN), tungsten nitride (WN), or alloys thereof.

[0144] Reference Figure 4A and Figure 16D A thinning process can be performed to remove a portion of the semiconductor substrate 100, thus allowing the semiconductor substrate 100 to have a reduced vertical thickness. The semiconductor substrate 100 can be inverted to perform the thinning process. A grinding or polishing process can be performed to remove a portion of the semiconductor substrate 100, followed by an anisotropic or isotropic etching process to remove residual surface defects from the semiconductor substrate 100. The thinning process on the semiconductor substrate 100 can expose the pixel separation structure 103 from the second surface 100b of the semiconductor substrate 100. For example, the pixel separation structure 103 can have a surface at a level substantially the same as the surface of the second surface 100b of the semiconductor substrate 100.

[0145] Subsequently, a fixed charge layer 300 can be formed on the second surface 100b of the semiconductor substrate 100. The fixed charge layer 300 can directly cover the second surface 100b of the semiconductor substrate 100. The fixed charge layer 300 can be formed of a metal oxide such as aluminum oxide and / or hafnium oxide.

[0146] A planar dielectric layer 310 can be formed on the fixed charge layer 300. The formation of the planar dielectric layer 310 may include the sequential deposition of a first planarization layer 311, a second planarization layer 313, and a third planarization layer 315. The first planarization layer 311, the second planarization layer 313, and the third planarization layer 315 may be formed of a transparent dielectric material and may have different thicknesses than each other. The first planarization layer 311, the second planarization layer 313, and the third planarization layer 315 may include, for example, metal oxides or silicon oxide.

[0147] A light-shielding layer 321 and a low-refractive-index layer 323 may be sequentially formed on a planar dielectric layer 310. The light-shielding layer 321 may be formed of a metallic material such as titanium, tungsten, or aluminum. As discussed above, the low-refractive-index layer 323 may be formed of a material whose refractive index is in the range of about 1.1 to about 1.3. The low-refractive-index layer 323 may include organic materials and oxides. The refractive index of the low-refractive-index layer 323 may depend on the concentration of oxides contained in the low-refractive-index layer 323. The formation of the low-refractive-index layer 323 may include: spin-coating a composition comprising organic materials and solvents onto the light-shielding layer 321; and performing a soft baking process or a dry process to remove the solvent.

[0148] Reference Figure 4A and Figure 16E The low-refractive-index layer 323 and the light-shielding layer 321 can be patterned to form a mesh structure 320 including a low-refractive-index pattern 324 and a light-shielding pattern 322. When viewed in a plane, as discussed above, the mesh structure 320 can be superimposed on the pixel separation structure 103 in the semiconductor substrate 100.

[0149] The formation of the mesh structure 320 may include: forming a mask pattern (not shown) on the low refractive index layer 323, and using the mask pattern as an etch mask through which the low refractive index layer 323 and the light-shielding layer 321 are sequentially etched to expose the flat dielectric layer 310. After the mesh structure 320 is formed, the mask pattern may be removed.

[0150] The grid structure 320 may include a first fence portion FS1 disposed between adjacent sub-pixel regions PG1 / PG2, PR, and PB, and a second fence portion FS2 disposed between adjacent pixel regions P1, P2, and P3. The first fence portion FS1 and the second fence portion FS2 may have substantially the same height. Furthermore, the first fence portion FS1 and the second fence portion FS2 may have substantially the same width.

[0151] Subsequently, a protective layer 330 can be formed to conformally cover the surface of the mesh structure 320 and the top surface of the planar dielectric layer 310 exposed by the mesh structure 320. The protective layer 330 can be formed by performing a chemical vapor deposition process or an atomic layer deposition process. The protective layer 330 can be formed from one or more single layers including an aluminum oxide layer and a silicon oxide layer.

[0152] Reference Figure 4A and Figure 16F It can be found in the corresponding pixel area (see Figure 3Initial color filters 340a and 340b are sequentially formed on the first pixel region P1, P2, and P3. For example, a first initial color filter 340a may be formed on the first pixel region P1, and a second initial color filter 340b may be formed on the second pixel region P2. Furthermore, a third initial color filter (not shown) may be formed on the third pixel region P3.

[0153] Each of the initial color filters 340a and 340b can be formed by performing a number of spin coating and patterning processes. The initial color filters 340a and 340b can fill the empty spaces defined by the mesh structure 320. For example, the initial color filters 340a and 340b can be formed by sequentially performing a coating process, a soft baking process, an exposure process, and a development process on a photoresist composition including dyes or pigments.

[0154] In some example embodiments, each of the initial color filters 340a and 340b may be configured for the sub-pixel regions PG1 / PG2, PR, and PB of pixel regions P1, P2, and P3. For example, when forming each of the initial color filters 340a and 340b, a coating process may be performed such that each of the initial color filters 340a and 340b may cover the first fence portion FS1 of the mesh structure 320. Each of the initial color filters 340a and 340b may have a relatively large thickness at the portion adjacent to the first fence portion FS1 and a relatively small thickness at the portion adjacent to the second fence portion FS2. Thus, each of the initial color filters 340a and 340b may have an upwardly convex top surface. Furthermore, the initial color filters 340a and 340b may be formed independently of each other, such that the initial color filters 340a and 340b may have different thicknesses than each other.

[0155] Reference Figure 4A and Figure 16GA sacrificial planarization layer 355 can be formed to cover the top surfaces of the initial color filters 340a and 340b. The sacrificial planarization layer 355 can be formed of a material having an etch selectivity of approximately 1:1 relative to the initial color filters 340a and 340b in an etching process using the same etch formulation. The sacrificial planarization layer 355 can be formed of a transparent dielectric material. The sacrificial planarization layer 355 can be formed of, for example, SOG (spin-coated glass), FSG (fluorinated silicate glass), FOX (flowable oxide), or TOSZ (tonen silazene). The sacrificial planarization layer 355 can be formed by spin-coating a flowable material. The sacrificial planarization layer 355 can cover the uneven top surfaces of the initial color filters 340a and 340b, but can have a substantially flat top surface. For example, the sacrificial planarization layer 355 can have different thicknesses on the first fence portion FS1 and the second fence portion FS2. That is, for example, as... Figure 16G As shown, the thickness of the sacrificial flattening layer 355 on the second fence portion FS2 can be greater than the thickness on the first fence portion FS1.

[0156] Reference Figure 4A and Figure 16H After the sacrificial planarization layer 355 is formed, a planarization process can be performed on the sacrificial planarization layer 355 and the initial color filters 340a and 340b. Therefore, a first color filter 345a, a second color filter 345b, and a third color filter (not shown) can be formed to correspond to the first pixel region P1, the second pixel region P2, and the third pixel region P3. For example, the planarization process may include an etch-back process or a chemical mechanical polishing process.

[0157] When performing a planarization process, the protective layer 330 covering the top surface of the mesh structure 320 can be used as an etch stop layer or a planarization stop layer. For example, the planarization process can continue until the protective layer 330 covering the top surface of the mesh structure 320 is exposed. After the planarization process, the first fence portion FS1 of the mesh structure 320 can separate the first initial color filter 340a into four first color filters 345a. This separation can be applied in the same way to the second initial color filter 340b.

[0158] During the planarization process, the sacrificial planarization layer 355 can be etched with an etch selectivity of approximately 1:1 relative to the initial color filters 340a and 340b. Therefore, each of the first color filter 345a, the second color filter 345b, and the third color filter can have substantially the same thickness on the first and second fencing portions FS2. For example, each of the first color filter 345a, the second color filter 345b, and the third color filter can have a substantially flat top surface. Furthermore, after the planarization process, the top surfaces of the first color filter 345a, the second color filter 345b, and the third color filter can be positioned at a level lower than the level of the top surface of the mesh structure 320, or positioned at a level substantially the same as the level of the top surface of the mesh structure 320.

[0159] After that, as Figure 4A and Figure 4B As shown, a microlens array 350 can be formed, including microlenses 353 corresponding to sub-pixel regions PG1 / PG2, PR, and PB.

[0160] The microlens array 350 can be formed by: forming a transparent photoresist layer; partially patterning the photoresist layer to form photoresist patterns corresponding to the sub-pixel regions PG1 / PG2, PR, and PB; and reflowing the photoresist patterns. Therefore, the microlens 353 can be formed with an upwardly convex shape having a constant curvature. Furthermore, a flat portion 351 can be formed with a uniform thickness between the microlens 353 and the first color filter 345a, the second color filter 345b, and the third color filter.

[0161] Because the microlens array 350 is formed by coating the first color filter 345a, the second color filter 345b, and the third color filter with a flat top surface, the microlens array 350 can have a substantially uniform thickness at its maximum thickness. The microlenses 353 can have a substantially constant curvature on the top surfaces of the color filters 345a and 345b. In this case, the thickness distribution of the microlens array 350 can be improved.

[0162] Subsequently, a passivation layer 360 can be formed to conformally cover the surface of the microlens 353. The passivation layer 360 can be formed, for example, from an inorganic oxide.

[0163] Figures 17A to 17D It shows along Figure 4A The line I-I' cuts out a cross-sectional view of a method for manufacturing an image sensor according to some example embodiments.

[0164] Reference Figure 17A As mentioned above Figure 16DAfter planarizing the second surface 100b of the semiconductor substrate 100 as discussed herein, a fixed charge layer 300 can be formed on the second surface 100b. A planar dielectric layer 310 can be formed on the fixed charge layer 300. In this case, the formation of the planar dielectric layer 310 may include sequentially depositing a first planarization layer 311 and a second planarization layer 313. The first planarization layer 311 and the second planarization layer 313 may be formed of a transparent dielectric material and may have different thicknesses and different refractive indices. The first planarization layer 311 may include a hafnium oxide layer, a tantalum oxide layer, or a titanium oxide layer. The second planarization layer 313 may include a silicon oxide layer such as TEOS.

[0165] Subsequently, a sacrificial pattern MP can be formed on the planar dielectric layer 310. The sacrificial pattern MP can have a thickness greater than that of the planar dielectric layer 310. The formation of the sacrificial pattern MP can include: coating a sacrificial layer on the planar dielectric layer 310; forming a photoresist pattern on the sacrificial layer; and using the photoresist pattern as an etch mask to etch the sacrificial layer. The sacrificial pattern MP can define an initial recess RR1 with a grid shape on the planar dielectric layer 310. The initial recess RR1 can expose the planar dielectric layer 310. The sacrificial pattern MP can contain carbon in an amount equal to or greater than about 70 wt%. For example, the sacrificial pattern MP can include a spin-coated hard mask (SOH) layer.

[0166] Reference Figure 17B A sacrificial pattern MP can be used as an etch mask to pattern the flat dielectric layer 310. Therefore, the flat dielectric layer 310 can have recesses RR2 therein, which are formed to expose the fixed charge layer 300. Optionally, in some example embodiments, the fixed charge layer 300 can be etched during the formation of the recesses RR2, so that the recesses RR2 can expose the pixel separation structure 103.

[0167] After the depression RR2 is formed, a low-refractive-index layer 323 can be formed to fill the depression RR2. The low-refractive-index layer 323 can be formed by performing a spin coating process. Therefore, the low-refractive-index layer 323 can completely fill the depression RR2 and can cover the top surface of the sacrificial pattern MP.

[0168] Subsequently, a planarization process can be performed relative to the low-refractive-index layer 323 until the top surface of the sacrificial pattern MP is exposed.

[0169] The sacrificial pattern MP can be selectively removed to expose the top surface of the flat dielectric layer 310 for each of the sub-pixel regions PG1 / PG2, PR, and PB. For example, the sacrificial pattern MP can be removed by using an oxygen ashing process.

[0170] Reference Figure 17CAfter selectively removing the sacrificial pattern MP, a protective layer 330 can be conformally formed. For example, the protective layer 330 can have a uniform thickness and covers the top surface of the planar dielectric layer 310 as well as the sidewalls and top surface of the mesh structure 320. The removal of the sacrificial pattern MP and the formation of the protective layer 330 can create an opening defined by the sidewalls of the mesh structure 320 and the top surface of the planar dielectric layer 310. As a result, as... Figure 17C As shown, a grid structure 320 including a low refractive index pattern can be formed.

[0171] Reference Figure 17D It can form a first initial color filter 340a, a second initial color filter 340b and a third initial color filter to correspond to the first pixel region P1, the second pixel region P2 and the third pixel region P3.

[0172] Because a coating process is performed to form as shown in the reference. Figure 16F Each of the first initial color filter 340a, the second initial color filter 340b, and the third initial color filter is discussed, so that each of the first initial color filter 340a, the second initial color filter 340b, and the third initial color filter can cover the first fence portion FS1 of the grid structure 320. Thus, each of the first initial color filter 340a, the second initial color filter 340b, and the third initial color filter can have an upwardly convex top surface.

[0173] Then, as per reference Figure 16G As discussed, a sacrificial planarization layer 355 can be formed to cover the top surfaces of the first initial color filter 340a, the second initial color filter 340b, and the third initial color filter. The sacrificial planarization layer 355 can cover the uneven top surfaces of the initial color filters 340a and 340b, but can have a substantially flat top surface.

[0174] Subsequently, as discussed above, a planarization process can be performed on the sacrificial planarization layer 355 and on the first initial color filter 340a, the second initial color filter 340b, and the third initial color filter. Therefore, the first color filter 345a, the second color filter 345b, and the third color filter can be formed to correspond to the first pixel region P1, the second pixel region P2, and the third pixel region P3. Color filters 345a and 345b can have substantially flat top surfaces.

[0175] According to some example embodiments, each pixel region of an image sensor may include a color filter whose top surface is flat and whose thickness is substantially the same at its opposite sidewalls. Therefore, the image sensor can improve its sensitivity degradation caused by uneven thickness of the color filter filling the empty spaces defined by the grid structure.

[0176] Furthermore, microlenses with uniform radii of curvature can be incorporated into the color filter. This minimizes crosstalk between pixel regions of the image sensor, resulting in improved sensitivity and signal-to-noise ratio characteristics.

[0177] Although the inventive concept has been described in conjunction with some exemplary embodiments shown in the accompanying drawings, those skilled in the art will understand that various changes and modifications can be made without departing from the technical spirit of the inventive concept. It will be apparent to those skilled in the art that various substitutions, modifications, and alterations can be made therein without departing from the scope and spirit of the claims.

Claims

1. An image sensor comprising: a substrate including a pixel separation structure defining a first pixel region and a second pixel region, the first pixel region including a plurality of first sub-pixel regions, and the second pixel region including a plurality of second sub-pixel regions; a mesh structure disposed on the substrate, extending along a first direction and a second direction crossing the first direction, and including first fence portions disposed between the plurality of first sub-pixel regions and the plurality of second sub-pixel regions, and second fence portions disposed between the first pixel region and the second pixel region, the mesh structure defining a plurality of openings corresponding to the plurality of first sub-pixel regions and the plurality of second sub-pixel regions, respectively; and a plurality of color filters disposed in the openings defined by the mesh structure, each color filter having a planar top surface, the planar top surface of each color filter being parallel to a bottom surface of each color filter, wherein the plurality of first sub-pixel regions are disposed adjacent to each other in the first direction and the second direction, and the plurality of second sub-pixel regions are disposed adjacent to each other in the first direction and the second direction, and wherein the plurality of color filters include a plurality of first color filters corresponding to the plurality of first sub-pixel regions of the first pixel region, and a plurality of second color filters corresponding to the plurality of second sub-pixel regions of the second pixel region.

2. The image sensor of claim 1, wherein, The color filters have a first height adjacent to the first fence portions and a second height adjacent to the second fence portions, and a difference between the first height and the second height is 10 Å to 100 Å.

3. The image sensor of claim 1, wherein, The mesh structure includes a protective layer covering a top surface of the mesh structure, and the planar top surface of the color filters is coplanar with a top surface of the protective layer.

4. The image sensor of claim 1, wherein, The top surface of the color filters is lower than a top surface of the mesh structure.

5. The image sensor of claim 1, wherein, The mesh structure includes a protective pattern covering only sidewalls of the mesh structure and bottom surfaces of the color filters, and The top surface of the color filters is lower than a top surface of the mesh structure. 6.The image sensor of claim 1, further comprising a fixed charge layer and a planar dielectric layer sequentially stacked between the substrate and the mesh structure, wherein the mesh structure includes a light-shielding pattern disposed on the planar dielectric layer, and a low refractive index pattern disposed on the light-shielding pattern.

7. The image sensor of claim 6, wherein, A height of the low refractive index pattern is 2000 Å to 5000 Å, and a thickness of each color filter is 5000 Å to 5500 Å. 8.The image sensor of claim 1, further comprising a microlens array disposed on the color filters, the microlens array including a planar portion disposed on the color filters, and a plurality of microlenses corresponding to the plurality of first sub-pixel regions and the plurality of second sub-pixel regions located on the planar portion.

9. The image sensor of claim 1, wherein, A height of the mesh structure is smaller than the thickness of each color filter.

10. The image sensor of claim 1, wherein, The substrate includes a pixel array region and a pad region around the pixel array region, the pixel array region including the first pixel region and the second pixel region, the pixel array region includes a center region and a peripheral region surrounding the center region, in a plan view, the mesh structure overlaps the pixel separation structure in the center region, and the plurality of color filters have a thickness in the peripheral region that is smaller than a thickness in the center region.

11. An image sensor comprising: a substrate having a first surface and a second surface opposite to the first surface, the substrate including a pixel separation structure defining a first pixel region and a second pixel region, the first pixel region including a plurality of first sub-pixel regions, and the second pixel region including a plurality of second sub-pixel regions; a device isolation layer disposed on each of the first pixel region and the second pixel region adjacent to the first surface of the substrate, the device isolation layer defining an active region in the first pixel region and the second pixel region; a plurality of interlayer dielectric layers stacked on the first surface of the substrate and including a contact plug and a connection line; a fixed charge layer disposed on the second surface of the substrate; a planarization dielectric layer disposed on the fixed charge layer; a mesh structure disposed on the planarization dielectric layer to overlap the pixel separation structure in a plan view and extending in a first direction and a second direction crossing the first direction, the mesh structure including a fence portion disposed between the first pixel region and the second pixel region, the mesh structure defining a plurality of openings corresponding to the first pixel region and the second pixel region, respectively; a plurality of color filters disposed in the openings defined by the mesh structure; a sacrificial planar layer between adjacent ones of the plurality of color filters, the sacrificial planar layer having a top surface coplanar with an uppermost surface of each color filter; and a microlens array disposed on the plurality of color filters, wherein the plurality of first sub-pixel regions are disposed adjacent to each other in the first direction and the second direction, and the plurality of second sub-pixel regions are disposed adjacent to each other in the first direction and the second direction, and wherein the plurality of color filters include a plurality of first color filters corresponding to the plurality of first sub-pixel regions of the first pixel region, and a plurality of second color filters corresponding to the plurality of second sub-pixel regions of the second pixel region. The sacrificial planar layer fills a space above each fence portion such that the top surface of the sacrificial planar layer is coplanar with the uppermost surface of each color filter.

12. The image sensor of claim 11, wherein, 13. The image sensor of claim 11, wherein the fence portion is a second fence portion, and the mesh structure further includes a first fence portion disposed between the plurality of first sub-pixel regions and the plurality of second sub-pixel regions, and each color filter has a first height at a portion adjacent to the first fence portion that is greater than a second height at a portion adjacent to the second fence portion. The microlens array includes a flat portion disposed on the color filter and a plurality of microlenses on the flat portion corresponding to the plurality of first sub-pixel regions and the plurality of second sub-pixel regions.

14. The image sensor of claim 13, wherein, The first pixel region and the second pixel region form a 2x2 matrix, and the sacrificial planar layer fills a space between the first pixel region and the second pixel region.

15. The image sensor of claim 11, wherein, The mesh structure includes a protective layer covering a top surface of the mesh structure, and the uppermost surface of each color filter is coplanar with a top surface of the protective layer.

16. The image sensor of claim 11, wherein, The mesh structure includes a light-shielding pattern disposed on the planarization dielectric layer and a low-refractive index pattern disposed on the light-shielding pattern.

17. The image sensor of claim 11, wherein, ​ 18. The image sensor of claim 17, wherein, The height of the low refractive index pattern is 2000 to 5000 A, and the thickness of each color filter is 5000 to 5500 A.

19. The image sensor of claim 11, wherein, The height of the grid structure is smaller than the maximum thickness of each color filter.

20. The image sensor of claim 11, wherein, The substrate includes a pixel array region and a pad region around the pixel array region, the pixel array region including a first pixel region and a second pixel region, The pixel array region includes a center region and a peripheral region surrounding the center region, In a plan view, the grid structure overlaps the pixel separation structure in the center region, and The maximum thickness of each color filter in the peripheral region is smaller than the maximum thickness of each color filter in the center region.

Images