Chopper drive circuit, method and electronic device

Abstract

The present invention provides a chopper drive circuit, method and electronic equipment, which relate to the technical field of thyristor drive triggering, and include a main controller and an AND gate circuit; the main controller is connected to a power grid and the AND gate circuit respectively; the present invention utilizes the main controller to generate a phase-shifted wide pulse signal and a preset PWM signal, and controls the first high-frequency pulse of the preset PWM signal to be synchronized with the phase-shifted wide pulse signal, and obtains a chopper drive signal through the AND gate circuit, without using expensive control chips or other drive synchronization circuits, thereby simplifying the system hardware design, reducing the production cost, and making the phase-shift trigger synchronization more accurate.

Description

Technical Field

[0001] The present invention relates to the technical field of thyristor drive triggering, and in particular to a chopper drive circuit, method and electronic equipment. Background Art

[0002] Thyristors are semi-controlled power devices. To conduct, they need to apply a positive anode voltage, add sufficient positive gate voltage, and have sufficient trigger power. Thyristors are widely used in the power electronics industry. All these applications require safe and reliable triggering and isolation. In practical applications, isolation is generally achieved through optocouplers or pulse transformers. Pulse transformer drive can not only achieve drive isolation, but also the high-frequency pulse signal can effectively reduce the drive power consumption and has stronger anti-interference ability. However, the pulse transformer requires a square wave in the form of a high-frequency pulse as a drive signal. Generally, the signal output by the controller is a wide pulse with a phase shift angle generated according to the synchronization point of the power grid. If a controller is used to generate a high-frequency drive pulse signal, a control chip with more powerful functions and performance is required, and the internal timing interrupt system will be very complex and the production cost will be high. Summary of the invention

[0003] The object of the present invention is to provide a chopper drive circuit, method and electronic equipment to simplify the system hardware design of the chopper drive circuit in the prior art and reduce the production cost.

[0004] In a first aspect, an embodiment of the present invention provides a chopper drive circuit, comprising: a main controller and an AND gate circuit; the main controller is connected to a power grid and the AND gate circuit respectively; the main controller is used to detect a power grid voltage, and output a phase-shifted wide pulse signal to the AND gate circuit based on the power grid voltage, wherein the phase-shifted wide pulse signal is a pulse signal having a preset offset angle with a power grid synchronization point; the main controller is also used to output a preset PWM signal to the AND gate circuit, and reset the preset PWM signal when outputting the phase-shifted wide pulse signal, wherein the first pulse of the preset PWM signal is a high level and is maintained longer than the remaining pulses; the AND gate circuit is used to output a chopper drive signal based on the phase-shifted wide pulse signal and the preset PWM signal.

[0005] In an optional embodiment, if the power grid is a single-phase power grid, the AND gate circuit includes: a first AND gate and a second AND gate; the first input end of the first AND gate is used to receive the first phase-shifted wide pulse signal output by the main controller; the second input end of the first AND gate is used to receive the preset PWM signal; the output end of the first AND gate is used to output a first chopping drive signal; the first input end of the second AND gate is used to receive the second phase-shifted wide pulse signal output by the main controller; the second input end of the second AND gate is used to receive the preset PWM signal; the output end of the second AND gate is used to output a second chopping drive signal.

[0006] In an optional embodiment, if the power grid is a three-phase power grid, the AND gate circuit includes: a third AND gate, a fourth AND gate, a fifth AND gate, a sixth AND gate, a seventh AND gate and an eighth AND gate; the first input end of the third AND gate is used to receive the third phase-shifted wide pulse signal output by the main controller; the second input end of the third AND gate is used to receive the preset PWM signal; the output end of the third AND gate is used to output a third chopping drive signal; the first input end of the fourth AND gate is used to receive the fourth phase-shifted wide pulse signal output by the main controller; the second input end of the fourth AND gate is used to receive the preset PWM signal; the output end of the fourth AND gate is used to output a fourth chopping drive signal; the first input end of the fifth AND gate is used to receive the fifth phase-shifted wide pulse signal output by the main controller; the second input end of the fifth AND gate is used to receive the preset Assume a PWM signal; the output end of the fifth AND gate is used to output a fifth chopping drive signal; the first input end of the sixth AND gate is used to receive the sixth phase-shifted wide pulse signal output by the main controller; the second input end of the sixth AND gate is used to receive the preset PWM signal; the output end of the sixth AND gate is used to output the sixth chopping drive signal; the first input end of the seventh AND gate is used to receive the seventh phase-shifted wide pulse signal output by the main controller; the second input end of the seventh AND gate is used to receive the preset PWM signal; the output end of the seventh AND gate is used to output the seventh chopping drive signal; the first input end of the eighth AND gate is used to receive the eighth phase-shifted wide pulse signal output by the main controller; the second input end of the eighth AND gate is used to receive the preset PWM signal; the output end of the eighth AND gate is used to output the eighth chopping drive signal.

[0007] In an optional embodiment, the chopping drive circuit also includes: an amplifier circuit, which is connected to the AND gate circuit; the amplifier circuit is used to receive the chopping drive signal output by the AND gate circuit and amplify the chopping drive signal so that the amplified chopping drive signal drives the pulse transformer.

[0008] In an optional implementation, the holding time of the first pulse of the preset PWM signal is 100 us.

[0009] In an optional implementation, the preset PWM signal, except for the first pulse, is a periodic high-frequency pulse of 10 kHz and a 30% duty cycle.

[0010] In an optional implementation, the main controller includes: a single chip microcomputer.

[0011] In a second aspect, an embodiment of the present invention provides a chopper drive method, which is applied to a main controller in a chopper drive circuit in any one of the aforementioned embodiments, comprising: detecting a grid voltage, and outputting a phase-shifted wide pulse signal to an AND gate circuit based on the grid voltage, wherein the phase-shifted wide pulse signal is a pulse signal having a preset offset angle with a grid synchronization point; outputting a preset PWM signal to the AND gate circuit, and resetting the preset PWM signal when outputting the phase-shifted wide pulse signal, so that the AND gate circuit outputs a chopper drive signal based on the phase-shifted wide pulse signal and the preset PWM signal, wherein the first pulse of the preset PWM signal is a high level and is held longer than the remaining pulses.

[0012] In a third aspect, an embodiment of the present invention provides an electronic device, including a memory and a processor, wherein the memory stores a computer program executable on the processor, and when the processor executes the computer program, the steps of the method described in the aforementioned embodiment are implemented.

[0013] In a fourth aspect, an embodiment of the present invention provides a computer-readable medium having a non-volatile program code executable by a processor, wherein the program code enables the processor to execute the method described in the aforementioned embodiment.

[0014] In the prior art, in order to obtain a high-frequency driving pulse signal, a control chip with relatively powerful functions and performance is required, but the cost of this solution is relatively high, and the control logic is also very complicated. Compared with the prior art, the present invention provides a chopper drive circuit, including: a main controller and an AND gate circuit; the main controller is connected to the power grid and the AND gate circuit respectively; the main controller is used to detect the power grid voltage, and output a phase-shifted wide pulse signal to the AND gate circuit based on the power grid voltage, wherein the phase-shifted wide pulse signal is a pulse signal with a preset offset angle with the power grid synchronization point; the main controller is also used to output a preset PWM signal to the AND gate circuit, and reset the preset PWM signal when outputting the phase-shifted wide pulse signal, wherein the first pulse of the preset PWM signal is a high level, and the holding time is longer than that of the remaining pulses; the AND gate circuit is used to output a chopper drive signal based on the phase-shifted wide pulse signal and the preset PWM signal. The present invention utilizes a main controller to generate a phase-shifted wide pulse signal and a preset PWM signal, and controls the first high-frequency pulse of the preset PWM signal to be synchronized with the phase-shifted wide pulse signal, and obtains a chopping drive signal through an AND gate circuit. There is no need to use expensive control chips or other drive synchronization circuits, which simplifies the system hardware design, reduces production costs, and makes the phase-shift trigger synchronization more accurate. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0016] Figure 1 A schematic diagram of the structure of a chopper drive circuit provided by an embodiment of the present invention;

[0017] Figure 2 A schematic structural diagram of an optional chopper drive circuit provided in an embodiment of the present invention;

[0018] Figure 3 A single-phase grid thyristor trigger topology diagram provided by an embodiment of the present invention;

[0019] Figure 4 A schematic diagram of a single-phase power grid thyristor chopper trigger provided by an embodiment of the present invention;

[0020] Figure 5 A schematic structural diagram of another optional chopper drive circuit provided in an embodiment of the present invention;

[0021] Figure 6 A three-phase power grid thyristor trigger topology diagram provided by an embodiment of the present invention;

[0022] Figure 7 A schematic diagram of a three-phase power grid thyristor chopper trigger provided by an embodiment of the present invention;

[0023] Figure 8 A flow chart of a chopping drive method provided by an embodiment of the present invention;

[0024] Fig. 9 A schematic diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0026] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0027] Some embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0028] In the prior art, if a controller is used to generate a high-frequency driving pulse signal, a control chip with more powerful functions and performance will be required, and the internal timing interrupt system will be very complicated and costly. The conventional practice is to use a controller to send a phase-shifted wide pulse signal, and an external hardware circuit (such as a 555 oscillator) generates a high-frequency signal and generates a square wave in the form of a high-frequency pulse with the above-mentioned phase-shifted wide pulse signal to drive the subsequent pulse transformer. However, the above method requires the support of an external complex hardware circuit, and synchronization with the starting wide pulse sent by the controller will require a more complex processing method, and it cannot be guaranteed that the conduction of the pulse transformer can be effectively triggered. In view of this, the present invention provides a chopper drive circuit to alleviate the technical problems mentioned above.

[0029] Embodiment 1

[0030] The embodiment of the present invention provides a chopper drive circuit, such as Figure 1 As shown, it includes: a main controller 100 and an AND gate circuit 200; the main controller 100 is connected to the power grid 300 and the AND gate circuit 200 respectively.

[0031] The main controller 100 is used to detect the grid voltage and output a phase-shifted wide pulse signal to the AND gate circuit 200 based on the grid voltage, wherein the phase-shifted wide pulse signal is a pulse signal having a preset offset angle with the grid synchronization point.

[0032] The main controller 100 is also used to output a preset PWM signal to the AND gate circuit 200, and reset the preset PWM signal when outputting a phase-shifted wide pulse signal, wherein the first pulse of the preset PWM signal is high level and is maintained longer than the remaining pulses.

[0033] The AND gate circuit 200 is used to output a chopping drive signal based on the phase-shifted wide pulse signal and the preset PWM signal.

[0034] Specifically, the chopper drive circuit provided in the embodiment of the present invention is mainly used to trigger and control the pulse transformer of the thyristor, and specifically includes a main controller 100 and an AND gate circuit 200 connected to the main controller 100. The main controller 100 is also connected to a power grid 300. The power grid input can be single-phase, three-phase or even multi-phase. The main controller 100 generates an adjusted phase-shifted wide pulse signal after detecting the power grid voltage. The phase-shifted wide pulse signal is a pulse signal with a preset offset angle with the power grid synchronization point. It is generated after closed-loop adjustment by detecting the output voltage and current, and can be moved to the required conduction position.

[0035] In order to make the phase-shift trigger synchronization more accurate, the embodiment of the present invention uses the main controller 100 to output a preset PWM signal of a high-frequency duty cycle to the AND gate circuit 200, and at the starting point of the phase-shift wide pulse signal, the preset PWM signal is immediately reset at the same time, and a high-frequency switching cycle is forced to be pulled up, that is, the first pulse of the preset PWM signal is a high level, and the retention time is longer than that of the remaining pulses. After receiving the above-mentioned phase-shift wide pulse signal and the preset PWM signal, the AND gate circuit 200 calculates the two phases and outputs a chopping drive signal. The chopping drive signal is a series of ordered pulse sequence strings, which are synchronized with the phase-shift wide pulse signal, and the overall width is equivalent to the phase-shift wide pulse signal. The first pulse of the pulse sequence string maintains a wider chopping width.

[0036] In the embodiment of the present invention, the main controller 100 resets the preset PWM signal when outputting the phase-shifted wide pulse signal, and the first pulse of the preset PWM signal is at a high level and is maintained longer than the remaining pulses, which has the following two advantages: first, the first pulse and the phase-shifted wide pulse signal are turned on at the same time, and can also be turned on and triggered at the same time after passing through the AND gate circuit 200, which can ensure the accuracy of the phase-shifted time; secondly, the first pulse of the preset PWM signal is maintained for a longer time than the remaining pulses, which can more effectively trigger the thyristor, and will not cause triggering failure due to the influence of grid harmonics, etc. The subsequent high-frequency pulses with a low duty cycle can also effectively reduce the driving power consumption.

[0037] In the prior art, in order to obtain a high-frequency driving pulse signal, a control chip with relatively powerful functions and performance is required, but the cost of this solution is relatively high, and the control logic is also very complicated. Compared with the prior art, the present invention provides a chopper drive circuit, including: a main controller 100 and an AND gate circuit 200; the main controller 100 is connected to the power grid and the AND gate circuit 200 respectively; the main controller 100 is used to detect the power grid voltage, and output a phase-shifted wide pulse signal to the AND gate circuit 200 based on the power grid voltage, wherein the phase-shifted wide pulse signal is a pulse signal with a preset offset angle with the power grid synchronization point; the main controller 100 is also used to output a preset PWM signal to the AND gate circuit 200, and reset the preset PWM signal when outputting the phase-shifted wide pulse signal, wherein the first pulse of the preset PWM signal is a high level, and the holding time is longer than that of the remaining pulses; the AND gate circuit 200 is used to output a chopper drive signal based on the phase-shifted wide pulse signal and the preset PWM signal. The present invention utilizes the main controller 100 to generate a phase-shifted wide pulse signal and a preset PWM signal, and controls the first high-frequency pulse of the preset PWM signal to be synchronized with the phase-shifted wide pulse signal, and obtains a chopping drive signal through an AND gate circuit 200. There is no need to use expensive control chips or other drive synchronization circuits, which simplifies the system hardware design, reduces production costs, and makes the phase-shift trigger synchronization more accurate.

[0038] The chopper drive circuit provided by the embodiment of the present invention is briefly described above, and some specific applications are described in detail below.

[0039] From the above description, it can be seen that the chopper drive circuit provided in the embodiment of the present invention is suitable for single-phase, three-phase or even multi-phase power grids, and is mainly used to trigger and control the pulse transformer of the thyristor. The thyristor power unit can also be a single-phase, three-phase or even multi-phase topology according to the actual topology. After the thyristor adjusts the conduction of the grid voltage, it supplies power to the subsequent load, thereby achieving the purpose of controlling the load output power.

[0040] In an optional embodiment, if Figure 2 As shown, if the power grid is a single-phase power grid, the AND gate circuit 200 includes: a first AND gate and a second AND gate.

[0041] The first input end of the first AND gate is used to receive the first phase-shifted wide pulse signal output by the main controller 100; the second input end of the first AND gate is used to receive the preset PWM signal; the output end of the first AND gate is used to output the first chopping drive signal.

[0042] The first input end of the second AND gate is used to receive the second phase-shifted wide pulse signal output by the main controller 100; the second input end of the second AND gate is used to receive the preset PWM signal; the output end of the second AND gate is used to output the second chopping drive signal.

[0043] Specifically, if the chopper drive circuit is applied to a single-phase power grid, the single-phase power grid thyristor trigger topology diagram is as follows: Figure 3 shown. Figure 2 In the chopper drive circuit shown, KP1 represents the first phase-shifted wide pulse signal, KP2 represents the second phase-shifted wide pulse signal, ZB represents the preset PWM signal, And1 represents the first AND gate, And2 represents the second AND gate, KQ1 represents the first chopper drive signal, and KQ2 represents the second chopper drive signal. If the chopper drive circuit is used to trigger the pulse transformer of the thyristor, KQ1 and KQ2 are controlled to be output to the pulse transformer after the post-stage enhanced load drive, and finally output to the corresponding thyristor VT drive port to drive the thyristor to be turned on. Figure 4 The schematic diagram of single-phase power grid thyristor chopper triggering is shown. Figure 4 In the example, the grid synchronization point is the zero-crossing point, and the preset offset angle is 90 degrees.

[0044] In an optional embodiment, if Figure 5 As shown, if the power grid is a three-phase power grid, the AND gate circuit 200 includes: a third AND gate, a fourth AND gate, a fifth AND gate, a sixth AND gate, a seventh AND gate and an eighth AND gate.

[0045] The first input terminal of the third AND gate is used to receive the third phase-shifted wide pulse signal output by the main controller 100; the second input terminal of the third AND gate is used to receive the preset PWM signal; and the output terminal of the third AND gate is used to output the third chopping drive signal.

[0046] The first input terminal of the fourth AND gate is used to receive the fourth phase-shifted wide pulse signal output by the main controller 100; the second input terminal of the fourth AND gate is used to receive the preset PWM signal; the output terminal of the fourth AND gate is used to output the fourth chopping drive signal.

[0047] The first input terminal of the fifth AND gate is used to receive the fifth phase-shifted wide pulse signal output by the main controller 100; the second input terminal of the fifth AND gate is used to receive the preset PWM signal; the output terminal of the fifth AND gate is used to output the fifth chopping drive signal.

[0048] The first input terminal of the sixth AND gate is used to receive the sixth phase-shifted wide pulse signal output by the main controller 100; the second input terminal of the sixth AND gate is used to receive the preset PWM signal; the output terminal of the sixth AND gate is used to output the sixth chopping drive signal.

[0049] The first input terminal of the seventh AND gate is used to receive the seventh phase-shifted wide pulse signal output by the main controller 100; the second input terminal of the seventh AND gate is used to receive the preset PWM signal; and the output terminal of the seventh AND gate is used to output the seventh chopping drive signal.

[0050] The first input terminal of the eighth AND gate is used to receive the eighth phase-shifted wide pulse signal output by the main controller 100; the second input terminal of the eighth AND gate is used to receive the preset PWM signal; and the output terminal of the eighth AND gate is used to output the eighth chopping drive signal.

[0051] Specifically, if the chopper drive circuit is applied to a three-phase power grid, the three-phase power grid thyristor trigger topology diagram is as follows: Figure 6 shown. Figure 5 In the chopper drive circuit shown, KP3 represents the third phase-shifted wide pulse signal, KP4 represents the fourth phase-shifted wide pulse signal, KP5 represents the fifth phase-shifted wide pulse signal, KP6 represents the sixth phase-shifted wide pulse signal, KP7 represents the seventh phase-shifted wide pulse signal, KP8 represents the eighth phase-shifted wide pulse signal, ZB represents the preset PWM signal, KQ3 represents the third chopper drive signal, KQ4 represents the fourth chopper drive signal, KQ5 represents the fifth chopper drive signal, KQ6 represents the sixth chopper drive signal, KQ7 represents the seventh chopper drive signal, and KQ8 represents the eighth chopper drive signal. If the chopper drive circuit is used to trigger and control the pulse transformer of the thyristor, KQ3 to KQ8 are controlled to be output to the pulse transformer after the post-stage enhanced load drive, and finally output to the corresponding thyristor VT drive port to drive the thyristor to be turned on. Figure 7 The schematic diagram of thyristor chopper triggering for three-phase power grid is shown. Figure 7 In the example, the grid synchronization point is the zero-crossing point, and the preset offset angle is 90 degrees.

[0052] In an optional implementation, the chopper drive circuit further includes: an amplifier circuit, the amplifier circuit being connected to the AND gate circuit 200;

[0053] The amplifier circuit is used to receive the chopping drive signal output by the AND gate circuit 200 and amplify the chopping drive signal so that the amplified chopping drive signal drives the pulse transformer.

[0054] In an optional implementation, the holding time of the first pulse of the preset PWM signal is 100us. The preset PWM signal is a periodic high-frequency pulse of 10kHz and 30% duty cycle except the first pulse. The embodiment of the present invention does not specifically limit the holding time of the first pulse and the frequency and period of the remaining pulses, and the user can set them according to actual needs.

[0055] In an optional implementation, the main controller 100 includes: a single chip microcomputer. If the main controller 100 is a single chip microcomputer, the PWM module of the single chip microcomputer is controlled to output a preset PWM signal.

[0056] To sum up, the chopping drive circuit provided by the embodiment of the present invention will force the output of a high-level pulse signal with a relatively long holding time at the beginning of each phase-shifted wide pulse, and then regularly output a periodic sequence pulse signal with a preset frequency and a preset duty cycle. Each phase-shifted wide pulse is finally output as a high-frequency chopping drive signal after being phase-anded with a preset PWM signal. Through the above processing, the chopping and pulse synchronization circuit of the hardware load can be simplified. It is only necessary to use the PWM pulse module of the single-chip microcomputer and then optimize the high-frequency PWM solution through software settings to accurately and effectively control the chopping of the phase-shifted wide pulse, which simplifies the system hardware design, reduces the cost and complexity of hardware devices, and makes the phase-shift trigger synchronization more accurate.

[0057] Embodiment 2

[0058] The embodiment of the present invention further provides a chopping drive method, which is applied to the main controller in the chopping drive circuit in the above embodiment 1. Figure 8 As shown, the chopping drive method specifically includes the following steps:

[0059] Step S102 , detecting the grid voltage, and outputting a phase-shifted wide pulse signal to an AND gate circuit based on the grid voltage, wherein the phase-shifted wide pulse signal is a pulse signal having a preset offset angle with the grid synchronization point.

[0060] Step S104, outputting a preset PWM signal to the AND gate circuit, and resetting the preset PWM signal when outputting a phase-shifted wide pulse signal, so that the AND gate circuit outputs a chopping drive signal based on the phase-shifted wide pulse signal and the preset PWM signal, wherein the first pulse of the preset PWM signal is a high level and is maintained longer than the remaining pulses.

[0061] In the prior art, in order to obtain a high-frequency driving pulse signal, a control chip with relatively powerful functions and performance is required, but the cost required for this solution is relatively high, and the control logic is also very complicated. Compared with the prior art, an embodiment of the present invention provides a chopping drive method, which is applied to the main controller in the chopping drive circuit in the above-mentioned embodiment 1, including: detecting the grid voltage, and outputting a phase-shifted wide pulse signal to an AND gate circuit based on the grid voltage, wherein the phase-shifted wide pulse signal is a pulse signal with a preset offset angle with the grid synchronization point; outputting a preset PWM signal to the AND gate circuit, and resetting the preset PWM signal when outputting the phase-shifted wide pulse signal, so that the AND gate circuit outputs a chopping drive signal based on the phase-shifted wide pulse signal and the preset PWM signal, wherein the first pulse of the preset PWM signal is a high level, and the holding time is longer than that of the remaining pulses. The present invention uses the main controller to generate a phase-shifted wide pulse signal and a preset PWM signal, and controls the first high-frequency pulse of the preset PWM signal to be synchronized with the phase-shifted wide pulse signal, and obtains a chopping drive signal through an AND gate circuit, without using an expensive control chip or other drive synchronization circuit, thereby simplifying the system hardware design, reducing the production cost, and making the phase-shifted trigger synchronization more accurate.

[0062] Embodiment 3

[0063] See also Fig. 9 An embodiment of the present invention provides an electronic device, which includes: a processor 60, a memory 61, a bus 62 and a communication interface 63, wherein the processor 60, the communication interface 63 and the memory 61 are connected via the bus 62; the processor 60 is used to execute an executable module stored in the memory 61, such as a computer program.

[0064] The memory 61 may include a high-speed random access memory (RAM), and may also include a non-volatile memory, such as at least one disk memory. The communication connection between the system network element and at least one other network element is realized through at least one communication interface 63 (which may be wired or wireless), and the Internet, wide area network, local area network, metropolitan area network, etc. may be used.

[0065] The bus 62 may be an ISA bus, a PCI bus, or an EISA bus, etc. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Fig. 9 Only one bidirectional arrow is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0066] Among them, the memory 61 is used to store programs, and the processor 60 executes the program after receiving the execution instruction. The method executed by the device for flow process definition disclosed in any embodiment of the above-mentioned embodiment of the present invention can be applied to the processor 60 or implemented by the processor 60.

[0067] The processor 60 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the hardware integrated logic circuit or software instructions in the processor 60. The above processor 60 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The methods, steps and logic block diagrams disclosed in the embodiments of the present invention can be implemented or executed. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor. The steps of the method disclosed in the embodiments of the present invention can be directly embodied as a hardware decoding processor to be executed, or the hardware and software modules in the decoding processor can be executed. The software module can be located in a mature storage medium in the field such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory 61, and the processor 60 reads the information in the memory 61 and completes the steps of the above method in combination with its hardware.

[0068] A chopper drive method and a computer program product of an electronic device provided in an embodiment of the present invention include a computer-readable storage medium storing a non-volatile program code executable by a processor, wherein the instructions included in the program code can be used to execute the method described in the previous method embodiment. For specific implementation, please refer to the method embodiment, which will not be described in detail here.

[0069] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0070] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0071] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0072] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inside", "outside", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, or the positions or positional relationships in which the product of the invention is usually placed when in use. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0073] In addition, the terms "horizontal", "vertical", "overhanging" and the like do not mean that the components are required to be absolutely horizontal or overhanging, but can be slightly tilted. For example, "horizontal" only means that its direction is more horizontal than "vertical", and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0074] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0075] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A chopper drive circuit, characterized in that: Used to trigger and control the pulse transformer of the thyristor, comprising: a main controller and an AND gate circuit; the main controller is connected to the power grid and the AND gate circuit respectively; The main controller is used to detect the grid voltage and output a phase-shifted wide pulse signal to the AND gate circuit based on the grid voltage, wherein the phase-shifted wide pulse signal is a pulse signal having a preset offset angle with a grid synchronization point; The main controller is further used to output a preset PWM signal to the AND gate circuit, and reset the preset PWM signal when outputting the phase-shifted wide pulse signal, wherein the first pulse of the preset PWM signal is a high level and is maintained longer than the remaining pulses; The AND gate circuit is used to output a chopping drive signal based on the phase-shifted wide pulse signal and the preset PWM signal.

2. The chopper drive circuit according to claim 1, characterized in that: If the power grid is a single-phase power grid, the AND gate circuit includes: a first AND gate and a second AND gate; The first input end of the first AND gate is used to receive the first phase-shifted wide pulse signal output by the main controller; the second input end of the first AND gate is used to receive the preset PWM signal; the output end of the first AND gate is used to output a first chopping drive signal; The first input end of the second AND gate is used to receive the second phase-shifted wide pulse signal output by the main controller; the second input end of the second AND gate is used to receive the preset PWM signal; the output end of the second AND gate is used to output a second chopping drive signal.

3. The chopper drive circuit according to claim 1, characterized in that: If the power grid is a three-phase power grid, the AND gate circuit includes: a third AND gate, a fourth AND gate, a fifth AND gate, a sixth AND gate, a seventh AND gate and an eighth AND gate; The first input end of the third AND gate is used to receive the third phase-shifted wide pulse signal output by the main controller; the second input end of the third AND gate is used to receive the preset PWM signal; the output end of the third AND gate is used to output a third chopping drive signal; The first input end of the fourth AND gate is used to receive the fourth phase-shifted wide pulse signal output by the main controller; the second input end of the fourth AND gate is used to receive the preset PWM signal; the output end of the fourth AND gate is used to output a fourth chopping drive signal; The first input end of the fifth AND gate is used to receive the fifth phase-shifted wide pulse signal output by the main controller; the second input end of the fifth AND gate is used to receive the preset PWM signal; the output end of the fifth AND gate is used to output the fifth chopping drive signal; The first input end of the sixth AND gate is used to receive the sixth phase-shifted wide pulse signal output by the main controller; the second input end of the sixth AND gate is used to receive the preset PWM signal; the output end of the sixth AND gate is used to output the sixth chopping drive signal; The first input end of the seventh AND gate is used to receive the seventh phase-shifted wide pulse signal output by the main controller; the second input end of the seventh AND gate is used to receive the preset PWM signal; the output end of the seventh AND gate is used to output the seventh chopping drive signal; The first input end of the eighth AND gate is used to receive the eighth phase-shifted wide pulse signal output by the main controller; the second input end of the eighth AND gate is used to receive the preset PWM signal; and the output end of the eighth AND gate is used to output the eighth chopping drive signal.

4. The chopper drive circuit according to claim 1, characterized in that: The chopper drive circuit further includes: an amplifier circuit, wherein the amplifier circuit is connected to the AND gate circuit; The amplifier circuit is used to receive the chopping drive signal output by the AND gate circuit and amplify the chopping drive signal so that the amplified chopping drive signal drives the pulse transformer.

5. The chopper drive circuit according to claim 1, characterized in that: The holding time of the first pulse of the preset PWM signal is 100 us.

6. The chopper drive circuit according to claim 1, characterized in that: The preset PWM signal, except the first pulse, is a periodic high-frequency pulse of 10 kHz and a 30% duty cycle.

7. The chopper drive circuit according to claim 6, characterized in that: The main controller includes: a single chip microcomputer.

8. A chopper drive method, characterized in that: A main controller used in a chopper drive circuit according to any one of claims 1 to 7, for triggering and controlling a pulse transformer of a thyristor, comprising: Detecting a grid voltage, and outputting a phase-shifted wide pulse signal to an AND gate circuit based on the grid voltage, wherein the phase-shifted wide pulse signal is a pulse signal having a preset offset angle with a grid synchronization point; Output a preset PWM signal to the AND gate circuit, and reset the preset PWM signal when outputting the phase-shifted wide pulse signal, so that the AND gate circuit outputs a chopping drive signal based on the phase-shifted wide pulse signal and the preset PWM signal, wherein the first pulse of the preset PWM signal is at a high level and is maintained longer than the remaining pulses.

9. An electronic device comprising a memory and a processor, wherein the memory stores a computer program that can be run on the processor, wherein: When the processor executes the computer program, the steps of the method described in claim 8 are implemented.

10. A computer readable medium having a non-volatile program code executable by a processor, characterized in that: The program code causes the processor to execute the method as claimed in claim 8.

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