All-digital phase-locked loop (ADPLL) with a frequency-locked loop

Abstract

A hardware apparatus includes a frequency locked loop (FLL) including a phase loop filter and a phase locked loop (PLL), such as an all-digital PLL (ADPLL), including a frequency loop filter. When the apparatus operates a controller, the controller provides a first control signal to the FLL and a second control signal to the PLL. The apparatus can also include a digitally controlled oscillator (DCO) and a portion of one or more of the FLL and the PLL. The FLL and the PLL include first and second filters, respectively. The filters are coupled to the DCO. A time-to-digital converter (TDC) and a frequency divider receive input from the DCO. The controller forms a first loop with the first filter, the TDC, and the frequency divider, and the controller forms a second loop with the second filter, the TDC, and the frequency divider.

Description

Technical Field

[0001] The present disclosure relates generally to a phase-locked loop (PLL), and more particularly to an all-digital phase-locked loop (ADPLL). Background Art

[0002] A PLL is a device that generates an output signal with a phase that is related to the phase of a reference signal. An all-digital PLL (ADPLL) is a PLL in which all or many of its components operate digitally. Conventional ADPLLs adjust and lock their output phase to a phase based on changes in the phase of a reference signal. Conventional ADPLLs typically accelerate their frequency locking process by expanding their bandwidth, which results in large modulation of their oscillators over a wide frequency range. If the modulation of the oscillator includes the desired locking frequency, the ADPLL can phase lock to that frequency if the system is a first-order system. Higher-order systems will pull the system to the correct frequency, which may take a long time if the frequency offset is large.

[0003] Additionally, if the clock is applied to one or more digital signal processors (DSPs), there will be some frequency modulation of the output signal, which can cause timing issues. However, the frequency locking behavior of the ADPLL is selected at design time, and some frequency locking operations can have serious adverse effects on the system. For example, the locking process can cause the system DSP to be clocked to an excessively high and incorrect frequency. In other cases, timing violations may occur in the digital modules of the DSP. Additionally, when the ADPLL locking range is wide (e.g., the ratio between the maximum and minimum oscillator frequencies is on the order of 2 or greater), there is a risk of false locking. During the ADPLL locking process, false locking occurs when the phase word is entangled in some way, resulting in a stable phase difference pattern. False locking can cause the ADPLL's oscillator to produce a fluctuating output frequency or a fixed but incorrect output frequency. Summary of the Invention

[0004] According to one aspect of the present invention, there is provided a hardware device, comprising:

[0005] a frequency locked loop (FLL) including a frequency loop filter;

[0006] a phase-locked loop (PLL) including a phase loop filter; and

[0007] A controller is configured to provide a first control signal to the FLL and a second control signal to the PLL.

[0008] According to one or more embodiments, one or more of the PLL and the FLL further comprises a digitally controlled oscillator (DCO) configured to provide an output signal and a time-to-digital converter (TDC) configured to receive an input signal from the DCO.

[0009] According to one or more embodiments, the PLL is an all-digital PLL (ADPLL).

[0010] According to one or more embodiments, the hardware device further comprises a quantizer coupled as an input to the frequency loop filter and configured to receive the frequency difference signal.

[0011] According to one or more embodiments, the frequency difference signal is based on a digital frequency control word and a feedback word from a feedback word generator.

[0012] According to one or more embodiments, the FLL is configured to compensate the output signal according to a first-order stability characteristic based on the frequency difference signal.

[0013] According to one or more embodiments, the hardware device further includes: a process (P), voltage (V), and temperature (T) (PVT) filter, wherein the hardware device is configured to adapt to changes in at least one of P, V, and T in the hardware device.

[0014] According to one or more embodiments, the PLL includes an acquisition filter tuned to a first range, wherein the controller operates the acquisition filter based on detecting a phase difference exceeding a first phase difference threshold; and a tracking filter tuned to a second range narrower than the first range.

[0015] According to one or more embodiments, the hardware device further comprises a feedback word generator coupled to the TDC and the output of the frequency divider, wherein the feedback word generator is configured to provide an input signal as a digital feedback word to the controller.

[0016] According to a second aspect of the present invention, there is provided a frequency and phase tuning device, comprising:

[0017] Digitally controlled oscillator (DCO);

[0018] a first filter configured to tune an output frequency of an output signal of the DCO and to receive a frequency difference signal, the first filter being coupled to the DCO as a first input;

[0019] a second filter configured to tune an output phase of the DCO and receive a phase difference signal, the second filter coupled to the DCO as a second input;

[0020] a time-to-digital converter (TDC) receiving input from the DCO;

[0021] a frequency divider configured to receive an input from the DCO; and

[0022] a controller coupled to the first filter and the second filter and configured to provide a frequency control signal to the first filter and a phase acquisition control signal to the second filter, wherein the controller forms a frequency locked loop (FLL) with the first filter, the TDC, and the frequency divider, and wherein the controller forms a fully digital phase locked loop (ADPLL) with the second filter, the TDC, and the frequency divider.

[0023] According to one or more embodiments, the controller is configured to: compare the calculated frequency with the measured frequency; and based on the comparison, compensate the first filter to reduce the settling time of the output signal of the DCO according to a first-order settling time using the frequency signal.

[0024] According to one or more embodiments, the first filter is configured to adjust for variations in at least one of process (P), voltage (V), and temperature (T) changes in the device.

[0025] According to one or more embodiments, the frequency and phase tuning device further includes: a third filter, which is used to tune the output phase of the output signal of the DCO, wherein: the third filter is tuned to a narrower frequency range than the second filter; the third filter provides a tracking signal to the DCO; and the DCO generates the output signal based on the frequency signal, the phase acquisition signal and the tracking signal.

[0026] According to one or more embodiments, the third filter includes proportional and integral control of the phase acquisition signal provided to the DCO.

[0027] According to one or more embodiments, the controller is configured to: operate the second filter in response to detecting a frequency difference exceeding a frequency threshold; and operate the third filter in response to detecting a phase difference exceeding a phase threshold.

[0028] According to one or more embodiments, the frequency and phase tuning arrangement further comprises a quantizer coupled as input to the first filter and configured to receive the frequency difference signal.

[0029] According to one or more embodiments, the frequency difference signal is based on a digital frequency control word and a feedback word from a feedback word generator.

[0030] According to a third aspect of the present invention, there is provided a method for providing frequency-locked and phase-locked operations in a hardware device, characterized in that the method comprises:

[0031] Applying a frequency locking operation in a frequency locked loop (FLL) until the digital frequency difference is within a frequency threshold; and

[0032] A first phase locking operation is applied in an all-digital phase locked loop (ADPLL) until the digital phase difference is within a first phase threshold.

[0033] According to one or more embodiments, the method further includes applying a second phase locking operation in the ADPLL after the digital phase difference is within the first phase threshold.

[0034] According to one or more embodiments, applying the second phase-locked operation includes providing proportional and integral control to the input signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The present disclosure may be better understood, and its numerous features and advantages made apparent to those skilled in the art by referencing the accompanying drawings. The use of the same reference numbers in different drawings indicates similar or identical items.

[0036] Figure 1 is a block diagram of an apparatus having an all-digital phase-locked loop (ADPLL) and a frequency-locked loop (FLL), according to some embodiments.

[0037] Figure 2 is a block diagram of an apparatus with an ADPLL and an FLL showing additional components according to some embodiments.

[0038] Figure 3 is a graph of phase sampling in a phase-locked mode for a device having an ADPLL and an FLL according to some embodiments.

[0039] Figure 4 is a graph of phase sampling outside of phase-locked mode in a device having an ADPLL and an FLL according to some embodiments.

[0040] Figure 5 is a block diagram of an apparatus having an ADPLL and an FLL according to another embodiment.

[0041] Figure 6 is a graph of frequency sampling in a device having an ADPLL and an FLL according to some embodiments.

[0042] Figure 7 is a flow chart of a method for applying an FLL to a device having an ADPLL according to some embodiments. DETAILED DESCRIPTION

[0043] In order to avoid undesirable locking behavior and improve the overall phase-locked behavior in the hardware device, a frequency-locked loop (FLL) is combined with an all-digital phase-locked loop (ADPLL). Examples of this type of hardware device include frequency generators, clock synthesizers, wireless transceivers, and frequency and phase tuning devices. Typically, an FLL is a device or a group of components that generates an output signal whose frequency is a function of the reference frequency of a reference signal. In operation, the output frequency of the ADPLL may change occasionally or regularly depending on the application. For example, the output frequency of the ADPLL changes when the device starts and changes when changing to a new frequency, which is a common activity of devices supporting frequency hopping protocols. Both FLL and ADPLL require a convergence period so that the output frequency stabilizes at a new value.

[0044] The FLL in a hardware device typically shares components with other loops. For example, the FLL shares components with the ADPLL. During the first phase of operation, when a new reference signal is received, components comprising those common to the FLL and ADPLL are first used to tune to the new frequency. In the second phase of operation, the device is tuned to a new phase with the ADPLL, at least some of whose components are also common to the FLL. The device typically remains in the second phase of operation until a subsequent new reference frequency or frequency control signal is provided to the device and detected by the device. Then, when the reference frequency or the multiplication factor in the form of a frequency control word (FCW) changes, the device tunes to a different output frequency.

[0045] When combined with an ADPLL, an FLL provides increased sensitivity to frequency changes and faster lock times relative to conventional PLLs, thereby reducing frequency overshoots that occur during lock. The FLL utilizes available information from commonly available components in the electronics and ADPLL, such as feedback dividers and time-to-digital converters (TDCs). Once a new frequency or frequency control setting is identified, a new phase is identified and the output phase is locked to the reference phase of the reference signal based on the new reference signal or frequency control setting and the output frequency locked thereto.

[0046] According to certain embodiments of the device, frequency information is obtained from: (1) differentiating a signal from the frequency divider / TDC to derive an oscillator frequency; and (2) comparing the derived frequency to an input frequency. The oscillator target frequency can be provided digitally in the form of a frequency control word (FCW) as one implementation of a multiplication factor between a reference frequency and an oscillator frequency. The FCW determines how many oscillator cycles should occur within one reference clock cycle. When the comparison is performed for each reference clock cycle, the FCW is a target value of the oscillator clock cycles expected for a locked FLL or PLL within the reference clock cycle. The device is capable of locking to any frequency to which its oscillator can be tuned. The frequency loop gain determines how quickly the new frequency is achieved. Based on the techniques and component combinations described herein, large frequency tuning jumps and frequency overshoots are avoided. Digital circuits controlled by the ADPLL clock can be designed to have a lower maximum operating frequency.

[0047] Figure 1 FIG1 is a block diagram of an apparatus 100 having an ADPLL and an FLL according to at least one embodiment. Apparatus 100 receives a reference signal 111 having a frequency reference and a phase reference. Based on reference signal 111, apparatus 100 generates an output signal 112. Output signal 112 includes an output frequency and an output phase, labeled "fOUT." Upon receiving a new reference signal 111 having one or more of a new frequency reference and a new phase reference, apparatus 100 first tunes and locks to the new output frequency fOUT. Second, apparatus 100 tunes and locks to the new output phase.

[0048] Device 100 includes a digitally controlled oscillator (DCO) 110, a controller 120, a reference phase generator 130 labeled PHI_REF, a feedback word generator 160 labeled F_FB, a frequency loop filter 101, and a phase loop filter 102. These devices will be described in further detail below. Device 100 also includes various other components, including a frequency divider 116 labeled ÷2q, a time-to-digital converter (TDC) 104, and adders 140 and 141. The FLL includes various components, including, for example, frequency loop filter 101, DCO 110, TDC 104, and controller 120. Some components in device 100 are analog and are shown with shading. Other components in device 100 are digital and are shown without shading.

[0049] Although not shown, a frequency divider can be provided as a post-divider between the DCO 110 and the TDC 104 and the frequency divider 116. The post-divider is not required for the FLL or PLL loop operation. In some embodiments, the frequency divider actually generates the desired frequency indirectly by synthesizing a higher frequency and then dividing the higher frequency.

[0050] The controller 120 provides a frequency control signal to the frequency loop filter 101, which enables the frequency loop filter 101 to operate, and a phase control signal to the phase loop filter 102, which enables the phase loop filter 102 to operate in turn. The loop filters 101 and 102 are in a loop region 103, which includes many components that form the FLL and ADPLL, and at least some of these components are common to both the FLL and ADPLL. The frequency control signal is a first control signal from the controller 120, and the phase control signal is a second control signal from the controller 120. In some embodiments, the control signals from the controller 120 provide enable signals to switch to the frequency locked mode and the phase locked mode, respectively. In other embodiments, the control signals from the controller 120 advantageously change one or more other settings, such as gain or bandwidth settings.

[0051] In turn, the frequency loop filter 101 provides a first signal 35, labeled “CTL 1,” to the DCO 110, and the phase loop filter 102 provides a second signal 36, labeled “CTL 2,” to the DCO 110. The DCO 110 generates an output signal 112 having an output frequency, labeled fOUT, based on the first signal 35 and the second signal 36. The DCO 110 provides the same or a different signal to the TDC 104 and the frequency divider 116. The TDC 104 receives a signal from the DCO 110 as an input. The received signal can be considered a local oscillator (LO) signal. The TDC 104 produces a TDC output 33, labeled PHV_F. The frequency divider 116 produces an output 34, which is labeled PHV_1.

[0052] The combination of the signals from the TDC 104 and the frequency divider 116 results in a negative input to the phase adder 140. The phase adder 140 adds a negative value of the signal and phase from the reference phase generator 130 based on the TDC output 33 and the frequency divider output 34 to generate a phase difference signal, labeled ΔPH, which is used as an input to the phase loop filter 102. The combination of the signals from the TDC 104 and the frequency divider 116 is also provided as an input to the feedback word generator 160.

[0053] In addition to reference signal 111, a reference frequency signal 108, labeled fREF, is provided to reference phase generator 130 and feedback word generator 160 of device 100. Based on reference frequency signal 108 and input from DCO 110, feedback word generator 160 generates feedback word signal 122, which is provided to controller 120 and second adder 141. In device 100, a frequency control word (FCW) signal 121 is provided to controller 120, reference phase generator 130, and second adder 141. Second adder 141 generates a difference between FBW signal 122 and FCW signal 121, a frequency difference signal labeled Δf, and this difference serves as an input to frequency loop filter 101.

[0054] In operation, the device 100 responds to changes and disturbances in frequency and phase. Based on changes to the FCW signal 121 as input to the device 100, the controller 120 adjusts the first signal 35 provided to the DCO 110 through the frequency loop filter 101 to tune to the new frequency. The reference frequency signal can be changed via the divider setting of the reference clock, where the divider is not in Figure 1 As shown in the apparatus 100, the FCW can be changed, either via the FCW. Both changes are performed by the system user via a control interface, or by software that detects a change in the DSP's load or excessive heating of the associated integrated circuit (IC) by the DSP's power consumption, necessitating an adjustment in the DSP's clock frequency. Based on the frequency loop providing feedback from the DCO 110 in the form of FBW signal 122, the controller 120 switches between modes via corresponding control signals. The controller 120 also locks to and maintains phase lock via the phase loop filter 102 providing a second signal 36 to the DCO 110. Based on feedback provided by the DCO 110 to the phase loop filter 102 via the first adder 140, the controller 120 remains in lock mode for any particular FCW 121 signal. The apparatus 100 thus provides two-stage or two-mode operation, providing both frequency and phase lock to the apparatus. Frequency lock behavior is adjusted by tuning the behavior of the frequency loop filter 101 and the operation of the controller 120. For example, the frequency loop filter 101 is provided with one or more of proportional, integral, and derivative (PID) control. The phase-locking behavior is adjusted by tuning the behavior of the phase loop filter 102 and the operation of the controller 120. For example, the phase loop filter 102 is provided with one or more of P, I, and D control.

[0055] Figure 2is a block diagram of another device 200 similar to device 100, and illustrates additional components according to some embodiments. Device 200 is implemented as an ADPLL, and includes DCO 110, controller 220, reference phase generator 130 labeled PHI REF, feedback word generator 160, coarse filter 201 labeled COARSE, and phase loop filter 250. These devices will be described in further detail below. Device 200 also includes a variety of other components, including output divider 211 labeled ÷p, divider 116 labeled ÷2q, TDC 104, and adders 140, 141. Certain components in device 200 are analog and are shown with shading. Other components in device 200 are digital and are shown without shading.

[0056] Controller 220 provides respective control signals to coarse filter 201 and phase loop filter 250. For example, coarse filter 201 can take the form of a PVT filter that provides a mechanism to adjust the output signal of the ADPLL in device 200 to accommodate variations in each of process (P), voltage (V), and temperature (T). Coarse filter 201 acts as a frequency tuner in device 200.

[0057] Phase loop filter 250 includes two filters: acquisition filter 202 labeled ACQ, and tracking filter 203 labeled TR. Filters 202, 203 provide phase locking for the ADPLL of device 200. As described further herein, each of these filters 202, 203 is tuned or configured differently than the other, and these filters 202, 203 are used for different purposes related to phase locking. In particular, acquisition filter 202 is tuned to a wider frequency range, and thereby stabilizes faster than tracking filter 203, which is more finely tuned. The operation of acquisition filter 202 and the operation of tracking filter 203 are based on phase difference.

[0058] A respective control signal is provided from the controller 220 to each of these filters 202, 203. As illustrated, the tracking filter 203 includes certain components that provide control to the apparatus 200. For example, as illustrated, the tracking filter 203 includes proportional-integral (PI) control for phase locking to the DCO 110 in the form of a signal labeled TR, as will be appreciated by those skilled in the art. For example, the tracking filter 203 includes adders, multipliers, registers, and integrator loops to provide the PI control. The acquisition filter 202 includes its own set of adders, multipliers, registers, and integrators (not shown) to provide its own PI control. The proportional control of the acquisition filter 202 is provided in accordance with a proportional gain labeled Kp, acq 252. The integral control of the acquisition filter 202 is provided in accordance with an integral gain labeled Ki, acq 253, as will be appreciated by those skilled in the art. The tracking filter 203 includes its own set of components for PI control, including adders, multipliers, registers, integrator loops, and the like. The proportional control of the tracking filter 203 is provided in accordance with a proportional gain labeled Kp, tr 254. The integral control of the tracking filter 203 is provided in accordance with an integral gain labeled Ki, tr 255. The acquisition filter 202 provides an acquisition signal to one or more other components. The tracking filter 203 provides a tracking signal to one or more other components.

[0059] The coarse filter 201 provides a first signal labeled PVT to the DCO 110. The ACQ filter 202 provides a second signal labeled ACQ to the DCO 110. The TR filter 203 provides a third signal labeled ACQ to the DCO 110. Based on the signals, and after the output divider 211, the DCO 110 generates an output signal 112 having an output frequency labeled fOUT. The DCO 110 also provides a signal to the divider 215. In turn, the divider 215 provides a signal to the TDC 104 and the divider 116. The TDC 104 receives a signal from the divider 215 as an input. For example, the divider 215 divides its input signal by a factor of 8 before passing its output to subsequent components. The TDC 104 produces a TDC output 113 labeled PHV_F. The divider 116 receives its signal from the divider 215 as an input, and produces a divider output 114 labeled PHV_I.

[0060] The TDC 104 and the frequency divider 116 provide their respective output signals 33 and 34 to the reference phase generator 140 and the feedback word generator 160. The TDC 104 is used to increase the phase resolution. Without the TDC 104, the phase resolution would be limited by the frequency divider 116, which is clocked by the oscillator or frequency divider 215. The resolution of the frequency divider 215 is limited by the input clock period of the frequency divider. The TDC 104 increases the resolution to a higher value. For example, depending on the type of TDC, the resolution can be half the period of the DCO 110 or a fraction of the period. In at least some embodiments, the resolution of the phase loop determines the performance of the ADPLL in the device 200.

[0061] The crystal 205 provides an output signal 206 having a stable frequency (e.g., 10 MHz, 60 MHz) labeled fXTAL through an input divider 207 shown as a reference frequency signal 208, which is used to clock components of the device 200 (such as the reference phase generator 130, the feedback word generator 160, and the phase loop filter 250).

[0062] The combination of the signals from TDC 104 and frequency divider 116 serves as an input to a first adder, referred to as phase adder 140. Phase adder 140 sums the signals from reference phase generator 130 and generates a phase difference signal, labeled ΔPH, which serves as an input to phase loop filter 250. The combination of the signals from TDC 104 and frequency divider 116 is also provided as an input to feedback word generator 160. Based on reference frequency signal 208 and input from DCO 110, feedback word generator 160 generates feedback word signal 261, which is provided to controller 220 and second adder 141. In apparatus 200, frequency control word (FCW) signal 121 is provided to controller 220, reference phase generator 130, and second adder 141. The second summer 141 combines the FBW signal 122 and the FCW signal 121 to generate a frequency difference signal denoted Δf, and the difference is used as input to the coarse filter 201 .

[0063] In operation, device 200 responds to frequency and phase changes and disturbances. Based on changes to FCW signal 121, controller 220 tunes to the new frequency by adjusting the PVT signal provided to DCO 110 via coarse filter 201. The ADPLL locks to the new frequency based on a frequency loop that provides feedback from DCO 110 in the form of FBW signal 261. Controller 220 observes the frequency difference and controls the corresponding loop, including phase loop filter 250, which provides the ACQ signal and TR signal to DCO 110. Based on the phase loop from DCO 110 providing feedback to phase loop filter 250 via first adder 140, controller 220 locks and remains locked to the desired phase of any particular FCW 121 signal. Device 200 thus provides three-stage or three-mode operation to provide both frequency and phase lock. That is, each of coarse filter 201, ACQ filter 202, and TR filter 203 are sequentially operated in a one-by-one mode to adapt to a set of changing conditions in device 200. For example, first, the frequency locking behavior is adjusted by tuning the behavior of coarse filter 201 enabled by controller 220.

[0064] Although three filters 201-203 and three modes are shown in the apparatus 200, any number of filters may be implemented. Preferably, the last mode is a PLL-based mode based on phase tracking. For example, the ACQ filter 202 may include various components and may be configured to operate in a first ACQ mode, which is an FLL / frequency mode, and then in a second or PLL / phase mode, which is coarser than the phase lock of the TR filter 203. In the example described, the TR filter 203 will only provide phase lock.

[0065] The coarse filter 201 has one or more of proportional, integral, and derivative (PID) controls configured therein, such as via a proportional controller having a proportional gain 251 labeled Kp,pvt. Second, the phase-locking behavior is adjusted by adjusting the behavior of the ACQ filter 202 enabled by the controller 220. The ACQ filter 202 has one or more of P, I, and D controls configured therein. Third, the phase-locking behavior is adjusted by adjusting the behavior of the TR filter 203 enabled by the controller 220. The TR filter 203 has one or more of P, I, and D controls configured therein.

[0066] Reference phase generator 130 includes an adder 231 and a register 232, which are arranged to integrate input frequency control word (FCW) signal 121. Reference phase generator 130 provides a reference phase ramp to first adder 140. First adder 140 provides a phase error signal to phase loop filter 250. FCW signal 121 may be added to the contents of register 232 during each fREF cycle. Specifically, reference phase generator 130 generates a reference phase signal by integrating FCW signal 121 over time.

[0067] In device 200, in at least some embodiments, each register represents a quantity using any number of bits (e.g., 8 bits, 9 bits, 10 bits, 12 bits, or 16 bits). In reference phase generator 130, application of FCW signal 121 causes the contents of register 232 to increase in a staircase fashion. The value of register 232 continues to increase until it reaches the maximum representable quantity defined by the bit width of register 232. The register is then reset to its initial value (e.g., 00000000). After reset, the contents of register 232 are the modulo value of the sum of the register contents and FCW signal 121, divided by the maximum quantity defined by the bit width of register 232, or by any other set of maximum quantities less than the maximum count defined by the bit width of register 232. This behavior occurs in other registers in device 200 based on corresponding inputs, such as FCW 121.

[0068] In apparatus 200, the ramp signal is applied to an adder, such as phase error adder 140. Adder 140 subtracts a feedback phase derived from one or more of feedback frequency signal 113 and feedback phase signal 114, respectively, provided by TDC 104 and phase divider 116, from a reference phase provided by reference phase generator 130. Thus, the feedback phase is compared with the input phase. The difference between the reference phase provided by reference phase generator 130 and the feedback phase is a signal for the loop of apparatus 200 and is provided by adder 140 to phase loop filter 250.

[0069] In device 200, components 201-203 correspond to respective operating modes of device 200, including a coarse variation mode, an acquisition mode, and a tracking mode. Control inputs from respective components 201-203 to DCO 110 control the output signal of DCO 110. The output signal of DCO 110 is provided to post-divider 211, which generates output signal 112 of device 200 having an output frequency designated as fOUT. As examples of components, DCO 110 includes a capacitor bank in the case of an LC oscillator, or, in the case of a ring oscillator, via one or more current digital-to-analog controllers (DACs) or a capacitor bank. Such components provide a means of controlling the frequency of DCO 110.

[0070] In operation, each of the modes is sequentially executed by coarse filter 201, acquisition filter 202, and tracking filter 203 of phase loop filter 250, and each of the corresponding modes sequentially narrows the frequency or phase range, respectively. The first mode is a coarse mode, in which the signal from coarse filter 201 has substantial control over DCO 110. Coarse filter 201 covers the large frequency locking range of device 200 and the corresponding process spread. For example, the PVT resolution of the DCO is approximately 10 MHz / bit. At the next stage in time, the second mode is an acquisition mode, in which the signal from ACQ filter 202 has substantial control over DCO 110. In this second mode, the ACQ resolution of the DCO is, for example, on the order of 1 MHz / bit.

[0071] During the third period of time, the third mode is tracking mode, in which the signal from tracking filter 203 exerts substantial control over DCO 110. In this third mode, the DCO's tracking resolution is, for example, approximately 20-50 kHz / bit. Proportional gain 154 (Kp, acq) and integral gain 155 (Ki, acq) are provided to tracking filter 203. In stable operation, once tuned to a particular frequency with a substantially constant FCW 121, device 200 operates in tracking mode. When device 200 starts up and when device 200 tunes to a new frequency, coarse mode, ACQ mode, and TR mode are successively engaged, and device 200 is updated in each of the corresponding modes. These modes are controlled by controller 220, as shown by the signal lines to coarse, ACQ, and TR components 201-203. At least some embodiments of controller 220 include a finite state machine (FSM).

[0072] In more detail, in response to a start-up event or a change to FCW 121, controller 220 switches device 200 to coarse mode. In the first mode, the frequency control loop is activated. When the coarse frequency loop stabilizes after multiple control cycles, controller 220 switches device 200 to ACQ mode. This switching is affected by the magnitude of the difference between the previous frequency and the new frequency. According to some embodiments, device 200 switches from coarse mode to the second ACQ mode when the frequency deviation is within a frequency control threshold of plus or minus one coarse step. When the threshold is set to a larger value, the ACQ group, as an embodiment of acquisition filter 202, needs to be able to cover more than plus or minus one coarse step. Alternatively, a coarse time period can be defined. If the time period is exceeded, device 200 is assumed to have stabilized in coarse mode, and the second ACQ phase is activated.

[0073] In the second acquisition mode and the third tracking mode, device 200 is in a frequency or phase mode corresponding to an operation in which the frequency or phase difference between the reference signal and the feedback signal is used to control the output behavior of device 200. In some embodiments, a transition from one mode to the other (frequency to phase) occurs by controller 220 determining that a corresponding predefined time interval for the respective mode has expired. In operation, acquisition mode operates as part of a frequency control loop or a phase control loop. Both are possible. When the frequency difference or phase difference is less than an acquisition threshold, device 200 is assumed to have stabilized in the second acquisition mode, and device 200 transitions to the third tracking mode at that point. Alternatively, device 200 switches to tracking mode after a time interval in which the ACQ loop can be assumed to be stable.

[0074] If the device 200 is in lock mode (acquisition mode or tracking mode), the frequency difference of the frequency loop can be used to switch back to coarse mode. This can happen when the FCW 121 changes (in which case the change can also be used directly), or if other events cause the device 200 to break out of lock, such as a change in loop parameters or a change in reference frequency 208. When changing the target frequency, destructive frequency steps can be avoided if the frequency update does not start from a predefined default frequency, but from the last frequency. During device startup, the stabilization time may be very short, such as when a default value is selected (e.g., the starting point is the center of the corresponding tuning range). Generally speaking, to avoid overclocking in the DSP, it is beneficial to start from the lowest possible frequency.

[0075] Regarding the behavior of device 200, the input to the integrator of the loop filter of device 200 is incremented or decremented by a specific value, depending on whether the feedback frequency is too high or too low. When the frequency difference is used to update the loop filter and tune the DCO 110 of device 200, the loop behaves as a first-order linear loop and follows an exponential or first-order stability characteristic to reach a locked frequency. In some embodiments, a higher loop order is used to further accelerate frequency locking.

[0076] Compared to such a stable response, a conventional PLL will produce frequency overshoot or undershoot unless the conventional device is characterized by a very large damping factor. Conventional PLLs cannot detect frequency differences, but can only detect phase differences between the clock edges of the reference and feedback signals. For example, the DCO frequency may be too low, but the clock edge associated with the comparison may occur before the reference clock edge, causing the PLL to further slow down the DCO speed for a period of time until the order of the clock edges during the comparison is reversed. This effect can lead to the phenomenon that during the lock period, the DCO frequency may be affected by the error (increase or decrease) relative to the frequency target, resulting in undesirable frequency overshoot and undershoot. This effect is overcome by the embodiments described herein.

[0077] Embodiments of ADPLLs, such as the ADPLL in device 200, can be used for frequency scaling where the operating frequency changes dynamically. This is beneficial in cases where the clock frequency of a digital signal processor (DSP) can be adjusted according to a periodic timing budget, its actual workload, or the need for dynamic power saving. In these cases, the DSP can continue to operate without the need for a reset or hold operation when adjusting the clock frequency, when it is possible to avoid excessively high frequencies or frequency glitches. For implementations of the FLL of device 200, additional components such as frequency counters are not necessary. Embodiments of ADPLLs, such as the ADPLL of device 200, also utilize elements and information that are typically already available in the device, such as the feedback phase information (e.g., FBW) and the frequency control word (FCW). The differential feedback phase provides the oscillator frequency when the phase or differential phase is properly scaled, and the differential phase can be directly compared to the FCW performed in device 200 in the form of a feedback word (FBW). A switch to the next state of the locking process is established when the frequency difference is less than a threshold value for a certain time interval. If the threshold value or another threshold value is exceeded when the ADPLL of device 200 is assumed to be in lock, the condition can be considered an indication that the ADPLL of device 200 is not actually locked, since the FCW 121 or the reference frequency 208 has changed, and the ADPLL of device 200 needs to tune to the new frequency. Typically, in certain embodiments, the frequency slope of the ADPLL of device 200 is controlled by the loop gain. The shape of the ADPLL behavior is controlled by the selected control method and one or more selected parameters. Since an incorrect frequency is detected during the operation of the ADPLL of device 200, and the output frequency of the output signal 112 is stabilized in a determined manner during frequency locking, false locking is reduced or eliminated.

[0078] Figure 3is a plot 300 of phase sampling in a phase-locked mode of an ADPLL with an FLL such as in the apparatus 100, 200, according to some embodiments. In the plot 300, phase words 301 are measured with respect to time 302. A first set of points 303, generally along a first line 313, are phase words from a reference accumulator or register such as the register 232 of the reference phase generator 130. A second set of points 304, generally along a second line 314, are feedback phase words generated by a counter and a time-to-digital converter (TDC) such as the TDC 104. The slope of the points 304 represents a value consistent with the FBW 122 or FBW 261 of the ADPLL of the apparatus 100, 200. The time between successive reference phase words 303 is a reference time (TREF) 305. The distance between successive phase words 301 (plot points) is a FCW 306 corresponding to a FCW similar to the FCW 121 in the apparatus 100, 200. The maximum value 317 in the plot 300 is consistent with the size of a register such as the divider 116, where the value is based on the number of bits of 2q-1.

[0079] In a system including the apparatus 100 or the apparatus 200, the reference phase words 303 are compared to the feedback phase words 304. Because the feedback phase words 304 are generated by a counter and a TDC, the feedback phase words 304 can be available at a higher resolution than the reference clock, because the clock intervals of the DCO itself translate into more points along the second line 314 of the feedback phase words 304 compared to the number of points of the reference phase words 303 in the plot 300. If the PLL is in a phase-locked state, as shown in the plot 300, then the number of points of the second set of points 304 is a FCW times the number of points of the first set of points 303. Additionally, the distance between two points on the reference curve 303 is FCW times larger than the distance between two points on the feedback curve 304. If multiple DCO phases are used, then an additional factor can be achieved, for example, if both rising and falling edges of a DCO are used within a TDC, then the factor is 2. The measurement of the phase difference is done with only the reference frequency, which results in a phase difference 307 with a reference period TREF 305.

[0080] Additionally, as shown in the plot 300, when the system is in lock, the steepness of the reference phase word line 313 and the steepness of the feedback phase line 314 are substantially equal. When equal, the frequencies of the input signal and the feedback signal are substantially the same, and is referred to as the lock-in condition. In the apparatus 200, the phase-locked mode includes the ACQ and the TR mode. In these modes, the reference phase words 303 are compared to the feedback phase words 304. If the system is not in lock and the frequencies are different, then the steepness (slope) of the lines 303, 304 are different, as shown in the plot 300. In the apparatus 200, the phase-locked mode includes the ACQ and the TR mode. In these modes, the reference phase words 303 are compared to the feedback phase words 304. If the system is not in lock and the frequencies are different, then the steepness (slope) of the lines 303, 304 are different, as shown in the plot 300. Figure 4. In phase lock, the slope of the line of reference phase word 303 and the slope of the line of feedback phase word 304 are the same (substantially equal), and the distance between these lines is constant and may be zero depending on the implementation of the ADPLL. The distance between reference phase word 303 and feedback phase word 304 is the phase difference.

[0081] In graph 300, when the phase reference signal is differentiated, the result is FCW / Tref, which corresponds to the value of the difference between consecutive phase words 306 divided by the amount of time 305. If the feedback phase is differentiated, the result is FBW / Tref. FBW 261 is based on a number of DCO cycles within one reference cycle. That is, as shown, one DCO cycle 315 is indicated between consecutive second points 304 on line 314, as indicated in close-up 310. The vertical distance 316 between consecutive points 304 can be defined as unity (labeled '1'). FBW 307 is determined based on the value of phase word points 301 separated by a number of TDCO cycles 315 equal to one reference cycle TREFTREF 305: FBW is the ratio between vertical distance 316 and TDCO cycle 315. Once the FBW is known, the oscillator frequency of DCO 110 is thus equal to (FBW)·(fREF). From graph 300 , when device 100 or 200 is frequency locked, FBW = FCW. From graph 300 , the frequency difference Δf provided at second adder 141 is (FCW-FBW)·fREF 108. Therefore, the value of FCW-FBW can be used to control the frequency control loop in device 100 or 200. Frequency and phase lock are demonstrated in graph 300 : frequency lock is achieved when the slopes of lines 313 and 314 are equal. Phase lock is achieved when the difference between the graphs of lines 313 and 314 is constant or even zero under certain circumstances.

[0082] In operation, the frequency difference Δf is scaled by the constant Kp,pvt to update the coarse integrator of the FLL. For a first order loop, this results in Figure 6 The exponential settling behavior is explained. When calculating the difference over several reference edges, averaging the values ​​of FBW 307 and FCW 306 eliminates the effects of noise or other interference. In embodiments of apparatus 100, 200, the contents of the integrator are incremented by FCW 306 at each reference clock edge, and FCW 306 is assumed to be constant. This results in a ramp signal as shown in graph 300.

[0083] Figure 4Graph 400 of phase sampling outside of phase-locked mode in a device, such as device 100 or 200, where the device is not in phase lock. In graph 400, phase word 301 is measured relative to time 302. A first set of points 303 along a first line 313 are phase words from a reference accumulator or register, the same as in graph 300. A second set of points 404 along a second line 414 are a set of feedback phase words generated by a counter and time-to-digital converter (TDC), and the slope of points 404 represents a value consistent with FBW 122 or FBW 261 of device 100 or 200. The time between consecutive reference phase words 303 is again reference time (TREF) 305. The vertical distance between consecutive phase words 301 is FCW 306.

[0084] In graph 400, second line 414 is not parallel to first line 313. The reference frequency, in the form of FCW, does not match the feedback frequency, in the form of FBW. Specifically, this is evident in the difference 416 in the feedback word values ​​for devices 100, 200 over one DCO cycle (TDCO) 315, which is not substantially identical to the value of FCW 306. Therefore, the system in this state is not frequency-locked, and devices 100, 200 will operate in coarse mode. In devices 100, 200, the oscillator frequency is equal to FBW·fREF, and the frequency difference Δf is equal to (FCW-FBW)·fREF.

[0085] Figure 5 FIG2 is a block diagram of an apparatus 500 having an FLL according to another embodiment. Apparatus 500 is similar to apparatus 200 and includes many of the same components as apparatus 200. Apparatus 500 includes: DCO 110, controller 220, reference phase generator 130, feedback word generator 160, coarse filter 201 and phase loop filter 250, frequency divider 116, TDC 104, and adders 140 and 141. These components are described with reference to apparatus 200. Phase loop filter 250 includes acquisition filter 202 and tracking filter 203. Apparatus 500 also includes quantizer 501, located between second adder 141 and coarse filter 201. Quantizer 501 provides a quantized output to, for example, DCO 110. Coarse filter 201 acts as a frequency loop filter. Based on the operation of the quantizer 501 providing input to the coarse filter 201, the output frequency of the DCO 110 changes by the same amount from one clock cycle to the next, which results in a linear frequency output ramp from the DCO 110. The quantizer 501 provides a +1 value when the frequency difference is zero or positive. In an alternative implementation, the quantizer provides zero when the frequency difference Δf is zero. When the frequency difference Δf is negative, the quantizer 501 provides a -1 value to the coarse filter 201.

[0086] Figure 6 Graph 600 illustrates frequency sampling in a device having an ADPLL and an FLL, according to some embodiments. Graph 600 illustrates the behavior of the device 100, 200, or 500 in a frequency adjustment mode, such as a coarse mode, thereby adapting to a new frequency by changing the frequency control word 121. In graph 600, a frequency difference 601, labeled Δf, is plotted against a reference clock increment 602 after a target frequency change in the device 100, 200, or 500. For comparison, an exponentially stabilizing or converging frequency difference is illustrated by a first set of points 603 and a second set of points 604, depicting a damped sine function. A conventional first-order ADPLL can be exponentially stable, but only when the frequency is within the modulation range of the system. In conventional ADPLL systems, there is always a risk of frequency overshoot, as illustrated by point 604. If the loop bandwidth is too small, the loop will only lock onto the new frequency within a smaller frequency range than in the embodiments of the devices 100, 200, or 500 described herein. Conventional devices with higher-order loops can pull the system to the correct frequency. However, in these conventional devices, the oscillator is over-pulled and modulated, which can cause overshoot. In addition, depending on the specific frequency offset, the adjustment and output may take a relatively long time to reach the desired stable point, such as within the convergence threshold 608. In some conventional system implementations, the wide frequency range also often carries the risk of encountering a metastable state where no tuning occurs. In addition, there is a risk of leakage or another effect of the frequency change in the compensation system, and thus leakage canceling out small tuning signals. In addition, there is a potential risk of phase error patterns repeating and no tuning occurring to guide the system to the new phase or new frequency.

[0087] In the example shown, the difference between the target frequency in the form of FCW and the feedback frequency in the form of FBW exceeds 50 reference clocks 602, reducing within the convergence threshold 608 of the conventional device as shown in the first group of points 603. For the second group of points 604, the threshold can be passed several times, which may result in false lock information because the signal has not yet stabilized. In contrast, a device with an ADPLL, a quantizer and an FLL, such as device 500, is stable below 30 reference clocks as drawn by the second group of points 606. Device 500 is stable in a linear manner and is faster than a conventional device with an ADPLL that does not adopt an FLL. Devices with an ADPLL and an FLL (such as devices 100, 200) are stable in about 20 reference clocks drawn by the third group of points 605. In at least some embodiments, the ADPLL with an FLL converges to a new frequency according to first-order decay or stable behavior.

[0088] Frequency lock operation ends after a dynamically determined lock time 609, and phase lock operation begins after the time 609. For example, FLL operation of the FLL in device 200 is applied until the new frequency in the form of the new FCW 121 reaches or exceeds the convergence threshold 608. After the lock time 609, acquisition mode operates in device 200, and active control is passed to acquisition filter 202, which begins phase lock operation in device 200.

[0089] In the graph 600, the second set of points 606 includes ringing behavior in the form of ringing around zero 607. The ringing 607 occurs because the ideal frequency cannot be met by only coarse settings and using a coarse filter (such as using only the coarse filter 201). The frequency ringing 607 is eliminated by applying the acquisition mode and the tracking mode through the acquisition filter 202 and the tracking filter 203. Therefore, at least the acquisition filter 202 needs to be able to cover at least plus or minus one coarse step size. Similar ringing problems may occur in the linear stable mode. In some embodiments, ringing around zero may occur when the expected frequency is not exactly matched. When the measured frequency offset is zero, the ringing is significantly reduced when the quantizer 501 also provides a zero at the output.

[0090] In certain alternative embodiments, a binary search mechanism can be implemented in coarse filter 201 instead of first-order stabilization. While binary search can be faster than first-order stabilization, some implementations of binary search may modulate DCO 110 in undesirable ways. Furthermore, if fast locking without frequency overshoot is desired in a device, a linear stepping approach with a quantizer, as shown in the second set of points 606, can be used in devices 100, 200, or 500 with adapted loop gain and frequency offset. Assuming the DCO gain is known from calibration activities performed at startup or during product testing, the initial step size or steps at the beginning of device tuning can be large. Once the offset reaches the order of the frequency resolution of DCO 110, the frequency step size can be made smaller. In this way, faster frequency filter stabilization can be achieved. One result of this type of adaptive stabilization is equally or even faster stabilization compared to a binary search mechanism, while also avoiding overshoot in frequency plot 600. The loop gain of a device employing an ADPLL and FLL can be adjusted either by the updated step size or by the gain of the loop filter in coarse mode.

[0091] Figure 7700 is a flowchart of a method for applying an FLL to a device with an ADPLL according to some embodiments. After startup or when the FCW changes, at block 701, a device such as one of the devices 100, 200, 500 shown switches to frequency or coarse mode. The mode is a first operating mode. In the first mode, the FLL is activated and control operations are performed based on the frequency difference. In this document, FLL is synonymous with frequency control loop (FCL). At block 702, a system or device using an ADPLL and an FLL determines whether the coarse loop in coarse mode is stable by determining whether the frequency difference is within a frequency threshold. Alternatively, at block 702, a coarse time period is defined. If the coarse time period is exceeded during the application of the frequency locked operation, it is assumed that the system has stabilized in coarse mode and another phase is activated.

[0092] If the frequency difference is within the frequency threshold, then at block 703, a new mode is entered and a phase-locked operation is applied in the system. In devices such as device 200 and device 500, the system switches to one of a plurality of phase-locked modes. For example, at block 705, an acquisition operation is applied. At block 706, the system determines whether the phase difference between the reference signal and the generated oscillator signal (e.g., the output signal of the DCO) is within a first phase threshold. In some embodiments, the first phase threshold is a second threshold, where the first threshold is a frequency threshold. In certain embodiments of devices 200, 500, the system switches from coarse mode to acquisition mode when the frequency deviation is within a threshold of plus or minus one coarse step. If the frequency threshold is set to a larger value, the acquisition circuit needs to be able to cover more than plus or minus one coarse step.

[0093] At block 707, when the phase difference between the reference signal and the generated oscillator signal is within the first phase threshold, a phase tracking operation is applied until further changes occur in the system, or until a second phase threshold is reached or exceeded. For example, the further change may include receiving a new frequency control word (FCW) by the system at block 704. At block 708, the system determines whether the phase difference is within the second phase threshold. If not, the system continues to apply the phase tracking operation.

[0094] In a relatively stable state, the loop operates in tracking mode by applying tracking operations. If there are small updates in the system, the loop can return to acquisition mode as needed. If there are larger updates, the system returns to coarse mode by applying coarse filter 201. In a specific example, for apparatus 200, at block 703, the second mode of the system's loop is in phase mode, meaning that the phase difference between the reference phase and the feedback phase is used to control the loop in the system. According to at least some embodiments, the modes (coarse mode, acquisition mode, and tracking mode) are controlled by exceeding corresponding thresholds for a certain minimum time or defined time interval. According to some alternative embodiments, acquisition mode operates as a second frequency control loop rather than the first phase control loop as in coarse mode. Detecting the frequency difference of the frequency loop during phase lock can be used to switch back to coarse mode. This event occurs when FCW 121 changes or when another event causes the system to lose lock, such as a change in loop parameters or a change to reference frequency 208. When changing the target frequency in the system, disruptive frequency steps can be avoided when the frequency update does not start from a predefined default frequency but from the last time frequency. During startup, settling time is typically minimized when a default frequency is selected (eg, a frequency approximately in the center of the system's tuning range).

[0095] As described above, Figures 1 to 7 The configurations shown in are some of the many possible configurations for providing a frequency locked loop to an ADPLL in a device or system, and illustrative methods for operating them. The techniques described herein are applicable to a variety of configurations of components and a variety of applications. Figures 1 to 7 The configuration shown in provides a frequency control loop within or in conjunction with an ADPLL without using a dedicated frequency counter, which is a typical component of a conventional ADPLL. The FLL is able to pull the ADPLL to any frequency allowed by the oscillator without changing the loop bandwidth to a very large value and without generating frequency overshoot or clock glitches. Instead, the described embodiments provide a fast and well-controlled frequency ramp. The embodiments provide a fast locking ADPLL and device that can quickly acquire a new frequency based on an FLL or frequency detector. The embodiments can be applied to many types of devices including tuner ICs and wired and wireless data transmission systems. The embodiments are ideal for deep submicron and nanometer technologies. The described device and ADPLL, together with the frequency control loop or frequency locked loop, support frequency scaling corresponding to a system that switches the system clock to different frequencies in a controlled manner according to cycle budget requirements.

[0096] Systems that change in a controlled manner avoid over-clocking of their DSPs and avoid timing violations that can require a reset to return to normal operation. A reset is very disadvantageous because the operation is interrupted. Timing violations in digital circuits due to frequency overshoot are typically avoided by over-constraining the circuit design, which results in higher power consumption and increased circuit area of the device and its components. Using the frequency control loop described herein prevents over-clocking and avoids over-constrained and over-designed systems.

[0097] In general, conventional systems and conventional ADPLLs use an additional frequency divider for frequency measurement, compute the oscillator frequency from the feedback phase, and perform a binary search to search for the new frequency. These conventional features result in a large frequency overshoot and can result in a large frequency glitch in the DSP. In addition, some conventional ADPLLs determine the phase error from the DCO output frequency and perform a successive approximation search. Such operations result in an overshoot of the output frequency from the DCO. Thus, conventional ADPLLs cannot be used for frequency scaling of the DSP without allowing for a reset and interruption of operation or without requiring over-constraining and increased design margins. Some conventional ADPLLs exploit the difference between frequency divider states to derive frequency information but do not use a TDC. In these ADPLLs, the frequency information is less accurate and the ringing of the oscillator frequency is increased. In some cases, dead zones and arbitrary lock can occur. For the next loop state with higher resolution, the frequency offset that should normally tend to stabilize can become larger and thus take longer. Although such behavior can be improved by taking an average, the use of an average lengthens the undesirable settling time.

[0098] Note that not all of the activities or elements described above can be required, that a portion of a specific activity or device can not be required, and that one or more further activities or including elements can be performed, in addition to those described, when a specific example is described. Still further, the order in which activities are listed are not necessarily the order in which they are performed. Also, the concepts have been described with reference to particular embodiments. Nevertheless, one of ordinary skill in the art will appreciate that various modifications and changes can be made without deviating from the scope of the present disclosure as set forth in the following claims. Accordingly, the specification and drawings are to be regarded in an illustrative, rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present disclosure.

[0099] The benefits, other advantages and solutions to problems have been described above with respect to specific embodiments. However, the benefits, advantages, solutions to problems, and any features that may cause any benefit, advantage or solution to appear or become more significant should not be construed as key, required or essential features of any or all of the claims. Moreover, the specific embodiments disclosed above are illustrative only, as the disclosed subject matter may be modified and practiced in different but equivalent manners by those skilled in the art having the benefit of the teachings herein. No limitation is intended to the details of the configuration or design shown herein, except as described in the claims below. Therefore, it is apparent that the specific embodiments disclosed above may be changed or modified, and all such variations are considered to be within the scope of the disclosed subject matter. Therefore, the protection sought herein is set forth in the claims below.

Claims

1. A hardware device, characterized in that: include: a frequency locked loop (FLL) including a frequency loop filter; a phase-locked loop (PLL) including a phase loop filter; as well as a controller configured to provide a first control signal to the FLL and a second control signal to the PLL; A quantizer is coupled as an input to the frequency loop filter and is configured to receive a frequency difference signal based on a digital frequency control word and a feedback word from a feedback word generator.

2. The hardware device according to claim 1, wherein: One or more of the PLL and the FLL additionally comprises: a digitally controlled oscillator (DCO) configured to provide an output signal; and A time-to-digital converter (TDC) is configured to receive an input signal from the DCO.

3. The hardware device according to claim 1, wherein: The PLL is an all-digital PLL (ADPLL).

4. The hardware device according to claim 1, wherein: The FLL is configured to: Based on the frequency difference signal, the output signal is compensated according to a first-order stability characteristic.

5. The hardware device according to claim 1, wherein: Also includes: A process (P), voltage (V), and temperature (T) (PVT) filter, wherein the hardware device is configured to accommodate variations in at least one of P, V, and T in the hardware device.

6. The hardware device according to claim 1, wherein: The PLL comprises: an acquisition filter tuned to a first range, wherein the controller operates the acquisition filter based on detecting a phase difference exceeding a first phase difference threshold; and A tracking filter is tuned to a second range narrower than the first range.

7. A frequency and phase tuning device, characterized in that: include: Digitally controlled oscillator (DCO); a first filter configured to tune an output frequency of an output signal of the DCO and to receive a frequency difference signal based on a digital frequency control word and a feedback word from a feedback word generator; the first filter being coupled to the DCO as a first input; a second filter configured to tune an output phase of the DCO and receive a phase difference signal, the second filter coupled to the DCO as a second input; a time-to-digital converter (TDC) receiving input from the DCO; a frequency divider configured to receive an input from the DCO; as well as a controller coupled to the first filter and the second filter and configured to provide a frequency control signal to the first filter and a phase acquisition control signal to the second filter, wherein the controller forms a frequency locked loop (FLL) with the first filter, the TDC, and the frequency divider, and wherein the controller forms a fully digital phase locked loop (ADPLL) with the second filter, the TDC, and the frequency divider.

8. A method for providing frequency-locked and phase-locked operation in a hardware device, characterized in that: The method comprises: Applying a frequency locking operation in a frequency locked loop (FLL) until the digital frequency difference is within a frequency threshold; and applying a first phase locking operation in an all-digital phase-locked loop (ADPLL) until a digital phase difference is within a first phase threshold; The quantizer is coupled as an input to the frequency loop filter, receiving a frequency difference signal based on the digital frequency control word and a feedback word from the feedback word generator.

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