Method and apparatus for a phase locked loop

Abstract

The PLL uses a virtual clock signal during delay and / or startup to maintain the closed loop of the PLL and allows the phase / frequency of the PLL output to be adjusted through a feedback divider during the delay / startup period when the reference clock provided to the PLL is not available. The virtual clock signal is a series of digital values ​​separated by a time period, where the digital values ​​indicate a transition of the virtual clock signal, and the time period corresponds to a period of the virtual clock signal. The selector circuit selects the virtual clock signal in the delay or startup mode as the digital reference clock signal and another reference clock signal in normal operation.

Description

Technical Field

[0001] The description herein relates to a phase-locked loop (PLL), and more particularly to the use of a virtual clock in a PLL. Background Art

[0002] Figure 1 A high-level block diagram of a typical phase-locked loop (PLL) 100 is shown, which has the ability to switch between reference clock signals INx 101 and INy 103 to generate a PLL output signal OUT 105, which is phase-locked to the currently selected reference clock signal. The PLL operates by continuously comparing the phase of the feedback (fb) clock signal 107 and the reference clock signal (ref) 109 in the phase and frequency detector (PFD) 111, and adjusting the phase of OUT 105 to keep the OUT phase aligned with the selected reference clock signal. The output divider 115 (R divider) divides the output 118 of the digitally controlled oscillator (DCO) 119 to generate OUT 105. The feedback divider 117 divides the output 118 of the DCO 119 to generate the feedback signal 107.

[0003] Some applications require control of the phase of the PLL output. Phase adjustment can be performed in various locations in the PLL. For example, in PLL 100, the phase adjustment of OUT 105 can be performed in either DCO 119, R divider 115 or M divider 117. Adjusting DCO 119 or R divider 115 has its disadvantages. The adjustment is immediately observed at the output of the PLL, which is rough and not filtered by the PLL loop bandwidth. Using the R divider requires the user to implement a filter externally so that OUT meets the required vibration and / or other noise requirements. The phase adjustment on the M divider 117 will be loop filtered and make the user interface simpler. The user specifies the phase adjustment to be performed, and OUT transitions to a new phase according to the user's needs.

[0004] If a signal loss is detected on one of the reference clock signals INx 101 or INy 103, the PLL switches to use the other input reference clock signal as the reference clock signal. The signal loss state can be based on the complete absence of the input reference clock signal or the attenuation of the signal, so that the other input reference clock signal is determined to be a better reference signal. However, sometimes a signal loss state can be detected on both the input reference clock signals INx and INy. In this case, the PLL enters a so-called holdover. Some systems use a single input reference clock signal, and the signal loss causes a delay.

[0005] Delay (the behavior of the PLL when no input is activated) is traditionally achieved by covering the output of the loop filter, interrupting the PLL loop and operating in open-loop mode. For example, for PLL 100, if both INx and INy fail, the traditional method is that the selector circuit 127 provides a delay control value 125, which is the average value of the previous loop filter value within a predetermined time. By selecting the delay control value 125 in the selector circuit 127, the DCO 119 continues to output a clock signal that allows the system to remain operational. However, selecting the delay control value 125 in the selector circuit 127 also disconnects the loop because the feedback through the feedback divider has no effect on the output of the DCO. Therefore, during the delay period, the phase adjustment on the M divider will not be observed at the output of the PLL because the loop is open.

[0006] Therefore, it is desirable to improve the delay mechanism in a PLL by providing a phase adjustment capability regardless of whether the PLL is in a delay state. Summary of the invention

[0007] Thus, in one embodiment, a method includes using a virtual clock signal as a reference clock signal for a phase-locked loop, wherein the virtual clock signal is a series of time stamps separated by a time period, the time stamps corresponding to corresponding transitions of the virtual clock signal, and the time period corresponding to a period of the virtual clock signal.

[0008] In another embodiment, the phase locked loop includes a virtual clock signal generator for providing a virtual clock signal, the virtual clock signal being a series of time stamps separated by a time period, the time stamps corresponding to respective transitions of the virtual clock signal, and the time period corresponding to a period of the virtual clock signal. A selector circuit selects the virtual clock signal as a reference clock signal instead of a second reference clock signal for use by a phase and frequency detector of the phase locked loop. The second reference clock signal is based on the input reference clock signal.

[0009] In another embodiment, an apparatus includes a virtual clock signal generator that provides a virtual clock signal, the virtual clock signal being a series of digital values ​​separated by a time period, the digital values ​​indicating respective transitions of the virtual clock signal, and the time period corresponding to one period of the virtual clock signal. A selector circuit selects the virtual clock signal as a digital reference clock signal in a first mode and a second reference clock signal in a second mode. A phase and frequency detector (PFD) is coupled to receive the reference clock signal and a feedback signal and to provide a PFD output signal indicating a difference between the reference clock signal and the feedback signal. A loop filter is coupled to the output of the phase and frequency detector to generate a loop filter output signal. An oscillator generates an oscillator output signal and is coupled to the loop filter output signal. A feedback divider is coupled to the oscillator output signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] By referencing the accompanying drawings, those skilled in the art may better understand the present invention, and clearly appreciate its numerous objects, features and advantages.

[0011] Figure 1 A prior art phase locked loop is shown in which the delay is achieved by opening the loop.

[0012] Figure 2 A high level block diagram of an embodiment providing a virtually delayed clock signal is shown.

[0013] Figure 3 Additional details of an embodiment of providing a virtually delayed clock signal are shown.

[0014] Figure 4 is a flow chart illustrating the operation of the virtual delayed clock signal generation logic.

[0015] Figure 5 is an embodiment of using a virtual clock signal at startup.

[0016] Figure 6 is a flow chart illustrating the operation of the virtual clock signal generation logic at startup.

[0017] The use of the same reference symbols in different drawings indicates similar or identical items. DETAILED DESCRIPTION

[0018] Embodiments described herein utilize closed-loop methods to implement the delay in PLL, which allows the output of PLL to be adjusted and the adjustment is filtered in the loop even when PLL is in delay. Therefore, any phase adjustment can utilize the loop bandwidth of PLL and filter the adjustment, thereby more easily meeting the system requirements related to the phase / frequency changes in the delay. Alternative technology is to adjust the M divider when not in delay, and adjust the delay control value when in delay. However, this method is more difficult to implement, and requires the application of synchronous phase adjustment based on the state (delay / closed loop) of PLL. On the contrary, embodiments described herein always adjust the feedback divider (M divider) to change the phase / frequency of PLL output, regardless of whether PLL operates in delay mode.

[0019] refer to Figure 2 , shows a high-level block diagram of an embodiment that implements a closed-loop delay mode by creating a 'virtual holdover' (vHO) clock internal to the integrated circuit in which the PLL resides. When all reference clock signals input to the PLL become invalid, the device switches to using the vHO clock signal instead of entering a traditional delay with the loop open. Figure 2 , PLL 200 includes two input reference clock signals INx 201 and INy 203. Dividers 205 and 207, which are optional in some embodiments, divide the input reference clock signals and provide a selector circuit 209 with refx 206 and refy 208. The selector circuit also receives a vHO clock signal 211 from a vHO clock signal generator 212. A selector control signal 214 selects one of the reference clock signals refx 206, refy 208, or vHO clock 211 based on whether the PLL is operating in a delay mode. The PFD 215 provides the difference between the reference clock signal (ref) 218 ​​and the feedback signal 223 to a loop filter 217. The loop filter provides a control signal to a DCO 219, which generates an oscillator output signal 220 received by a feedback divider 221. While the virtual delayed clock signal is provided to the PFD and the loop is operating in a delay mode, a modulator control signal 224 can be used to adjust the phase of the output signal OUT 225. Although not in Figure 2 , but in a preferred embodiment, the vHO clock signals, refx, refy, ref and fb are all referenced Figure 3 The digital signals are described in more detail. Although in some embodiments the vHO clock generator 212 may be implemented as a DCO, this approach would cost chip real estate and power.

[0020] Figure 3 Additional details of an embodiment of providing a virtual delayed clock signal are shown. Figure 3In the illustrated embodiment, the digital PLL 300 uses a time-to-digital converter (TDC) to convert the time when a clock edge (a transition of a clock signal from high to low or from low to high) occurs into a digital representation. The PLL 300 receives INx 301 and INy 303. The frequency divider 302 receives INx 301 and provides a divided signal refx 305. The frequency divider 304 receives INy 303 and provides a divided signal refy 307. The TDC 309 receives refx 305 and converts the active edge (or both edges) of refx 305 into a digital value and provides drefx 315 to the selector circuit 316. The TDC 311 receives refy 307 and converts the active edge (or both edges) of refy 307 into a digital value and provides drefy 317 to the selector circuit 316. Depending on the selected reference clock signal, the selector circuit 316 selects either drefx or drefy as the digital reference signal dref 319 when not in the delay mode. Although shown as a multiplexer, note that the selector circuit 316 may be implemented as a slave memory ( Figure 3 315 and drefx 315. The PFD 321 receives the dref 319 and the digital feedback signal dfb 323, determines the phase difference between the signals, and provides the phase difference to the loop filter 325, which in turn controls the digital controlled oscillator (DCO) 327. The DCO 327 generates an oscillator output signal 329, which is provided to the output divider 330 and the feedback divider 331. The feedback divider 331 divides the oscillator output signal 329 and generates the feedback signal 332. The output divider 330 divides the oscillator output signal 329 and generates OUT 336. The TDC 334 receives the feedback signal 332 and generates the digital feedback signal dfb 323.

[0021] The TDC operates by sampling a counter for each active clock edge of refx and refy, thereby providing a timestamp indicating when an edge occurs. TDCs are well known in the art. Digital values ​​corresponding to clock edges can be stored in memory for a period of time, thereby providing a delay when the input reference clock signal is evaluated to determine whether the PLL should enter delay. Loss of signal detection schemes are well known in the art, and various loss of signal schemes can be used in embodiments utilizing the vHO clock signal.

[0022] In a digital PLL that uses a TDC to convert the time at which a clock edge occurs into a digital representation, the vHO clock signal can be digitally generated in the vHO clock signal generation logic 322. On a switch that uses the vHO clock signal due to entering a delay mode, the vHO clock signal can be generated by using the current clock edge of the digital feedback signal dfb 323 as the first edge of vHO and generating subsequent edges at a rate based on the delay period. The delay period can be calculated based on the difference between the two most recent adjacent feedback clock signal timestamps. In other embodiments, the delay period rate is a nominal value written to the integrated circuit at startup, for example, or stored in a non-volatile memory during manufacturing and available at startup. In other embodiments, the average period of dfb or the earlier value of the period of refx or refy before the delay or the average of the earlier values ​​provides the delay period. Once the delay period is determined, the value of the delay period is added to the timestamp associated with the first edge to generate a sum corresponding to the next edge, which is stored in the memory. When the count value associated with the TDC reaches the value corresponding to the next edge, the timestamp associated with the next edge is provided to the PFD 321. In an embodiment, while in delay, selector circuit 316 selects vHO 333 rather than drefx 315 or drefy 317. In normal operation, either drefx 315 or drefy 317 is selected. Note that rather than being implemented as a multiplexing circuit that selects the desired digital value, the selection logic may retrieve dref from the appropriate memory location associated with vHO rather than the memory location associated with drefx or drefy. In an embodiment, the use of the timestamp is delayed to provide time, for example, to evaluate the input reference signal as explained above. Thus, in an embodiment that includes a delay, when the count value associated with the TDC reaches a value corresponding to the next edge plus a predetermined delay, the timestamp associated with the next edge is provided to the PFD 321 as dref 319.

[0023] When the vHO clock signal is used in the delay, the phase of OUT 336 can be modulated using modulation control 337 and still use the loop to filter the modulation because using vHO in the delay allows for a closed loop delay solution. The modulation control can come from a source external to the integrated circuit on which the PLL 300 is placed.

[0024] Figure 4A flow chart of the operation of the virtual delayed clock generation logic 322 in delay mode is shown. In one embodiment, in 401, the virtual clock generation logic determines the delay period by comparing consecutive digital representations (timestamps) of the feedback clock edges generated by the TDC 334. Alternatively, the delay period can be determined from a stored nominal period value in which step 401 of the embodiment is omitted. In another embodiment, the delay period is based on the period of the reference clock signal drefx or drefy before the signal is lost. In 403, the virtual clock generation logic checks whether the delay has been entered. If not, the virtual clock generation logic returns to 401 to update the delay period, or if the period is obtained from the stored nominal value, the virtual clock generation logic waits to enter the delay. Once the delay is active, in 405, the vHO clock generation logic uses the latest edge of the feedback clock signal as the first edge of the delayed clock. Based on the value determined in the TDC 334, the latest edge of the feedback signal dfb is digitally represented as a timestamp ( Figure 3 ). This value is provided as dref 319 at a time corresponding to the timestamp and is stored for use in making the next clock edge. At 407, the delay period is added to the stored first edge of the delayed clock signal to generate the next edge of the delayed clock signal. When the count value associated with the TDC counter reaches the stored value corresponding to the next edge (plus a predetermined delay in some embodiments), the next edge is stored and also used as the reference clock signal dref 319 ( Figure 3 ) is provided to PFD 321. Figure 4 In the example of , only the active edge of the clock signal is tracked with the timestamp. At 409, the virtual delay clock generation logic checks whether it is time to exit the delay, for example, because one of the reference clocks has recovered. If so, the virtual delay clock generation logic exits the process and returns to 401 to determine the vHO period (if necessary) and wait for the next delay. If the delay continues, the virtual delay clock generation logic returns to 407 to generate the next edge by adding the delay period to the most recently stored edge and storing the value of the next edge. The vHO clock generation logic 322 can be implemented with digital logic to provide a combination of Figure 3 and Figure 4 The necessary functions described may be implemented in programmable logic, such as a programmable microcontroller, or in any combination of digital logic and programmable logic required to achieve the required functions.

[0025] Note that vHO can also be generated as a free-running clock at a delayed frequency. Thus, for example, the vHO clock signal can be continuously generated even when the loop is locked to a good reference clock signal. In this case, the device will switch to this clock when the other reference clock is lost due to phase accumulation by absorbing the phase offset between fb and vHO into the loop.

[0026] Although the virtual delayed clock signal has been described as being useful in delay mode, in embodiments, the virtual clock signal may be used in other applications instead of, or in conjunction with, using the virtual clock signal vHO in delay mode. One such example is using the virtual clock signal at startup, e.g., in response to a power-on reset. When the system boots up, it may take some time for the reference clock to become available and stable. In this case, the virtual clock may be used until the reference clock is available. Figure 5 , this embodiment shows the use of a virtual clock at startup in PLL 500. Figure 5 The system shown is Figure 3 Same system as shown, except Figure 3 309, 310, and 334. In addition, the virtual delayed clock generation logic 322 in has been replaced by the virtual clock generation logic 522. Note that in a system that utilizes a virtual clock at startup and delay, the virtual clock generation logic 522 and the virtual delayed clock generation 322 are typically substantially shared logic with the differences described herein. The virtual clock generation logic receives a start signal 501. The start signal is based on a power-on reset signal or other start signal. In addition, the virtual clock generation logic can wait to start generating the virtual clock until the memory location 503 storing the virtual clock signal period is written. In other embodiments, the virtual clock signal period is stored in a non-volatile memory in the integrated circuit during manufacturing. In either case, once the integrated circuit (including the TDC counter logic associated with TDC 309, 311, and 334) that provides a count value indicating the current time reaches a known and stable condition at power-on reset, the virtual clock generator samples the TDC counter at any time in response to startup and generates a digital value corresponding to the first edge of the virtual clock. Then, the selection logic generates the next virtual edge by adding the virtual clock signal period to the current virtual clock signal edge.

[0027] Figure 6is a flow chart illustrating the operation of the virtual clock generation logic 522. At 601, the virtual clock generation logic waits for a start indication. As described above, the start indication may be based on a power-on reset, a write to a virtual clock signal period memory location, or some other indication that the virtual clock generation logic should begin generating a virtual clock, such as a predetermined time after a power-on reset. Upon receiving the start indication, the virtual clock generation logic samples the TDC counters associated with the various TDCs in the system to generate a first edge of the clock signal in 603. The first edge is provided as dref 319. In 605, the virtual clock generation logic generates a next edge by adding the virtual period to the current edge and provides the next edge as dref 319 at a time corresponding to the value of the TDC counter equal to the next edge. The virtual clock period is a nominal period stored in the memory 503.

[0028] PLL 500 generates a clock signal based on dref. By operating with a virtual clock signal, PLL 500 can generate a clock at a nominal frequency more quickly, even modulating the PLL output through a feedback divider, when other reference signals are not available at startup. When the system reference clock becomes available and the system switches to the system reference clock, if PLL 500 is already generating a clock signal at the nominal frequency, PLL 500 can switch to the new reference clock signal more easily and quickly. In 607, the virtual clock generation logic determines whether the virtual clock generation logic should stop based on the availability of the reference clock signals (e.g., INx and / or INy). In other embodiments, the virtual clock generation logic stops after a predetermined time period sufficient for the rest of the system to become stable. If the virtual clock generation logic determines in 607 that the clock generation logic should continue to generate the virtual clock signal, the flow returns to 605 to generate the next edge by adding the virtual period to the current edge. The virtual clock generation logic 522 may be implemented with digital logic to provide a combination of Figure 3 and Figure 4 The necessary functions described may be implemented in programmable logic, such as a programmable microcontroller, or in any combination of digital logic and programmable logic required to achieve the required functions.

[0029] Thus, various aspects related to the use of a virtual reference clock signal have been described. The description of the invention herein is illustrative and is not intended to limit the scope of the invention as set forth in the following claims. Other changes and modifications may be made to the embodiments disclosed herein based on the description herein without departing from the scope of the invention as set forth in the following claims.

Claims

1. A method for a phase-locked loop, comprising: using a virtual clock signal as a reference clock signal for the phase locked loop, the virtual clock signal being time stamps separated by a time period, the time stamps corresponding to respective transitions of the virtual clock signal, The method further comprises: using the virtual clock signal as a reference clock signal in a delay mode in response to a signal loss of an input reference clock signal, and Edges of the virtual clock signal are generated based on edges of the feedback clock signal.

2. The method of claim 1, further comprising: The period of the virtual clock signal is determined based on the difference in time stamps between successive edges of the feedback clock signal.

3. The method of claim 1, further comprising: The period of the virtual clock signal is determined based on a nominal period value stored in an integrated circuit in which the phase locked loop is disposed.

4. The method of claim 1, further comprising: The virtual clock signal is used as a reference clock signal in response to a start condition.

5. The method of claim 4, comprising: Use of the virtual clock signal as a reference clock signal is discontinued in response to availability of an input reference clock signal.

6. The method of claim 1, further comprising: While using the virtual clock signal as the reference clock signal, the phase of the output of the phase-locked loop is modulated by adjusting the frequency division value of the feedback frequency divider of the phase-locked loop.

7. A phase-locked loop, comprising: a virtual clock signal generator for providing a virtual clock signal, the virtual clock signal being a series of time stamps separated by a time period, the time stamps corresponding to respective transitions of the virtual clock signal; as well as a selector circuit for selecting the virtual clock signal as a reference clock signal instead of another input clock signal based on an input reference clock signal for use by a phase and frequency detector of the phase locked loop, The phase and frequency detector is coupled to receive the reference clock signal and the feedback clock signal; the selector circuit is responsive to a signal loss of the input reference clock signal to use the virtual clock signal instead of another input clock signal as the reference clock signal; and The virtual clock signal generator is configured to generate edges of the virtual clock signal based on edges of the feedback clock signal.

8. The phase-locked loop according to claim 7, wherein: The reference clock signal is provided as a digital reference clock signal, which is a timestamp associated with a transition of an analog reference clock signal, and the feedback clock signal is provided as a digital feedback signal, which is another timestamp associated with a transition of the analog feedback clock signal.

9. The phase locked loop of claim 8, further comprising: A time-to-digital converter is used to convert the analog feedback clock signal into the digital feedback signal.

10. The phase-locked loop according to claim 7, in, The virtual clock signal generator generates a virtual clock signal having a period based on a nominal period value stored in an integrated circuit in which the phase locked loop is placed.

11. The phase-locked loop according to claim 8, wherein: The virtual clock signal generator is configured to determine a period of the reference clock signal based on a period of the feedback clock signal.

12. The phase-locked loop according to claim 7, wherein: The selector circuit selects the virtual clock signal as a reference clock signal in response to a start condition.

13. The phase locked loop as claimed in claim 12, wherein: The selector circuit selects the other input clock signal as the reference clock signal in response to availability of the input reference clock signal after using the virtual clock signal during the start condition.

14. The phase locked loop of claim 7, further comprising: Feedback divider circuit; and The phase-locked loop is configured to modulate the phase of the output of the phase-locked loop through the feedback divider circuit while using the virtual clock signal as the reference clock signal.

15. A phase-locked loop device, comprising: a virtual clock signal generator for providing a virtual clock signal, the virtual clock signal being a series of digital values ​​separated by a time period, the digital values ​​indicating respective transitions of the virtual clock signal; a selector circuit that selects the virtual clock signal as the digital reference clock signal in a first mode and another input clock signal as the digital reference clock signal in a second mode, the first mode being delay or start-up, and the second mode being normal operation; a phase and frequency detector (PFD) coupled to receive the digital reference clock signal and a digital feedback signal and to provide a PFD output signal indicative of a difference between the digital reference clock signal and the digital feedback signal; a loop filter coupled to the output of the phase and frequency detector to generate a loop filter output signal; an oscillator generating an oscillator output signal and coupled to the loop filter output signal; as well as a feedback divider coupled to the oscillator output signal, The virtual clock signal generator is configured to generate edges of the virtual clock signal based on edges of the digital feedback signal.

16. The device of claim 15, wherein: During the delay period, the phase of the oscillator output signal is controlled by adjusting the frequency division value of the feedback frequency divider.

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