A chip packaging structure and packaging method thereof

Abstract

The present invention discloses a chip packaging structure and a packaging method thereof, belonging to the technical field of semiconductor packaging. A chip unit body (10) of the first plastic packaging body is provided with a chip electrode (113), a passivation layer I (210), and an insulating layer I (310); an alignment mark protection block (150) is provided at the original alignment mark (120); a metal connector I is provided in an opening I (311) of the insulating layer I; a plastic packaging material I (510) plastic-seales the alignment mark protection block (150) and the metal connector I; the plastic packaging material II (610) covers the first plastic packaging body to form a second plastic packaging body; the rewiring metal layer (710) is provided above the second plastic packaging body with reference to the alignment mark protection block (150); a passivation layer II (810) and a metal connector II (900) are provided above the rewiring metal layer (710). The present invention can effectively protect the front side of the chip and improve the reliability of the product.

Description

Technical Field

[0001] The invention relates to a chip packaging structure and a packaging method thereof, belonging to the technical field of semiconductor chip packaging. Background Art

[0002] Currently common fan-out packaging products, such as Figure 1 As shown, it includes a chip unit body 100 with an active surface, the active surface of the chip unit body 100 is provided with a chip electrode 101, the active surface of the chip unit body 100 and the upper surface of the chip electrode 101 are provided with a protective layer 200, the protective layer 200 has a protective layer opening above the chip electrode 101, a metal bump 300 is arranged in the protective layer opening, and the metal bump 300 is connected to the chip electrode 101 through the protective layer opening; the back side of the chip unit body 100 is provided with a back side protective layer 600. At present, the protection of the front side of the chip packaging product is weak, and the chip function failure problem is easy to occur when the front side of the chip is subjected to a large force. Summary of the invention

[0003] The purpose of the present invention is to overcome the shortcomings of the existing packaging technology and provide a chip packaging structure with a protected chip front side and a packaging method thereof.

[0004] The object of the present invention is achieved in that:

[0005] The present invention provides a chip packaging structure, which includes a first plastic package body, a plastic package material II, a rewiring metal layer, a passivation layer II and a metal connector II.

[0006] The first plastic encapsulation body comprises a chip unit body with an active surface, an original alignment mark and a plastic encapsulation material I, the active surface of the chip unit body is provided with a chip electrode, the active surface of the chip unit body and the upper surface of the chip electrode are provided with a passivation layer I and a passivation layer I opening, an insulating layer I and an insulating layer I opening I and an insulating layer I opening II are provided in the passivation layer I opening, the insulating layer I opening I exposes the upper surface of the chip electrode, a metal connector I is provided in the insulating layer I opening I, the metal connector I is connected to the chip electrode through the insulating layer I opening I, the insulating layer I opening II exposes the original alignment mark, an alignment mark protection block is provided at the original alignment mark through the insulating layer I opening II, the plastic encapsulation material I plastic encapsulates the metal connector I and the alignment mark protection block, and its upper surface is flush with the upper surface of the metal connector I;

[0007] The plastic encapsulation material II covers the periphery and back of the first plastic encapsulation body to form a second plastic encapsulation body, the upper surface of which is flush with the upper surface of the first plastic encapsulation body;

[0008] The rewiring metal layer reference alignment mark protection block is arranged above the second plastic package body, the rewiring metal layer includes a plurality of metal layers and an insulating filling layer, the upper and lower adjacent metal layers are selectively connected, the insulating filling layer is arranged between the metal layers, the lowermost starting layer of the rewiring metal layer is provided with a lower pad, and the uppermost stopping layer is provided with an upper pad, the lower pad and the upper pad are both exposed from the insulating filling layer, wherein the lower pad is connected to the upper surface of the metal connector I of the first plastic package body;

[0009] A passivation layer II and an opening of the passivation layer II are arranged above the rewiring metal layer, and the opening of the passivation layer II exposes the upper pad of the rewiring metal layer;

[0010] A metal connector II is disposed above the passivation layer II, and the metal connector II is connected to an upper pad of the rewiring metal layer.

[0011] Optionally, the metal connector I is provided with an adhesion barrier layer, a metal seed layer I and a metal bump in sequence from bottom to top, and the adhesion barrier layer is a composite layer composed of one or two layers of material.

[0012] Optionally, the cross-sectional shape of the metal bump includes but is not limited to a rectangle, a circle or an ellipse.

[0013] Optionally, the metal seed layer I and the metal bump are an integrated structure.

[0014] Optionally, the metal connector II includes an adhesion layer, a metal seed layer II, a metal column and a solder ball in order from bottom to top.

[0015] Optionally, the metal seed layer II and the metal column are an integrated structure, and the cross-sectional shape of the metal column includes but is not limited to a rectangle, a circle or an ellipse.

[0016] The present invention also provides a packaging method for a chip packaging structure, and the process steps are as follows:

[0017] Step 1: Take an integrated circuit wafer, on the upper surface of which a chip electrode, an original alignment mark and a passivation layer I are provided, the chip electrode realizes electrical communication in the integrated circuit wafer and partially exposes the opening of the passivation layer I to form an input / output terminal of the chip electrode; the original alignment mark is also exposed through the opening of the passivation layer I;

[0018] Step 2: An insulating layer I, an opening I in the insulating layer I, an opening II in the insulating layer I, and a scribe line are provided on the passivation layer I by photolithography, wherein the opening I in the insulating layer I exposes the input / output terminal of the chip electrode, and the opening II in the insulating layer I exposes the original alignment mark, and the scribe lines are interlaced horizontally and vertically, and the integrated circuit wafer is pre-divided into a plurality of chip unit bodies arranged in an array;

[0019] Step three, by sputtering, an adhesion barrier layer is provided in the opening I of the insulating layer I; then, by sputtering, photolithography, electroplating, degumming and etching methods, a metal seed layer I and a metal bump are provided on the adhesion barrier layer in sequence; by a dispensing process or a printing process, an alignment mark protection block is provided at the original alignment mark on the front side of the wafer through the opening II of the insulating layer I;

[0020] Step 4: on the insulating layer I, the alignment mark protection block, the adhesion barrier layer, the metal seed layer I and the metal bump are firstly plastic-sealed with a plastic sealing material I to form a first plastic sealing body;

[0021] Step 5: Remove excess plastic encapsulation material I on the surface of the wafer by grinding to expose the upper surface of the metal bump to form the input / output end of the metal column;

[0022] Step 6, thinning the back side of the wafer and cutting it into a plurality of chip monomers with the front side protected;

[0023] Step 7: by means of a bonding method, the chip monomers I are placed upside down in a certain order on a carrier sheet with a temporary bonding film attached thereto;

[0024] Step 8, using plastic encapsulation material II to perform a second plastic encapsulation on the chip monomer I on the carrier to form a second plastic encapsulation body;

[0025] Step nine, removing the carrier and temporary bonding film by a debonding method, exposing the input / output ends of the metal pillars of the chip monomer, and completing the reconstructed wafer;

[0026] Step ten, through the metal rewiring process, with reference to the alignment mark protection block, a rewiring metal layer is set on the surface of the reconstructed wafer, the rewiring metal layer includes a plurality of metal layers and an insulating filling layer, the upper and lower adjacent metal layers are selectively connected, the insulating filling layer is set on the metal layer, and plays an insulating protection role, the lower starting layer of the rewiring metal layer is set with a lower pad, and the upper end layer is set with an upper pad, the lower pad and the upper pad are both exposed from the insulating layer, wherein the lower pad is connected to the upper surface of the metal connector I of the first plastic package body;

[0027] Step 11, by photolithography, a passivation layer II and an opening of the passivation layer II are provided above the rewiring metal layer, wherein the opening of the passivation layer II exposes an upper pad of the rewiring metal layer;

[0028] Step 12, again by sputtering, an adhesion layer is provided in the opening of the passivation layer II; then by sputtering, photolithography, electroplating, degumming and etching methods, metal connectors II are provided on the adhesion layer in sequence, and the metal connectors II include metal seed layer II, metal pillars and solder balls in sequence from bottom to top;

[0029] Step 13: Cut the plastic package into a plurality of chip packaging units by dicing.

[0030] Furthermore, in step three, the metal bump is formed by chemical plating.

[0031] Furthermore, in step seven, the bonding method is to coat or press a temporary bonding film on the surface of the carrier, and then bond it to the front side of the chip monomer I under the action of pressure, temperature and vacuum.

[0032] Furthermore, in step twelve, the metal column is formed by chemical plating.

[0033] Beneficial Effects

[0034] 1. The present invention first performs the first plastic sealing after completing the metal bump on the front side of the incoming wafer to form a first plastic sealing body, and exposes the upper surface of the metal bump to form an electrical connection surface; after completing the front plastic sealing, the surrounding and back sides of the chip are plastic sealed to form a second plastic sealing body, and the wafer reconstruction after cutting is completed; through the two plastic sealings, a buffering effect is formed on the chip surface, which can effectively protect the chip front side, improve the mechanical strength and rigidity of the chip front side, reduce the damage to the chip surface due to the force of the solder ball, overcome the problem of chip fragments in the packaged finished product, and improve the reliability of the product;

[0035] 2. Since plastic encapsulation material (EMC) is set on both the front and back of the chip, the stress of the two offsets each other, which is beneficial to improve the warping problem of the product, and is conducive to the subsequent metal rewiring process, ball planting process, etc., reducing the process difficulty;

[0036] 3. The present invention effectively prevents the diffusion of metal atoms such as Cu by providing an adhesion barrier layer, and effectively avoids chip function failure caused by the diffusion of metal atoms;

[0037] 4. All processes of the present invention are completed on the incoming wafer 100 with good coplanarity, which improves the uniformity of metal exposure and is conducive to improving the yield;

[0038] 5. In the process of the present invention, by setting the alignment mark protection block 150, the plastic packaging material avoids blocking the original alignment mark 120, improves the alignment accuracy of the photolithography process in the metal rewiring process, and solves the photolithography offset problem caused by wafer reconstruction. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 This is a schematic diagram of the traditional chip packaging structure;

[0040] Figure 2 A schematic cross-sectional view of a chip packaging structure of the present invention;

[0041] Figures 3A to 3M A schematic flow chart of a packaging method for a chip packaging structure of the present invention;

[0042] In the figure:

[0043] Chip unit body 10

[0044] Original registration mark 120

[0045] Position mark protection block 150

[0046] Chip electrode 113

[0047] Passivation layer Ⅰ210

[0048] Passivation layer I opening 213

[0049] Insulation layer Ⅰ310

[0050] Insulation layer Ⅰ opening Ⅰ 311

[0051] Adhesion barrier layer 410

[0052] Metal Bump 430

[0053] Plastic packaging material Ⅰ510

[0054] Plastic packaging material Ⅱ610

[0055] Rewiring metal layer 710

[0056] Lower pad 713

[0057] Upper pad 715

[0058] Passivation layer II 810

[0059] Passivation layer II opening 813

[0060] Metal connector Ⅱ900

[0061] Adhesion layer 910

[0062] Metal column 920

[0063] Solder ball 950;

[0064] Wafer 100

[0065] Slide L1

[0066] Temporary bonding film L2. DETAILED DESCRIPTION

[0067] The specific implementation modes of the present invention are described in detail below with reference to the accompanying drawings. Example

[0068] The present invention provides a chip packaging structure, which includes a first plastic packaging body, a plastic packaging material II 610 , a rewiring metal layer 710 , a passivation layer II 810 and a metal connector II 900 .

[0069] The first plastic package body includes a chip unit body 10 with an active surface, an original alignment mark 120 and a plastic package material I 510. The thickness of the chip unit body 10 is generally 25 to 150 microns. The active surface of the chip unit body 10 is provided with a chip electrode 113. The active surface of the chip unit body 10 and the upper surface of the chip electrode 113 are provided with a passivation layer I 210 and a passivation layer I opening 213. The passivation layer I opening 213 is provided with an insulating layer I 310 and an insulating layer I opening I 311 and an insulating layer I opening II 312. The insulating layer I opening I 311 exposes the upper surface of the chip electrode 113. The insulating layer I opening I 311 is provided with a metal connector I. The metal connector I is connected to the chip electrode 113 through the insulating layer I opening I 311. The metal connector I is provided with an adhesion barrier layer 410, a metal seed layer I and a metal bump 430 in sequence from bottom to top. The material of the metal seed layer I is Cu, Ni, etc., and the thickness of the metal seed layer I is 0.01~1 micron. The metal material of the metal bump 430 includes but is not limited to Ti, Cu, Ni, Sn, Au elements, and its cross-sectional shape includes but is not limited to rectangular, circular or elliptical. Preferably, the metal seed layer I and the metal bump 430 are an integral structure. The material of the adhesion barrier layer 410 is Cr, Ti, TiW, V, NiV, etc., and can be a composite layer composed of one or two layers of material, and the thickness of the adhesion barrier layer 410 is 0.1~3 microns. In addition to combining with the chip electrode 113, the adhesion barrier layer 410 also blocks the metal atoms or other metal particles of the metal seed layer I and the metal bump 430 from diffusing into the chip unit body 10.

[0070] The positions of the original alignment mark 120 and the chip electrode 113 are not fixed. According to actual design requirements, the original alignment mark 120 is set at a relatively sparse location of the chip electrode 113. Generally, one original alignment mark 120 is set for one chip unit body 10.

[0071] The insulating layer I opening II 312 exposes the original alignment mark 120 , and an alignment mark protection block 150 is disposed at the original alignment mark 120 through the insulating layer I opening II 312 . The alignment mark protection block 150 may be made of a transparent resin and has any shape.

[0072] The plastic encapsulation material I510 plastic encapsulates the metal connector I and the alignment mark protection block 150, and its upper surface is flush with the upper surface of the metal connector I; the material of the plastic encapsulation material I510 is a thermosetting polymer such as epoxy resin, phenolic resin, silica gel, amino, and unsaturated resin; in order to improve the heat dissipation capacity, the plastic encapsulation material I510 can be a composite material containing powders or fibers such as metal, ceramics, silicon oxide, and graphene.

[0073] The plastic packaging material II 610 covers the four sides and the back of the first plastic packaging body to form a second plastic packaging body, whose upper surface is flush with the upper surface of the first plastic packaging body; the material of the plastic packaging material II 610 is a thermosetting polymer such as epoxy resin, phenolic resin, silica gel, amino, and unsaturated resin; in order to improve the heat dissipation capacity, the plastic packaging material II 610 can be a composite material containing powders or fibers such as metal, ceramic, silicon oxide, and graphene.

[0074] The rewiring metal layer 710 is disposed above the second plastic package body with reference to the alignment mark protection block 150. The rewiring metal layer 710 includes a plurality of metal layers and an insulating filling layer. The upper and lower adjacent metal layers are selectively connected. The insulating filling layer is disposed between the metal layers. The lowermost starting layer of the rewiring metal layer 710 is provided with a lower pad 713, and the uppermost stopping layer is provided with an upper pad 715. The lower pad 713 and the upper pad 715 are both exposed from the insulating filling layer, wherein the lower pad 713 is connected to the upper surface of the metal connector I of the first plastic package body.

[0075] A passivation layer II 810 and a passivation layer II opening 813 are disposed above the rewiring metal layer 710 , and the passivation layer II opening 813 exposes an upper pad 715 of the rewiring metal layer 710 ;

[0076] A metal connector II 900 is disposed above the passivation layer II 810, and the metal connector II 900 is connected to the upper pad 715 of the rewiring metal layer 710. The metal connector II 900 includes an adhesion layer 910, a metal seed layer II, a metal column 920 and a solder ball 950 from bottom to top. The material of the metal seed layer II is Cu, Ni, etc., and the thickness of the metal seed layer II is 0.01 to 1 micron. Usually, the metal seed layer II and the metal column 920 are an integral structure, and the height of the metal column 920 is usually 2 to 100 microns. The metal material of the metal column 920 is usually Cu, CuNi, CuNiAu, NiAu, etc., and its cross-sectional shape includes but is not limited to rectangular, circular or elliptical. The material of the adhesion layer 910 is Cr, Ti, TiW, V, NiV, etc., and can be a composite layer composed of one or two layers of material, and the thickness of the adhesion layer 910 is 0.01 to 2 microns. The adhesion layer 910 may function to be combined with the upper pad 715 of the rewiring metal layer 710 .

[0077] The present invention provides a packaging method for a chip packaging structure, and the process steps are as follows:

[0078] Step 1, such as Figure 3AAs shown, an integrated circuit wafer 100 is taken, and a chip electrode 113, an original alignment mark 120, a passivation layer I 210, and an opening 213 of the passivation layer I are provided on the upper surface thereof. The chip electrode 113 realizes electrical communication within the integrated circuit wafer 100 and partially exposes the opening 213 of the passivation layer I to form the input / output terminal of the chip electrode 113; the original alignment mark 120 is also exposed through the opening 213 of the passivation layer I.

[0079] Step 2, such as Figure 3B As shown, an insulating layer I 310, an insulating layer I opening I 311, an insulating layer I opening II 312, and a scribe line 313 are provided on the passivation layer I 210 by photolithography, wherein the insulating layer I opening I 311 exposes the input / output end of the chip electrode 113, and the insulating layer I opening II 312 exposes the original alignment mark 120. The scribe line 313 is interlaced horizontally and vertically, and pre-divides the integrated circuit wafer 100 into a plurality of chip unit bodies 10 arranged in an array.

[0080] Step three, such as Figure 3C As shown, an adhesion barrier layer 410 is disposed in the opening I311 of the insulating layer I by sputtering; the adhesion barrier layer 410 is made of Cr, Ti, TiW, V, NiV, etc., and may be a composite layer composed of one or two layers of material, and the thickness of the adhesion barrier layer 410 is 0.1 to 3 microns.

[0081] Then, a metal seed layer I and a metal bump 430 are sequentially arranged on the adhesion barrier layer 410 by sputtering, photolithography, electroplating, degumming and etching. The metal material of the metal bump 430 includes but is not limited to Ti, Cu, Ni, Sn, and Au elements. The metal bump 430 can also be formed by chemical plating. Its cross-sectional shape is designed according to actual needs, including but not limited to rectangular, circular or elliptical. The material of the metal seed layer I is Cu, Ni, etc., and the thickness of the metal seed layer I is 0.01 to 1 micron. Usually, the metal seed layer I and the metal bump 430 are an integrated structure; in addition to combining with the chip electrode 113, the adhesion barrier layer 410 also plays a role in preventing the metal atoms or other metal particles of the metal seed layer I and the metal bump 430 from diffusing into the wafer 100.

[0082] By dispensing or printing, an alignment mark protection block 150 is set at the original alignment mark 120 on the front side of the wafer 100 through the insulating layer I opening II 312. The alignment mark protection block 150 can be made of transparent resin and has any shape, but can be clearly distinguished visually.

[0083] The alignment mark protection block 150 may be provided before or after the adhesion barrier layer 410 , the metal seed layer I and the metal bump 430 are formed.

[0084] Step 4: Figure 3D As shown, above the insulating layer I310, the alignment mark protection block 150, the adhesion barrier layer 410, the metal seed layer I and the metal bump 430 are firstly encapsulated with the encapsulation material I510 to form a first encapsulation body, and the first encapsulation body realizes the front protection of the wafer 100; the material of the encapsulation material I510 is a thermosetting polymer such as epoxy resin, phenolic resin, silica gel, amino, unsaturated resin; in order to improve the heat dissipation capacity, the encapsulation material I510 can be a composite material containing metal, ceramic, silicon oxide, graphene and other powders or fibers;

[0085] Step 5: Figure 3E As shown, the excess plastic encapsulation material I510 on the surface of the wafer 100 is removed by grinding, exposing the upper surface of the metal bump 430, forming the input / output end 431 of the metal column, and exposing the alignment mark protection block 150 at the same time.

[0086] Step 6: Figure 3F As shown, the back side of the wafer 100 is thinned and cut into a plurality of chip monomers I with the front side protected. The thickness of the chip unit body 10 formed after thinning is usually 25 to 150 microns. The thinning method can be mechanical thinning or chemical mechanical thinning.

[0087] Step 7: Figure 3G As shown, the chip monomers I are placed upside down in a certain order on a carrier L1 with a temporary bonding film L2. Preferably, the material of the temporary bonding film L2 is a thermoplastic liquid material, or a film material sensitive to UV light. The bonding method is usually to apply or press the temporary bonding film L2 on the surface of the carrier L1, and then bond it to the front side of the chip monomer I under the action of pressure, temperature, and vacuum.

[0088] Step 8: Figure 3H As shown, the chip monomer I is plastic-sealed for the second time on the carrier L1 using plastic packaging material II 610 to form a second plastic packaging body; the material of the plastic packaging material II 610 is a thermosetting polymer such as epoxy resin, phenolic resin, silica gel, amino, and unsaturated resin; in order to improve the heat dissipation capacity, the plastic packaging material II 610 can be a composite material containing powders or fibers such as metal, ceramic, silicon oxide, and graphene.

[0089] Step nine, such as Fig. 3IAs shown, the carrier L1 and the temporary bonding film L2 are removed by a debonding method to expose the input / output terminal 431 of the metal column of the chip monomer I, and the reconstructed wafer is completed. The process of reconstructing the wafer overcomes the problems of large warping and large thickness fluctuation of the chip packaging structure completed by the prior art, which reduces the process difficulty and is beneficial to improving the product yield; the debonding method can be thermal debonding, chemical debonding, laser debonding or UV debonding, etc.

[0090] Step 10: Figure 3J As shown, through the metal rewiring process, with reference to the alignment mark protection block 150, a rewiring metal layer 710 is set on the surface of the reconstructed wafer, and the rewiring metal layer 710 includes several metal layers and an insulating filling layer. The upper and lower adjacent metal layers are selectively connected, and the insulating filling layer is set on the metal layer to play an insulating protection role. The lower starting layer of the rewiring metal layer 710 is set with a lower pad 713, and the upper termination layer is set with an upper pad 715. The lower pad 713 and the upper pad 715 are both exposed from the insulating layer, wherein the lower pad 713 is connected to the upper surface of the metal connector Ⅰ of the first plastic package body; since an obvious alignment mark protection block 150 is set for precise alignment, the difficulty of the alignment process of the rewiring metal layer 710 is reduced, and the alignment accuracy is improved.

[0091] Step 11: Figure 3K As shown, a passivation layer II 810 and a passivation layer II opening 813 are disposed above the rewiring metal layer 710 by photolithography, and the passivation layer II opening 813 exposes an upper pad 715 of the rewiring metal layer 710 .

[0092] Step 12: Figure 3L As shown, an adhesion layer 910 is disposed in the opening 813 of the passivation layer II by sputtering again; the adhesion layer 910 is made of Cr, Ti, TiW, V, NiV, etc., and may be a composite layer composed of one or two layers of material, and the thickness of the adhesion layer 910 is 0.01 to 2 microns.

[0093] Then, metal connector II 900 is sequentially arranged on the adhesion layer 910 by sputtering, photolithography, electroplating, degumming and etching methods. The metal connector II 900 includes metal seed layer II, metal pillar 920 and solder ball 950 from bottom to top. The metal material of metal pillar 920 is usually Cu, CuNi, CuNiAu, NiAu, etc. The metal pillar 920 can also be formed by chemical plating. The cross-sectional shape of metal pillar 920 is designed according to actual needs, including but not limited to rectangular, circular or elliptical.

[0094] The material of the metal seed layer II is Cu, Ni, etc., and the thickness of the metal seed layer II is 0.01-1 micrometer. Usually, the metal seed layer II and the metal pillar 920 are an integrated structure, and the height of the metal pillar 920 is usually 2-100 micrometers. The adhesion layer 910 can play a role in combining with the upper pad 715 of the rewiring metal layer 710.

[0095] Step 13: Figure 3M As shown, the plastic package is cut into a plurality of chip package units by scribing. The scribing can be performed using a blade containing diamond or ceramic particles, or laser cutting can be used.

[0096] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A chip packaging structure, It is characterized in that The invention comprises a first plastic package, a plastic package II (610), a rewiring metal layer (710), a passivation layer II (810) and a metal connector II (900), wherein the first plastic package comprises a chip unit body (10) having an active surface, an original alignment mark (120) and a plastic package I (510), wherein the active surface of the chip unit body (10) is provided with a chip electrode (113), the active surface of the chip unit body (10) and the upper surface of the chip electrode (113) are provided with a passivation layer I (210) and a passivation layer I opening (213), wherein an insulating layer I (310) and an insulating layer I opening I (311) and an insulating layer I opening II (312) are provided in the passivation layer I opening (213), wherein the insulating layer I opening I (311) exposes the chip electrode The upper surface of the electrode (113), a metal connector I is arranged in the opening I (311) of the insulating layer I, the metal connector I is connected to the chip electrode (113) through the opening I (311) of the insulating layer I, the opening II (312) of the insulating layer I exposes the original alignment mark (120), an alignment mark protection block (150) is arranged at the original alignment mark (120) through the opening II (312) of the insulating layer I, the plastic encapsulation material I (510) is located above the insulating layer I (310) and plastic encapsulates the metal connector I and the alignment mark protection block (150), and the upper surface thereof is flush with the upper surface of the metal connector I, the alignment mark protection block (150) is made of a transparent resin, and the plastic encapsulation material I (510) exposes the surface of the alignment mark protection block; The plastic encapsulation material II (610) covers the periphery and back of the first plastic encapsulation body to form a second plastic encapsulation body, the upper surface of which is flush with the upper surface of the first plastic encapsulation body; The rewiring metal layer (710) is arranged above the second plastic package body with reference to the alignment mark protection block (150), the rewiring metal layer (710) comprises a plurality of metal layers and an insulating filling layer, the upper and lower adjacent metal layers are selectively connected, the insulating filling layer is arranged between the metal layers, the lowermost starting layer of the rewiring metal layer (710) is provided with a lower pad (713), and the uppermost stopping layer is provided with an upper pad (715), the lower pad (713) and the upper pad (715) are both exposed from the insulating filling layer, wherein the lower pad (713) is connected to the upper surface of the metal connector I of the first plastic package body; A passivation layer II (810) and a passivation layer II opening (813) are provided above the rewiring metal layer (710), and the passivation layer II opening (813) exposes an upper pad (715) of the rewiring metal layer (710); A metal connector II (900) is disposed above the passivation layer II (810), and the metal connector II (900) is connected to an upper pad (715) of the rewiring metal layer (710).

2. The packaging structure according to claim 1, It is characterized in that The metal connector I is provided with an adhesion barrier layer (410), a metal seed layer I and a metal bump (430) in sequence from bottom to top, and the adhesion barrier layer (410) is a composite layer composed of one or two layers of material.

3. The packaging structure according to claim 2, It is characterized in that The cross-sectional shape of the metal bump (430) is rectangular, circular or elliptical.

4. The packaging structure according to claim 2 or 3, It is characterized in that The metal seed layer I and the metal bump (430) are an integrated structure.

5. The packaging structure according to claim 1, It is characterized in that The metal connector II (900) comprises, from bottom to top, an adhesion layer (910), a metal seed layer II, a metal column (920) and a solder ball (950).

6. The packaging structure according to claim 5, It is characterized in that The metal seed layer II and the metal column (920) are an integrated structure, and the cross-sectional shape of the metal column (920) is rectangular, circular or elliptical.

7. A packaging method for a chip packaging structure, the process steps are as follows: Step 1: Take an integrated circuit wafer (100), the upper surface of which is provided with a chip electrode (113), an original alignment mark (120), a passivation layer I (210), and an opening (213) of the passivation layer I; the chip electrode (113) realizes electrical communication within the integrated circuit wafer (100) and partially exposes the opening (213) of the passivation layer I, thereby forming an input / output terminal of the chip electrode (113); the original alignment mark (120) is also exposed through the opening (213) of the passivation layer I; Step 2: an insulating layer I (310), an insulating layer I opening I (311), an insulating layer I opening II (312), and a scribe line (313) are provided on the passivation layer I (210) by photolithography, wherein the insulating layer I opening I (311) exposes the input / output end of the chip electrode (113), and the insulating layer I opening II (312) exposes the original alignment mark (120), and the scribe line (313) is vertically interlaced in the horizontal and vertical directions, so as to pre-divide the integrated circuit wafer (100) into a plurality of chip unit bodies (10) arranged in an array; Step three, by sputtering, an adhesion barrier layer (410) is provided in the opening I (311) of the insulating layer I; then, by sputtering, photolithography, electroplating, degumming and etching, a metal seed layer I and a metal bump (430) are provided on the adhesion barrier layer (410) in sequence; by a dispensing process or a printing process, an alignment mark protection block (150) is provided at the original alignment mark (120) on the front side of the wafer (100) through the opening II (312) of the insulating layer I; Step 4: on the insulating layer I (310), the alignment mark protection block (150), the adhesion barrier layer (410), the metal seed layer I and the metal bump (430) are firstly encapsulated with a plastic encapsulation material I (510) to form a first plastic encapsulation body, wherein the alignment mark protection block (150) is made of a transparent resin, and the plastic encapsulation material I (510) exposes the surface of the alignment mark protection block; Step 5: removing excess plastic encapsulation material I (510) on the surface of the wafer (100) by grinding, exposing the upper surface of the metal bump (430), and forming the input / output end (431) of the metal column; Step 6, thinning the back side of the wafer (100) and cutting it into a plurality of chip monomers (I) with the front side protected; Step 7: by means of a bonding method, the chip monomers (I) are placed upside down in a certain order on a carrier (L1) affixed with a temporary bonding film (L2); Step 8, using a plastic encapsulation material II (610) on the carrier (L1) to perform a second plastic encapsulation on the chip unit (I) to form a second plastic encapsulation body; Step nine, removing the carrier (L1) and the temporary bonding film (L2) by a debonding method, exposing the input / output end (431) of the metal column of the chip monomer (I), and completing the reconstructed wafer; Step ten, through the metal rewiring process, with reference to the alignment mark protection block (150), a rewiring metal layer (710) is set on the surface of the reconstructed wafer, the rewiring metal layer (710) includes a plurality of metal layers and an insulating filling layer, the upper and lower adjacent metal layers are selectively connected, the insulating filling layer is set on the metal layer, and plays an insulating protection role, the lower starting layer of the rewiring metal layer (710) is set with a lower pad (713), and the upper end layer is set with an upper pad (715), the lower pad (713) and the upper pad (715) are both exposed from the insulating layer, wherein the lower pad (713) is connected to the upper surface of the metal connector I of the first plastic package body; Step 11: using a photolithography method, a passivation layer II (810) and a passivation layer II opening (813) are provided above the rewiring metal layer (710), wherein the passivation layer II opening (813) exposes an upper pad (715) of the rewiring metal layer (710); Step twelve, again using a sputtering method to provide an adhesion layer (910) in the opening (813) of the passivation layer II; and then using sputtering, photolithography, electroplating, degumming and etching methods to sequentially provide metal connectors II (900) on the adhesion layer (910), wherein the metal connectors II (900) sequentially include a metal seed layer II, a metal column (920) and a solder ball (950) from bottom to top; Step 13: Cut the plastic package into a plurality of chip packaging units by dicing.

8. The packaging method according to claim 7, It is characterized in that In step three, the metal bump (430) is formed by chemical plating.

9. The packaging method according to claim 8, It is characterized in that In step seven, the bonding method is to coat or press a temporary bonding film (L2) onto the surface of the carrier (L1), and then bond it to the front side of the chip monomer (I) under the action of pressure, temperature and vacuum.

10. The packaging method according to claim 9, It is characterized in that In step twelve, the metal pillar (920) is formed by chemical plating.

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