Devices containing barrier materials in access line structures, and related methods and electronic systems

Abstract

The present application relates to a device including a barrier material in an access line structure, and related methods and electronic systems. The device includes a memory array having access lines. Each of the access lines includes an insulating material adjacent to a bottom surface and sidewalls of a substrate material, a first conductive material adjacent to the insulating material, a second conductive material adjacent to the first conductive material, and a barrier material between the first conductive material and the second conductive material. The barrier material is configured to inhibit migration of reactive species from the second conductive material.

Description

[0001] Priority claim

[0002] This application claims the benefit of the filing date of U.S. Patent Application No. 16 / 504,681, filed on July 8, 2019, entitled "APPARATUS INCLUDING BARRIER MATERIALS WITHIN ACCESSLINE STRUCTURES, AND RELATED METHODS AND ELECTRONIC SYSTEMS." Technical Field

[0003] Embodiments disclosed herein relate to microelectronic devices and microelectronic device fabrication. More specifically, embodiments of the present disclosure relate to devices including a barrier material between two conductive materials within an access line structure, and to related electronic systems and methods for forming the same. Background Art

[0004] A memory device such as a dynamic random access memory (DRAM) device includes numerous memory cells, each of which stores one bit of information. The memory cell includes a memory storage element (e.g., a capacitor) and an access device (e.g., a transistor) operably coupled to the memory storage element. The source region or drain region of the transistor is electrically connected to one of the capacitor terminals. The other of the source region or drain region of the transistor and the gate electrode are respectively connected to a digital line (e.g., a bit line) and an access line (e.g., a word line). In addition, the other capacitor terminal is connected to a reference voltage. The transistor includes a channel region between the source region and the drain region and further includes a gate configured to electrically connect the source region and the drain region to each other through the channel region. The channel region includes a semiconductor material, such as silicon. The memory cells are arranged in a matrix of rows and columns.

[0005] As DRAM technology advances, the size of memory cells has been scaled down to increase the density of memory cells. The increase in density increases the storage capacity of DRAM devices. However, the increased density also results in a decrease in the spacing between adjacent word lines, which increases the coupling effect between adjacent word lines. For example, when a row (e.g., a word line) in a matrix is ​​repeatedly activated and refreshed, noise can be injected into an adjacent row (e.g., a victim row), causing data corruption to occur in one or more memory cells in the victim row. The repeated activation and refreshing of a row is referred to as the so-called "row hammering" effect. A so-called "row hammering event" occurs when a refresh command is executed to refresh a word line adjacent to the hammered word line. A particular word line is "hammered" when it is accessed via a memory access operation, such as an active command, in a manner that may cause data errors in an adjacent word line. The leakage and parasitic currents caused by row hammering can cause data corruption in a physically adjacent row (e.g., a victim row) that is not accessed. In some cases, such leakage and parasitic currents may be the result of degradation of the gate dielectric material (e.g., gate oxide) during use and operation of the DRAM device and / or during its formation. For example, the formation of chlorine-related trapping sites during deposition of the conductive material and / or during process actions that remove (e.g., etch) portions of the conductive material may cause defects within the gate dielectric material (e.g., at its interface). Chlorine or other reactive species may diffuse into the gate dielectric material during deposition of the conductive material and form trapping sites. The trapping sites increase the threshold voltage and gate leakage in the DRAM device.

[0006] Some methods of reducing the adverse effects of row hammering on neighboring rows include refreshing neighboring rows in response to determining that a hammering event has occurred. For example, in response to determining that a particular row has been the target of repeated accesses (e.g., the row has experienced more than a threshold number of accesses within a refresh cycle), physically adjacent neighboring rows may be selected for target refresh operations, which may be referred to as row hammering refresh operations. However, in conventional DRAM devices, row hammering performance is insufficient. Summary of the invention

[0007] According to an embodiment of the present disclosure, a device includes a memory array having access lines. Each of the access lines includes an insulating material adjacent to a bottom surface and sidewalls of a substrate material, a first conductive material adjacent to the insulating material, a second conductive material adjacent to the first conductive material, and a barrier material between the first conductive material and the second conductive material. The barrier material is configured to inhibit migration of reactive species from the second conductive material.

[0008] Therefore, according to an embodiment of the present disclosure, a method of forming a device is also disclosed. The method includes forming at least one insulating material in and adjacent to a trench in a substrate material; forming a first conductive material adjacent to an exposed surface of the at least one insulating material; forming a barrier material adjacent to the first conductive material; and forming a second conductive material adjacent to the barrier material. The barrier material is formulated to reduce diffusion of reactive species from the second conductive material and into the at least one insulating material.

[0009] An electronic system according to an embodiment of the present disclosure includes an input device; an output device; a processor device operatively coupled to the input device and the output device; and a memory device operatively coupled to the processor device and including memory cells. One or more of the memory cells include one or more insulating materials adjacent to a bottom surface and sidewalls of a substrate material; a first conductive material overlying the one or more insulating materials; a barrier material overlying the first conductive material; and a second conductive material overlying the barrier material, the barrier material being formulated to prevent reactive species from diffusing from the second conductive material. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figures 1A to 1F is a simplified partial cross-sectional view illustrating various stages of forming a device including an access line structure according to an embodiment of the present disclosure;

[0011] Figure 2 is a cross-sectional view of a microelectronic device including an access line structure according to an embodiment of the present disclosure;

[0012] Figure 3 is a functional block diagram of a memory device according to an embodiment of the present disclosure;

[0013] Figure 4 is a schematic block diagram of an electronic system according to an embodiment of the present disclosure; and

[0014] Figure 5 is a graph of the row hammer performance as a function of the number of deposition cycles of the barrier material. DETAILED DESCRIPTION

[0015] A device (e.g., an electronic device, a semiconductor device, a memory device) is disclosed that includes an access line structure (e.g., a word line structure) that includes a barrier material between two conductive materials. The barrier material can be configured to reduce the migration (e.g., diffusion) of reactive species from the conductive materials. The reactive species can be generated during the manufacture of one or more of the conductive materials or during the removal action of one or more of the conductive materials. The access line structure also includes an insulating material that isolates the conductive materials of adjacent access line structures. In some embodiments, the thickness of the conductive material located adjacent to the insulating material can be relatively less than the thickness of another conductive material located in the central portion of the access line trench, and the thickness of the barrier material can be relatively less than the thickness of each of the conductive materials. The conductive material and the barrier material of the access line structure can be formed in situ using, for example, a single continuous ALD process, a single continuous CVD process, a single wafer process, or a furnace process. The barrier material can substantially inhibit (e.g., block, prevent) the formation of so-called "trapping sites" within the insulating material of the device. The device including the access line structure exhibits improved row hammering performance properties compared to conventional devices without a barrier material between two conductive materials.

[0016] The following description provides specific details, such as material composition and processing conditions, in order to provide a full description of the embodiments of the present disclosure. However, it will be understood by those skilled in the art that the embodiments of the present disclosure may be practiced without adopting these specific details. In fact, the embodiments of the present disclosure may be practiced in conjunction with conventional semiconductor manufacturing techniques used in the semiconductor industry. In addition, the description provided below does not form a complete process flow for manufacturing equipment. The structures described below do not form a complete microelectronic device. Only those process actions and structures necessary for understanding the embodiments of the present disclosure are described in detail below. Additional actions to form a complete microelectronic device may be performed by conventional manufacturing techniques.

[0017] The materials described herein may be formed by conventional techniques including, but not limited to, spin coating, blanket coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma enhanced ALD, physical vapor deposition (PVD), single wafer processes, or furnace growth (e.g., diffusion). In addition, the formation process may be performed continuously or as a batch process. Alternatively, the material may be grown in situ. Depending on the specific material to be formed, the technique for depositing or growing the material may be selected by one of ordinary skill in the art. Unless the context indicates otherwise, material removal may be achieved by any suitable technique including, but not limited to, dry etching, wet etching, wet cleaning, grinding planarization (e.g., chemical-mechanical planarization), or other known methods.

[0018] The drawings presented herein are for illustrative purposes only and are not intended to be actual views of any particular material, component, structure, device or system. Changes in the shapes depicted in the drawings, for example, due to manufacturing techniques and / or tolerances, should be expected. Therefore, the embodiments described herein should not be interpreted as being limited to specific shapes or regions as described, but rather include shape deviations, for example, caused by manufacturing. For example, a region described or described as box-shaped may have rough and / or nonlinear features, and a region described or described as circular may include some rough and / or linear features. In addition, the sharp angles described may be rounded, and vice versa. Therefore, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions and do not limit the scope of the claims of the present invention. The accompanying drawings are not necessarily drawn to scale. In addition, common elements between the drawings may retain the same numbering.

[0019] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0020] As used herein, "and / or" includes any and all combinations of one or more of the associated listed items.

[0021] As used herein, "about" or "approximately" with respect to a numerical value of a particular parameter includes numerical values ​​and degrees of variation of numerical values ​​that one of ordinary skill in the art would understand to be within an acceptable tolerance for the particular parameter. For example, "about" or "approximately" with respect to a numerical value may include additional numerical values ​​that are within the 90.0% to 110.0% range of the numerical value, such as within the 95.0% to 105.0% range of the numerical value, within the 97.5% to 102.5% range of the numerical value, within the 99.0% to 101.0% range of the numerical value, within the 99.5% to 100.5% range of the numerical value, or within the 99.9% to 100.1% range of the numerical value.

[0022] As used herein, spatially relative terms such as "below," "beneath," "lower," "bottom," "above," "upper," "top," "front," "back," "left," "right," and the like may be used herein for ease of description purposes to describe the relationship of one element or feature to another element or feature as illustrated in the figures. Unless otherwise specified, spatially relative terms are intended to encompass different orientations of material in addition to the orientation depicted in the drawings. For example, if the material in the drawings is reversed, an element described as being "below" or "under" or "under" or "on the bottom" of other elements or features would be oriented "above" or "on the top" of the other elements or features. Thus, the term "below" may encompass both above and below orientations depending on the context in which the term is used, as will be apparent to one of ordinary skill in the art. The material may be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped), and the spatially relative descriptors used herein may be interpreted accordingly.

[0023] As used herein, the terms "vertical", "longitudinal", "horizontal", and "lateral" are relative to a principal plane of a structure and are not necessarily defined by the Earth's gravitational field. A "horizontal" or "lateral" direction is a direction substantially parallel to a principal plane of a structure, while a "vertical" or "longitudinal" direction is a direction substantially perpendicular to a principal plane of a structure. A principal plane of a structure is defined by a surface of the structure having a relatively large area compared to other surfaces of the structure.

[0024] As used herein, the term "configured to" refers to the size, shape, material composition, orientation, and arrangement of one or more of at least one structure and at least one device to facilitate operation of the one or more of the structure and the device in a predetermined manner.

[0025] As used herein, referring to an element as being "on" or "above" another element means and includes the element being directly on top of, adjacent to (e.g., laterally adjacent to, vertically adjacent to) another element, directly below another element, or in direct contact with another element. It also includes the element being indirectly on top of, indirectly adjacent to (e.g., indirectly laterally adjacent to, indirectly vertically adjacent to), indirectly below, or near another element, with other elements present in between. Conversely, when an element is referred to as being "directly on" or "immediately adjacent to" another element, there are no intervening elements.

[0026] As used herein, the term "device" includes, but is not limited to, memory devices, and other microelectronic devices (e.g., semiconductor devices) that may or may not incorporate memory, such as logic devices, processor devices, or radio frequency (RF) devices. In addition, the device may incorporate memory as well as other functions, such as a so-called "system on a chip" (SoC) that includes a processor and memory, or a device that includes logic and memory. The device may be a 3D microelectronic device, including, but not limited to, a 3D NAND flash memory device, such as a 3D floating gate NAND flash memory device or a 3D replacement gate NAND flash memory device.

[0027] As used herein, the term "barrier material" means and includes a material that is formulated to substantially inhibit (e.g., significantly reduce, significantly prevent) diffusion of reactive species from a conductive material and into an adjacent insulating material. In the absence of a barrier material, defects (e.g., trapping sites) may form in an insulating material (e.g., a gate dielectric material) due to diffusion of reactive species.

[0028] As used herein, the term "substantially" with respect to a given parameter, property, or condition means and encompasses the degree to which a person of ordinary skill in the art would understand that the given parameter, property, or condition meets a degree of variance (e.g., within an acceptable tolerance). By way of example, depending on the particular parameter, property, or condition that is substantially met, the parameter, property, or condition may be met by at least 90.0%, at least 95.0%, at least 99.0%, at least 99.9%, or even 100.0%.

[0029] As used herein, the term "substrate" means and includes a material (e.g., base material) or a structure on which additional materials are formed. The substrate may be a semiconductor substrate, a base semiconductor material on a support structure, a metal electrode, or a semiconductor substrate having one or more materials, layers, structures, or regions formed thereon. The materials on the semiconductor substrate may include, but are not limited to, semiconductive materials, insulating materials, conductive materials, and the like. The substrate may be a conventional silicon substrate or other bulk substrate including a layer of semiconductive material. As used herein, the term "bulk substrate" means and includes not only silicon wafers, but also silicon-on-insulator (SOI) substrates, such as silicon-on-sapphire ("SOS") substrates and silicon-on-glass ("SOG") substrates, silicon epitaxial layers on a base semiconductor foundation, and other semiconductor or optoelectronic materials, such as silicon-germanium, germanium, gallium arsenide, gallium nitride, and indium phosphide. The substrate may be doped or undoped.

[0030] Figures 1A to 1F1 is a simplified partial cross-sectional view illustrating an embodiment of a method of forming a device (e.g., a microelectronic device such as a DRAM device) including an access line structure (e.g., a word line structure) at various stages of the method. For simplicity, the formation of a single access line structure is illustrated, but one of ordinary skill will understand that the method includes forming multiple devices (e.g., more than one device, an array of devices) including such access line structures. In conjunction with the description provided below, it will be apparent to one of ordinary skill in the art that the methods described herein can be used to manufacture a variety of devices. In other words, the methods of the present disclosure can be used whenever it is desired to form the device.

[0031] refer to Figure 1A , a partially fabricated access line structure 100 for use in an apparatus (e.g., an electronic device, a memory device (e.g., a DRAM memory device)) is shown. The apparatus includes the access line structure 100, a substrate material 102, an active region 104 within the substrate material 102, and a drain region 106 within the substrate material 102. Figure 1A As shown in FIG. 1 , portions of the substrate material 102 are selectively removed to form access line trenches 108 having a bottom surface 108a and side surfaces 108b (e.g., sidewalls) corresponding to the orientation of conductive lines (e.g., access lines, word lines) that will eventually be formed therein. The access line trenches 108 (e.g., word line trenches) traverse the active region 104 of the substrate material 102. In the active region 104, a pair of access line trenches 108 may be connected to the source region 226 (see FIG. 1 ). Figure 2 ) is separated from the drain region 106, wherein the drain region 106 is disposed to either side of the source region 226 (e.g., laterally adjacent to the source region 226). The source region 226 and the drain region 106 may be defined by doped regions of the substrate material 102 proximate to the upper surface of the substrate material 102. For example, as known in the art, the source region 226 and the drain region 106 may be doped with n-type dopants or p-type dopants. The source region 226 and the drain region 106 may be formed in the active region 104 by conventional techniques. The access line trench 108 may be defined by the side surface 108b and the bottom surface 108a of the substrate material 102.

[0032] The access line structure 100 also includes a first insulating material 110 and a second insulating material 112 adjacent to (e.g., vertically overlying) at least a portion of the first insulating material 110. The first insulating material 110 may be formed within the access line trench 108 and above the substrate material 102, and the second insulating material 112 may be formed above the first insulating material 110 outside the access line trench 108. For example, the first insulating material 110 may be conformally formed on the bottom surface 108a and the side surface 108b of the access line trench 108 and on the upper surface of the substrate material 102 adjacent to (e.g., positioned outside the access line trench 108). The first insulating material 110 may be conformally formed on the upper surface, bottom surface 108a, and side surface 108b of the substrate material 102 by conventional techniques. As shown in FIG. Figure 1A As shown in , the upper surface of the first insulating material 110 within the access line trench 108 may be exposed, while the upper surface of the first insulating material 110 adjacent to the access line trench 108 (e.g., outside the access line trench 108) is at least partially (e.g., substantially) covered by the second insulating material 112. In other embodiments, the second insulating material 112 may also be formed above the first insulating material 110 within the access line trench 108. The first insulating material 110 and the second insulating material 112 may together form a so-called "gate dielectric" material. The first insulating material 110 and the second insulating material 112 may be formed by conventional techniques and are not described in detail herein. The first insulating material 110 may be formed to any desired thickness. By way of non-limiting example, the first insulating material 110 may be formed to be between about About between, for example, between about About between About between About Between or about About The thickness between.

[0033] The first insulating material 110 and the second insulating material 112 may each be formed of and include at least one dielectric material including, but not limited to, oxide, nitride, or oxynitride. The first insulating material 110 and / or the second insulating material 112 may be formed of and include at least one oxygen-containing dielectric material, such as one or more of the following: a dielectric oxide material (e.g., silicon oxide (SiO x ), phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, alumina (AlO x ), hafnium oxide (HfO x ), niobium oxide (NbOx ) and titanium oxide (TiO x ), nitrogen-containing dielectric materials (e.g., silicon nitride (SiN y ), dielectric oxynitride materials (e.g., silicon oxynitride (SiO x N y )), or dielectric carbon oxynitride materials (e.g., silicon carbon oxynitride (SiO x C z N y )), wherein each of x, y, and z is independently an integer or a non-integer. The dielectric material may be a stoichiometric compound having one of the above chemical formulas or a non-stoichiometric compound having one of the above chemical formulas. The first insulating material 110 and the second insulating material 112 may be the same material (e.g., chemical composition) or different materials (e.g., chemical composition) from each other. In some embodiments, at least one of the first insulating material 110 and the second insulating material 112 (e.g., each of them) is composed of SiO x (e.g., silicon dioxide (SiO2)) formed and containing SiO x (For example, silicon dioxide (SiO 2 )). In other embodiments, the material of the first insulating material 110 may be formed of a different material having an etch selectivity different from that of the second insulating material 112 .

[0034] Next reference Figure 1B , the first conductive material 114 may be formed in the access line trench 108 and above the upper surface of the second insulating material 112. In particular, the first conductive material 114 may be conformally formed adjacent to (e.g., above) the upper surface of the second insulating material 112 and the bottom surface 108a and the side surface 108b within the access line trench 108. Figure 1B As shown in FIG. 1 , the first conductive material 114 substantially covers the exposed surfaces of the first insulating material 110 and the second insulating material 112. The first conductive material 114 can be formed to exhibit any desired thickness. By way of non-limiting example, the first conductive material 114 can be formed to be between about About between, for example, between about About between About between About Between or about About The thickness of the first conductive material 114 can be substantially uniform along its length.

[0035] The first conductive material 114 may be formed of and include at least one conductive material. By way of non-limiting example, the first conductive material 114 may be a metal material (e.g., a transition metal material) or a metal nitride material (e.g., a transition metal nitride material), such as one or more of the following: titanium nitride (TiN y ), tungsten (W), tungsten nitride (WN y ), Tantalum Nitride (TaN y ), molybdenum nitride (MoN y ) or ruthenium (Ru), wherein y is independently an integer or a non-integer. In some embodiments, the first conductive material 114 includes titanium nitride TiN y , such as TiN. In other embodiments, the first conductive material 114 includes tungsten (W). In still other embodiments, the first conductive material 114 includes ruthenium (Ru).

[0036] The first conductive material 114 may be formed using one or more conventional conformal deposition techniques, including but not limited to one or more of a conventional CVD process, a conventional ALD process, a single wafer process, or a conventional furnace process. To form the first conductive material 114, the access line structure 100 (in Figure 1A 114) is disposed in a conventional deposition apparatus (e.g., a single chamber of a conventional ALD reactor, a conventional CVD reactor, a conventional single wafer apparatus, or a conventional furnace) and alternating pulses of at least one metal-containing precursor and at least one nitrogen-containing precursor are introduced to the deposition apparatus in a continuous process or a batch process. The metal-containing precursor and the nitrogen-containing precursor may be conventional CVD precursors or ALD precursors. The metal-containing precursor may, for example, comprise a complex of at least one metal of the first conductive material 114 (e.g., Ti, W, Ta, Co, Mo, Ni) and at least one ligand formulated to react with the nitrogen-containing precursor to form at least a portion of the first conductive material 114. A monolayer or less of the metal from the metal-containing precursor and a monolayer or less of the nitrogen from the nitrogen-containing precursor may be continuously formed until a desired thickness of the first conductive material 114 is achieved. The first conductive material 114 may form a substantially continuous material over the first insulating material 110 and the second insulating material 112. In some embodiments, the metal-containing precursor comprises titanium tetrachloride (TiCl4) and the nitrogen-containing precursor comprises ammonia (NH3). In some embodiments, the first conductive material 114 may be formed in-situ. The first conductive material 114 may promote (eg, improve) adhesion of subsequent materials to the first insulating material 110.

[0037] refer to Figure 1C, barrier material 116 may be formed adjacent to (e.g., on or above) a surface of first conductive material 114. For example, barrier material 116 may be conformally formed on the exposed side surfaces and exposed upper surface of first conductive material 114 and may at least partially (e.g., substantially) cover the exposed surface of first conductive material 114. Barrier material 116 may be formed at any desired thickness. By way of non-limiting example, barrier material 116 may be formed to be between about About between, for example, between about About between About between About between About between About between About Between or about About The thickness of the barrier material 116 can be generally uniform along its length.

[0038] The barrier material 116 may be formed of and include at least one dielectric material through which reactive species (e.g., ions) do not diffuse. By way of non-limiting example, the barrier material 116 may be formed of and include at least one dielectric material that is substantially free of oxygen, such as a dielectric nitride material (e.g., silicon nitride (Si 2+)). x N y ), Boron Nitride (BN y ), Germanium Nitride (GeN y ), aluminum nitride (AlN y )) and dielectric carbonitride materials (e.g., silicon carbonitride (SiC z N y )), wherein each of x, y, and z is independently an integer or a non-integer. The barrier material 116 may be a binary or multi-component (e.g., ternary) compound. In some embodiments, the barrier material 116 is composed of Si x N y (e.g., Si3N4) formed and containing Si x N y (eg, Si3N4). In other embodiments, the barrier material 116 may be formed of and include an oxynitride material, including but not limited to silicon oxynitride (SiO x N y), boron oxynitride (BO x N y ), germanium oxynitride (GeO x N y ) and aluminum oxynitride (AlO x N y ).

[0039] The barrier material 116 may be formed using one or more conventional conformal deposition techniques, such as one or more of a conventional ALD process, a conventional conformal CVD process, a conventional single wafer process, or a conventional furnace process. The formation process may, for example, include depositing the access line structure 100 (in Figure 1C 116) is exposed to alternating pulses of at least one precursor, such as a silicon precursor, and at least one precursor, such as a nitrogen precursor, with the intermediate pulses being at least one inert gas (e.g., nitrogen, argon, helium, neon, krypton, xenon, and / or other gases that are not inert but appear to be inert under the conditions of the dielectric formation process) to form the barrier material 116. The silicon and nitrogen precursors may be selected based on the chemical nature of the barrier material 116 to be formed (e.g., metal species, ligands). In some embodiments, the silicon precursor includes a silicon-containing compound including a complex of Si and at least one ligand that is formulated to react with the nitrogen precursor to form at least a portion of the barrier material 116. As a non-limiting example, the silicon precursor may include silicon and at least one ligand including one or more of hydrogen, nitrogen, and carbon, such as an alkylamidosilane compound, including but not limited to silane (SiH4), disilane (DiSi), dichlorosilane (DCS), tris(dimethylamido)silane (TDMAS), or combinations thereof. In some embodiments, the silicon precursor is DCS. At least one oxidant including but not limited to, for example, O2, O3, H2O, H2O2, N2O may be used in combination with at least one nitrogen precursor (including but not limited to NH3, N2H4). In some embodiments, the oxidant includes H2O and the nitrogen precursor includes NH3.

[0040] The barrier material 116 may be formed in situ (e.g., in the same deposition apparatus (e.g., ALD chamber, CVD chamber, single wafer apparatus, furnace)) with the first conductive material 114 and with subsequent materials (e.g., conductive materials) discussed in more detail below. The barrier material 116 may, for example, be formed on the first conductive material 114 without first moving (e.g., transferring) the access line structure 100 from a deposition chamber used to form the first conductive material 114 to another deposition chamber. By way of non-limiting example, if the first conductive material 114 and the barrier material 116 are each formed using an ALD process, a CVD process, a single wafer process, or a furnace process, then after the first conductive material 114 is formed, a pulse of a silicon precursor (e.g., a Si-containing precursor) and a nitrogen precursor used to form the barrier material 116 may be introduced into the deposition chamber. The deposition chamber may be purged prior to the introduction of the silicon and nitrogen precursors. Thus, each of the first conductive material 114 and the barrier material 116 can be formed in the same deposition chamber using a continuous deposition process (e.g., a single continuous ALD process; a single continuous CVD process; a single wafer process, or a single continuous furnace process) or using a batch process. In some embodiments, an ALD process is performed in an ALD chamber using continuous pulses of a metal precursor and a nitrogen precursor to form the first conductive material 114 (e.g., TiN x ), and then sequential pulses of a silicon precursor and a nitrogen precursor are introduced into the ALD chamber to form a barrier material 116 (e.g., SiN x ). In additional embodiments, the first conductive material 114 and / or the barrier material 116 may be formed ex-situ. For example, after forming the first conductive material 114, the access line structure 100 may be moved and transferred from a deposition device (e.g., an ALD chamber, a CVD chamber, a single wafer device, a furnace) used to form the first conductive material 114 to a different deposition device to form the barrier material 116 on the first conductive material 114 through an additional conformal deposition process.

[0041] Other processing conditions of the deposition action, such as temperature, pressure, or gas flow rate of the precursor, may be selected as needed to achieve the desired composition and thickness of the barrier material 116. By way of non-limiting example, the process temperature within a deposition apparatus (e.g., a chamber) may be greater than about 300° C., such as between about 300° C. and about 1000° C., between about 400° C. and about 600° C., or between about 600° C. and about 800° C. The selection of the precursor may depend, at least in part, on the processing conditions within the deposition apparatus. For example, DCS may be used as a silicon precursor at a process temperature greater than about 600° C. In addition, the process time for each processing cycle (e.g., cycle count) may vary depending on the desired thickness of the barrier material 116. The deposition action may be performed for an amount of time sufficient to form the barrier material 116 to the desired thickness, with each cycle forming a monolayer or less of silicon and a monolayer or less of nitrogen. As a non-limiting example, each processing cycle of the deposition action may be performed from about 0.05 seconds to about 15 seconds, such as from about 0.05 seconds to about 2.0 seconds, or from about 1.0 seconds to about 2.0 seconds. The average thickness of the barrier material 116 may depend at least in part on the materials, precursors, processing conditions (e.g., temperature), and / or processing time utilized. By way of non-limiting example, the barrier material 116 may be formed using between about 1 deposition cycle and about 25 deposition cycles, such as between about 1 deposition cycle and about 3 deposition cycles, between about 3 deposition cycles and about 10 deposition cycles, between about 10 deposition cycles and about 15 deposition cycles, or between about 16 deposition cycles and about 25 deposition cycles. Depending on the material composition and processing conditions of the barrier material 116, the thickness of the barrier material 116 may be, for example, less than or equal to about 100 Å. For example, in the case of a single layer of about Up to 25 single layers By way of example only, if the barrier material 116 is a silicon nitride material, the precursor is DCS, and the process temperature is greater than about 600° C., each of the silicon or nitrogen monolayers may be formed at a temperature between about 100 and about 200° C. in each deposition cycle ranging from about 1.0 seconds to about 2.0 seconds. About Between, for example Under the thickness.

[0042] By forming the barrier material 116 by means of ALD or CVD, for example, the barrier material 116 is formed using a so-called "self-limiting" process. In other words, the deposition of each monolayer of silicon or nitrogen can be constrained (e.g., confined) when the material and / or precursor becomes saturated during the deposition process. Therefore, the barrier material 116 including the silicon nitride material may include a so-called "silicon nitride (SiN) stop" material. Once the desired thickness of the barrier material 116 is reached, the deposition process may be interrupted (e.g., terminated). Optionally, a native oxide material (not shown) may be formed to be adjacent to the exposed surface ( Figure 1B ) is adjacent to (eg, overlying). In other embodiments, the barrier material 116 can inhibit (eg, prohibit, prevent) undesirable surface oxidation of the first conductive material 114, which can otherwise adversely affect contact resistance.

[0043] Continue to refer Figure 1C , the second conductive material 118 may be formed adjacent to (eg, on or above) a surface of the barrier material 116. Figure 1C As shown in , the second conductive material 118 may at least partially (e.g., substantially) cover the upper surface of the barrier material 116 and extend from and between the side surfaces (e.g., sidewalls) of the barrier material 116 and above the horizontal surface of the barrier material 116. In other words, the second conductive material 118 may substantially fill the remaining portion of the access line trench 108 and also be formed above the horizontal surface of the barrier material 116. The second conductive material 118 may be formed to exhibit any desired thickness. By way of non-limiting example, the second conductive material 118 may be formed to be between about About between, for example, between about About between About between About Between or about About The thickness (e.g., average thickness) of the first conductive material 114 may be relatively smaller than the thickness (e.g., average thickness) of the second conductive material 118, and the thickness (e.g., average thickness) of the barrier material 116 may be relatively smaller than the thickness (e.g., average thickness) of each of the first conductive material 114 and the second conductive material 118.

[0044] like Figure 1CAs shown in , the barrier material 116 may substantially surround (e.g., substantially continuously surround) the second conductive material 118 on at least three (3) sides. In other words, the barrier material 116 may substantially completely cover the bottom surface and the side surfaces (e.g., the sidewalls) of the second conductive material 118. The barrier material 116 may be horizontally interposed between the side surfaces of the second conductive material 118 and the side surfaces of the first conductive material 114 and may be vertically interposed between the bottom surface of the second conductive material 118 and the upper surface of the first conductive material 114. In addition, the barrier material 116 may serve as an interface between the first conductive material 114 and the second conductive material 118, such that reactive species (e.g., chloride ions, fluoride ions) are inhibited from being transferred from the second conductive material 118 to the first insulating material 110. In other words, the barrier material 116 may be configured to inhibit the migration of reactive species from the second conductive material 118 to the first insulating material 110. The reactive species may be generated during the formation of the second conductive material 118, for example, from ligands of a metal precursor. In particular, the barrier material 116 can substantially prohibit (e.g., block, prevent) the formation of so-called “chlorine-related trapping sites” within the gate dielectric material (e.g., the first insulating material 110 and the second insulating material 112) because the barrier material 116 can substantially inhibit the migration (e.g., diffusion) of chloride ions from the metal precursor through the first conductive material 114 and into the first insulating material 110 and / or the substrate material 102.

[0045] The second conductive material 118 may be formed of and include at least one conductive material, such as one of the transition metal materials or metal nitride materials described above for the first conductive material 114. In some embodiments, the second conductive material 118 includes titanium nitride TiN y(e.g., TiN). In other embodiments, the second conductive material 118 includes tungsten (W). In yet other embodiments, the second conductive material 118 includes ruthenium (Ru). The first conductive material 114 and the second conductive material 118 may be the same material as each other or different materials from each other. In addition, the first conductive material 114 and / or the second conductive material 118 may be formed of and include a crystalline material. For example, the first conductive material 114 and the second conductive material 118 may include a columnar grain structure. In addition, the barrier material 116 may be formed of and include an amorphous material. In particular, the material of each of the first conductive material 114 and the second conductive material 118 may be formed to exhibit a desired orientation of a columnar grain structure (e.g., a continuous or discontinuous columnar grain structure). Without being bound by any theory, it is believed that the columnar grain structure significantly reduces (e.g., blocks) diffusion of reactive species across grain boundaries between the second conductive material 118 and the barrier material 116 and across grain boundaries between the barrier material 116 and the first conductive material 114 during formation of the second conductive material 118 and / or during use and operation of the access line structure 100. In other words, the barrier material 116 having an amorphous material formed between each of the first conductive material 114 and the second conductive material 118 having a columnar grain structure can significantly reduce diffusion of reactive species at grain boundaries therebetween (e.g., by blocking the path). By way of non-limiting example, the barrier material 116 can include a silicon nitride material having an amorphous structure, while one or both (e.g., each) of the first conductive material 114 and the second conductive material 118 include a metal nitride material (e.g., TiN) having a crystalline structure (e.g., a columnar grain structure).

[0046] The second conductive material 118 may be formed using one or more conventional conformal deposition processes, such as one or more of a conventional conformal CVD process, a conventional ALD process, a conventional single wafer process, and a conventional furnace process. Figure 1C ) may be provided, for example, to a deposition apparatus configured to receive sequential pulses of a metal-containing precursor and a nitrogen-containing precursor. The metal-containing precursor may include a complex of at least one metal species of the second conductive material 118 (e.g., Ti, W, Ta, Co, Mo, Ni) and at least one ligand configured to react with the nitrogen-containing precursor to form the second conductive material 118. The ligand may include a chemical element that is reactive in ionic form (e.g., a chlorine atom or a fluorine atom). In some embodiments, the metal-containing precursor includes titanium tetrachloride (TiCl4) and the nitrogen-containing precursor includes NH3.

[0047] In some embodiments, the second conductive material 118 may be formed in situ with the first conductive material 114 and the barrier material 116. The second conductive material 118 may, for example, be formed on the barrier material 116 without moving (e.g., transferring) out of the access line structure 100 from the deposition device used to form the first conductive material 114 and the barrier material and into an additional deposition device as discussed above. By way of non-limiting example, the first conductive material 114, the barrier material 116, and the second conductive material 118 may each be formed in the same deposition device using a conventional ALD process, a conventional CVD process, a conventional single wafer process, or a conventional furnace process. Thus, each of the first conductive material 114, the barrier material 116, and the second conductive material 118 may be formed using a single continuous deposition process (e.g., a single continuous ALD process; a single continuous CVD process, a continuous single wafer process) or, alternatively, using a batch process (e.g., a furnace batch process). In additional embodiments, the first conductive material 114, the barrier material 116, and / or the second conductive material 118 may be formed ex situ. For example, the access line structure 100 may be removed from a deposition apparatus (e.g., an ALD chamber, a CVD chamber, a single wafer apparatus, a furnace) used to form the first conductive material 114 and / or the barrier material 116 and transferred to a different deposition chamber before forming the second conductive material 118 on the barrier material 116 by an additional conformal deposition process. Alternatively, the second conductive material 118 may be formed using one or more conventional non-conformal deposition processes, such as one or more of a conventional PVD process (e.g., a conventional radio frequency PVD (RFPVD) process), a conventional non-conformal CVD process, a conventional non-conformal single wafer process, and a conventional non-conformal furnace process.

[0048] In an embodiment according to the present disclosure, the presence of a barrier material 116 (e.g., silicon nitride) between two titanium nitride materials (e.g., first conductive material 114 and second conductive material 118) can substantially block chlorine or fluorine reactive species from diffusing from, for example, the second conductive material 118 and entering the first insulating material 110 and / or the substrate material 102 during the formation of the second conductive material 118. The barrier material 116 can also prevent the reactive species from being removed during a subsequent removal (e.g., recessing) operation (e.g., removing a portion of the material within the access line trench 108 ( Figure 1B )) and / or during use and operation of the access line structure 100. In an embodiment, by including tungsten (W) or tungsten nitride (WN y ) material as the second conductive material 118 , the barrier material 116 can block (eg, prohibit, prevent) undesired diffusion of chloride ions or fluoride ions, for example, from the second conductive material 118 and into the first insulating material 110 and / or the base material 102 .

[0049] Next reference Figure 1D, one or more removal actions may be performed to remove portions of the first conductive material 114, the barrier material 116, and the second conductive material 118 that extend above the upper surface of the base material 102 (e.g., above the exposed upper surface of the second insulating material 112), and portions of the first conductive material 114, the barrier material 116, and the second conductive material 118 that are within the access line trench 108, as shown. Figure 1D . In particular, an upper portion of each of the first conductive material 114, the barrier material 116, and the second conductive material 118 may be removed by conventional techniques to form a gate structure 120 within the access line trench 108. The gate structure 120 includes a recessed portion of the first conductive material 114, the barrier material 116, and the second conductive material 118 that remains in the access line trench 108. After the removal action, each of the first conductive material 114, the barrier material 116, and the second conductive material 118 may partially fill the access line trench 108, wherein a portion of a sidewall of at least one (e.g., both) of the first insulating material 110 and the second insulating material 112 (e.g., gate dielectric material) extends along the exposed side surface 108b of the access line trench 108. By way of example only, one or more dry etching actions may be performed to recess portions of the first conductive material 114, the barrier material 116, and the second conductive material 118 in the access line trench 108. The removal action may generate reactive species depending on the etching chemistry and etching conditions used. For example, if a chlorine-based or fluorine-based etching chemistry is used to recess the first conductive material 114, the barrier material 116, and the second conductive material 118, the reactive species may include chloride ions or fluorine ions. In addition, the barrier material 116 may be positioned and configured to use the barrier material 116 to inhibit the movement of reactive species (e.g., ions (e.g., chlorine, fluorine) between the second conductive material 118 and the first insulating material 110, so that the first insulating material 110 remains substantially free of reactive species during the deposition and removal actions of the second conductive material 118.

[0050] refer to Figure 1E , a conductive structure 122 (eg, a conductive plug) may be formed in the remaining (eg, unfilled) portion of the access line trench 108 ( Figure 1D ) Figure 1E As shown in , the conductive structure 122 may be formed on a portion of (e.g., over) each of the first conductive material 114, the barrier material 116, and the second conductive material 118 within the access line trench 108 and may extend horizontally from and between opposite side surfaces of the first insulating material 110 within the access line trench 108. The conductive structure 122 may also overlie an upper surface of the second insulating material 112. The conductive structure 122 may be formed by conventional techniques.

[0051] The conductive structure 122 may be formed of and include at least one conductive material, such as one or more of a metal, an alloy, a conductive metal oxide, a conductive metal nitride, a conductive metal silicide, and a conductively doped semiconductor material. By way of non-limiting example, the conductive structure 122 may be formed of and include one or more of: tungsten (W), tungsten nitride (WN y ), nickel (Ni), tantalum (Ta), tantalum nitride (TaN y ), Tantalum silicide (TaSi x ), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al), molybdenum (Mo), titanium (Ti), titanium nitride (TiN y ), titanium silicide (TiSi x ), titanium silicon nitride (TiSi x N y ), titanium aluminum nitride (TiAl x N y ), molybdenum nitride (MoN x ), iridium (Ir), iridium oxide (IrO z ), ruthenium (Ru), ruthenium oxide (RuO z ) and conductively doped silicon. In some embodiments, the conductive structure 122 is formed of and includes tungsten (W).

[0052] refer to Figure 1F , portions of the conductive structure 122 that vertically extend beyond the horizontal plane defined by the upper surface of the second insulating material 112 may be removed using one or more conventional material removal processes (e.g., by means of a grinding planarization action, such as a chemical mechanical planarization (CMP) action) to form the conductive structure 122 within the access line trench 108 and expose the upper surface of the second insulating material 112. The upper surface of the conductive structure 122 may be substantially coplanar with the upper surface of the second insulating material 112. In some embodiments, substantially no second insulating material 112 is removed in the removal action. In other embodiments, portions (e.g., upper portions, substantially all portions) of the second insulating material 112 may be removed in the removal action.

[0053] like Figure 1FAs shown in , an access line structure 100 including a first conductive material 114, a barrier material 116, and a second conductive material 118 provides improved row hammering characteristics for an electronic device including the access line structure 100. Without being limited by any theory, it is believed that the barrier material 116 serves to block (e.g., inhibit, prevent) undesired diffusion of reactive species through the first conductive material 114 and into the first insulating material 110 and / or the base material 102. Without being limited by any theory, it is believed that the barrier material 116 improves the "row hammering" characteristics of the electronic device by reducing the likelihood that the electronic device will experience undesired leakage between adjacent access line structures 100. Unexpectedly and surprisingly, the barrier material 116 in the access line structure 100 has a thickness of, for example, about 100% of the barrier material 116. The barrier material 116 may improve the row hammering properties of the access line structure 100 (e.g., may reduce leakage of the access line structure 100) by reducing (e.g., preventing) the formation of trapping sites (e.g., chlorine-related trapping sites or fluorine-related trapping sites) in the gate dielectric material during use and operation of the electronic device, such that the trapping sites may cause defects within the gate dielectric material (e.g., at the interface thereof). Therefore, it is determined that the barrier material 116 of the access line structure 100 according to embodiments of the present disclosure improves the row hammering performance properties of the electronic device and increases the threshold voltage thereof.

[0054] Thus, a device including a memory array having access lines is disclosed. Each of the access lines includes an insulating material adjacent to a bottom surface and sidewalls of a substrate material, a first conductive material adjacent to the insulating material, a second conductive material adjacent to the first conductive material, and a barrier material between the first conductive material and the second conductive material. The barrier material is configured to inhibit migration of reactive species from the second conductive material.

[0055] The above references may be employed in additional methods of forming a device Figures 1A to 1F Aspects of the described methods (e.g., processing actions and structures) are provided to facilitate one or more benefits over conventional methods and conventional apparatus (e.g., as described above with reference to Figures 1A to 1FAt least some of the benefits achieved by the described methods, and / or additional benefits). For example, the access line structure 100 including the first conductive material 114, the barrier material 116, and the second conductive material 118 provides improved row hammer characteristics for the electronic device including the access line structure 100 as compared to a plurality of conventional electronic devices including word line structures, because the barrier material 116 can block (e.g., inhibit, prevent) undesired diffusion of reactive species, such as through the first conductive material 114 and into the first insulating material 110 and / or the base material 102, and improves the "row hammer" characteristics of the memory device by reducing the likelihood that the electronic device including the access line structure 100 experiences undesired leakage between adjacent access line structures 100. In addition, the methods of the present disclosure can reduce or eliminate process actions for forming a plurality of conventional devices that can be used for operations similar to the access line structure 100. By using a single deposition action within a single chamber, the access line structure 100 according to an embodiment of the present disclosure is formed using fewer process actions as compared to conventional word line structures.

[0056] Thus, a method of forming a device is also disclosed. The method includes forming at least one insulating material within and adjacent to a trench in a substrate material; forming a first conductive material adjacent to an exposed surface of the at least one insulating material; forming a barrier material adjacent to the first conductive material; and forming a second conductive material adjacent to the barrier material. The barrier material is formulated to reduce diffusion of reactive species from the second conductive material and into the at least one insulating material.

[0057] Additional processing actions may be performed on the access line structure 100 to form Figure 2 A microelectronic device 200 (e.g., an apparatus) is shown that includes one or more access line structures 100 and additional components. The process actions described may be performed by conventional techniques. The microelectronic device 200 includes a drain region 106, a source region 226 within an active region 104, a dielectric material 230, a contact material 234, an isolation trench 236, and another dielectric material 238. The microelectronic device 200 also includes a gate structure 120, at least one data line 232 (e.g., a bit line), and at least one memory cell (not shown). Each memory cell is coupled to an associated gate structure 120 (e.g., an access line, a word line) and an associated data line 232. A digit line contact (not shown) including a contact material 234 extends vertically to the data line 232 to allow electrical communication with more remote components of the microelectronic device 200 that includes the access line structure 100. The contact formed by the contact material 234 is in electrical communication with the drain region 106. The dielectric material 230 may be adjacent to (e.g., overlying) at least a portion of the access line trench 108 including the conductive structure 122, the first insulating material 110, the second insulating material 112, the first conductive material 114, the barrier material 116, and the second conductive material 118. Figure 2 As shown, the contact material 234 and the data line 232 may be separated from each other by the dielectric material 230 .

[0058] The isolation trenches 236 provide shallow trench isolation (STI) for the active region 104 of the base material 102. The isolation trenches 236 may be defined by sidewalls of the base material 102. The isolation trenches 236 may be partially filled with another dielectric material 238, for example, at the bottom of the isolation trenches 236. The another dielectric material 238 may include, but is not limited to, an oxide (e.g., silicon dioxide (SiO2)), a nitride (e.g., silicon nitride (SiN)), or an oxynitride. One or more of the isolation trenches 236 may include one of the access line trenches 108. For example, one access line trench 108 may be formed within one of the isolation trenches 236. The isolation trenches 236 may also contain the first conductive material 114, the barrier material 116, the second conductive material 118, and another dielectric material 238. One or more gate dielectric materials (e.g., first insulating material 110 and / or second insulating material 112) may be present in the isolation trench 236, for example, on the sidewalls of the substrate material 102, while another dielectric material 238 is present in the bottom of the isolation trench 236. The first insulating material 110 and / or the second insulating material 112 may surround the first conductive material 114, the barrier material 116, and the second conductive material 118 in the isolation trench 236. The dielectric material 230, the another dielectric material 238, and the gate dielectric material may be the same material as one another or different materials from one another. The first insulating material 110 may be above (e.g., directly above, immediately adjacent to, vertically adjacent to) the another dielectric material 238 in the isolation trench 236, and the second insulating material 112 may be adjacent to (e.g., immediately adjacent to, above, directly above) the first insulating material 110. The remaining portion of the isolation trench 236 may contain another dielectric material 238.

[0059] The microelectronic device 200 also includes an active region 104 that can be aligned at an angle (e.g., at an angle of about forty-five degrees) relative to the alignment of word lines (e.g., gate structures 120) within access line trenches 108 and data lines 232 within isolation trenches 236. In the active region 104, a pair of access line trenches 108 can separate source regions 226 from drain regions 106, wherein the drain regions 106 are disposed to either side of the source regions 226. The source regions 226 and the drain regions 106 can be defined by doped regions of the substrate material 102 proximate to the upper surface of the substrate material 102. For example, the source regions 226 and the drain regions 106 can be doped with n-type dopants or p-type dopants. The source regions 226 and the drain regions 106 can be formed by conventional techniques. Each word line (e.g., gate structure 120) is isolated from source region 226 and drain region 106 of an array (e.g., memory array) by gate dielectric material (e.g., first insulating material 110 and / or second insulating material 112). In some embodiments, microelectronic device 200 is a dynamic random access memory (DRAM) device.

[0060] Therefore, a memory device including access lines is disclosed. Each of the access lines includes an insulating material adjacent to a bottom surface and sidewalls of a substrate material, a first conductive material adjacent to the insulating material, a second conductive material adjacent to the first conductive material, and a barrier material between the first conductive material and the second conductive material. The barrier material is configured to inhibit migration of reactive species from the second conductive material.

[0061] Figure 3 1 is a functional block diagram illustrating a memory device 300 (eg, a DRAM device) according to an embodiment of the present disclosure. The memory device 300 may include an embodiment of the access line structure 100 described previously herein, for example. Figure 3 As shown in , memory device 300 may include memory cells 302 , digit lines 304 , word lines 306 , row decoders 308 , column decoders 310 , memory controller 312 , sensing devices 314 , and input / output devices 316 .

[0062] The memory cell 302 of the memory device 300 is programmable to at least two different logic states (e.g., logic 0 and logic 1). The access line structure 100 according to an embodiment of the present disclosure may be included in the memory cell 302 of the memory device 300. Each memory cell 302 may individually include a storage node structure and a transistor. The storage node structure stores a charge representing the programmable logic state of the memory cell 302 (e.g., a charged capacitor may represent a first logic state, such as logic 1; and an uncharged capacitor may represent a second logic state, such as logic 0). The transistor grants access to the capacitor in response to a minimum threshold voltage being applied to its semiconducting channel for an operation (e.g., reading, writing, rewriting) on ​​the storage node structure.

[0063] The digit lines 304 are connected to the storage node structures of the memory cells 302 by means of the transistors of the memory cells 302. The word lines 306 extend perpendicular to the digit lines 304 and are connected to the gates of the transistors of the memory cells 302. Operations can be performed on the memory cells 302 by activating the appropriate digit lines 304 and word lines 306. Activating the digit lines 304 or word lines 306 can include applying a voltage potential to the digit lines 304 or word lines 306. Each column of the memory cells 302 can be individually connected to one of the digit lines 304, and each row of the memory cells 302 can be individually connected to one of the word lines 306. Individual memory cells 302 can be addressed and accessed through the intersections (e.g., cross intersections) of the digit lines 304 and word lines 306.

[0064] The memory controller 312 may control the operation of the memory cell 302 through various components, including a row decoder 308, a column decoder 310, and a sensing device 314. The memory controller 312 may generate row address signals directed to the row decoder 308 to activate (e.g., apply a voltage potential to) predetermined word lines 306, and may generate column address signals directed to the column decoder 310 to activate (e.g., apply a voltage potential to) predetermined digit lines 304. The memory controller 312 may also generate and control various voltage potentials employed during operation of the memory device 300. In general, the magnitude, shape, and / or duration of the applied voltage may be adjusted (e.g., changed), and may be different for various operations of the memory device 300.

[0065] During use and operation of the memory device 300, after being accessed, the memory cell 302 may be read (e.g., sensed) by the sensing device 314. The sensing device 314 may compare the signal (e.g., voltage) of the appropriate digital line 304 with a reference signal in order to determine the logic state of the memory cell 302. If, for example, the digital line 304 has a voltage higher than the reference voltage, the sensing device 314 may determine that the stored logic state of the memory cell 302 is a logic 1, and vice versa. The sensing device 314 may include a transistor and an amplifier to detect and amplify the difference of the signal (commonly referred to as "latching" in the art). The detected logic state of the memory cell 302 may be output to the input / output device 316 by the column decoder 310. In addition, the memory cell 302 may be set (e.g., written) by similarly activating the appropriate word line 306 and the appropriate digital line 304 of the memory device 300. By controlling the digital line 304 when the word line 306 is activated, the memory cell 302 may be set (e.g., a logic value may be stored in the memory cell 302). The column decoder 310 can accept data from the input / output device 316 to be written to the memory cell 302. In addition, the memory cell 302 can also be refreshed (e.g., recharged) by reading the memory cell 302. The read operation places the contents of the memory cell 302 on the appropriate digit line 304, which is then pulled up to a full level (e.g., fully charged or discharged) by the sense device 314. When the word line 306 associated with the memory cell 302 is deactivated, all memory cells 302 in the row associated with the word line 306 are restored to a full charge or discharge.

[0066] The apparatus including the access line structure 100 and the microelectronic device (eg, the memory device 300) incorporating the access line structure 100 according to the embodiments of the present disclosure may be used in the embodiments of the electronic system of the present disclosure. For example, Figure 4 4 is a block diagram of an illustrative electronic system 400 according to an embodiment of the present disclosure. The electronic system 400 may include, for example, one or more of the following: a computer or computer hardware component, a server or other network connection hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a Wi-Fi or cellular enabled tablet computer (e.g., or The electronic system 400 includes at least one memory device 402. The memory device 402 may include, for example, an embodiment of a device (e.g., access line structure 100) previously described herein incorporated in a microelectronic device (e.g., memory device 300). The electronic system 400 may additionally include at least one electronic signal processor device 404 (often referred to as a "microprocessor"). The electronic signal processor device 404 may optionally include an embodiment of a device (e.g., access line structure 100) previously described herein incorporated in a microelectronic device (e.g., memory device 300), such arrangements being generally referred to as a "system on a chip" (SoC). The electronic system 400 may additionally include one or more input devices 406 for inputting information into the electronic system 400 by a user, such as a mouse or other pointing device, keyboard, touch pad, button, or control panel. The electronic system 400 may additionally include one or more output devices 408 for outputting information (e.g., visual or audio output) to a user, such as a monitor, display, printer, audio output jack, speaker, etc. In some embodiments, input device 406 and output device 408 may include a single touch screen device that can be used to input information to electronic system 400 and output visual information to a user. Input device 406 and output device 408 may be in electrical communication with one or more of memory device 402 and electronic signal processor device 404.

[0067] Therefore, an electronic system according to an embodiment of the present disclosure includes an input device, an output device, a processor device operably coupled to the input device and the output device, and a memory device operably coupled to the processor device and including memory cells. One or more of the memory cells include one or more insulating materials adjacent to a bottom surface and sidewalls of a substrate material, a first conductive material overlying the one or more insulating materials, a barrier material overlying the first conductive material, and a second conductive material overlying the barrier material, the barrier material being formulated to prevent reactive species from diffusing from the second conductive material.

[0068] The following examples are used to explain the embodiments of the present disclosure in more detail. This example should not be understood as being exhaustive or exclusive with respect to the scope of the present disclosure.

[0069] Example 1

[0070] As mentioned above Figures 1A-1F As described to prepare Figure 1F. The samples of the access line structure include two portions of a conductive material (e.g., titanium nitride) and a barrier material (e.g., silicon nitride) between the two portions of the conductive material. Three (3) samples were prepared having different thicknesses of silicon nitride positioned between the two portions of the titanium nitride. The three samples were prepared using a single continuous ALD process in a deposition chamber at a temperature greater than about 600° C. using DCS as a silicon precursor and ammonia as a nitrogen precursor. A first sample was prepared in which three (3) deposition cycles (e.g., cycle count) of silicon nitride were used to form about A second sample was prepared in which ten (10) deposition cycles of silicon nitride were used to form a silicon nitride layer of approximately A third sample was prepared using fifteen (15) deposition cycles of silicon nitride to form about After forming materials (eg, titanium nitride and silicon nitride) within the access line trenches and recessing the materials, a conductive structure is formed over the materials, thereby creating an access line structure.

[0071] For comparison, a control sample was prepared as described above, except that a single titanium nitride material was formed without depositing silicon nitride. Thus, silicon nitride was not present in the control sample.

[0072] The impact properties of the sample are determined by conventional techniques. Figure 5 As shown in , the row hammer performance of the sample including silicon nitride between two portions of titanium nitride exhibits improved row hammer performance without degrading the refresh properties. Figure 5 The number of failed bits caused by the row hammer test is shown as a function of the number of failed bits caused by the refresh test. In the row hammer test, the aggressor access line (e.g., word line) is repeatedly activated and deactivated 5000 times. The failed bits caused by the row hammer test are coupled to the victim access line adjacent to the aggressor access line. The refresh test includes operations performed in 80 millisecond cycles. Three (3) deposition cycles (at Figure 5 3 cycles), ten (10) cycles (in Figure 5 TiSiN 10cycle) and fifteen (15) cycles (in Figure 5 The sample including the access line structure according to the embodiment of the present disclosure was prepared by using a control sample (marked as TiSiN 15cycle in FIG. Figure 5 The sample labeled as a single TiN sample in Figure 1 does not contain silicon nitride. Figure 5As shown in , compared to the control access line structure (single TiN sample), the samples including silicon nitride (TiSiN 3cycle, TiSiN 10cycle, TiSiN 15cycle) exhibit lower row hammering performance without substantially affecting the refresh rate.

[0073] Furthermore, the sample prepared using three (3) deposition cycles (TiSiN 3cycle) exhibited improved (e.g., lower) line hammer performance compared to the two remaining samples (TiSiN 10cycle, TiSiN 15cycle) without significantly affecting the resistance. Thus, it was determined that even a minimal amount of silicon nitride between the two portions of titanium nitride would still result in improved line hammer performance. However, it was unexpectedly found that the inclusion of less than about An access line structure having a silicon nitride layer of a thickness of about 1000 nm (e.g., formed using less than three (3) deposition cycles) provides substantially the same row hammering properties as a conventional word line structure (e.g., a word line structure without a barrier material) and includes a thickness of greater than about 1000 nm. Access line structures having a thickness of barrier material (e.g., formed using 15 or more deposition cycles) may cause undesirably increased resistivity levels within electronic devices. Additionally, samples prepared using three (3) deposition cycles (TiSiN 3cycle) exhibited lower resistivity relative to control access line structures (single TiN sample), which was also unexpected. A reduction in resistivity of approximately 33% was observed for the TiSiN 3cycle sample, and an improvement in uniformity (e.g., step coverage) of approximately three (3) times greater than that of the single TiN sample was also observed. These results are believed to indicate an improvement in the performance of an insulating material (e.g., gate dielectric material) that isolates conductive materials due to a reduction (e.g., prevention) of the formation of chlorine-related trapping sites that can cause defects within the gate dielectric material (e.g., at its interface). One of ordinary skill in the art will appreciate that the selective arrangement of materials (e.g., thickness) and the formation of such materials, including the type of material, precursors, processing conditions (e.g., temperature), etc., can be selected to achieve desired performance requirements while minimizing undesirable resistivity levels, and that these variables can be optimized to achieve improved row hammering properties.

[0074] The methods, apparatus, devices (e.g., memory devices such as DRAM devices), and electronic systems of the present disclosure may contribute to one or more of the following: improved performance, improved efficiency, improved reliability, and increased durability compared to conventional methods, conventional apparatus, conventional devices, and conventional electronic systems.

[0075]

[0013] Embodiments of the present disclosure may be further characterized as set forth below but are not limited to the manner set forth below.

[0076] Embodiment 1: A device comprising: a memory array including access lines, each of the access lines comprising: an insulating material adjacent to a bottom surface and side walls of a substrate material; a first conductive material adjacent to the insulating material; a second conductive material adjacent to the first conductive material; and a barrier material between the first conductive material and the second conductive material, the barrier material being configured to inhibit migration of reactive species from the second conductive material.

[0077] Embodiment 2: The apparatus of Embodiment 1, wherein the first conductive material comprises a first metal nitride material and the second conductive material comprises a second metal nitride material.

[0078] Embodiment 3: The apparatus of Embodiment 2, wherein each of the first metal nitride material and the second metal nitride material comprises titanium nitride, and the barrier material is configured to inhibit migration of chlorine from the second metal nitride material.

[0079] Embodiment 4: The apparatus of any of embodiments 1 to 3, wherein the first conductive material comprises titanium nitride and the second conductive material comprises tungsten, the barrier material being configured to inhibit migration of fluorine from the tungsten.

[0080] Embodiment 5: The apparatus of any one of embodiments 1 to 4, wherein the barrier material is directly adjacent to an upper surface and sidewalls of the first conductive material, and the second conductive material is directly adjacent to an upper surface and sidewalls of the barrier material.

[0081] Embodiment 6: The apparatus of any one of embodiments 1 to 5, wherein an average thickness of the first conductive material is relatively smaller than an average thickness of the second conductive material, and an average thickness of the barrier material is relatively smaller than an average thickness of the first conductive material.

[0082] Embodiment 7: The apparatus of any one of embodiments 1 to 6, wherein the first conductive material on the insulating material comprises a uniform thickness along its length.

[0083] Embodiment 8: The apparatus of any one of embodiments 1 to 7, wherein the barrier material comprises a uniform thickness along its length.

[0084] Embodiment 9: The apparatus of any one of embodiments 1 to 8, wherein the barrier material comprises at least one of silicon nitride, boron nitride, germanium nitride, aluminum nitride, silicon oxynitride, boron oxynitride, germanium oxynitride, aluminum oxynitride, or silicon carbonitride.

[0085] Embodiment 10: The device of any one of embodiments 1 to 9, wherein the barrier material comprises between about About The thickness between.

[0086] Embodiment 11: A method of forming a device, comprising: forming at least one insulating material within and adjacent to a groove in a substrate material; forming a first conductive material adjacent to an exposed surface of the at least one insulating material; forming a barrier material adjacent to the first conductive material; and forming a second conductive material adjacent to the barrier material, wherein the barrier material is formulated to reduce the diffusion of reactive species from the second conductive material and into the at least one insulating material.

[0087] Embodiment 12: The method according to embodiment 11 further comprises: removing a portion of each of the first conductive material, the barrier material and the second conductive material so that the first conductive material, the barrier material and the second conductive material are recessed within the groove, wherein the barrier material is formulated to reduce the diffusion of reactive species generated during the removal of the second conductive material.

[0088] Embodiment 13: The method according to embodiment 12 further includes forming a conductive structure within the groove and above the recessed first conductive material, the recessed barrier material and the recessed second conductive material, wherein the conductive structure includes at least one of a metal, an alloy, a conductive metal oxide, a conductive metal nitride, a conductive metal silicide or a conductively doped semiconductor material.

[0089] Embodiment 14: A method according to any one of embodiments 11 to 13, wherein: forming the first conductive material includes forming a metal nitride material using a first conformal deposition process; forming the barrier material includes forming a silicon nitride material using a second conformal deposition process; and forming the second conductive material includes forming a second metal nitride material using a third conformal deposition process, and one or more of the first conformal deposition process, the second conformal deposition process, and the third conformal deposition process include an in-situ conformal deposition process.

[0090] Embodiment 15: A method according to any one of embodiments 11 to 14, wherein forming each of the first conductive material, the barrier material, and the second conductive material includes depositing each of the first conductive material, the barrier material, and the second conductive material using a single continuous ALD process or a single continuous CVD process in the same deposition chamber.

[0091] Embodiment 16: The method of any one of embodiments 11 to 15, wherein forming the barrier material comprises forming a About The thickness of the barrier material is between .

[0092] Embodiment 17: A method according to any one of embodiments 11 to 16, wherein forming the second conductive material adjacent to the barrier material includes depositing a metal nitride material above the upper surface and sidewalls of the barrier material using an ALD process, a CVD process, a PVD process, a single wafer process, a furnace process, or a combination thereof.

[0093] Embodiment 18: The method of Embodiment 17, wherein depositing the metal nitride material over the upper surface and sidewalls of the barrier material comprises depositing a titanium nitride material on the upper surface and sidewalls of a silicon nitride material.

[0094] Embodiment 19: A method according to any one of embodiments 11 to 18, wherein forming the barrier material includes conformally forming a silicon nitride material having an amorphous structure between two metal nitride materials, each of the two metal nitride materials having a columnar grain structure at a grain boundary with the barrier material.

[0095] Embodiment 20: An electronic system comprising: an input device; an output device; a processor device operably coupled to the input device and the output device; and a memory device operably coupled to the processor device and comprising memory cells, one or more of the memory cells comprising: one or more insulating materials adjacent to a bottom surface and side walls of a substrate material; a first conductive material overlying the one or more insulating materials; a barrier material overlying the first conductive material; and a second conductive material overlying the barrier material, the barrier material being formulated to prevent reactive species from diffusing from the second conductive material.

[0096] Embodiment 21: The electronic system according to embodiment 20 further comprises: a gate structure which is in the groove and vertically covers the base material; and a gate dielectric material which is between the gate structure and the base material, the gate dielectric material comprising at least a portion of the one or more insulating materials.

[0097] Embodiment 22: The electronic system of Embodiment 20 or Embodiment 21, wherein the first conductive material comprises titanium nitride, and the second conductive material comprises titanium nitride, tungsten, or tungsten nitride.

[0098] Embodiment 23: The electronic system of Embodiments 20 to 22, wherein each of the first conductive material and the second conductive material comprises titanium nitride, and the barrier material comprises silicon nitride.

[0099] Embodiment 24: The electronic system of Embodiments 20-23, wherein the barrier material substantially surrounds the first conductive material on at least three sides.

[0100] Embodiment 25: The electronic system of embodiments 20 to 24, wherein: each of the first conductive material and the second conductive material comprises a crystalline titanium nitride material; and the barrier material comprises an amorphous silicon nitride material between the first conductive material and the second conductive material.

[0101] Embodiment 26: The electronic system of embodiments 20 to 25, wherein: the first conductive material comprises between about About The barrier material comprises an average thickness between about About and the second conductive material comprises an average thickness between about About The average thickness between.

[0102] Although the present disclosure is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, the present disclosure is not intended to be limited to the specific forms disclosed. Rather, the present disclosure encompasses all modifications, equivalents, and alternatives that fall within the scope of the present disclosure as defined by the appended claims and their legal equivalents.

Claims

1. A memory device, comprising: A memory array comprising access lines extending through a substrate material, the substrate material comprising at least one drain region and at least one source region, each of the access lines comprising: an insulating material adjacent to the bottom surface and sidewalls of the base material; a first conductive material adjacent to the insulating material and laterally adjacent to the at least one drain region and the at least one source region; a second conductive material adjacent to the first conductive material; and A barrier material is disposed between the first conductive material and the second conductive material, the barrier material comprising a silicon nitride material having an amorphous structure and configured to inhibit migration of reactive species from the second conductive material, each of the first conductive material and the second conductive material having a columnar grain structure at a grain boundary with the barrier material. 2 . The memory device of claim 1 , wherein the first conductive material comprises a first metal nitride material and the second conductive material comprises a second metal nitride material.

3. The memory device of claim 2, wherein each of the first metal nitride material and the second metal nitride material comprises titanium nitride, and the barrier material is configured to inhibit migration of chlorine from the second metal nitride material.

4. The memory device of any one of claims 1 to 3, wherein the first conductive material comprises titanium nitride and the second conductive material comprises tungsten, the barrier material being configured to inhibit migration of fluorine from the tungsten.

5. The memory device of any one of claims 1 to 3, wherein the barrier material is directly adjacent to an upper surface and sidewalls of the first conductive material, and the second conductive material is directly adjacent to an upper surface and sidewalls of the barrier material.

6. The memory device of any one of claims 1 to 3, wherein an average thickness of the first conductive material is relatively smaller than an average thickness of the second conductive material, and an average thickness of the barrier material is relatively smaller than an average thickness of the first conductive material.

7. The memory device of any one of claims 1-3, wherein the first conductive material adjacent to the insulating material comprises a uniform thickness along its length.

8. The memory device of any one of claims 1-3, wherein the barrier material comprises a uniform thickness along its length.

9. The memory device of any one of claims 1 to 3, wherein the barrier material comprises and The thickness between.

10. The memory device of any one of claims 1 to 3, wherein the substrate material comprises an active region including the at least one drain region and the at least one source region, the access line extending through the substrate material adjacent the active region.

11. The memory device of any one of claims 1 to 3, wherein the access lines are configured as word lines.

12. The memory device of any one of claims 1 to 3, further comprising a data line overlying the access line and a conductive plug structure directly between the data line and upper surfaces of the first conductive material, the second conductive material, and the barrier material.

13. The memory device of any one of claims 1-3, further comprising additional insulating material vertically overlying the insulating material.

14. A method of forming a memory device, comprising: forming at least one insulating material within and adjacent to the trench in a base material, the base material comprising at least one drain region and at least one source region; forming a first conductive material adjacent to an exposed surface of at least one insulating material and laterally adjacent to the at least one drain region and the at least one source region; forming a barrier material adjacent to the first conductive material, wherein the barrier material comprises a silicon nitride material having an amorphous structure; and forming a second conductive material adjacent to the barrier material, each of the first conductive material and the second conductive material having a columnar grain structure at a grain boundary with the barrier material, Wherein the barrier material is formulated to reduce diffusion of reactive species from the second conductive material and into the at least one insulating material.

15. The method of claim 14, further comprising: removing a portion of each of the first conductive material, the barrier material, and the second conductive material so that the first conductive material, the barrier material, and the second conductive material are recessed within the trench, Wherein the barrier material is formulated to reduce diffusion of reactive species generated during removal of the second conductive material.

16. The method of claim 15, further comprising forming a conductive structure within the trench and directly on the recessed first conductive material, the recessed barrier material, and the recessed second conductive material, wherein the conductive structure comprises at least one of a metal, an alloy, a conductive metal oxide, a conductive metal nitride, a conductive metal silicide, or a conductively doped semiconductor material.

17. The method according to any one of claims 14 to 16, wherein: Forming the first conductive material includes forming a first metal nitride material using a first conformal deposition process; forming the barrier material includes forming the silicon nitride material using a second conformal deposition process; and forming the second conductive material includes forming a second metal nitride material using a third conformal deposition process, One or more of the first conformal deposition process, the second conformal deposition process, and the third conformal deposition process include an in-situ conformal deposition process.

18. The method of any one of claims 14 to 16, wherein forming each of the first conductive material, the barrier material, and the second conductive material comprises depositing each of the first conductive material, the barrier material, and the second conductive material using a single continuous ALD process or a single continuous CVD process in the same deposition chamber.

19. The method of any one of claims 14 to 16, wherein forming the barrier material comprises forming a and The thickness of the barrier material is between .

20. The method of any one of claims 14 to 16, wherein forming the second conductive material adjacent to the barrier material comprises depositing a metal nitride material over an upper surface and sidewalls of the barrier material using an ALD process, a CVD process, a PVD process, a single wafer process, a furnace process, or a combination thereof.

21. The method of claim 20, wherein depositing the metal nitride material over the upper surface and sidewalls of the barrier material comprises depositing a titanium nitride material on the upper surface and sidewalls of the silicon nitride material of the barrier material.

22. The method of any one of claims 14-16, wherein forming the barrier material comprises conformally forming the silicon nitride material between two metal nitride materials.

23. A memory system comprising: Input device; Output device; a processor device operatively coupled to the input device and the output device; and a memory device operatively coupled to the processor device and comprising memory cells, one or more of the memory cells comprising: one or more insulating materials adjacent to a bottom surface and sidewalls of a base material including a drain region and at least one source region; a first conductive material overlying the one or more insulating materials, wherein an upper portion of the first conductive material vertically overlaps the drain region and the at least one source region; a barrier material comprising an amorphous silicon nitride material overlying the first conductive material; and A second conductive material overlies the barrier material, each of the first conductive material and the second conductive material comprising a crystalline titanium nitride material, the barrier material being formulated to prevent diffusion of reactive species from the second conductive material.

24. The memory system of claim 23, further comprising: a gate structure located in the trench and vertically overlying the base material; and A gate dielectric material is disposed between the gate structure and the base material, wherein the gate dielectric material includes at least a portion of the one or more insulating materials.

25. The memory system of claim 23 or claim 24, wherein the barrier material surrounds the second conductive material on at least three sides.

26. A memory system according to claim 23 or claim 24, wherein: The first conductive material includes and The average thickness between The barrier material includes and The average thickness between The second conductive material includes and The average thickness between.

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