Embedded circuit board, electronic device

Abstract

The present invention provides an embedded circuit board and an electronic device, comprising: a multi-layer circuit layer; at least a first core board and a second core board, which are arranged between two adjacent intermediate layers of the circuit layer; a plurality of slots are formed on the first core board and the second core board; and a plurality of components are correspondingly arranged in the plurality of slots. In this way, during the lamination process, the stresses generated by the circuit layers outside the first core board and the second core board are offset from each other, thereby preventing the circuit board from warping.

Description

Technical Field

[0001] This application relates to the technical field of chip embedding, and particularly to an embedded circuit board and an electronic device. Background Art

[0002] A printed circuit board is an important electronic component, a support for electronic components, and a provider of electrical connections for electronic components. To meet special performance requirements, more and more printed circuit boards adopt the method of embedding components in the board. However, embedding components in the board will cause the circuit board to warp during the lamination process of manufacturing the circuit board.

[0003] Currently, the main methods in the industry to solve the warping of circuit boards are as follows: 1. Extend the lamination time to release residual stress. However, using this method will cause the production cycle to increase exponentially and reduce production efficiency; 2. Perform pressure baking treatment after drilling to release mechanical pressure; 3. Perform hot press leveling before shipment. Using the second and third methods increases additional production costs and cannot solve the problem of circuit board warping at the source, resulting in a low production qualification rate. Summary of the Invention

[0004] This application mainly provides an embedded circuit board and an electronic device to prevent the circuit board from warping.

[0005] To solve the above technical problems, a technical solution provided by the present invention is: to provide an embedded circuit board, including: multiple circuit layers; at least a first core board and a second core board, disposed between two adjacent intermediate layers of the circuit layers; a plurality of slots are formed on the first core board and the second core board; a plurality of components are correspondingly disposed in the plurality of slots.

[0006] Among them, the plurality of components are symmetrically disposed.

[0007] Among them, the plurality of components are symmetrically disposed with respect to the plane between the first core board and the second core board as the mirror plane.

[0008] Among them, the surfaces of the first core board and the second core board are copper layers, and the thickness of the copper layers of the first core board and the second core board away from the intermediate layer is 60 - 80 um. The intermediate layer is multiple layers and is a copper layer, and the thickness of the intermediate layer is 150 - 200 um.

[0009] Among them, the thickness of each circuit layer is symmetrically disposed with respect to the plane between the first core board and the second core board as the mirror plane.

[0010] Wherein, at least a third core board is provided between the multi-layer circuit layers on the side of the first core board facing away from the second core board, and at least a fourth core board is provided between the multi-layer circuit layers on the side of the second core board facing away from the first core board; the first core board group composed of all the first core boards and the third core board and the second core board group composed of all the second core boards and the fourth core board are symmetrically arranged with respect to the plane between the first core board and the second core board as a mirror.

[0011] Wherein, all the embedded circuit boards are symmetrically arranged with respect to the plane between the first core board and the second core board as a mirror; or all the embedded circuit boards are rotationally symmetrically arranged with respect to the midpoint between the first core board and the second core board as the center.

[0012] Wherein, the multi-layer circuit layers further include an outer layer circuit layer, the outer layer circuit layer is located outside the intermediate layer, and the thickness of the outer layer circuit layer is 60 - 80 um, the thickness of the intermediate layer is 150 - 200 um, and the thickness of all the circuit layers from the intermediate layer to the outer layer circuit layer is 150 - 200 um.

[0013] Wherein, a first groove group is provided on the first core board, and a second groove group is provided at a position corresponding to the first groove group on the second core board; the components include a first power device and a second power device, all the first power devices are arranged in their respective grooves in the first groove group, and all the second power devices are arranged in their respective grooves in the second groove group; the first power devices located in the first groove group are interconnected with each other, and the second power devices located in the second groove group are interconnected with each other.

[0014] Wherein, all the first power devices are arranged in an array in their respective grooves in the first groove, the first power devices located in the same row are connected in series with each other to form a plurality of power device groups, and the plurality of power device groups are connected in parallel with each other; all the second power devices are arranged in an array in their respective grooves in the second groove, the second power devices located in the same row are connected in series with each other to form a plurality of power device groups, and the plurality of power device groups are connected in parallel with each other.

[0015] Among them, one side of the first power device close to the intermediate layer has a second connection terminal and a third connection terminal, and the other side has a first connection terminal; among them, the first connection terminal of one of the first power devices is connected to the second connection terminal of the adjacent first power device in the same row to connect the first power devices in the same row in series with each other to form a plurality of power device groups; among them, the second connection terminal of the first power device is connected to the intermediate layer close to the first core board, and the first connection terminals of the adjacent first power devices in the same row are connected to the copper layer on the surface of the first core board far from the intermediate layer to connect the plurality of power device groups in parallel; one side of the second power device close to the intermediate layer has a second connection terminal and a third connection terminal, and the other side has a first connection terminal; among them, the first connection terminal of one of the second power devices is connected to the second connection terminal of the adjacent second power device in the same row to connect the second power devices in the same row in series with each other to form a plurality of power device groups; among them, the second connection terminal of the second power device is connected to the intermediate layer close to the second core board, and the first connection terminals of the adjacent second power devices in the same row are connected to the copper layer on the surface of the second core board far from the intermediate layer to connect the plurality of power device groups in parallel.

[0016] Among them, the third connection terminals of all the first power devices are connected to one of the circuit layers in the circuit layer on the side of the first core board far from the second core board; the third connection terminals of all the second power devices are connected to one of the circuit layers in the circuit layer on the side of the second core board far from the first core board.

[0017] Among them, the embedded circuit board is applied to mobile devices, automotive devices, base station devices or sensing components.

[0018] To solve the above technical problems, the second technical solution provided by the present invention is: to provide an embedded circuit board, at least including a plurality of circuit layers; a core board disposed in the intermediate layer of the plurality of circuit layers; among them, the core board is provided with a plurality of slots; a plurality of components are correspondingly disposed in the plurality of slots; among them, the embedded circuit board is symmetrically disposed at least in part of the structure or part of the physical quantity with the core board as the center, so that the stress of the embedded circuit board is balanced when the temperature changes, and the warpage degree is reduced.

[0019] To solve the above technical problems, the third technical solution provided by the present invention is: to provide an electronic device, and the electronic device includes the embedded circuit board according to any one of the above.

[0020] The beneficial effects of the present invention are different from the prior art. The embedded circuit board provided by the present invention includes multiple circuit layers. Among them, a first core board and a second core board are arranged between two adjacent intermediate layers in the multiple circuit layers. Grooves are formed on the first core board and the second core board, and a plurality of components are respectively arranged in the plurality of grooves. In this way, when or after the embedded circuit board is laminated, the stress between the circuit layers outside the first core board and the second core board can be offset from each other to prevent the circuit board from warping. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a schematic structural diagram of the first embodiment of the embedded circuit board of the present invention;

[0022] Figure 2a and Figure 2b is Figure 1 a schematic diagram of the first power device interconnection structure and a schematic diagram of the second power device interconnection structure shown in;

[0023] Figure 3 is a schematic structural diagram of the second embodiment of the embedded circuit board of the present invention;

[0024] Figure 4 is a schematic flowchart of the third embodiment of the embedded circuit board of the present invention;

[0025] Figure 5 is a schematic structural diagram of an embodiment of the electronic device of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0026] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0027] Please refer to Figure 1 , which is a schematic structural diagram of the first embodiment of the embedded circuit board of the present invention. The embedded circuit board of this embodiment has multiple circuit layers. In addition to the multiple circuit layers, it also includes a first core board 11 and a second core board 12. The first core board 11 and the second core board 12 are located between the adjacent intermediate layers 13 and 14 of the multiple circuit layers. It can be understood that the first core board 11, the second core board 12, and the intermediate layers 13 and 14 are respectively bonded by prepregs. This embodiment is described by taking two circuit layers as an example.

[0028] In this embodiment, a plurality of slots are provided on both the first core board 11 and the second core board 12, and a plurality of components 15 are disposed in the slots. The first core board 11 and the second core board 12 are bonded by a prepreg 21. In one embodiment, the prepreg is a 1080 prepreg. To improve the adhesion between the first core board 11 and the second core board 12, multiple layers of 1080 prepregs can be provided. Specifically, in this embodiment, a first slot group is provided on the first core board 11, and a second slot group is provided at a position corresponding to the first slot group on the second core board 12; the components 15 include a first power device 151 and a second power device 152. The first power device 151 is disposed in respective slots in the first slot group, and the second power device 152 is disposed in respective slots in the second slot group. In this embodiment, one component 15 is disposed in one slot. In another embodiment, multiple components 15 can also be disposed in one slot.

[0029] In this embodiment, the first slot group and the second slot group in the first core board 11 and the second core board 12 can be through slots penetrating the first core board 11 and the second core board, or can be blind slots not penetrating the first core board 11 and the second core board. The intermediate layers 13 and 14 described in this embodiment are directly soldered to the surfaces of the first power device 151 and the second power device 152 by using solder. In another embodiment, the intermediate layers 13 and 14 can also be laminated on the surfaces of the first power device 151 and the second power device 152 through prepregs. Figure 1 The structural schematic diagram of the illustrated embodiment is described by taking the case of directly soldering to the surfaces of the first power device 151 and the second power device 152 by using solder as an example.

[0030] In one embodiment, the first power devices 151 located in the first slot group are interconnected, and the second power devices 152 located in the second slot group are interconnected. Both the surfaces of the first power device 151 and the second power device 152 have connection terminals (not shown in the figure). When the first power devices 151 in the first slot group are interconnected, the connection can be achieved through the intermediate layer 13 and the copper layer 112 adjacent to the first power device 151. When the second power devices 152 in the second slot group are interconnected, the connection can be achieved through the intermediate layer 14 and the copper layer 122 adjacent to the second power device 152.

[0031] Specifically, in one embodiment, all the first power devices 151 are arranged in an array in respective slots in the first slot group, and the first power devices 151 in the same row are connected in series with each other to form a plurality of power device groups. The plurality of power device groups are connected in parallel.

[0032] For details, please refer to Figure 2a, is a schematic structural diagram of an embodiment of the interconnection between the first power devices 151. The first power device 151 includes a first connection terminal 1511, a second connection terminal 1512, and a third connection terminal 1513. Among them, the first connection terminal 1511 is located on a surface of the first power device 151 close to the copper layer 112 of the first core board 11, and the second connection terminal 1512 and the third connection terminal 1513 are located on one side of the first power device 151 close to the intermediate layer 13. Among them, when the first power devices 151 in the same row are connected in series with each other to form a plurality of power device groups, the first connection terminal 1511 of a first power device 151 is connected to the second connection terminal 1512 of the adjacent first power device 151 in the same row, so as to connect the first power devices 151 in the same row in series with each other to form a plurality of power device groups. Specifically, the first connection terminal 1511 of a first power device 151 is connected to the second connection terminal 1512 of another first power device 151 through a conductive hole 113. After forming the power device group, the second connection terminal 1512 of the first power device 151 is connected to the intermediate layer 13 close to the first core board 11, and the first connection terminal 1511 of another first power device 151 is connected to the copper layer 112 on the surface of the first core board 11 far from the intermediate layer 13, so as to connect the plurality of power device groups in parallel.

[0033] Optionally, when interconnecting a plurality of first power devices 151, their first connection terminals 1511 and second connection terminals 1512 can be connected to the same line network of the same line layer, or can be connected to different line networks. Further, the first connection terminal 1511 and the second connection terminal 1512 can be connected to different line networks of different layers.

[0034] In this embodiment, the third connection terminals 1513 of all the first power devices 151 are connected to one of the line layers in the line layer on the side of the first core board 11 away from the second core board 12. Specifically, in one embodiment, the third connection terminal 1513 can be connected to the same line layer as the first connection terminal 1511 and the second connection terminal 1512, or can be connected to a different line layer.

[0035] In a specific embodiment, the first connection terminal 1511, the second connection terminal 1512, and the third connection terminal 1513 of the first power device 151 can correspond to the source electrode, the drain electrode, and the gate electrode, respectively.

[0036] All the second power devices 152 are arranged in an array in each slot of the second slot group. The second power devices 152 in the same row are connected in series with each other to form a plurality of power device groups, and the plurality of power device groups are connected in parallel with each other.

[0037] For details, please refer to Figure 2b, is a schematic structural diagram of an embodiment of the interconnection between the second power devices 152. The second power device 152 includes a first connection terminal 1521, a second connection terminal 1522, and a third connection terminal 1523. Among them, the first connection terminal 1521 is located on a surface of the second power device 152 close to the copper layer 122 of the second core board 12, and the second connection terminal 1522 and the third connection terminal 1523 are located on one side of the second power device 152 close to the intermediate layer 14. Among them, when the second power devices 152 in the same row are connected in series with each other to form a plurality of power device groups, the first connection terminal 1521 of a second power device 152 is connected to the second connection terminal 1522 of the adjacent second power device 152 in the same row, so as to connect the second power devices 152 in the same row in series with each other to form a plurality of power device groups. Specifically, the first connection terminal 1521 of a second power device 152 is connected to the second connection terminal 1522 of another second power device 152 through a conductive hole 123. After the power device group is formed, the second connection terminal 1522 of the second power device 152 is connected to the intermediate layer 14 close to the second core board 12, and the first connection terminal 1521 of another second power device 152 is connected to the copper layer 122 on the surface of the second core board 12 far from the intermediate layer 14, so as to connect the plurality of power device groups in parallel.

[0038] Optionally, when interconnecting a plurality of second power devices 152, their first connection terminals 1521 and second connection terminals 1522 can be connected to the same circuit network of the same circuit layer, or can be connected to different circuit networks. Further, the first connection terminal 1521 and the second connection terminal 1522 can be connected to different circuit networks of different layers.

[0039] In this embodiment, the third connection terminals 1523 of all the second power devices 152 are connected to one of the circuit layers in the circuit layer on the side of the second core board 12 away from the first core board 11. Specifically, in one embodiment, the third connection terminal 1523 can be connected to the same circuit layer as the first connection terminal 1521 and the second connection terminal 1522, or can be connected to different circuit layers.

[0040] In a specific embodiment, the first connection terminal 1521, the second connection terminal 1522, and the third connection terminal 1523 of the second power device 152 can correspond to the source electrode, the drain electrode, and the gate electrode, respectively.

[0041] In this embodiment, only one surface of the first core board 11 and the second core board 12 is provided with a copper layer, such as Figure 1As described above, one surface of the first core board 11 close to the second core board 12 has a copper layer 112, and one surface of the second core board 12 close to the first core board 11 has a copper layer 122. The surfaces of the first core board 11 and the second core board 12 without copper layers are connected to the intermediate layer. Specifically, one surface of the first core board 11 away from the second core board 12 without a copper layer is in contact with the intermediate layer 13, and one surface of the second core board 12 away from the first core board 11 without a copper layer is in contact with the intermediate layer 14.

[0042] In this embodiment, a plurality of first power devices 151 and a plurality of second power devices 152 are symmetrically arranged. Specifically, the plurality of first power devices 151 and the plurality of second power devices 152 are arranged in mirror symmetry along the plane between the first core board 11 and the second core board 12. In this way, when pressing, the warping of the circuit board caused by the deformation of the first power device 151 and the second power device 152 can be reduced.

[0043] Furthermore, in this embodiment, the first core board 11, the intermediate layer 13, the second core board 12, and the intermediate layer 14 are symmetrically arranged. Specifically, the first core board 11, the intermediate layer 13, the second core board 12, and the intermediate layer 14 are arranged in mirror symmetry along the plane between the first core board 11 and the second core board 12.

[0044] In this embodiment, the intermediate layer 13 and the intermediate layer 14 are the outer circuit layers of the multi-layer circuit layers. In order to facilitate surface mounting of other electronic devices on the surface of the embedded circuit board and achieve high-density wiring of the circuit board, the thickness of the intermediate layer 13 and the intermediate layer 14 is 60 - 80 um. If there are also circuit layers outside the intermediate layer 13 and the intermediate layer 14, in order to facilitate the transmission of large currents, the thickness of the intermediate layer 13 and the intermediate layer 14 is 150 - 200 um.

[0045] The first core board 11 and the second core board 12 described in this embodiment are both copper-clad laminates, which are composed of prepregs 111, 121 and copper layers 112, 122. They are the basic materials for manufacturing circuit boards.

[0046] For the embedded circuit board provided in this embodiment, in order to solve the problem that the circuit board warps during the pressing process and the circuit board is uneven, the embedded circuit board is set as a symmetric structure. In this way, when pressing, the stresses generated by the circuit boards on both sides of the symmetry line can cancel each other out, thereby preventing the circuit board from warping and making the circuit board flatter.

[0047] Please refer to Figure 3 , which is a schematic structural diagram of the second embodiment of the embedded circuit board of the present invention. This embodiment is the same as Figure 1Compared with the first embodiment shown, the difference is that: the embedded circuit board shown in this embodiment further has a third core board 15 on the side of the first core board 11 away from the second core board 12, and a fourth core board 16 on the side of the second core board 12 away from the first core board 11.

[0048] It can be understood that when the third core board 15 is arranged on the side of the first core board 11 away from the second core board 12, the third core board 15 can be directly soldered to the surface of the first core board 11 with solder, or the third core board 15 can be bonded to the first core board 11 with a prepreg. When the fourth core board 16 is arranged on the side of the second core board 12 away from the first core board 11, similarly, the fourth core board 16 can be directly soldered to the surface of the second core board 12 with solder, or the fourth core board 16 can be bonded to the second core board 12 with a prepreg, as long as it can satisfy that the first core board 11 and the third core board 15 are symmetric with the second core board 12 and the fourth core board 16 along the plane between the first core board 11 and the second core board 12, which will not be elaborated here.

[0049] Figure 3 The embedded circuit board shown includes one layer of the third core board 15 and one layer of the fourth core board 16. In another embodiment, the third core board 15 and the fourth core board 16 can be multi-layered.

[0050] Furthermore, both surfaces of the third core board 15 and the fourth core board 16 provided in this embodiment are covered with copper foil layers. As Figure 3 shown, the third core board 15 includes a prepreg 152 and copper layers 151 and 153 on both sides of the prepreg 152; the fourth core board 16 includes a prepreg 162 and copper layers 161 and 163 on both sides of the prepreg 162. In this embodiment, in order to enable the embedded circuit board to achieve large-current transmission in application, the copper layers 151, 153 on both surfaces of the third core board 15 and the copper layers 161, 163 on both surfaces of the fourth core board 16 are all thick copper layers, and their thickness is 150 - 200 μm. Preferably, in one embodiment, the copper layers 151, 153 on both surfaces of the third core board 15 and the copper layers 161, 163 on both surfaces of the fourth core board 16 are all 175 μm.

[0051] Specifically, the thicknesses of the respective copper layers of the third core board 15 and the fourth core board 16 in this embodiment are the same, and they are mirror-symmetric along the plane between the first core board 11 and the second core board 12. In this way, the stresses generated on the upper and lower surfaces can cancel each other out during the lamination process, preventing the circuit board from warping, and thus making the surface of the embedded circuit board flatter.

[0052] Specifically, the embedded circuit board shown in this embodiment further includes an intermediate layer 13 on the side of the third core board 15 away from the first core board 11, and an intermediate layer 14 on the side of the fourth core board 16 away from the second core board 12. In this embodiment, the intermediate layer 13 and the intermediate layer 14 are located on the outer layer of the embedded circuit board. To facilitate the mounting of other electronic devices on the outer side of the embedded circuit board and enable high-density wiring on the outer side of the embedded circuit board, the thickness of the intermediate layer 13 and the intermediate layer 14 is 60 - 80 um. Preferably, in one embodiment, the thickness of the intermediate layer 13 and the intermediate layer 14 is 66 um, 70 um, 73 um, or 75 um.

[0053] In this embodiment, the intermediate layer 13, the first core board 11, the third core board 15 are symmetrical with the intermediate layer 14, the second core board 12, the fourth core board 16. Specifically, the intermediate layer 13, the first core board 11, the third core board 15 and the intermediate layer 14, the second core board 12, the fourth core board 16 are arranged in mirror symmetry along the plane between the first core board 11 and the second core board 12.

[0054] Optionally, in one embodiment, the first core board 11, the intermediate layer 13, the third core board 15 can also be rotationally symmetric along the center point between the first core board 11 and the second core board 12.

[0055] It can be understood that in order to achieve the conduction between the copper layers in the embedded circuit board, via holes (not shown in the figure) are provided between the layers in the middle of the embedded circuit board described in this application. Further, the via holes provided in the embedded circuit board are also arranged in mirror symmetry along the plane between the first core board 11 and the second core board.

[0056] For the embedded circuit board provided in this embodiment, the first core board and the second core board embedding components and the respective circuit layers outside the first core board and the second core board are symmetrically arranged, so that when the circuit board is laminated after production, the warping of the circuit board can be reduced. In addition, in order to make the embedded circuit board suitable for high-current transmission in applications, the embedded circuit board provided by the present invention includes multiple thick copper layers.

[0057] Please refer to Figure 4 , which is a schematic structural diagram of the third embodiment of the embedded circuit board of the present invention. Compared with the second embodiment shown above Figure 3 , the difference is that: the embedded circuit board shown in this embodiment further includes a via hole 17 for conducting the intermediate layer 13, the third core board 15, the first core board 11 and the second core board 12, the fourth core board 16, the intermediate layer 14. The via hole 17 conducts all the circuit layers of the embedded circuit board. It can be understood that isolation rings are provided at positions where conduction is not required. Details are not described herein again.

[0058] The embedded circuit board described in this embodiment further includes blind vias 18 for conducting the intermediate layer 13, the third core board 15, and the first core board 11, and blind vias 19 for conducting the intermediate layer 14, the fourth core board 16, and the second core board 12. In this embodiment, the through hole 17, the blind vias 18, and the blind vias 19 are symmetrically arranged along the plane between the first core board 11 and the second core board 12.

[0059] In the circuit board provided in this application, there are also other via holes for conducting circuit layers. Each of the via holes can be symmetrically arranged along the plane between the first core board 11 and the second core board 12, or can be asymmetrically arranged, as long as the surface of the embedded circuit board can be kept flat. Details are not described herein again.

[0060] As provided by the present invention Figures 1 to 4 The shown embedded circuit board can be applied to mobile devices, automotive devices, base station devices, or sensing components. Due to its copper layer setting of 150 - 200um, it can support the transmission of large currents during use.

[0061] In the embedded circuit board provided in this application, the first core board and the second core board are arranged between two adjacent intermediate layers of the multi - layer circuit board, and components are arranged in the groove bodies of the first core board and the second core board. When the embedded circuit board is pressed in this way, the stresses between the circuit layers outside the first core board and the second core board cancel each other out, which can prevent the circuit board from warping and thus make the surface of the circuit board uneven.

[0062] Please refer to Figure 5 , which is a schematic structural diagram of an embodiment of the electronic device of the present invention. The electronic device provided by the present invention includes the embedded circuit board 51 described in any one of the above Figures 1 to 4 embodiments. The electronic device provided by the present invention can be a mobile device, an automotive device, a base station device, or a sensing component. Optionally, the electronic device provided by the present invention can support the transmission of large currents during application.

[0063] The above is only the implementation manner of this application, and does not limit the patent scope of this application. All equivalent structural or equivalent process transformations made by using the content of the specification and drawings of this application, directly or indirectly applied in other related technical fields, are equally included in the patent protection scope of this application.

Claims

1. An embedded circuit board, characterized in that, Comprising at least: Multiple circuit layers; At least a first core board and a second core board, disposed between two adjacent intermediate layers of the circuit layers; A plurality of slots are formed on the first core board and the second core board; A plurality of components, correspondingly disposed in the plurality of slots; Wherein, the plurality of components are symmetrically disposed; and the plurality of components are symmetrically disposed with respect to the plane between the first core board and the second core board as a mirror; A first slot group is disposed on the first core board, and a second slot group is disposed at a position corresponding to the first slot group on the second core board; the components include a first power device and a second power device, and all the first power devices are disposed in their respective slots in the first slot group, and all the second power devices are disposed in their respective slots in the second slot group; The first power devices located in the first slot group are interconnected with each other, and the second power devices located in the second slot group are interconnected with each other; Wherein, one side of the first power device close to the intermediate layer has a second connection terminal and a third connection terminal, and the other side has a first connection terminal; Wherein, at least the mutually adjacent respective surfaces of the first core board and the second core board are provided with copper layers, and the thickness of the copper layers of the first core board and the second core board away from the intermediate layer is 60 - 80 um, the intermediate layer is one or more layers, and the intermediate layer is a copper layer, and the thickness of the intermediate layer is 150 - 200 um; The thickness of each layer of the circuit layers is symmetrically disposed with respect to the plane between the first core board and the second core board as a mirror.

2. The embedded circuit board according to claim 1, wherein At least a third core board is disposed between the multiple circuit layers on the side of the first core board facing away from the second core board, and at least a fourth core board is disposed between the multiple circuit layers on the side of the second core board facing away from the first core board; All the first core boards and the third core boards constituting the first core board group and all the second core boards and the fourth core boards constituting the second core board group are symmetrically disposed with respect to the plane between the first core board and the second core board as a mirror.

3. The embedded circuit board according to claim 1, wherein All the embedded circuit boards are symmetrically disposed with respect to the plane between the first core board and the second core board as a mirror; or, All the embedded circuit boards are rotationally symmetrically disposed centered on the midpoint between the first core board and the second core board.

4. The embedded circuit board according to claim 1, wherein The multiple circuit layers include an outer circuit layer, the outer circuit layer is located outside the intermediate layer, and the thickness of the outer circuit layer is 60 - 80 um, the thickness of the intermediate layer is 150 - 200 um, and the thickness of all the circuit layers from the intermediate layer to the outer circuit layer is 150 - 200 um.

5. The embedded circuit board according to claim 1, wherein All the first power devices are arranged in an array in their respective slots in the first slot, the first power devices in the same row are connected in series with each other to form a plurality of power device groups, and the plurality of power device groups are connected in parallel; All the second power devices are arranged in an array in each slot of the second slot body. The second power devices in the same row are connected in series with each other to form a plurality of power device groups, and the plurality of power device groups are connected in parallel with each other.

6. The embedded circuit board according to claim 5, wherein the first connection terminal of one of the first power devices is connected to the second connection terminal of the adjacent first power device in the same row to connect the first power devices in the same row in series with each other to form a plurality of power device groups; wherein, the second connection terminal of the first power device is connected to the intermediate layer close to the first core board, and the first connection terminals of the adjacent first power devices in the same row are connected to the copper layer on the surface of the first core board away from the intermediate layer to connect the plurality of power device groups in parallel; one side of the second power device close to the intermediate layer has a second connection terminal and a third connection terminal, and the other side has a first connection terminal; wherein, the first connection terminal of one of the second power devices is connected to the second connection terminal of the adjacent second power device in the same row to connect the second power devices in the same row in series with each other to form a plurality of power device groups; wherein, the second connection terminal of the second power device is connected to the intermediate layer close to the second core board, and the first connection terminals of the adjacent second power devices in the same row are connected to the copper layer on the surface of the second core board away from the intermediate layer to connect the plurality of power device groups in parallel.

7. The embedded circuit board according to claim 6, wherein the third connection terminals of all the first power devices are connected to one of the circuit layers in the circuit layer on the side of the first core board away from the second core board; the third connection terminals of all the second power devices are connected to one of the circuit layers in the circuit layer on the side of the second core board away from the first core board.

8. The embedded circuit board according to claim 7, characterized in that, The embedded circuit board is applied to mobile devices, automotive devices, base station devices or sensing components.

9. An electronic device, characterized in that, The electronic device includes the embedded circuit board according to any one of claims 1 to 8 above.

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