A chip layout structure of a single switch IGBT module

Abstract

The present invention discloses a chip layout structure of a single switch IGBT module, which is composed of three groups of IGBT chipsets; each group of IGBT chipsets is composed of 8 IGBT chips and 4 anti-parallel freewheeling diode FRD chips; each group of IGBT chipsets is welded on two upper and lower DBC linings; on the upper and lower DBC linings, the gates of the IGBT chips located at the upper left and upper right positions are located at the lower middle position of the IGBT chip; the gates of the IGBT chips located at the lower left and lower right positions are located at the upper middle position of the IGBT chip; the anti-parallel freewheeling diode FRD chip is located between the upper and lower IGBT chips of the same DBC lining. In the structure of the present invention, the junction temperature rise of the IGBT chip is reduced by about 2°C, and the reduction of the junction temperature rise of the chip is conducive to the long-term stable operation of the chip.

Description

Technical Field

[0001] The invention belongs to the technical field of controllable power semiconductor devices, and in particular relates to a chip layout structure of a single-switch IGBT module. Background Art

[0002] The chip layout of a traditional single-switch IGBT module is as follows: Figure 1 As shown, it is composed of three groups of IGBT chip groups, each group of IGBT chip groups is composed of 8 IGBT chips and 4 anti-parallel freewheeling diodes FRD. The back of the first group of IGBT chips 1-1, 1-2, 1-3, 1-4, 1-5, 1-6, 1-7, 1-8 and the anti-parallel FRD chips 1-9, 1-10, 1-11, 1-12 are welded on the DBC liner 1, 2, and the front of each chip is connected through the bonding wire group 10-1, 10-2; the second group of IGBT chips 2-1, 2-2, 2-3, 2-4, 2-5, 2-6, 2-7, 2-8 and the anti-parallel FRD chips 2-9, The backs of 2-10, 2-11, and 2-12 are welded on DBC substrates 3 and 4, and the front of each chip is connected through bonding wire groups 10-3 and 10-4; the backs of the third group of IGBT chips 3-1, 3-2, 3-3, 3-4, 3-5, 3-6, 3-7, and 3-8 and the anti-parallel FRD chips 3-9, 3-10, 3-11, and 3-12 are welded on DBC substrates 5 and 6, and the front of each chip is connected through bonding wire groups 10-5 and 10-6; DBC substrates 1, 2, 3, 4, 5, and 6 are welded on substrate 7; the three groups of IGBT chip groups are connected to the external circuit via the positive terminal 8 and the negative terminal 9.

[0003] In the chip layout of the above-mentioned traditional single-switch IGBT module, since the IGBT chip and the FRD chip are uniformly distributed in sequence, the uniformity of the temperature rise on the substrate caused by the loss of the IGBT chip and the FRD chip is generally not considered in detail. When the chip current increases, it leads to a more obvious thermal coupling effect, and the temperature non-uniformity increases significantly, which greatly increases the failure risk of high junction temperature chips. Due to the difference in size and loss between the IGBT chip and the FRD chip, a certain temperature gradient is generated, resulting in uneven base plate temperature. Due to the thermal coupling effect, when the chip current increases, the temperature non-uniformity increases significantly, which greatly increases the failure risk of high junction temperature chips. If the junction temperature of the chip is too high, it is easy to cause chip failure or even damage the main circuit. For this reason, it is necessary to take corresponding layout adjustment and optimization measures to improve the junction temperature rise of certain IGBT chips. Summary of the invention

[0004] The purpose of the present invention is to provide a chip layout structure of a single-switch IGBT module to solve the problem of high junction temperature rise of the IGBT chip in the existing module, and to reduce the chip junction temperature by further optimizing the chip layout to avoid premature chip failure.

[0005] To achieve the above object, the technical solution adopted by the present invention is as follows:

[0006] The present invention provides a chip layout structure of a single switch IGBT module, which is composed of three groups of IGBT chipsets; each group of IGBT chipsets is composed of 8 IGBT chips and 4 anti-parallel freewheeling diode FRD chips; each group of IGBT chipsets is welded on two upper and lower DBC liner boards; the DBC liner boards are welded on a substrate; each group of IGBT chipsets is configured with a positive terminal and a negative terminal, and the three groups of IGBT chipsets are connected to an external circuit through the positive terminal and the negative terminal; the front sides of the chips on the DBC liner boards are connected through a bonding wire group;

[0007] On the upper and lower DBC substrates, the gates of the IGBT chips located at the upper left and upper right positions are located at the lower middle position of the IGBT chip; the gates of the IGBT chips located at the lower left and lower right positions are located at the upper middle position of the IGBT chip; the anti-parallel freewheeling diode FRD chip is located between the upper and lower IGBT chips on the same DBC substrate.

[0008] Furthermore, in each IGBT chipset, the back sides of every four IGBT chips and two anti-parallel freewheeling diode (FRD) chips are welded on a DBC liner.

[0009] Furthermore, the four IGBT chips and the two freewheeling diode FRD chips on each DBC substrate are symmetrically distributed about the center of the DBC substrate.

[0010] Furthermore, in each group of IGBT chipsets, the upper DBC liner and the lower DBC liner are symmetrically distributed about the center line of the IGBT module substrate and the center of the substrate.

[0011] Furthermore, the sizes of the IGBT chip and the FRD chip are adjusted according to voltage and current requirements.

[0012] Furthermore, the IGBT chip and the FRD chip are chips based on silicon, silicon carbide and gallium nitride.

[0013] Furthermore, the substrate is an AlSiC substrate.

[0014] The beneficial effects achieved by the present invention are:

[0015] The present invention proposes a chip layout of a multi-chip parallel single-switch IGBT module, which calculates the junction temperature rise of the IGBT chip by simulating the power loss of the IGBT module and simulating the temperature distribution of the IGBT chip when the IGBT module is working in a steady state. The IGBT chip position is changed and the gate position is changed, so that the thermal coupling effect between the IGBT chips is reduced, so that the temperature of the IGBT chip with the highest junction temperature in the layout is reduced; under the same operating loss, by comparing the junction temperature rise of the corresponding IGBT chip in the original IGBT module, it can be seen that the junction temperature rise of the IGBT chip in the structure of the present invention is reduced by about 2°C, and the reduction of the chip junction temperature rise is conducive to the long-term stable operation of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 The chip layout for a traditional single-switch IGBT module;

[0017] Figure 2 This is the chip layout of the single-switch IGBT module proposed by the present invention. DETAILED DESCRIPTION

[0018] The present invention is further described below. The following examples are only used to more clearly illustrate the technical solution of the present invention, and are not intended to limit the protection scope of the present invention.

[0019] The present invention provides a chip layout structure of a single switch IGBT module, which is composed of three groups of IGBT chipsets. Each group of IGBT chipsets is composed of 8 IGBT chips and 4 anti-parallel freewheeling diode FRD chips. Each group of IGBT chipsets is welded on two upper and lower DBC linings. Specifically, the backs of each of the 4 IGBT chips and the 2 anti-parallel freewheeling diode FRD chips are welded on one DBC lining. Each group of IGBT chipsets is configured with a positive terminal and a negative terminal, and the three groups of IGBT chipsets are connected to an external circuit through the positive terminal and the negative terminal.

[0020] Specifically, in each IGBT chipset group, the upper DBC liner and the lower DBC liner are symmetrically distributed about the center line of the IGBT module substrate and the center of the substrate.

[0021] Specifically, the four IGBT chips and the two freewheeling diode FRD chips on each DBC substrate are symmetrically distributed about the center of the DBC substrate.

[0022] Specifically, in each IGBT chip group, on the upper DBC substrate and the lower DBC substrate, the gate of the IGBT chip located at the upper left and upper right positions is located at the lower middle position of the IGBT chip; the gate of the IGBT chip located at the lower left and lower right positions is located at the upper middle position of the IGBT chip; the anti-parallel freewheeling diode FRD chip is located between the upper and lower IGBT chips of a DBC substrate. The front sides of the chips are connected through a bonding wire group.

[0023] Preferably, the sizes of the IGBT chip and the FRD chip can be adjusted according to voltage and current requirements.

[0024] Preferably, the IGBT chip and the FRD chip are chips based on silicon, silicon carbide and gallium nitride. Example

[0025] The embodiment of the present invention provides a chip layout structure of a single switch IGBT module with multiple chips connected in parallel. Figure 1 The following improvements are made to the layout structure shown:

[0026] For the first group of IGBT chips: the positions of IGBT chips 1-3, 1-4, 1-7, and 1-8 remain unchanged, the positions of IGBT chip 1-1 and FRD chip 1-9 are swapped, the positions of IGBT chip 1-2 and FRD chip 1-10 are swapped, the positions of IGBT chip 1-5 and FRD chip 1-11 are swapped, and the positions of IGBT chip 1-6 and FRD chip 1-12 are swapped. The gates of IGBT chips 1-1, 1-2, 1-5, and 1-6 are moved upward and parallel from the center of the IGBT chip to the upper middle position of the IGBT chip. -7, the gate of 1-8 is moved downward in parallel from the center position of the IGBT chip to the lower middle position of the IGBT chip; for the second group of IGBT chips: the positions of IGBT chips 2-3, 2-4, 2-7, and 2-8 remain unchanged, the positions of IGBT chip 2-1 and FRD chip 2-9 are swapped, the positions of IGBT chip 2-2 and FRD chip 2-10 are swapped, the positions of IGBT chip 2-5 and FRD chip 2-11 are swapped, and the positions of IGBT chip 2-6 and FRD chip 2-12 are swapped. The gates of IGBT chips 2-1, 2-2, 2-5, and 2-6 are moved parallelly upward from the center of the IGBT chip to the upper middle position of the IGBT chip, and the gates of IGBT chips 2-3, 2-4, 2-7, and 2-8 are moved parallelly downward from the center of the IGBT chip to the lower middle position of the IGBT chip; for the third group of IGBT chips: the positions of IGBT chips 3-3, 3-4, 3-7, and 3-8 remain unchanged, the positions of IGBT chip 3-1 and FRD chip 3-9 are interchanged, the positions of IGBT chip 3-2 and FRD chip 3-10 are interchanged, the positions of IGBT chip 3-5 and FRD chip 3-11 are interchanged, and the positions of IGBT chip 3-6 and FRD chip 3-12 are interchanged. The gates of IGBT chips 3-1, 3-2, 3-5, and 3-6 are moved parallel upward from the center of the IGBT chip to the upper middle position of the IGBT chip, and the gates of IGBT chips 3-3, 3-4, 3-7, and 3-8 are moved parallel downward from the center of the IGBT chip to the lower middle position of the IGBT chip. After the chip positions are interchanged, the bonding wire connection does not change, and the copper layer layout on the DBC liner is adjusted accordingly. After the gate position is moved, the gate bonding wire bonding is smoother.

[0027] Based on the above improvements, an embodiment of the present invention provides a single switch IGBT module chip packaging structure as shown in FIG. Figure 2 As shown:

[0028] It consists of three groups of IGBT chipsets, each of which consists of 8 IGBT chips and 4 anti-parallel freewheeling diodes FRD, and each group of IGBT chipsets is welded on the upper and lower DBC liner plates.

[0029] In the first group of IGBT chips, the gates of the IGBT chips 1-4 at the upper left and the IGBT chips 1-3 at the upper right of the upper DBC substrate 1 are located in the lower middle of the IGBT chips, the gates of the IGBT chips 1-2 at the lower left and the IGBT chips 1-1 at the lower right are located in the upper middle of the IGBT chips, an anti-parallel freewheeling diode FRD chip 1-9 is located between the IGBT chips 1-3 and the IGBT chips 1-1, and another anti-parallel freewheeling diode FRD chip 1-10 is located between the IGBT chips 1-4 and the IGBT chips 1-2; the backs of the IGBT chips 1-1, 1-2, 1-3, 1-4 and the anti-parallel freewheeling diode FRD chips 1-9 and 1-10 are welded on the upper DBC substrate 1; each of the chips on the upper DBC substrate 1 The front side of the chip is connected by a bonding wire group 10-1; the gates of the IGBT chip 1-6 at the upper left position and the IGBT chip 1-5 at the upper right position of the lower DBC substrate 2 are located in the lower middle position of the IGBT chip, the gates of the IGBT chip 1-8 at the lower left position and the IGBT chip 1-7 at the lower right position are located in the upper middle position of the IGBT chip, an anti-parallel freewheeling diode FRD chip 1-11 is located between the IGBT chip 1-5 and the IGBT chip 1-7, and another anti-parallel freewheeling diode FRD chip 1-12 is located between the IGBT chip 1-6 and the IGBT chip 1-8; the back sides of the IGBT chips 1-5, 1-6, 1-7, 1-8 and the anti-parallel freewheeling diode FRD chips 1-11 and 1-12 are welded on the lower DBC substrate 2. The front sides of the chips on the lower DBC substrate 2 are connected by a bonding wire group 10-2.

[0030] In the second group of IGBT chips, the gates of the IGBT chip 2-4 at the upper left position and the IGBT chip 2-3 at the upper right position of the upper DBC liner 3 are located in the lower middle position of the IGBT chip, the gates of the IGBT chip 2-2 at the lower left position and the IGBT chip 2-1 at the lower right position are located in the upper middle position of the IGBT chip, an anti-parallel freewheeling diode FRD chip 2-9 is located between the IGBT chip 2-3 and the IGBT chip 2-1, and another anti-parallel freewheeling diode FRD chip 2-10 is located between the IGBT chip 2-4 and the IGBT chip 2-2; the backs of the IGBT chips 2-1, 2-2, 2-3, 2-4 and the anti-parallel freewheeling diode FRD chips 2-9 and 2-10 are welded on the upper DBC liner 3; each of the chips on the upper DBC liner 3 The front side of the chip is connected by a bonding wire group 10-3; the gates of the IGBT chip 2-6 at the upper left position and the IGBT chip 2-5 at the upper right position of the lower DBC liner 4 are located in the lower middle position of the IGBT chip, the gates of the IGBT chip 2-8 at the lower left position and the IGBT chip 2-7 at the lower right position are located in the upper middle position of the IGBT chip, an anti-parallel freewheeling diode FRD chip 2-11 is located between the IGBT chip 2-5 and the IGBT chip 2-7, and another anti-parallel freewheeling diode FRD chip 2-12 is located between the IGBT chip 2-6 and the IGBT chip 2-8; the back sides of the IGBT chips 2-5, 2-6, 2-7, 2-8 and the anti-parallel freewheeling diode FRD chips 2-11 and 2-12 are welded on the lower DBC liner 4. The front sides of the chips on the lower DBC liner 4 are connected by a bonding wire group 10-4.

[0031] In the third group of IGBT chips, the gates of the IGBT chip 3-4 at the upper left position and the IGBT chip 3-3 at the upper right position of the upper DBC liner 5 are located in the lower middle position of the IGBT chip, the gates of the IGBT chip 3-2 at the lower left position and the IGBT chip 3-1 at the lower right position are located in the upper middle position of the IGBT chip, an anti-parallel freewheeling diode FRD chip 3-9 is located between the IGBT chip 3-3 and the IGBT chip 3-1, and another anti-parallel freewheeling diode FRD chip 3-10 is located between the IGBT chip 3-4 and the IGBT chip 3-2; the backs of the IGBT chips 3-1, 3-2, 3-3, 3-4 and the anti-parallel freewheeling diode FRD chips 3-9 and 3-10 are welded on the upper DBC liner 5; each of the chips on the upper DBC liner 5 is welded on the upper DBC liner 5; The front side of the chip is connected by a bonding wire group 10-5; the gates of the IGBT chip 3-6 at the upper left position and the IGBT chip 3-5 at the upper right position of the lower DBC substrate 6 are located in the lower middle position of the IGBT chip, the gates of the IGBT chip 3-8 at the lower left position and the IGBT chip 3-7 at the lower right position are located in the upper middle position of the IGBT chip, an anti-parallel freewheeling diode FRD chip 3-11 is located between the IGBT chip 3-5 and the IGBT chip 3-7, and another anti-parallel freewheeling diode FRD chip 3-12 is located between the IGBT chip 3-6 and the IGBT chip 3-8; the back sides of the IGBT chips 3-5, 3-6, 3-7, 3-8 and the anti-parallel freewheeling diode FRD chips 3-11 and 3-12 are welded on the lower DBC substrate 6. The front sides of the chips on the lower DBC substrate 6 are connected by a bonding wire group 10-6.

[0032] DBC liner boards 1, 2, 3, 4, 5, 6 are welded on AlSiC substrate 7; three IGBT chip groups are connected to the external circuit via positive terminal 8 and negative terminal 9. The four IGBT chips and two FRD chips of each DBC liner board are symmetrically distributed about the center of the DBC liner board, and the upper and lower DBC liner boards are symmetrically distributed about the module midline and the center.

[0033] Preferably, the sizes of the IGBT chip and the FRD chip can be adjusted.

[0034] Preferably, the IGBT chip and the FRD chip are chips based on silicon, silicon carbide and gallium nitride.

[0035] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A chip layout structure of a single switch IGBT module, characterized in that: It is composed of three groups of IGBT chipsets; each group of IGBT chipsets is composed of 8 IGBT chips and 4 anti-parallel freewheeling diode FRD chips; each group of IGBT chipsets is welded on the upper and lower DBC liner boards; the DBC liner boards are welded on the substrate; each group of IGBT chipsets is configured with a positive terminal and a negative terminal, and the three groups of IGBT chipsets are connected to the external circuit through the positive terminal and the negative terminal; the front of each chip on the DBC liner board is connected through a bonding wire group; On the upper and lower DBC substrates, the gates of the IGBT chips located at the upper left and upper right positions are located at the lower middle position of the IGBT chip; the gates of the IGBT chips located at the lower left and lower right positions are located at the upper middle position of the IGBT chip; the anti-parallel freewheeling diode FRD chip is located between the upper and lower IGBT chips on the same DBC substrate.

2. The chip layout structure of a single switch IGBT module according to claim 1, characterized in that: In each IGBT chip group, the back sides of every four IGBT chips and two anti-parallel freewheeling diode FRD chips are welded on a DBC liner.

3. The chip layout structure of a single switch IGBT module according to claim 2, characterized in that: The four IGBT chips and two freewheeling diode (FRD) chips on each DBC substrate are symmetrically distributed about the center of the DBC substrate.

4. The chip layout structure of a single switch IGBT module according to claim 1, characterized in that: In each group of IGBT chipsets, the upper DBC liner and the lower DBC liner are symmetrically distributed about the center line of the IGBT module substrate and the center of the substrate.

5. The chip layout structure of a single switch IGBT module according to claim 1, characterized in that: The sizes of the IGBT chip and the FRD chip are adjusted according to voltage and current requirements.

6. The chip layout structure of a single switch IGBT module according to claim 1, characterized in that: The IGBT chip and the FRD chip are chips based on silicon, silicon carbide and gallium nitride.

7. The chip layout structure of a single switch IGBT module according to claim 1, characterized in that: The substrate is an AlSiC substrate.

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