Image Sensor

Abstract

The present disclosure relates to an image sensor, which includes a plurality of pixels, each pixel including: a doped photosensitive region of a first conductivity type extending vertically in a semiconductor substrate; a charge collection region doped with the first conductivity type more heavily than the photosensitive region, the charge collection region extending vertically from an upper surface of the substrate in the substrate and arranged above the photosensitive region; and a vertical stack including a vertical transfer gate and a vertical electrical insulating wall, the stack passing through the substrate and contacting the charge collection region, the gate being arranged on the upper surface side of the substrate and penetrating deeper into the substrate than the charge collection region.

Description

Technical Field

[0001] The present disclosure relates generally to electronic circuits and, more particularly, to image sensors, and in particular, image sensor pixels. Background Art

[0002] The following image sensor is known: it includes a plurality of pixels, each pixel including a photosensitive region or area formed in a semiconductor substrate. When light is received by the photosensitive region, electron-hole pairs are generated in the photosensitive region, and photogenerated electrons or photogenerated holes are accumulated in the photosensitive region. During the reading phase, the charge transfer device is controlled to transfer the photogenerated charges that have accumulated in the photosensitive region to the doped charge collection semiconductor region.

[0003] In sensors comprising pixels intended to receive backside illumination of the substrate, for each pixel the charge collection region and the various transistors of the pixel are arranged on the front side of the substrate, ie the surface of the substrate with the interconnect structures thereon.

[0004] Known backside illuminated pixels suffer from various disadvantages, particularly with respect to their charge transfer devices. Summary of the invention

[0005] It would be desirable to overcome all or part of the disadvantages of known backside illuminated pixels, and in particular all or part of the disadvantages of known charge transfer devices of such pixels.

[0006] One embodiment overcomes all or part of the disadvantages of known backside illuminated pixels, and in particular all or part of the disadvantages of known charge transfer devices of such pixels.

[0007] One embodiment provides an image sensor comprising a plurality of pixels, each pixel comprising:

[0008] a doped photosensitive region of a first conductivity type extending vertically in the semiconductor substrate;

[0009] a charge collection region, more heavily doped with the first conductivity type than the photosensitive region, extending vertically in the substrate from an upper surface of the substrate and arranged above the photosensitive region; and

[0010] A vertical stack, including a vertical transfer gate and a vertical electrically insulating wall, is stacked through the substrate and in contact with the charge collection region, the gate being arranged on the upper surface side of the substrate and penetrating deeper into the substrate than the charge collection region.

[0011] According to one embodiment, each pixel further comprises a vertical electrically insulating structure passing through the substrate and laterally delimiting the photosensitive area and the pixel.

[0012] According to one embodiment, the vertical transfer gates of the stack are common to at least two adjacent pixels, the stack being in contact with the charge collection area of ​​each of the at least two pixels.

[0013] According to one embodiment, at least one pixel further comprises:

[0014] a vertical electrically insulating structure that passes through the substrate and divides the photosensitive area into two halves; and

[0015] Another charge collection region, which is more heavily doped with the first conductivity type than the photosensitive region, extends vertically in the substrate from the upper surface, each charge collection region being arranged over a different half of the photosensitive region.

[0016] According to one embodiment, the stack of at least one pixel is aligned with the structure and in contact with the further charge collecting region.

[0017] According to an embodiment, the vertical electrically insulating wall is part of the vertical electrically insulating structure.

[0018] According to one embodiment, the vertical electrically insulating structure is interrupted continuously along its entire height by a portion of the substrate, by the stack, and by another portion of the substrate.

[0019] According to one embodiment, the wall is made of:

[0020] at least one insulating material; or

[0021] At least one conductive material and at least one insulating layer electrically insulating the substrate from the at least one conductive material.

[0022] According to one embodiment, the vertical transfer gate is made of at least one conductive material and at least one insulating layer, which electrically insulates the substrate from the at least one conductive material of the vertical transfer gate and completely covers the lower surface of the at least one conductive material of the vertical transfer gate.

[0023] According to one embodiment, each pixel further comprises a doped well of the second conductivity type extending in the substrate from the upper surface towards the photosensitive area.

[0024] According to one embodiment, in each pixel the vertical transfer gate penetrates into the substrate at least down to the level of the lower surface of the well, preferably to a level approximately equal to the level of the lower surface of the well plus half the pitch between sensor pixels.

[0025] Another embodiment provides a method of manufacturing an image sensor pixel, the method comprising the steps of:

[0026] a) forming a charge collection region more heavily doped with the first conductivity type than the photosensitive region by doping on the upper surface side of the semiconductor substrate including the doped photosensitive region of the first conductivity type, above the photosensitive region;

[0027] b) etching a trench penetrating vertically into the substrate;

[0028] c) forming a vertical electrically insulating wall in the trench, the vertical electrically insulating wall completely filling the trench;

[0029] d) forming a cavity by removing a portion of the insulating wall deeper than the charge collection region by etching on the upper surface side; and

[0030] e) forming a vertical transfer gate in the cavity, steps a) and b) being performed such that a vertical stack comprising the vertical transfer gate and the vertical electrically insulating wall is in contact with the charge collecting region.

[0031] According to one embodiment, step c) comprises the following steps:

[0032] c1) forming at least one insulating layer on the wall and bottom of the trench; and

[0033] c2) Filling the trench with at least one conductive material.

[0034] According to one embodiment, step c) comprises filling the trench with at least one insulating material.

[0035] According to one embodiment, step e) comprises the following consecutive steps:

[0036] e1) forming at least one insulating layer on the wall and the bottom of the cavity; and

[0037] e2) Filling the cavity with at least one electrically conductive material.

[0038] The foregoing and other features and advantages will be discussed in detail in the following non-limiting description of specific embodiments in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1A and Figure 1B One embodiment of a pixel of an image sensor is illustrated in simplified top view and cross-sectional view, respectively;

[0040] Figure 2 yes Figure 1A A simplified cross-sectional view of

[0041] Figure 3A and Figure 3B An alternative embodiment of an image sensor is shown in simplified top view and cross-sectional view, respectively;

[0042] Figure 4yes Figure 3A A simplified cross-sectional view of

[0043] Figure 5A and Figure 5B Another alternative embodiment of an image sensor is illustrated in simplified top view A and cross-sectional view B, respectively;

[0044] Fig. 6A and Figure 6B A further alternative embodiment of an image sensor is illustrated in simplified top view and cross-sectional view, respectively;

[0045] Fig. 7A and 7B A further alternative embodiment of one of the image sensors is illustrated in simplified top view A and cross-sectional view B, respectively;

[0046] Fig. 8A , Figure 8B and Figure 8C Illustration of manufacturing Figure 1A , Figure 1B and Figure 2 Embodiments of the method steps of providing a charge transfer device for a pixel.

[0047] Fig.9A , Fig. 9B and Fig. 9C Illustration of manufacturing Figure 1A , Figure 1B and Figure 2 Another embodiment of the method of providing a charge transfer device for a pixel.

[0048] Fig. 10A , Fig. 10B and Fig. 10C Illustration of manufacturing Figure 1A , Figure 1B and Figure 2 Another embodiment of the method of providing a charge transfer device for a pixel.

[0049] Fig.11A , Fig. 11B and Fig. 11C Illustration of manufacturing Figure 3A , Figure 3B and Figure 4 Embodiments of the method steps of providing a charge transfer device for a pixel.

[0050] Fig. 12A , Fig. 12B and Fig. 12C Illustration of manufacturing Figure 3A , Figure 3B and Figure 4 Another embodiment of the method of providing a charge transfer device for a pixel.

[0051] Fig.13A , Fig. 13B and Fig. 13C Illustration of manufacturing Figure 3A , Figure 3B and Figure 4 Another embodiment of the method of providing a charge transfer device for a pixel. DETAILED DESCRIPTION

[0052] In different drawings, the same elements are designated by the same reference numerals. In particular, structural and / or functional elements common to different embodiments and variations may be designated by the same reference numerals and may have the same structure, size and material properties.

[0053] For clarity, only steps and elements useful for understanding the described embodiments are shown and described in detail. In particular, conventional steps for manufacturing pixels of image sensors (e.g., back-side illuminated) are not described in detail, and the described embodiments and variants are compatible with such conventional steps. In addition, the circuitry (transistors and connections) of pixels (e.g., back-side illuminated) is not described, and the described embodiments and variants are compatible with the circuitry of known pixels, such as back-side illuminated. In addition, the readout circuitry, or column decoders, control circuitry, or row decoders, and applications that may provide image sensors are not described in detail, and the described embodiments and variants are compatible with conventional image sensor readout circuitry and control circuitry, and conventional applications that may provide image sensors.

[0054] Throughout this disclosure, the term "connected" is used to specify a direct electrical connection between circuit elements without intervening elements other than conductors, while the term "coupled" is used to specify an electrical connection between circuit elements, which may be direct or via one or more other elements.

[0055] In the following description, when terms defining absolute positions (such as terms “front”, “back”, “top”, “bottom”, “left”, “right”, etc.), or terms defining relative positions (such as terms “above”, “below”, “higher than”, “lower than”, etc.) or terms defining directions (such as “horizontal”, “vertical”, etc.) are mentioned, unless otherwise specified, they refer to the orientation of the drawings.

[0056] The terms "about," "approximately," "substantially," and "on the order of" are used herein to designate a tolerance of ±10%, preferably ±5%, of the value in question.

[0057] Figure 1A and Figure 1B An embodiment of a pixel 1A of an image sensor 2A is illustrated in simplified top view and cross-sectional view, respectively, which in this example is back-illuminated. More particularly, Figure 1B It is along Figure 1A Cross-sectional view of cross section BB.

[0058] Figure 2 is along Figure 1A Simplified cross-sectional view of section CC.

[0059] exist Figure 1A , Figure 1B and Figure 2 In FIG. 1 , only a portion of the array of pixels 1 of the image sensor 2A is shown, only two pixels 1 are shown completely, and only pixels 1 next to the two pixels 1 are shown partially.

[0060] Sensor 2A is formed inside and / or on a semiconductor substrate 100, which is made of, for example, silicon, for example a doped silicon substrate of a first conductivity type (e.g., P-type). As an example, for a sensor intended to operate at a wavelength in the range from 350 nm to 950 nm, substrate 100 has a thickness in the range from about 2 μm to about 8 μm.

[0061] Optionally, the surface 101 of the substrate 100 (the back side in this example) intended to receive light Figure 1B and Figure 2 The lower surface of the substrate 100 is coated with one or more passivation layers 102, and / or filters 103 (e.g., color filters, each filter 103 being arranged opposite to a corresponding pixel 1), and / or microlenses 104, each microlens 104 being arranged opposite to a corresponding pixel 1. More specifically, in this example, the filter 103 rests on and is in contact with the layer(s) 102, and the microlens 104 rests on and is in contact with the filter 103.

[0062] Each pixel 1 comprises a photosensitive region 105. Each photosensitive region 105 corresponds to a doped semiconductor region of a first conductivity type (in this example, P-type). Each photosensitive region corresponds to a portion of the substrate 100. Each photosensitive region 105 extends vertically in the substrate 100, with a back side 101 of the substrate 100 and a front side 106 of the substrate 100 ( Figure 1B The regions 105 extend vertically from a layer and / or region and / or well formed on a first surface side of the substrate 100 to a layer and / or region and / or well formed on a second surface side of the substrate 100 opposite to the first surface.

[0063] Preferably, a doped layer 107 of the second conductivity type (here N-type) is arranged in the substrate 100, at the level of its back side 101. For each pixel 1, the layer 107 completely covers the surface of the region 105 arranged on the back side 101 of the substrate 100. In other words, each region 105 is completely covered by the layer 107 on the back side 101 of the substrate 100. Thus, the layer 107 extends across the thickness between the surface 101 and each photosensitive region 105 (at Figure 1B and Figure 2 extends vertically in the middle).

[0064] Each pixel 1, in particular the photosensitive area 105 of the pixel 1, is laterally delimited by a vertical electrically insulating structure 108. The structure 108 extends vertically ( Figure 2 ) penetrates into the substrate 100. Preferably, the structure 108 passes through the substrate 100 across the entire thickness of the substrate 100 and thus extends all the way to the back side 101 of the substrate 100. In this example, Figure 1A In FIG. 1 , structure 108 defines or defines a square pixel 1 , although other pixel shapes may also be provided.

[0065] In Figure 1 and Figure 2 In the illustrated embodiment, the vertical insulating structure is a deep trench insulation (DTI), i.e., a wall made of one or more insulating materials, formed by etching trenches into the substrate 100 and filling the trenches with (multiple) insulating materials. In other words, the structure 108 is an insulating wall made of, for example, silicon oxide.

[0066] exist Figure 1A , Figure 1B and Figure 2 In the illustrated embodiment, preferably, the doping layer 109 ( Figure 2 ) coats the side walls of the structure 108, at least at the level of the surface of these walls adjacent to the photosensitive region 105. The layer 109 makes it possible to avoid interface defects trapping holes photogenerated in the region 105.

[0067] Each pixel 1 further comprises a charge collection region 110, which is intended to receive photogenerated charges transferred from the photosensitive region 105 of the pixel 1. The region 110 of each pixel 1 is doped with a first conductivity type (in this example, P-type), being more heavily doped (P+) than the photosensitive region 105 of the pixel 1. The region 110 of each pixel 1 is arranged on the front surface side 106 of the substrate 100. The region 110 of each pixel 1 extends vertically (across the thickness) in the substrate 100 from the surface 106. The region 110 of each pixel 1 is arranged above the photosensitive region 105 of the pixel.

[0068] Each pixel 1 further comprises a doped well 111 of the second conductivity type (in this example, N-type), which is arranged on the front surface side 106 of the substrate 100. The well 111 of each pixel 1 extends vertically (across the thickness) in the substrate 100 from the surface 106, all the way to the photosensitive region 105 of the pixel. Components (not shown), such as transistors, of the pixel 1 are formed inside and / or above the well 111 of each pixel 1. Preferably, on the front surface side 106, the well 111 of each pixel 1 occupies the entire surface of the pixel 1 except the surface occupied by the region 110.

[0069] Each pixel 1 also includes a vertical stack comprising: a vertical transfer gate 115 corresponding to the charge transfer device of the pixel 1; and a vertical electrically insulating wall 116. The gate 115 of each pixel rests on the wall 116 of the pixel 1 ( Figure 1B ). The gate 115 of each pixel 1 is arranged on the front surface side 106. The gate 115 of each pixel penetrates into the substrate 100 deeper than the charge collection area 110 of the pixel. As an example, the gate 115 of each pixel 1 penetrates the substrate 110 at least down to the lower level of the well 111 of the pixel, i.e. the level of the lower surface of the well 111 in contact with the area 105 ( Figure 1B ). Preferably, the gate 115 of each pixel penetrates down into the substrate 100 to a level approximately equal to (e.g., equal to) the lower level of the well 111 of the pixel plus half the pitch between the sensor pixels 1. As an example, for a pixel 1 having a square shape with a side length of approximately 1 μm in the top view A, the pitch between the pixels 1 is equal to 1 μm.

[0070] In each pixel 1, the stack of gate 115 and wall 116 is adjacent to, and preferably in contact with, the charge collection region 110 of the pixel. Therefore, the stack of gate 115 and wall 116 is also in contact with the photosensitive region 105 of the pixel 1. In each pixel 1, the gate 115 is configured to allow or prevent the photogenerated charges (holes in this example) that have accumulated in the region 105 of the pixel 1 from being transferred to the charge collection region 110 of the pixel 1, depending on the control signal applied thereto.

[0071] In each pixel 1, the vertical transfer gate 115 includes a gate conductor 1151 made of one or more conductive materials (e.g., doped polysilicon). The gate conductor 1151 has the function of a gate electrode and is configured to receive a signal for controlling the gate 115. The gate 115 also includes one or more insulating layers 1152 (e.g., a silicon dioxide layer 1152) that completely cover the side surfaces of the conductor 1151 and the lower surface of the conductor 1151 (i.e., the surface of the conductor 1151 on the wall 116 side). The (multiple) layers 1152 have the function of a gate insulator. The (multiple) layers 1152 electrically insulate the conductor 1151 from the substrate 100 (e.g., the regions 105 and 110).

[0072] In each pixel 1, the wall 116 is made of one or more insulating materials. In other words, the electrically insulating wall 116 is an insulating wall made of silicon dioxide, for example.

[0073] exist Figure 1A , Figure 1B and Figure 2 In the embodiment shown, the wall 116 is made of one or more insulating materials, and the doped layer 117 ( Figure 1B ) preferably covers the side walls of the stack of gate 115 and walls 116 at least at the surface level of these walls adjacent to region 105. Layer 117 makes it possible to avoid interface defects from trapping photogenerated holes.

[0074] The stack of gate 115 and wall 116 contributes to laterally delimiting pixel 1 and electrically insulating it from adjacent pixels 1. Figure 1A , Figure 1B and Figure 2 In the embodiment shown, vertical electrically insulating wall 116 corresponds to a portion of vertical electrically insulating structure 108, and layer 117 corresponds to a portion of layer 109. In other words, gate 115 is arranged in vertical electrically insulating structure 108 or penetrates therein.

[0075] In operation, during the charge accumulation phase in the photosensitive region 105 of the pixel 1, a first potential level (in this example, a positive potential level, e.g., about 2.5 V) is applied to the pixel well 111. The region 105 of the pixel 1 is then almost completely surrounded by a region (here comprising layers 107, 109 and 117 and the well 111 of the pixel 1) to which the first type of photogenerated charges (electrons in this example) are attracted at this first potential level. The region 105 then corresponds to a potential well in which the second type of photogenerated charges (holes in this example) can accumulate. The potential well is substantially largest at the center of the region 105. Furthermore, a second potential level (in this example, a positive potential level, e.g., equal to the first potential level) is applied to the conductor 1151 of the gate 115. Therefore, the transfer of holes that have accumulated in the photosensitive region 105 to the region 110 of the pixel 1 is prevented, in particular because the portion of the region 105 surrounded by the gate 115 and the well 111 (i.e., the portion of the region 115 that is arranged below the region 110 and extends from the region 110 to the lower surface level of the well 111) corresponds to the potential maximum.

[0076] In the phase of transferring the photogenerated charges from region 105 to region 110, a third potential level is applied to gate conductor 115, the third potential level being, for example, a positive potential, a negative potential, or a zero potential (e.g., a ground potential) lower than the potential applied in the charge accumulation phase. Thus, the potential level in region 105 is reduced from the center of region 105 (which contains the largest potential well during the photogenerated charge accumulation phase) to region 110. All the second type of photogenerated charges that have been accumulated in region 105 are then transferred from region 105 to region 110.

[0077] Providing a vertical transfer gate 115 that penetrates into the substrate 110 only across a portion of the thickness of the substrate 110 (in particular, a gate 115 whose bottom or lower surface is at a level higher than the center of the region 105 (which contains the largest potential well during the accumulation phase of the second type of photogenerated charges (holes in this case)) has the advantage of preventing charge from settling at a local minimum potential along the gate 115 during the transfer phase.

[0078] This absence of a local potential minimum is not obtained in a pixel similar to pixel 1 (i.e. a pixel having the same dimensions, receiving the same bias and control potential levels, and having a semiconductor region with the same doping level as pixel 1), but rather in a pixel at a level in which the gate 115 would reach the center of region 105 (containing the largest potential well during the charge accumulation phase), or would even pass through the substrate 100.

[0079] An example of such a pixel is described in an article by Hamzeh Alaibakhsh and Mohammad Azim Karami, entitled “A 3-DDevice-Level Investigation of a Lag-Free PPD Pixel With a Capacitive DeepTrench Isolation as Shared Vertical Transfer Gate,” published in IEEE Transactions on Electron Devices (Vol. 65, No. 10) in October 2018. As shown in FIG. 8 (not shown) of the article, during the transfer phase illustrated by the “Transfer Phase” curve of the figure, there is a local potential minimum at the level of point B, which is located along the vertical transfer gate (CDTI in the article) at the same level as the potential well maximum in the photosensitive region (PPD in the article) when the pixel is in the photogenerated charge accumulation phase. Therefore, holes that have been photogenerated and accumulated in the photosensitive region remain trapped in this local potential minimum and are not transferred to the charge collection region (FD in the article).

[0080] As an example, the depth to which the gate 115 of each pixel 1 penetrates down into the substrate 100 is configured, for example, according to the operating wavelength of the pixel, the doping levels of the various regions and / or layers and / or wells of the pixel, the thickness and / or material of (multiple) layers 1152, and / or the potential level applied to the pixel, to prevent the formation of a potential well along the gate 115 during the charge transfer phase in the pixel. As an example, the depth can be determined by computer-assisted simulation, for example with the aid of computer-assisted simulation software distributed by Synopsys. More generally, it will be within the capabilities of a person skilled in the art to determine the depth of the gate 115 according to the functional indications given above.

[0081] Figure 3A and Figure 3B An alternative embodiment of an image sensor 2B including a pixel 1 is illustrated in simplified top view and cross-sectional view, respectively. More particularly, Figure 3B It is along Figure 3A Cross-sectional view of section BB. Figure 3A and Figure 3B Respectively Figure 1A and Figure 1B Corresponding.

[0082] Figure 4 It is along Figure 3A A simplified cross-sectional view of section CC, and Figure 2 The view corresponds to .

[0083] Only the Figure 1A , Figure 1B and Figure 2 The image sensor 2A in Figure 3A , Figure 3B and Figure 4 The differences between the alternative image sensor 2B.

[0084] Figure 3A , Figure 3B and Figure 4 An alternative embodiment of FIG. 1 and Figure 2 The embodiment of is different in that the wall 116 is replaced by a wall 116 ′ and the vertical electrically insulating structure 108 is replaced by a vertical electrically insulating structure 108 ′. Furthermore, in this variant, the layers 117 and 109 are preferably omitted.

[0085] In this alternative embodiment, the vertical insulating structure 108' is a capacitive deep trench insulation (CDTI), i.e., a wall made of one or more conductive materials 1081 (e.g., doped polysilicon) covered with one or more insulating layers 1082 (e.g., made of silicon dioxide) that electrically insulate the conductive wall 1081 from the substrate 100. In other words, the structure 108' is an insulated conductive wall 1081 (layer 1082).

[0086] In operation, a bias potential is applied to the conductive wall 1081 of the structure 108' to accumulate the first type of photogenerated charges along the sidewalls of the structure 108'. In this example where the region 105 is of P-type, the first type of photogenerated charges are electrons, and the bias potential applied to the conductive wall 1082 of the structure 108' is preferably positive, for example, about 2.5V. The accumulation of the first type of charges along the structure 108' has a similar effect to the combination of Figure 1A , Figure 1B and Figure 2 The layer 109 described above has the same function.

[0087] In this alternative embodiment, the vertical electrically insulating wall 116′ on which the gate 115 rests is a capacitive deep trench insulation (CDTI), i.e., a wall made of one or more conductive materials 1161 (e.g., doped polysilicon) covered with one or more insulating layers 1162 (e.g., of silicon dioxide) that electrically insulate the conductive wall 1161 from the substrate 100. In other words, the wall 116′ is an insulated conductive wall 1161 (layer 1162).

[0088] In operation, a bias potential is applied to the conductive wall 1161 to accumulate the first type of photogenerated charges along the sidewall 116'. In this example where the region 105 is of P-type, the first type of photogenerated charges are electrons, and the bias potential applied to the conductive wall 1161 is preferably positive, for example, about 2.5V. The accumulation of the first type of charges along the wall 116 has a similar effect to the combination of Figure 1A , Figure 1B and Figure 2 The layer 117 has the same function as described.

[0089] The operation of the gate 115 is the same as that described above. Figure 3A , Figure 3B and Figure 4 An alternative embodiment benefits from combining Figure 1A , Figure 1B and Figure 2 The advantages are the same as those of the described embodiments.

[0090] Combined with Figure 1A , Figure 1B and Figure 2 Similar to what has been described, the stack of gate 115 and wall 116' contributes to laterally delimiting pixel 1 and electrically insulating it from adjacent pixels 1. In particular, Figure 3A , Figure 3B and Figure 4 In the alternative embodiment shown, as in Figure 1A , Figure 1B and Figure 2 As in the illustrated embodiment, the vertical electrically insulating wall 116′ corresponds to a portion of the vertical electrically insulating structure 108′. The vertical conductive wall 1161 then corresponds to a portion of the vertical conductive wall 1081, and the (multiple) insulating layer 1162 corresponds to a portion of the (multiple) insulating layer 1082. In other words, the gate 115 is arranged in or penetrates into the vertical electrically insulating structure 108′.

[0091] Figure 5A and Figure 5B Another alternative embodiment of an image sensor 2C including a pixel 1 is illustrated in simplified top view and cross-sectional view, respectively. More particularly, Figure 5B is along Figure 5A Cross-sectional view of section BB. Figure 5A and Figure 5B and Figure 1A and Figure 1B Correspondingly, Figure 5B and Figure 1B In addition, no Figure 5A Simplified cross-sectional view of section CC, the latter with Figure 2 The simplified cross-sectional view is the same.

[0092] Only image sensor 2A and Figure 5A and Figure 5B The differences between the alternative image sensors 2C.

[0093] Image sensor 2C differs from image sensor 2A in that, on the one hand, the stack of gate 115 and vertical electrically insulating wall 116 is not continuous with, or in other words, does not touch, vertical electrically insulating structure 108. In other words, structure 108 is interrupted continuously along its entire height by a portion 1000 of substrate 100, the stack of gate 115 and wall 116, and a portion 1001 of substrate 100. Well 111 may be present in portions 1000 and 1001 of substrate 100.

[0094] In another alternative embodiment not shown, Figure 5A The vertical electrical insulating structure 108 can be combined with Figure 3A , Figure 3B and Figure 4 The vertical electrically insulating structure 108 ′ described above is replaced by the vertical electrically insulating structure 108 ′, and / or Figure 5B The insulating wall 116 may be formed by combining Figure 3A , Figure 3B and Figure 4 Where wall 116' is used in place of wall 116, it is preferred that a portion of wall 116' abuts gate 115 up to surface 106 of substrate 100 to bias conductive wall 116'.

[0095] Fig. 6A and Figure 6B A further alternative embodiment of an image sensor 2D comprising a pixel 1 is illustrated in simplified top view and cross-sectional view, respectively. More particularly, Figure 6B It is along Fig. 6A Cross-sectional view of section BB. Fig. 6A and Figure 6B Respectively Figure 1A and Figure 1B In addition, no Fig. 6A Simplified cross-sectional view of section CC, the latter with Figure 2 The simplified cross-sectional view is the same.

[0096] Only the Figure 1A , Figure 1B and Figure 2 The image sensor 2A and Fig. 6A and Figure 6B The differences between alternative image sensors 2D.

[0097] In this alternative embodiment, the vertical transfer gate 115 of a pixel 1, and therefore the stack of gate 115 and vertical wall 116 (on top of which the gate 115 is) is shared with at least one other adjacent pixel 1. Fig. 6A and Figure 6BIn the example of , the gate 115 is common to two adjacent pixels 1, and the stack of layer 115 and vertical wall 116 (on top of which the gate 115 is) is common to the two pixels 1. Therefore, the stack of gate 115 and wall 116 is adjacent to the charge collection region 110 and the photosensitive region 105 of each of the pixels 1 sharing the same gate 115, and the stack is preferably in contact with the region 110 and the region 105.

[0098] Therefore, when the gate 115 is controlled to respectively block and allow charge transfer between the region 105 and the region 110 of the pixel 1, charge transfer between the region 105 and the region 110 of each other pixel 1 sharing the gate 115 is respectively blocked and allowed.

[0099] Although not shown in this article, in combination with Figure 3A , Figure 3B and Figure 4 And combined Figure 5A and Figure 5B In the described alternative embodiment, it is possible to provide for the sharing of the same gate 115 and thus the same stack of gate 115 and wall 116 by at least two pixels by replacing wall 116 with wall 116 ′.

[0100] Fig. 7A and Figure 7B A further alternative embodiment of an image sensor 2E comprising a pixel 1' is illustrated in simplified top view and cross-sectional view, respectively. More particularly, Figure 7B is along Fig. 7A Cross-sectional view of section BB.

[0101] Only the Figure 1A , Figure 1B and Figure 2 The image sensor 2A and Fig. 7A and Figure 7B The differences between the alternative image sensors 2E.

[0102] In this variant, at least one pixel 1 of the sensor 2E (here a single pixel designated hereinafter by reference numeral 1′) comprises a vertical electrically insulating structure 120 dividing the pixel 1 into two parts. In particular, the structure 120 divides the photosensitive area 105 of the pixel 1 into two halves 105A and 105B. The structure 120 corresponds to a portion of the structure 108, although the portion 120 of the insulating structure 108 does not laterally delimit the pixel 1′.

[0103] In this variant, the pixel 1′ comprises two charge collection regions 110A and 110B. The regions 110A and 110B are arranged over the halves 105A and 105B of the photosensitive area of ​​the pixel 1′, respectively. The regions 105A and 105B are identical to the previously described region 110. What was previously described for the region 110 applies to each of the regions 110A and 110B.

[0104] according to Fig. 7A and Figure 7B In the alternative embodiment shown in , in pixel 1′, the stack of gate 115 and wall 116 is shared by the two halves 105A and 105B of the photosensitive area of ​​pixel 1′. In other words, the gate 115 of pixel 1′ is common to the two halves 105A and 105B of the photosensitive area of ​​pixel 1′, and therefore is common to the two charge collection regions 110A and 110B of pixel 1′. Therefore, the stack of gate 115 and wall 116 is in contact with each of the halves 105A and 105B of the photosensitive area of ​​pixel 1′, and each of the charge collection regions 110A and 110B of pixel 1′.

[0105] exist Fig. 7A and Figure 7B In the alternative embodiment shown in , the stack of gate 115 and wall 116 is aligned with the vertical insulating structure 120. More specifically, gate 115 is arranged in the vertical electrically insulating structure 120, separating pixel 1 'into two parts. Thus, wall 116 and layer 117 correspond to a portion of structure 120 (and therefore structure 108) and a portion of layer 109, respectively.

[0106] According to another variant, not shown, the pixel 1′ can be provided as two stacks including a gate 115 and a wall 116, a first stack of the two stacks being in contact with half 105A of the photosensitive area of ​​the pixel 1′ and with the area 110A, and the other stack of the two stacks being in contact with half 105B of the photosensitive area of ​​the pixel 1′ and with the area 110B. For example, the first stack of the two stacks is aligned with a first section of the vertical insulating structure 108 (e.g., a section defining a first lateral surface of the pixel 1′), the wall 116 of the first stack corresponding to a portion of the first section of the structure 108, and the second stack of the two stacks is aligned with a second section of the vertical electrically insulating structure 108 (e.g., a section defining a second lateral surface of the pixel 1′ opposite to the first lateral surface), the wall 116 of the second stack corresponding, for example, to a portion of the second section of the structure 108. In this variant, in combination with Fig. 6A and Figure 6B Similar to what has been described, each of the two stacks of the gate 115 and the wall 116 of the pixel 1 ′ may be provided to be shared with an adjacent pixel 1 .

[0107] Furthermore, although not illustrated herein, an alternative embodiment in which the pixel 1' is split into two parts and includes two charge collection regions 110A and 110B may be combined with the embodiment of the present invention by replacing the wall 116 with the wall 116'. Figure 3A , Figure 3B and Figure 4 And combined Figure 5A and Figure 5B Combinations of the described alternative embodiments.

[0108] The pixel 1′ allows an operation in which the amount of light received by each half 105A and 105B of the photosensitive area of ​​the pixel 1′ can be determined from readings from each of the areas 110A and 110B, i.e., by determining the number of photosensitive charges that have been transferred from the corresponding area 110A or 110B to each (corresponding) area of ​​the areas 105A and 105B. Such an operation can be implemented, for example, during a phase of automatically setting the focal plane of a lens associated with an image sensor (e.g., in a digital reflex camera, or in a time-of-flight (TOF) image sensor).

[0109] Pixel 1′ also allows operation similar to that of pixel 1, where the amount of light received by all halves 105A and 105B of the photosensitive area of ​​pixel 1′ can be determined based on areas 105A and 105B by summing the number of photogenerated charges in the two halves 105A and 105B of the photosensitive area of ​​pixel 1′.

[0110] Now combine FIG. 8A to FIG. 10C Describe manufacturing combination Figure 1A , Figure 1B and Figure 2 8 . The figures show neither the region 110 of the pixel 1, nor the well 111 nor the region 105, but only the substrate 100 (here doped of P type), and the region 110 and the well 111 can be formed before or after the steps shown in FIG8 . In particular, the region 110 is formed, for example, by a doping step performed on the side of the front surface 106 of the semiconductor substrate above the photosensitive region 105.

[0111] Fig. 8A , Figure 8B and Figure 8C Simplified view of the manufacturing Figure 1A , Figure 1B and Figure 2 Embodiments of the steps of a method of forming a vertical charge transfer gate 115 of a pixel 1. Figure 8B and Figure 8C is along Fig. 8A The corresponding cross-sectional views of sections BB and CC, Fig. 8A So Figure 8B and Figure 8C A top view taken at section AA.

[0112] exist Fig. 8A , Figure 8B and Figure 8C In the step of , a trench 800 has been etched in the substrate 100 at the location of the future stack of gate 115 and wall 116, and at the location of the future vertical electrically insulating structure 108. In this embodiment, in which the future gate 115 will be arranged in the structure 108 and in which the wall 116 will correspond to a portion of the structure 108, the same continuous trench 800 will be used to form the gate 115, the wall 116 and the structure 108 ( Fig. 8A ).

[0113] In this step, the substrate 100 is Figures 1A to 7B The substrate thickness in Figure 8B and Figure 8C ). The trench 800 is etched down to a depth that is at least equal to the desired depth of the substrate 100 in the fabricated sensor.

[0114] In which the pixel area 110 has been Fig. 8A , Figure 8B and Figure 8C In the case where the trench 800 is formed at a step (not shown), the trench 800 is etched so that one of its side walls is adjacent to the lateral surface of the region 110 .

[0115] Although not illustrated herein, layers 117 and 109 may be formed simultaneously by implanting dopant atoms into the walls and bottom of trench 800 .

[0116] Fig.9A , Fig. 9B and Fig. 9C With Fig. 8A , Figure 8B and Figure 8C The corresponding simplified view of the corresponding view illustrates the manufacturing Figure 1A , Figure 1B and Figure 2 Another step of the method of forming a gate 115 of a pixel 1 is an embodiment of the present invention. Fig.9A , Fig. 9B and Fig. 9C The steps are Fig. 8A , Figure 8B and Figure 8C is implemented after the steps.

[0117] exist Fig.9A , Fig. 9B and Fig. 9C In step 114 , the trench 800 has been filled with insulating material(s) forming the structure 108 and the walls 116 .

[0118] For example, one or more insulating layers are deposited and / or formed in the trench 800 to completely fill the trench with one or more insulating materials, after which, for example during a planarization step down to the front side 106 of the substrate 100 by CMP (chemical mechanical planarization), excess insulating material(s) arranged above the level of the front side 106 is removed ( Fig. 9B and Fig. 9C ).

[0119] As a specific example not shown, the trench 800 is filled by performing thermal oxidation on the wall and the bottom of the trench 800 and then forming a silicon dioxide layer by depositing a silicon dioxide layer on the thermal oxide layer.

[0120] exist Fig.9A , Fig. 9B and Fig. 9C In the step of , in the insulating material(s) filling the trench 800, a cavity 900 has also been etched at the location of the future gate 115. The cavity 900 is etched down to a depth (preferably equal) to which the gate 115 will penetrate into the substrate 100. Fig. 9B Then, the insulating material(s) disposed below the cavity 900 form the wall 116 ( Fig. 9B ).

[0121] Still in Fig.9A , Fig. 9B and Fig. 9C In the step of, for example, by deposition and / or thermal oxidation, one or more insulating layers 1152 are formed on the wall and bottom of the cavity 900 ( Fig.9A and Fig. 9B In the example shown, layer 1152 (e.g. made of silicon dioxide) is formed by thermal oxidation of the entire exposed surface of substrate 100 ( Fig. 9B and Fig. 9C ).

[0122] Fig. 10A , Fig. 10B and Fig. 10C In a simplified view (with Fig. 8A , Figure 8B and Figure 8C as well as Fig.9A , Fig. 9B and Fig. 9C ) illustrates the manufacturing Figure 1A , Figure 1B and Figure 2 The gate 115 of the pixel 1 is formed by a plurality of electrodes. Fig. 10A , Fig. 10B and Fig. 10C The steps are Fig.9A , Fig. 9B and Fig. 9C After the steps.

[0123] exist Fig. 10A , Fig. 10B and Fig. 10C In the step of filling the cavity 900 with (multiple) conductive materials forming the gate conductor 1151, the gate conductor 1151 has been formed in the cavity 900 ( Fig. 10A and Fig. 10B ).

[0124] For example, one or more layers made of a conductive material of the gate conductor 1151 are deposited and / or formed in the cavity 900 to completely fill it, and then, for example during a CMP step down to the front side 106 of the substrate 100, the excess conductive material(s) arranged above the level of the surface 106 and possibly the portion of the gate insulator 1152 resting on the surface 106 of the substrate 100 are removed. Then a stack of gates 115 and walls 116 is obtained ( Fig. 10B ).

[0125] As an example, a single polysilicon layer is deposited to fill cavity 900 .

[0126] In a next step (not shown), the substrate 100 is Figure 1A , Figure 1B and Figure 2 ) is thinned to a desired thickness. In particular, the thinning step is performed at least to reach the bottom or base of the structure 108 and the wall 116.

[0127] The steps of forming the layer 107, the layer(s) 102, the filter 103 and / or the microlens 104 on the back side 101 of the thinned substrate 100, and the steps of forming the well 111, the region 110, the transistors in the well 111, the interconnect structures, etc. on the front surface side 106 of the substrate 100 are within the capabilities of a person skilled in the art and are not described in detail, especially with regard to the steps that may be related to FIG. 8A to FIG. 10C The order in which the steps are implemented.

[0128] exist FIG. 8A to FIG. 10C In another embodiment (not shown) of the step of Figure 5A and Figure 5B The stack of gate 115 and wall 116 shown separated from structure 108 provides Fig. 8A , Figure 8B and Figure 8CIn the step of , the trench 800 includes portions separated from each other. Then, a stack of gate 115 and wall 116 is formed in a first portion of these portions of the trench 800, and structure 108 is formed in at least another portion of these portions of the trench 800. In this other embodiment, cavity 900 is etched only in the first portion of the trench 800.

[0129] Now combine FIG. 11A to FIG. 13C Description of manufacturing Figure 3A , Figure 3B and Figure 4 1. These figures show neither the region 110 of the pixel 1, nor the well 111, nor the region 105, but only the substrate 100 (here P-doped), and can be Fig.11A , Fig. 11B and Fig. 11C The region 110 and the well 111 are formed before or after the steps shown. In particular, the region 110 is formed, for example, by a doping step performed on the side of the front surface 106 of the semiconductor substrate, above the photosensitive region 105.

[0130] Fig.11A , Fig. 11B and Fig. 11C Simplified view of the manufacturing Figure 3A , Figure 3B and Figure 4 Embodiments of the steps of a method of forming a vertical charge transfer gate 115 of a pixel 1. Fig. 11B and Fig. 11C is along Fig.11A The corresponding cross-sectional views of sections BB and CC, Fig.11A is along Fig. 11B and Fig. 11C A top view taken at section AA. Fig.11A , Fig. 11B and Fig. 11C and Fig. 8A , Figure 8B and Figure 8C In addition, Fig.11A , Fig. 11B and Fig. 11C The steps shown in Fig. 8A , Figure 8B and Figure 8C Follow the steps shown.

[0131] exist Fig.11A , Fig. 11B and Fig. 11C In the step of, for example, by deposition and / or thermal oxidation, one or more insulating layers 1082 and one or more layers 1162 have been formed on the walls and bottom of the trench 800, the latter corresponding to parts of the (multiple) layers 1082 ( Fig. 11Band Fig. 11C As an example, the silicon dioxide layer 1082 is formed by thermal oxidation of the entire exposed surface of the substrate 100.

[0132] exist Fig.11A , Fig. 11B and Fig. 11C In the step of , the trench 800 has also been filled with (multiple) conductive materials 1081, thereby being filled with conductive material 1161 ( Fig. 11B and Fig. 11C ). For example, one or more layers made of conductive material(s) 1081, 1161 are deposited and / or formed in the trench 800 to completely fill the trench 800, after which the excess conductive material arranged above the level of the surface 106, and possibly parts of the insulating layer(s) 1082, 1162 resting on the surface 106 of the substrate 100, are removed, for example during a CMP step down to the front side 106 of the substrate 100. The structure 108′ ( Fig. 11C ) and wall 116′( Fig. 11B ), in this step in which the gate 115 is not formed, the structure 108′ ( Fig. 11C ) and wall 116′( Fig. 11B ) extends along the entire height of the groove 800.

[0133] Fig. 12A , Fig. 12B and Fig. 12C Simplified view of the manufacturing Figure 3A , Figure 3B and Figure 4 Another embodiment of the method of providing a charge transfer device for a pixel. Fig. 12A , Fig. 12B and Fig. 12C The steps are Fig.11A , Fig. 11B and Fig. 11C After the steps, and Fig. 12A , Fig. 12B and Fig. 12C With the corresponding Fig.11A , Fig. 11B and Fig. 11C Corresponding.

[0134] exist Fig. 12A , Fig. 12B and Fig. 12C In the step of Fig. 12B), i.e., etched into the (multiple) layers 1162 and the (multiple) conductive material 1161. Cavity 1200 is etched down to a depth that is substantially equal (preferably equal) to the depth that gate 115 will penetrate into substrate 100. The portions of the (multiple) layers 1162 and the portions of the (multiple) materials 1161 that remain in cavity 1200 form walls 116′ that will support the future gate 115.

[0135] Still in Fig. 12A , Fig. 12B and Fig. 12C In the step of forming one or more insulating layers 1152 ( Fig. 12B In the example shown, a layer 1152 (eg, made of silicon dioxide) is formed by thermally oxidizing the entire exposed surface of the substrate 100 and the material(s) 1081. Fig. 12B and 12C ).

[0136] Fig.13A , Fig. 13B and Fig. 13C Simplified view of the manufacturing Figure 3A , Figure 3B and Figure 4 Another embodiment of the method of providing a charge transfer device for a pixel. Fig.13A , Fig. 13B and Fig. 13C The steps are Fig. 12A , Fig. 12B and Fig. 12C After the steps of Fig.13A , Fig. 13B and Fig. 13C With the corresponding Fig. 12A , Fig. 12B and Fig. 12C Corresponding.

[0137] exist Fig.13A , Fig. 13B and Fig. 13C In the step of filling the cavity 1200 with (multiple) conductive materials for forming the gate conductor 1151, the gate conductor 1151 ( Fig.13A and Fig. 13B ).

[0138] For example, one or more layers made of conductive material(s) of the gate conductor 1151 are deposited and / or formed in the cavity 1200 to completely fill it, after which the excess conductive material(s) arranged above the level of the surface 106, and possibly the portion of the gate insulator 1152 resting on the surface 106 of the substrate 100, are removed, for example during a CMP step down to the front side 106 of the substrate 100. A stack of gates 115 and walls 116′ is then obtained.

[0139] As an example, a single polysilicon layer is deposited to fill cavity 1200 .

[0140] In a next step (not shown), the substrate 100 is Figure 3A , Figure 3B and Figure 4 ) is thinned to a desired thickness. In particular, the thinning step is performed at least to reach the bottom or base of the structure 108' and the wall 116'.

[0141] The steps of forming the layer 107, the layer(s) 102, the filter 103 and / or the microlens 104 on the back side 101 of the thinned substrate 100, and the steps of forming the well 111, the region 110, the transistors in the well 111, the interconnect structures, etc. on the front side 106 of the substrate 100 are within the capabilities of a person skilled in the art and are not described in detail, especially with regard to the steps related to FIG. 8A to FIG. 8C and FIG. 11A to FIG. 13C The order in which the steps are implemented.

[0142] exist FIG. 8A to FIG. 8C and FIG. 11A to FIG. 13C In another embodiment of the step of (not shown), it is possible to form a stack of gate 115 and wall 116' separated from structure 108', providing Fig. 8A , Figure 8B and Figure 8C In the step of , the trench 800 includes portions separated from each other. Then, a stack of gate 115 and wall 116' is formed in a first portion of these portions of the trench 800, and structure 108' is formed in at least another portion of these portions of the trench 800. In this other embodiment, cavity 1200 is etched only in the first portion of the trench 800.

[0143] Although not illustrated or described in detail, the above-described manufacturing method is adapted to combine FIG. 6A to FIG. 6B and FIG. 7A to FIG. 7B The context of the described alternative embodiments will be within the capabilities of those skilled in the art.

[0144] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variations may be combined, and that other variations will occur to those skilled in the art. In particular, despite the situation where photogenerated holes have accumulated in region 105 (if present, in 105A and 105B) and have been transferred to region 110 (if present, 110A and 110B), adapting the described embodiments, implementation modes and variations to the situation where photogenerated electrons accumulate and are transferred will be within the capabilities of those skilled in the art. For example, such adaptation includes reversing all previously indicated conductivity types and adapting the potential levels applied to conductive materials 1161, 1151, 1081′ and well 111, for example, by providing a biasing of well 111 to zero potential, biasing structure 108′ to a negative potential, such as −1.5 V, and causing gate 115 to receive a positive potential during the transfer phase and a negative or zero potential (e.g., −1.5 V) during the phase accumulation phase.

[0145] Furthermore, although backside illuminated pixels 1 and 1' have been described herein, a person skilled in the art may provide a stack of vertical transfer gates and vertical electrically insulating walls to transfer charge from the photosensitive regions to the charge collection regions in frontside illuminated pixels.

[0146] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variants is within the capabilities of a person skilled in the art.

[0147] Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and scope of the disclosure.Accordingly, the foregoing description is by way of example only and not limiting.

[0148] The various embodiments described above can be combined to provide other embodiments. In view of the above detailed description, these and other changes can be made to the embodiments. Generally, in the following claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted as including all possible embodiments and the full range of equivalents enjoyed by these claims. Therefore, the claims are not limited by this disclosure.

Claims

1. An image sensor, the image sensor comprising a plurality of pixels, each pixel comprising: A doped photosensitive region of a first conductivity type extending vertically in the semiconductor substrate; a first charge collection region, more heavily doped with the first conductivity type than the doped photosensitive region, the first charge collection region extending vertically in the substrate from the upper surface of the substrate and arranged above the doped photosensitive region; as well as a vertical stack, comprising a vertical transfer gate and a vertical electrically insulating wall, the vertical stack passing through the substrate and in contact with the first charge collection region, the vertical transfer gate being arranged at the upper surface of the substrate and penetrating deeper into the substrate than the first charge collection region, wherein the vertical transfer gate comprises a gate electrode and a gate dielectric, the gate electrode and the gate dielectric being arranged on the vertical electrically insulating wall; as well as A vertical electrically insulating structure passes through the substrate and laterally delimits the doped photosensitive region and the pixel, wherein the vertical electrically insulating wall is part of the vertical electrically insulating structure. 2 . The sensor of claim 1 , wherein the vertical transfer gate of each vertical stack is common to two adjacent pixels, the vertical stack being in contact with the first charge collection regions of the two adjacent pixels.

3. The sensor of claim 1 , wherein at least one pixel of the plurality of pixels further comprises: A second charge collection region, which is more heavily doped with the first conductive type than the doped photosensitive region, extends vertically from the upper surface in the substrate, and the vertical electrical insulating structure divides the doped photosensitive region into a first half and a second half, and the first charge collection region and the second charge collection region of the pixel are respectively arranged above the first half and the second half of the doped photosensitive region. 4 . The sensor of claim 3 , wherein the vertical stack of the at least one pixel is aligned with the vertical electrically insulating structure and is in contact with the second charge collection region. 5 . The sensor of claim 1 , wherein the vertical electrically insulating structure is interrupted continuously along its entire height by a portion of the substrate, the vertical stack, and another portion of the substrate.

6. The sensor of claim 1 , wherein the vertical electrically insulating wall is formed by: at least one insulating material; or At least one conductive material and at least one insulating layer, the at least one insulating layer electrically insulating the substrate from the at least one conductive material. 7 . The sensor of claim 1 , wherein in each pixel, the gate dielectric electrically insulates the substrate from the gate electrode of the vertical transfer gate and completely covers a lower surface of the gate electrode.

8. The sensor of claim 1, wherein each pixel further comprises a doped well of the second conductivity type extending in the substrate from the upper surface to the doped photosensitive region.

9. The sensor of claim 8, wherein in each pixel the vertical transfer gate penetrates into the substrate, at least down to the level of the lower surface of the doped well.

10. An imaging pixel comprising: a doped photosensitive region of a first conductivity type in a semiconductor substrate; a first charge collection region, more heavily doped with the first conductivity type than the doped photosensitive region, the first charge collection region extending in the substrate from the upper surface of the substrate and arranged above the doped photosensitive region; as well as a vertical stack, comprising a vertical transfer gate and a vertical electrically insulating wall, the vertical stack passing through the substrate and in contact with the first charge collection region, the vertical transfer gate being arranged at the upper surface of the substrate and penetrating deeper into the substrate than the first charge collection region, wherein the vertical transfer gate comprises a gate electrode and a gate dielectric, the gate electrode and the gate dielectric being arranged on the vertical electrically insulating wall; a vertical electrical insulating structure passing through the substrate and dividing the doped photosensitive region into a first half and a second half; as well as A second charge collection region, which is more heavily doped with the first conductivity type than the doped photosensitive region, extends vertically from the upper surface in the substrate, and the first charge collection region and the second charge collection region of the pixel are respectively arranged above the first half and the second half of the doped photosensitive region.

11. The imaging pixel of claim 10, wherein the vertical stack is aligned with the vertical electrically insulating structure and is in contact with the second charge collection region.

12. The imaging pixel of claim 10 , further comprising a vertical electrically insulating structure extending through the substrate and laterally defining the doped photosensitive region and the pixel, wherein the vertical electrically insulating structure is continuously interrupted along its entire height by a portion of the substrate, the vertical stack, and another portion of the substrate.

13. An imaging pixel comprising: a doped photosensitive region of a first conductivity type in a semiconductor substrate; a first charge collection region, more heavily doped with the first conductivity type than the doped photosensitive region, the first charge collection region extending in the substrate from the upper surface of the substrate and arranged above the doped photosensitive region; as well as a vertical stack, comprising a vertical transfer gate and a vertical electrically insulating wall, the vertical stack passing through the substrate and in contact with the first charge collection region, the vertical transfer gate being arranged at the upper surface of the substrate and penetrating deeper into the substrate than the first charge collection region, wherein the vertical transfer gate comprises a gate electrode and a gate dielectric, the gate electrode and the gate dielectric being arranged on the vertical electrically insulating wall; as well as A vertical electrically insulating structure passes through the substrate and laterally delimits the doped photosensitive regions and the imaging pixels, wherein the vertical electrically insulating structure is interrupted continuously along its entire height by a portion of the substrate, the vertical stack, and another portion of the substrate.

14. The imaging pixel of claim 13, wherein the portion of the substrate, the vertical stack, and the other portion of the substrate are aligned with one another.

Images