Stacked package

Abstract

A stacked package is provided. The stacked package may include a first substrate package, a second substrate package, an interposer, and at least one semiconductor chip. The first substrate package may include a plurality of first pads that are isolated from each other by a first pitch and do not directly contact each other. The second substrate package may be below the first substrate package. The second substrate package may include a plurality of second pads that are isolated from each other by a second pitch and do not directly contact each other. The second pitch may be different from the first pitch. The interposer may be above the first substrate package. The interposer may include a plurality of third pads that are isolated from each other by a third pitch and do not directly contact each other. The semiconductor chip may be disposed above the interposer.

Description

[0001] This application claims priority to both Korean Patent Application No. 10-2019-0088474, filed on Jul. 22, 2019, and Korean Patent Application No. 10-2020-0026921, filed on Mar. 4, 2020, with the Korean Intellectual Property Office (KIPO), the content of each of the foregoing Korean patent applications being incorporated herein by reference in its entirety. Technical Field

[0002] Example embodiments relate to a semiconductor package and a method of manufacturing the same. More specifically, example embodiments relate to a stacked package including an interposer and a method of manufacturing the stacked package. Background Art

[0003] Generally, when substrate packages including pads (also referred to as “lands”) that may have different pitches can be stacked, an interposer may be used. The interposer may be interposed between the substrate packages to electrically connect the pads of the substrate packages to each other.

[0004] According to the prior art, the interposer may be applied to any one of substrate packages, for example, any one of an ABF (Ajinomoto build-up film) package and a high density interconnect (HDI) package. When the interposer is applied to the ABF package, high costs are incurred to manufacture a stacked package having a large area. When the interposer is applied to the HDI package, the interposer may include horizontal signal lines configured to connect the pads of the interposer to each other for a fine pitch corresponding to the interposer. The horizontal signal lines increase resistance, thereby degrading the performance of the stacked package. Summary of the Invention

[0005] Some example embodiments provide a stacked package using a low-cost and having improved performance.

[0006] Some example embodiments also provide a method of manufacturing the above-described stacked package.

[0007] According to some example embodiments, a stacked package may include a first substrate package, a second substrate package, an interposer, and at least one semiconductor chip. The first substrate package may include a plurality of first pads that are isolated from each other by a first pitch and do not directly contact each other. The second substrate package may be below the first substrate package. The second substrate package may include a plurality of second pads that are isolated from each other by a second pitch and do not directly contact each other. The second pitch may be different from the first pitch. The interposer may be above the first substrate package. The interposer may include a plurality of third pads that are isolated from each other by a third pitch and do not directly contact each other. The semiconductor chip may be disposed above the interposer.

[0008] According to some example embodiments, a stacked package may include a first substrate package that includes a plurality of first pads that are isolated from each other by a first pitch and do not directly contact each other. The stacked package may further include a second substrate package below the first substrate package. The second substrate package may include a plurality of second pads that are isolated from each other by a second pitch and do not directly contact each other. The second pitch may be different from the first pitch. The stacked package may further include a plurality of first conductive bumps between the first substrate package and the second substrate package to electrically connect the plurality of second pads to the first substrate package. The stacked package may further include an interposer above the first substrate package. The interposer may include a plurality of third pads, a plurality of fourth pads, and a plurality of connection lines, the plurality of third pads being isolated from each other by a third pitch and not directly contacting each other, the third pitch being substantially the same as the first pitch, the plurality of fourth pads being isolated from each other by a fourth pitch that is narrower than the third pitch, the plurality of connection lines extending from respective separated fourth pads among the plurality of fourth pads. The stacked package may further include a plurality of second conductive bumps between the first substrate package and the interposer to electrically connect the plurality of first pads to the interposer. The stacked package may further include at least one first semiconductor chip above the interposer and electrically connected to the plurality of third pads and the plurality of connection lines. The stacked package may further include at least one second semiconductor chip above the interposer and electrically connected to the plurality of fourth pads. The stacked package may further include a plurality of third conductive bumps between the interposer and the first semiconductor chip and the second semiconductor chip to electrically connect the interposer to the first semiconductor chip and the second semiconductor chip.

[0009] According to some example embodiments, a stacked package may include an ABF package including a plurality of first pads that are isolated from each other by a first pitch and do not directly contact each other, where the first pitch is from about 55 μm to about 150 μm. The stacked package may further include a high density interconnect (HDI) package below the ABF package, the HDI package including a plurality of second pads that are isolated from each other by a second pitch and do not directly contact each other, where the second pitch is from about 400 μm to about 600 μm, and where the area of the HDI package is larger than the area of the ABF package. The stacked package may further include a plurality of first conductive bumps between the ABF package and the HDI package to electrically connect the plurality of second pads to the ABF package. The stacked package may further include an interposer above the ABF package, the interposer including a plurality of third pads that are isolated from each other by a third pitch and do not directly contact each other, where the third pitch is from about 55 μm to about 150 μm, the interposer further including a plurality of vertical signal lines extending downward from respective third pads separated from among the plurality of third pads, a plurality of fourth pads that are isolated from each other by a fourth pitch and do not directly contact each other, where the fourth pitch is less than about 55 μm, the interposer further including a plurality of connection lines extending downward from respective third pads separated from among the plurality of fourth pads, and where the area of the interposer is smaller than the area of the ABF package. The stacked package may further include a plurality of second conductive bumps between the ABF package and the interposer to electrically connect the plurality of first pads to the plurality of vertical signal lines. The stacked package may further include at least one application specific integrated circuit (ASIC) above the interposer and electrically connected to the plurality of third pads and the plurality of connection lines. The stacked package may further include at least one high bandwidth memory (HBM) above the interposer and electrically connected to the plurality of fourth pads. The stacked package may further include a plurality of third conductive bumps between the interposer and the ASIC and the HBM to electrically connect the interposer to the ASIC and the HBM. The stacked package may further include a molding member configured to cover the ABF package, the HDI package, the interposer, the ASIC, and the HBM.

[0010] According to some example embodiments, a method of manufacturing a stacked package may include: disposing a first substrate package above a second substrate package. The first substrate package may include a plurality of first pads that are isolated from each other by a first pitch and do not directly contact each other. The second substrate package may include a plurality of second pads that are isolated from each other by a second pitch and do not directly contact each other, the second pitch being different from the first pitch. The method may further include: disposing an interposer above the first substrate package. The interposer may include a plurality of third pads that are isolated from each other by a third pitch and do not directly contact each other. The method may further include: disposing at least one first semiconductor chip above the interposer.

[0011] According to some example embodiments, a stacked package may include HDI packages, ABF packages, interposers, and ASICs having different pitches to reduce the cost of manufacturing a stacked package having a large area.

[0012] In addition, the ABF package and the interposer may have substantially the same pitch. Accordingly, the ABF package and the interposer may be electrically connected to each other only through vertical signal lines in the interposer. Therefore, it is not necessary to form horizontal signal lines in the interposer. As a result, an increase in resistance caused by the horizontal signal lines may be reduced or prevented, so that the stacked package may have improved performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Example embodiments will be more clearly understood from the following detailed description in conjunction with the accompanying drawings. Figures 1 to 20 represent non-limiting example embodiments as described herein.

[0014] Figure 1 is a cross-sectional view showing a stacked package according to an example embodiment;

[0015] Figure 2 is a plan view showing Figure 1 the stacked package in;

[0016] Figure 3 is a plan view showing Figure 2 the first base package of the stacked package in;

[0017] Figure 4 is a plan view showing Figure 2 the second base package of the stacked package in;

[0018] Figure 5 is a plan view showing Figure 2 the interposer of the stacked package in;

[0019] Figure 6 , Figure 7 , Figure 8 , Figure 9 and Figure 10 are cross-sectional views showing a method of manufacturing the stacked package in Figure 1 ;

[0020] Figure 11 is a cross-sectional view showing a stacked package according to an example embodiment;

[0021] Figure 12 is a plan view showing Figure 11 the stacked package in;

[0022] Figure 13 is a plan view showing Figure 12 the interposer of the stacked package in;

[0023] Figure 14 is a cross-sectional view showing a stacked package according to an exemplary embodiment;

[0024] Figure 15 is showing Figure 14 a plan view of the stacked package in;

[0025] Figure 16 is showing Figure 15 a plan view of the interposer of the stacked package in;

[0026] Figure 17 is a cross-sectional view showing a stacked package according to an exemplary embodiment;

[0027] Figure 18 is showing Figure 17 a plan view of the interposer of the stacked package in;

[0028] Figure 19 is a cross-sectional view showing a stacked package according to an exemplary embodiment; and

[0029] Figure 20 is showing Figure 19 a plan view of the stacked package in. DETAILED DESCRIPTION

[0030] Hereinafter, some exemplary embodiments will be described in detail with reference to the accompanying drawings.

[0031] Figure 1 is a cross-sectional view showing a stacked package according to an exemplary embodiment, Figure 2 is showing Figure 1 a plan view of the stacked package in.

[0032] Referring to Figure 1 and Figure 2 , a stacked package 100 of some exemplary embodiments may include a first base package 110, a second base package 120, an interposer 130, a first semiconductor chip 140, first to third conductive bumps 170, 172, and 174, a molding member 150, and a plurality of external terminals 160.

[0033] The second base package 120 may be disposed below (e.g., beneath) (e.g., at least as Figure 1as shown on the lower surface of the first substrate package 110). The interposer 130 may be disposed above (e.g., on top of) the first substrate package 110 such that the first substrate package 110 is located between the interposer 130 and the second substrate package 120. The first semiconductor chip 140 may be disposed above (e.g., on top of) the interposer 130 such that the interposer 130 is located between the first substrate package 110 and the first semiconductor chip 140. That is, the second substrate package 120, the first substrate package 110, the interposer 130, and the first semiconductor chip may be stacked in sequence.

[0034] The first substrate package 110 may have a first area. In some example embodiments, the first area of the first substrate package 110 may be in the range of about 30 μm × 30 μm to about 50 μm × 50 μm. However, the first area of the first substrate package 110 may not be limited to the above range.

[0035] The second substrate package 120 may have a second area larger than the first area of the first substrate package 110 such that the first substrate package 110 with the first area is smaller than the second substrate package 120 with the second area. In some example embodiments, the second area of the second substrate package 120 may be not less than about 50 μm × 50 μm. However, the second area of the second substrate package 120 may not be limited to the above range.

[0036] The interposer 130 may have a third area smaller than the first area of the first substrate package 110 such that the first substrate package 110 with the first area is larger than the interposer 130 with the third area. In some example embodiments, the third area of the interposer 130 may be in the range of 20 μm × 20 μm to about 50 μm × 50 μm. In some example embodiments, the third area of the interposer 130 may be in the range of 20 μm × 20 μm to about 30 μm × 30 μm. However, the third area of the interposer 130 may not be limited to the above range.

[0037] The first semiconductor chip 140 may have a fourth area smaller than the third area of the interposer 130. In some example embodiments, the fourth area of the first semiconductor chip 140 may be in the range of 5 μm × 5 μm to about 20 μm × 20 μm. However, the fourth area of the first semiconductor chip 140 may not be limited to the above range. The first semiconductor chip 140 may include a logic chip. For example, the first semiconductor chip 140 may include an application specific integrated circuit (ASIC).

[0038] Thus, the stacked package 100 including the second substrate package 120, the first substrate package 110, the interposer 130, and the first semiconductor chip 140 that are sequentially stacked and have gradually decreasing areas can have a stepped pyramid structure.

[0039] A plurality of first conductive bumps 170 can be disposed between the second substrate package 120 and the first substrate package 110 to electrically connect the second substrate package 120 and the first substrate package 110. A plurality of second conductive bumps 172 can be disposed between the first substrate package 110 and the interposer 130 to electrically connect the first substrate package 110 and the interposer 130. A plurality of third conductive bumps 174 can be disposed between the interposer 130 and the first semiconductor chip 140 to electrically connect the interposer 130 and the first semiconductor chip 140. In some example embodiments, the second conductive bumps 172 can each have a size not greater than the size of a single one of the first conductive bumps 170 among the first conductive bumps 170. The third conductive bumps 174 can each have a size not greater than the size of a single one of the second conductive bumps 172 among the second conductive bumps 172. The first to third conductive bumps 170, 172, and 174 can include solder.

[0040] The molding member 150 can be configured to cover the second substrate package 120, the first substrate package 110, the interposer 130, and the first semiconductor chip 140. The molding member 150 can include a first molding member 152 and a second molding member 154. The first molding member 152 can be configured to cover the first substrate package 110, the interposer 130, and the first semiconductor chip 140. The second molding member 154 can be configured to surround the side surface of the second substrate package 120. The molding member 150 can include an epoxy molding compound (EMC).

[0041] The external terminals 160 can be mounted on the lower surface of the second substrate package 120. The external terminals 160 can include solder.

[0042] Figure 3 is a plan view of the first substrate package of the stacked package shown in Figure 2 the stacked package.

[0043] Referring to Figures 1 to 3 , the first substrate package 110 can include a first insulating substrate 112, a plurality of first pads 114, a plurality of first horizontal signal lines 116, and a plurality of first vertical (or upright) signal lines 118.

[0044] As Figure 1 and Figure 3As shown, the first pads 114 may be disposed on the upper surface of the first insulating substrate 112. The first pads 114 may be arranged to be separated from each other by a first pitch P1 along a first horizontal direction, so as to be isolated from each other on the upper surface of the first insulating substrate 112 without direct contact. The pitch between the first pads 114 along a second horizontal direction substantially perpendicular to the first horizontal direction may be substantially the same as the first pitch P1 between the first pads 114 along the first horizontal direction. The second conductive bumps 172 may be connected to the first pads 114. Accordingly, the second conductive bumps 172 may also be arranged to be separated from each other by the first pitch P1 along the first horizontal direction. In some example embodiments, the pitch between the first pads 114 along the second horizontal direction may be different from the first pitch P1 between the first pads 114 along the first horizontal direction.

[0045] In some example embodiments, the first pitch P1 may be from about 55 μm to about 150 μm. However, the first pitch P1 may not be limited to the above range.

[0046] The first horizontal signal lines 116 may extend from the respective separated first pads 114 on the upper surface of the first insulating substrate 112. The first vertical signal lines 118 may extend vertically (vertically) from the ends of the respective separated first horizontal signal lines 116 through the first insulating substrate 112 to the lower surface of the first insulating substrate 112. The first vertical signal lines 118 may include lower ends exposed through the lower surface of the first insulating substrate 112. The first conductive bumps 170 may be connected to the exposed lower ends of the first vertical signal lines 118.

[0047] In some example embodiments, the first substrate package 110 may include an ABF (Ajinomoto build-up film) package, and the ABF package includes ABF. The first pads 114 having the first pitch P1 may be formed on the upper surface of the first insulating substrate 112 using ABF.

[0048] Figure 4 is a plan view showing Figure 2 the second substrate package of the stacked package in

[0049] Referring to Figure 1 , Figure 2 and Figure 4 , the second substrate package 120 may include a second insulating substrate 122, a plurality of second pads 124, a plurality of second horizontal signal lines 126, and a plurality of second vertical signal lines 128.

[0050] The second pads 124 may be disposed on the upper surface of the second insulating substrate 122. The second pads 124 may be disposed to be separated from each other by a second pitch P2 along a first horizontal direction so as to be isolated from each other without direct contact. The pitch between the second pads 124 along a second horizontal direction may be substantially the same as the second pitch P2 between the second pads 124 along the first horizontal direction. The first conductive bumps 170 may be connected to the second pads 124. Accordingly, the first conductive bumps 170 may also be disposed to be separated from each other by the second pitch P2 along the first horizontal direction. The first vertical signal lines 118 of the first substrate package 110 may be electrically connected to the second pads 124 of the second substrate package 120 via the first conductive bumps 170. In some example embodiments, the pitch between the second pads 124 along the second horizontal direction may be different from the second pitch P2 between the second pads 124 along the first horizontal direction.

[0051] The second pitch P2 may be different from the first pitch P1. In some example embodiments, the second pitch P2 may be wider (e.g., larger) than the first pitch P1 such that the first pitch P1 is narrower (e.g., smaller) than the second pitch P2. The second pitch P2 may be about 400 μm to about 600 μm. However, the second pitch P2 may not be limited to the above range. In some example embodiments, the second pitch P2 may be narrower than the first pitch P1.

[0052] When the terms “about” or “substantially” are used in connection with a numerical value in this specification, the associated numerical value is intended to include a tolerance of ±10% around the stated numerical value. When a range is specified, the range includes all values between the ranges, such as increments of 0.1%.

[0053] The second horizontal signal lines 126 may extend from respective second pads 124 that are separated and on the upper surface of the second insulating substrate 122. The second vertical signal lines 128 may extend vertically through the second insulating substrate 122 from the ends of the respective second horizontal signal lines 126 that are separated to the lower surface of the second insulating substrate 122. The second vertical signal lines 128 may include lower ends that are exposed through the lower surface of the second insulating substrate 122. The external terminals 160 may be connected to the exposed lower ends of the second vertical signal lines 128.

[0054] In some example embodiments, the second substrate package 120 may include a high density interconnect (HDI) package. The HDI package may include an HDI substrate that includes a core layer, a prepreg layer, and a dielectric layer.

[0055] Figure 5 is a plan view of an interposer of the stacked package in Figure 2

[0056] Referring to Figure 1 、Figure 2 and Figure 5 ,the interposer 130 may include a plurality of third pads 134 and a plurality of third vertical signal lines 138. The interposer 130 of some example embodiments may not include horizontal signal lines. In addition, the interposer 130 may include silicon.

[0057] The third pads 134 may be disposed on the upper surface of the interposer 130. The third pads 134 may be disposed to be separated from each other by a third pitch P3 along a first horizontal direction so as to be isolated from each other without direct contact. The pitch between the third pads 134 along a second horizontal direction may be substantially the same as the third pitch P3 between the third pads 134 along the first horizontal direction. The third conductive bumps 174 may be connected to the third pads 134. Accordingly, the third conductive bumps 174 may also be disposed to be separated from each other by the third pitch P3 along the first horizontal direction. In some example embodiments, the pitch between the third pads 134 along the second horizontal direction may be different from the third pitch P3 between the third pads 134 along the first horizontal direction.

[0058] The third pads 134 of the interposer 130 may be electrically connected to the first semiconductor chip 140 via the third conductive bumps 174. In some example embodiments, the third pitch P3 may be substantially the same as the first pitch P1 (e.g., the same within manufacturing tolerances and / or material tolerances). In some example embodiments, the third pitch P3 may be narrower or wider than the first pitch P1. In some example embodiments, the third pitch P3 may be about 55 μm to about 150 μm.

[0059] The third vertical signal lines 138 may vertically extend through the interposer 130 from the ends of the respective separated third pads 134 to the lower surface of the interposer 130. The third vertical signal lines 138 may include lower ends exposed through the lower surface of the interposer 130. The second conductive bumps 172 may be connected to the exposed lower ends of the third vertical signal lines 138. Accordingly, the interposer 130 may be electrically connected to the first substrate package 110 via the second conductive bumps 172.

[0060] In some example embodiments, the first substrate package 110 may be disposed between the interposer 130 and the second substrate package 120. Since the first substrate package 110 may include an ABF package (the ABF package includes first pads 114 separated from each other by a first pitch P1, and the first pitch P1 may be substantially the same as the fine third pitch P3 of the interposer 130), the third pads 134 of the interposer 130 may be electrically connected to the first pads 114 of the first substrate package 110 only through the third vertical signal lines 138. Accordingly, there may be no need to form horizontal signal lines that may generate high resistance in the interposer 130. As a result, the stacked package 100 of some example embodiments may have improved performance.

[0061] In addition, the second substrate package 120 and the first substrate package 110 can be electrically connected to the first semiconductor chip 140 via the interposer 130. Accordingly, the interposer 130 can have a size smaller than that of the first substrate package 110. Moreover, since the expensive first substrate package 110 can be disposed between the interposer 130 and the second substrate package 120, there is no need to provide a first substrate package 110 having a large size. As a result, the cost for manufacturing the stacked package 100 having a large size can be reduced.

[0062] Figure 6 , Figure 7 , Figure 8 , Figure 9 and Figure 10 are cross-sectional views showing a method of manufacturing Figure 1 the stacked package. It will be understood that the operations of the method as shown in Figures 6 to 10 can be implemented in an order different from the order as shown in Figures 6 to 10 . For example, in some example embodiments, the operation(s) as shown in Figure 9 can be implemented before the operation(s) as shown in Figure 6 . The method as described herein can be implemented by any known apparatus for manufacturing a stacked package, and any known apparatus includes any known computing device configured to control such an apparatus for manufacturing one or more stacked packages. Such a known computing device can include one or more instances of a processing circuit (such as hardware including logic circuits), a hardware / software combination (such as a processor executing software), or a combination thereof. For example, the processing circuit can more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc. In some example embodiments, the processing circuit can include a non-transitory computer-readable storage device (e.g., a solid state drive (SSD)), a program storing instructions, and a processor configured to execute the instructions to control one or more known apparatuses for manufacturing a stacked package to implement some or all of any method for manufacturing one or more stacked packages regarding any example embodiment.

[0063] Referring to Figure 6 , the interposer 130 can be disposed above (e.g., on top of) the first substrate package 110, wherein the interposer 130 includes a plurality of third pads 134 that are isolated from each other by a third pitch P3 and do not directly contact each other. Still referring to Figure 6, the second conductive bump 172 can be disposed between the first substrate package 110 and the interposer 130 to electrically connect the first substrate package 110 and the interposer 130. The second conductive bump 172 can be formed on the upper surface of the first substrate package 110. The second conductive bump 172 can be electrically connected to the first pad 114 of the first substrate package 110.

[0064] The interposer 130 can be disposed on the second conductive bump 172. The third vertical signal line 138 of the interposer 130 can be electrically connected to the second conductive bump 172. Thus, the interposer 130 can be electrically connected to the first substrate package 110 via the second conductive bump 172.

[0065] Referring to Figure 7 , at least one first semiconductor chip 140 can be disposed above (e.g., on top of) the interposer 130. Still referring to Figure 7 , the third conductive bump 174 can be disposed between the interposer 130 and the first semiconductor chip 140 to electrically connect the interposer 130 and the first semiconductor chip 140. The third conductive bump 174 can be formed on the upper surface of the interposer 130. The third conductive bump 174 can be electrically connected to the third pad 134 of the interposer 130.

[0066] The first semiconductor chip 140 can be disposed on the upper surface of the interposer 130. The first semiconductor chip 140 can be electrically connected to the third conductive bump 174. Thus, the first semiconductor chip 140 can be electrically connected to the interposer 130 via the third conductive bump 174.

[0067] A test signal can be applied to the first substrate package 110, the interposer 130, and the first semiconductor chip 140 to test the first substrate package 110, the interposer 130, and the first semiconductor chip 140.

[0068] Referring to Figure 8 , the first molding member 152 can be formed on the upper surface of the first substrate package 110 to cover the interposer 130 and the first semiconductor chip 140 with the first molding member 152.

[0069] Referring to Figure 9 , the first substrate package 110 can be disposed above (e.g., on top of) the second substrate package 120, wherein the first substrate package 110 includes a plurality of first pads 114 that are spaced apart from each other by a first pitch P1 and do not directly contact each other, and the second substrate package 120 includes a plurality of second pads 124 that are spaced apart from each other by a second pitch P2 and do not directly contact each other, and the second pitch P2 is different from the first pitch P1. Still referring to Figure 9, the first conductive bump 170 can be disposed between the first substrate package 110 and the second substrate package 120 to electrically connect the first substrate package 110 and the second substrate package 120. The first conductive bump 170 can be formed on the upper surface of the second substrate package 120. The first conductive bump 170 can be connected to the second pad 124 of the second substrate package 120.

[0070] The first substrate package 110, the interposer 130, and the first semiconductor chip 140 covered by the first molding member 152 can be arranged on the upper surface of the second substrate package 120. The first vertical signal line 118 of the first substrate package 110 can be connected to the first conductive bump 170. Thus, the first substrate package 110 can be electrically connected to the second substrate package 120 via the first conductive bump 170.

[0071] A test signal can be applied to the second substrate package 120, the first substrate package 110, the interposer 130, and the first semiconductor chip 140 to test the second substrate package 120, the first substrate package 110, the interposer 130, and the first semiconductor chip 140.

[0072] Referring to Figure 10 , a second molding member 154 can be formed on the side surface of the second substrate package 120 to surround the side surface of the second substrate package 120 with the second molding member 154. Thus, as Figure 8 and Figure 10 shown, the method according to some example embodiments can include: forming a molding member 150 on the first substrate package 110, the second substrate package 120, the interposer 130, and the first semiconductor chip 140. As Figure 8 shown, the step of forming the molding member 150 can include: covering the first substrate package 110, the interposer 130, and the first semiconductor chip 140 with the first molding member 152. As Figure 10 shown, the step of forming the molding member 150 can include: surrounding the side surface of the second substrate package 120 with the second molding member 154.

[0073] A plurality of external terminals 160 can be mounted on the lower ends of the second vertical signal lines 128 of the second substrate package 120 to complete the Figure 1 stacked package 100 in

[0074] Figure 11 is a cross-sectional view showing a stacked package according to an example embodiment, Figure 12 is showing Figure 11 the plan view of the stacked package in Figure 13 is showingFigure 12 A plan view of an interposer of a stacked package in

[0075] Referring to Figures 11 to 13 , a stacked package 100a of some example embodiments may include a first substrate package 110, a second substrate package 120, an interposer 130, a first semiconductor chip 140, a second semiconductor chip 180, first through third conductive bumps 170, 172, and 174, a molding member 150, and external terminals 160.

[0076] Figures 11 to 13 The first substrate package 110, the second substrate package 120, the first semiconductor chip 140, the first through third conductive bumps 170, 172, and 174, the molding member 150, and the external terminals 160 in Figure 1 may respectively have structures and functions that are substantially the same as the structures and functions of the first substrate package 110, the second substrate package 120, the first semiconductor chip 140, the first through third conductive bumps 170, 172, and 174, the molding member 150, and the external terminals 160 in Figures 11 to 13 . Accordingly, the same reference numerals may denote the same elements, and any further description of the first substrate package 110, the second substrate package 120, the first semiconductor chip 140, the first through third conductive bumps 170, 172, and 174, the molding member 150, and the external terminals 160 in Figure 11 may be omitted here for the sake of brevity. As shown in Figure 11 , the molding member 150 may be configured to cover the first substrate package 110, the second substrate package 120, the interposer 130, the first semiconductor chip 140, and the second semiconductor chip 180. As shown in

[0077] The second semiconductor chip 180 may be disposed on the upper surface of the interposer 130 such that the second semiconductor chip 180 may be understood to be above the interposer 130. In some example embodiments, the second semiconductor chip 180 may include a high bandwidth memory (HBM). The second semiconductor chip 180 may be electrically connected to the first semiconductor chip 140 via the interposer 130. To electrically connect the first semiconductor chip 140 to the second semiconductor chip 180, the interposer 130 may further include a pair of multiple fourth pads 136, 137 and connection lines 135 (i.e., a pair of the fourth pads and the connection lines).

[0078] The fourth pads 136 and 137 may be disposed on the upper surface of the interposer 130. Each of the fourth pads 136 and 137 may be disposed to be separated from each other along a first horizontal direction (e.g., isolated from each other without direct contact) by a fourth pitch P4. The pitch along a second horizontal direction between the fourth pads 136 and 137 may be substantially the same as the fourth pitch P4 along the first horizontal direction between the fourth pads 136 and 137. In some example embodiments, the fourth pitch P4 may be narrower than the third pitch P3. In some example embodiments, the pitch along the second horizontal direction between the fourth pads 136 and 137 may be different from the fourth pitch P4 along the first horizontal direction between the fourth pads 136 and 137. In some example embodiments, the fourth pitch P4 may be less than about 55 μm.

[0079] The first semiconductor chip 140 may be disposed above the right fourth pad 136 adjacent to the third pad 134. The third conductive bumps 174 may be disposed between the first semiconductor chip 140 and the right fourth pad 136. As Figure 11 shown, the first semiconductor chip 140 may be electrically connected to the third pad 134 (e.g., by connecting to the third conductive bumps 174 connected to the third pad 134) and (e.g., as Figure 11 shown by connecting to the first set of third conductive bumps 174 connected to the right fourth pad 136) electrically connected to the connection line 135.

[0080] The second semiconductor chip 180 may be disposed above the plurality of left fourth pads 137 such that the left fourth pads 137 (e.g., based on the second semiconductor chip 180 connected to the second set of third conductive bumps 174 connected to the left fourth pads 137) are electrically connected to the second semiconductor chip 180. The third conductive bumps 174 may be disposed between the second semiconductor chip 180 and the left fourth pads 137.

[0081] The connection line 135 may be formed at the interposer 130 to electrically connect the respective separated fourth pads 136 and the respective separated fourth pads 137 to each other and electrically connect to the first semiconductor chip 140. The connection line 135 may extend in the interposer 130. In some example embodiments, the connection line 135 may be disposed on the upper surface of the interposer 130.

[0082] Accordingly, the second semiconductor chip 180 may be electrically connected to the first semiconductor chip 140 through the third conductive bumps 174, the left fourth pads 137, the connection line 135, the right fourth pads 136, and the third conductive bumps 174. Thus, the interposer 130 may be understood to be electrically connected to the first semiconductor chip 140 and the second semiconductor chip 180 via the plurality of third conductive bumps 174, and the third conductive bumps 174 may be understood to electrically connect the interposer 130 to the first semiconductor chip 140 and the second semiconductor chip 180.

[0083] The method of manufacturing the stacked package 100a according to an exemplary embodiment may include processes substantially the same as those shown with reference to Figures 6 to 10 except for further including a process of forming a second semiconductor chip 180 on the upper surface of the interposer 130. Such processes may include arranging at least one second semiconductor chip 180 above the interposer 130, wherein the second semiconductor chip 180 is electrically connected to the first semiconductor chip 140 and the second semiconductor chip 180 has a fourth pitch P4 that is narrower than a third pitch P3. Accordingly, for the sake of brevity, any further description of the method may be omitted herein.

[0084] Figure 14 is a cross-sectional view showing a stacked package according to an exemplary embodiment, Figure 15 is showing Figure 14 a plan view of the stacked package in Figure 16 is showing Figure 15 a plan view of the interposer of the stacked package in

[0085] The stacked package 100b of some exemplary embodiments may include elements substantially the same as those of the stacked package 100a in Figure 11 except for including two second semiconductor chips. Accordingly, the same reference numerals may denote the same elements and, for the sake of brevity, any further description of the same elements may be omitted herein.

[0086] With reference to Figures 14 to 16 , two second semiconductor chips 180 and 182 may be arranged on the upper surface of the interposer 130. The second semiconductor chips 180 and 182 may be arranged on both sides of the first semiconductor chip 140.

[0087] Accordingly, fourth pads 136 and 137 may be arranged on the upper surface of the interposer 130 below two edge portions of the first semiconductor chip 140. The second semiconductor chips 180 and 182 may be electrically connected to the first semiconductor chip 140 via connection lines 135.

[0088] Figure 17 is a cross-sectional view showing a stacked package according to an exemplary embodiment, Figure 18 is showing Figure 17 a plan view of the interposer of the stacked package in

[0089] The stacked package 100c of some exemplary embodiments may include elements substantially the same as those of Figure 14The components of the stacked package 100b in [reference] are substantially the same as those of the components in [reference]. Therefore, the same reference numerals may denote the same components, and any further description of the same components may be omitted here for the sake of brevity.

[0090] Referring to Figure 17 and Figure 18 , two first semiconductor chips 140 and 142 may be disposed on the central portion of the upper surface of the interposer 130. Eight second semiconductor chips 180 and 182 may be disposed on the edge portion of the upper surface of the interposer 130.

[0091] Accordingly, the second semiconductor chips 180 and 182 may be positioned on both sides of the first semiconductor chips 140 and 142. Four second semiconductor chips 180 and four second semiconductor chips 182 may be electrically connected to the first semiconductor chips 140 and 142, respectively. The second semiconductor chips 180 and 182 may be electrically connected to the first semiconductor chips 140 and 142 via connection lines 135.

[0092] Figure 19 is a cross-sectional view showing a stacked package according to an exemplary embodiment, Figure 20 is showing Figure 19 a plan view of the stacked package in [reference].

[0093] Except for further including a third substrate package, the stacked package 100d of some exemplary embodiments may include components substantially the same as those of the components of the stacked package 100 in [reference]. Therefore, the same reference numerals may denote the same components, and any further description of the same components may be omitted here for the sake of brevity. Figure 1 The components of the stacked package 100b in [reference] are substantially the same as those of the components in [reference]. Therefore, the same reference numerals may denote the same components, and any further description of the same components may be omitted here for the sake of brevity.

[0094] Referring to Figure 19 and Figure 20 , the third substrate package 190 may be disposed between the first substrate package 110 and the second substrate package 120. In some exemplary embodiments, the third substrate package 190 may include an ABF package or an HDI package. The third substrate package 190 may function to improve the characteristics of the stacked package 100d and reduce the routing complexity of signal lines.

[0095] The first conductive bumps 170 may be disposed between the third substrate package 190 and the first substrate package 110 to electrically connect the third substrate package 190 and the first substrate package 110. The fourth conductive bumps 176 may be disposed between the third substrate package 190 and the second substrate package 120 to electrically connect the third substrate package 190 and the second substrate package 120.

[0096] The third substrate package 190 may include a third insulating substrate 192, a plurality of fifth pads 194, a plurality of third horizontal signal lines 196, and a plurality of third vertical signal lines 198.

[0097] The plurality of fifth pads 194 may be disposed on the upper surface of the third insulating substrate 192. The first conductive bumps 170 may be connected to the fifth pads 194. The fifth pads 194 may be arranged to be separated from each other along a first horizontal direction (e.g., isolated from each other without direct contact) by a fifth pitch P5. The fifth pitch P5 may be different from the first pitch P1. The fifth pitch P5 may be wider than the first pitch P1 and narrower than the second pitch P2. The pitch between the fifth pads 194 along a second horizontal direction may be substantially the same as the fifth pitch P5 between the fifth pads 194 along the first horizontal direction. In some example embodiments, the pitch between the fifth pads 194 along the second horizontal direction may be different from the fifth pitch P5 between the fifth pads 194 along the first horizontal direction. In some example embodiments, the fifth pitch P5 is about 150 μm to about 400 μm.

[0098] The third horizontal signal lines 196 may extend from respective separated fifth pads 194 on the upper surface of the third insulating substrate 192. The third vertical signal lines 198 may extend vertically through the third insulating substrate 192 from the ends of the respective separated third horizontal signal lines to the lower surface of the third insulating substrate 192. The third vertical signal lines 198 may include lower ends exposed through the lower surface of the third insulating substrate 192. The fourth conductive bumps 176 may be connected to the exposed lower ends of the third vertical signal lines 198.

[0099] The molding member 150 may be configured to cover the second substrate package 120, the third substrate package 190, the first substrate package 110, the interposer 130, and the first semiconductor chip 140. The molding member 150 may include a first molding member 152, a second molding member 154, and a third molding member 156. The first molding member 152 may be configured to cover the first substrate package 110, the interposer 130, and the first semiconductor chip 140. The second molding member 154 may be configured to surround the side surface of the second substrate package 120. The third molding member 156 may be configured to surround the side surface of the third substrate package 190. The molding member 150 may include an EMC.

[0100] In some example embodiments, the stacked package 100d of some example embodiments may include at least two first semiconductor chips and / or at least one second semiconductor chip.

[0101] In addition to further including a process for forming the third substrate package 190, the method of manufacturing the stacked package 100d according to an example embodiment may include with reference to Figures 6 to 10A process that is substantially the same as the process shown. Such a process may include: forming a third substrate package 190 between a first substrate package 110 and a second substrate package 120, the third substrate package 190 including a plurality of fifth pads 194 that are isolated from each other by a fifth pitch P5 and do not contact directly, and the fifth pitch P5 is different from the first pitch P1. Such a process may also include: placing a plurality of fourth conductive bumps 176 between the second substrate package 120 and the third substrate package 190 to electrically connect the second substrate package 120 and the third substrate package 190. Therefore, for the sake of brevity, any further description of the method may be omitted here.

[0102] The stacked packages of some example embodiments can be applied to network devices, artificial intelligence (AI) devices, etc. However, the stacked packages of some example embodiments can also be applied to other devices as well as network devices, AI devices, etc.

[0103] According to some example embodiments, the stacked package may include HDI packages, ABF packages, interposers, and ASICs with different pitches to reduce the cost of manufacturing a stacked package with a large area.

[0104] In addition, the ABF package and the interposer may have substantially the same pitch. Therefore, the ABF package and the interposer can be electrically connected to each other only through the vertical signal lines in the interposer. Therefore, it is not necessary to form horizontal signal lines in the interposer. As a result, the increase in resistance caused by the horizontal signal lines can be reduced or prevented, so that the stacked package can have improved performance.

[0105] The foregoing is an illustration of some exemplary embodiments and should not be construed as a limitation thereof. Although some example embodiments have been described, those skilled in the art will readily understand that many modifications in the example embodiments are feasible without materially departing from the novel teachings and advantages of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. In the claims, the means-plus-function limitation is intended to cover the structures described herein as performing the functions and covers not only structural equivalents but also equivalent structures. Therefore, it will be understood that the foregoing is an illustration of various example embodiments and should not be construed as limited to the specific example embodiments disclosed, and modifications to the disclosed example embodiments as well as other example embodiments are intended to be included within the scope of the appended claims.

Claims

1. A stacked package, the stacked package comprising: A first substrate package, including a plurality of first pads, the plurality of first pads being isolated from each other by a first pitch and not in direct contact; A second substrate package, located below the first substrate package, the second substrate package including a plurality of second pads, the plurality of second pads being isolated from each other by a second pitch and not in direct contact, the second pitch being different from the first pitch; An interposer, located above the first substrate package, the interposer including a plurality of third pads and a plurality of vertical signal lines, the plurality of third pads being isolated from each other by a third pitch and not in direct contact; and At least one first semiconductor chip, located above the interposer, Wherein, the plurality of vertical signal lines extend vertically through the interposer from respective separated third pads among the plurality of third pads to the lower surface of the interposer, such that the plurality of third pads are electrically connected to the plurality of first pads only through the plurality of vertical signal lines, and the interposer does not include horizontal signal lines.

2. The stacked package according to claim 1, wherein, The first pitch is narrower than the second pitch.

3. The stacked package according to claim 1, wherein, The first pitch is substantially the same as the third pitch.

4. The stacked package according to claim 1, wherein, The area of the first substrate package is smaller than the area of the second substrate package and larger than the area of the interposer.

5. The stacked package according to claim 1, wherein, The first substrate package includes: A first insulating substrate, wherein the plurality of first pads are located on the upper surface of the first insulating substrate; A plurality of first horizontal signal lines, extending from respective separated first pads among the plurality of first pads on the upper surface of the first insulating substrate; and A plurality of first vertical signal lines, extending vertically through the first insulating substrate from respective separated first horizontal signal lines among the plurality of first horizontal signal lines to the lower surface of the first insulating substrate.

6. The stacked package according to claim 1, wherein, The second substrate package includes: A second insulating substrate, wherein the plurality of second pads are located on the upper surface of the second insulating substrate; A plurality of second horizontal signal lines, extending from respective separated second pads among the plurality of second pads on the upper surface of the second insulating substrate; and A plurality of second vertical signal lines, extending vertically through the second insulating substrate from respective separated second horizontal signal lines among the plurality of second horizontal signal lines to the lower surface of the second insulating substrate.

7. The stacked package according to any one of claims 1 to 6, the stacked package further comprising: A plurality of first conductive bumps, located between the first substrate package and the second substrate package to electrically connect the first substrate package and the second substrate package; A plurality of second conductive bumps, located between the first substrate package and the interposer to electrically connect the first substrate package and the interposer; And A plurality of third conductive bumps, located between the interposer and the first semiconductor chip to electrically connect the interposer and the first semiconductor chip.

8. The stacked package according to claim 7, wherein, The plurality of second conductive bumps each have a size not greater than the size of a single first conductive bump among the plurality of first conductive bumps and greater than the size of a single third conductive bump among the plurality of third conductive bumps.

9. The stacked package according to any one of claims 1 to 6, the stacked package further comprising at least one second semiconductor chip located above the interposer.

10. The stacked package according to claim 9, wherein, The interposer further includes a plurality of fourth pads, the plurality of fourth pads being isolated from each other by a fourth pitch and not in direct contact and electrically connected to the at least one second semiconductor chip.

11. The stacked package according to claim 10, wherein, The interposer further includes connection lines that extend from respective separated fourth pads among the plurality of fourth pads and are connected to the at least one first semiconductor chip.

12. The stacked package according to claim 11, wherein, The connection lines extend in the interposer.

13. The stacked package according to claim 10, wherein, The fourth pitch is narrower than the third pitch.

14. The stacked package according to claim 1, the stacked package further comprising: A third substrate package located between the first substrate package and the second substrate package, the third substrate package including a plurality of fifth pads that are isolated from each other by a fifth pitch and do not directly contact each other.

15. The stacked package according to claim 14, wherein, The fifth pitch is wider than the first pitch and narrower than the second pitch.

16. The stacked package according to claim 14, wherein, The third substrate package includes: A third insulating substrate, wherein the plurality of fifth pads are located on the upper surface of the third insulating substrate; A plurality of third horizontal signal lines extending from respective separated fifth pads among the plurality of fifth pads on the upper surface of the third insulating substrate; and A plurality of third vertical signal lines extending vertically through the third insulating substrate from respective separated third horizontal signal lines among the plurality of third horizontal signal lines to the lower surface of the third insulating substrate.

17. The stacked package according to claim 14, the stacked package further comprising: A plurality of fourth conductive bumps located between the second substrate package and the third substrate package to electrically connect the second substrate package and the third substrate package.

18. A stacked package, the stacked package comprising: An ABF package including a plurality of first pads that are isolated from each other by a first pitch and do not directly contact each other, wherein the first pitch is 55 μm to 150 μm; A high density interconnect package located below the ABF package, the high density interconnect package including a plurality of second pads that are isolated from each other by a second pitch and do not directly contact each other, wherein the second pitch is 400 μm to 600 μm, and wherein the area of the high density interconnect package is larger than the area of the ABF package; A plurality of first conductive bumps located between the ABF package and the high density interconnect package to electrically connect the plurality of second pads and the ABF package; An interposer located above the ABF package, the interposer including a plurality of third pads that are isolated from each other by a third pitch and do not directly contact each other, wherein the third pitch is 55 μm to 150 μm, the interposer further includes a plurality of vertical signal lines, a plurality of fourth pads that are isolated from each other by a fourth pitch and do not directly contact each other, the fourth pitch being less than 55 μm, the interposer further includes a plurality of connection lines extending downward from respective separated fourth pads among the plurality of fourth pads, wherein the area of the interposer is smaller than the area of the ABF package; A plurality of second conductive bumps located between the ABF package and the interposer to electrically connect the plurality of first pads and the plurality of vertical signal lines; At least one application specific integrated circuit located above the interposer and electrically connected to the plurality of third pads and the plurality of connection lines; At least one high bandwidth memory located above the interposer and electrically connected to the plurality of fourth pads; A plurality of third conductive bumps located between the interposer and the application specific integrated circuit and the high bandwidth memory to electrically connect the interposer and the application specific integrated circuit and the high bandwidth memory; and A molded component configured to cover an ABF package, a high density interconnect package, an interposer, an application specific integrated circuit, and a high bandwidth memory, wherein the plurality of vertical signal lines extend vertically through the interposer from respective separated third pads of the plurality of third pads to a lower surface of the interposer such that the plurality of third pads are electrically connected to the plurality of second conductive bumps only through the plurality of vertical signal lines, and the interposer does not include horizontal signal lines.

19. The stacked package according to claim 18, the stacked package further comprising: A second ABF package located between the ABF package and the high density interconnect package, the second ABF package including a plurality of fifth pads that are isolated from each other by a fifth pitch and do not directly contact each other, the fifth pitch being 150 μm to 400 μm; and A plurality of fourth conductive bumps located between the high density interconnect package and the second ABF package to electrically connect the high density interconnect package and the second ABF package.

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