A CTC encoder and encoding method based on pipeline structure

Abstract

The present invention discloses a CTC encoder and encoding method based on a pipeline structure, and belongs to the field of wireless communication technology. Aiming at the problems that the prior art encoding consumes a long clock cycle, has low encoding efficiency, and consumes too much resources in the prior art, the present invention provides a CTC encoder and encoding method based on a pipeline structure, adopts a sub-encoder of a pipeline structure, performs pre-coding of an inner interleaving sequence while encoding an original information sequence, reduces the encoding operation cycle, reuses a sequence sub-interleaving unit to realize sub-interleaving of the original information sequence encoding and sub-interleaving of the inner interleaving sequence encoding, performs inner interleaving and sub-interleaving operations in the algorithm through external input sequence inner interleaving addresses and sequence sub-interleaving addresses, reduces the internal complex calculation of the CTC encoder, improves the performance and flexibility of the system, and reduces the hardware overhead, has good practical application value, and is suitable for hardware implementation.

Description

Technical Field

[0001] The present invention relates to the field of wireless communication technology, and more specifically, to a CTC encoder and encoding method based on a pipeline structure. Background Art

[0002] Wireless communication systems have gone through a century since Gugliemo Marconi invented the telegraph in 1895, and now transmit voice, image or data information on wireless broadband devices such as 3G and LTE. Especially in the second half of the 20th century, the rapid development of wireless communication systems is largely due to the development of two independent fields: information theory and microelectronics.

[0003] Shannon published a groundbreaking academic paper, “A mathematical theory of communication” in 1948. He pointed out the limits of reliable communication transmission under unreliable channel conditions and the methods to achieve these limits, and systematically proposed the relationship between communication reliability and effectiveness.

[0004] In the early 1990s, the coding community proposed three main ideas that must be followed to design a good code, and Turbo codes are the perfect combination of these ideas, mainly for the following three reasons:

[0005] 1. Use systematic convolutional codes instead of non-systematic convolutional codes so that the output of the encoder does not contain the input information.

[0006] 2. The input of the decoder is soft information, not hard decision information, and soft information can be extracted from the output of the decoder for information exchange between component decoders. Benedetto first used SISO to describe such a decoder.

[0007] 3. The encoder encodes different arrangements of the same input information sequence, and the two component decoders can feed their respective outputs back to the other component decoder in an iterative manner. The interleaver changes the order of the original input information sequence, which is the key factor for the performance of Turbo codes to approach the Shannon limit, and also caters to the idea of ​​Shannon random coding.

[0008] The dual binary turbo code used in CTC (Convolutional Turbo Code) in the IEEE 802.16e protocol is a channel coding technology. By introducing an iterative decoding structure and maximum a posteriori probability decoding with soft input and soft output, better decoding performance can be achieved at a lower decoding complexity. The simulation results under the addition of Gaussian white noise channel show that the performance of CTC can approach the Shannon limit.

[0009] WIMAX technology is a broadband wireless access technology based on the IEEE802.16 series of standards. There are two main technical standards, one is the IEEE802.16d standard for fixed broadband wireless access, and the other is the IEEE802.16e standard for mobile broadband wireless access. In a system based on the IEEE802.16 standard, choosing a high-performance codec is very important for achieving high-quality and high-speed wireless transmission.

[0010] CTC (Convolutional Turbo Code) is one of the channel coding schemes adopted by the WIMAX standard. The CTC in the standard has a variety of selectable code rates (such as from 1 / 3 to 5 / 6) and very flexible packet lengths (such as from 64bits to 8192bits). Compared with the classic Turbo code, CTC has the following advantages:

[0011] (a) Using CRSC (recursive systematic convolutional code) as subcode to improve coding efficiency;

[0012] (b) The interleaving depth is half of the classic Turbo code, and the decoding delay is reduced;

[0013] (c) Increasing the minimum free distance by inter-symbol interleaving can reduce the error floor;

[0014] The CTC encoder uses two dual binary cyclic recursive systematic convolutional code (CRSC) encoders. The information bits are input in parallel from the A and B terminals. The bit group entering the encoder at each moment is one of 00, 01, 10, and 11. The packet length of the input data is k bits or N pairs of bits (k = 2*N).

[0015] When only two dual binary cyclic recursive systematic convolutional code (CRSC) encoders are used and the internal calculation of sequence sub-interleaving addresses and intra-sequence interleaving addresses consumes a lot of computing resources, each encoding consumes a long clock cycle, the encoding efficiency is low, and the resource consumption is too large. Summary of the invention

[0016] 1. Technical issues to be solved

[0017] In view of the problems in the prior art that the prior art encoding consumes a long clock cycle, has low encoding efficiency and consumes too much resources, the present invention provides a CTC encoder and encoding method based on a pipeline structure, which adopts a sub-encoder with a pipeline structure to pre-encode an inner interleaved sequence while encoding the original information sequence, thereby reducing the encoding operation cycle and improving the algorithm efficiency and hardware utilization.

[0018] 2. Technical solution

[0019] The purpose of the present invention is achieved through the following technical solutions.

[0020] A CTC encoder based on a pipeline structure comprises a control module and an encoding module, wherein the control module is connected to the encoding module; the control module comprises a control unit; the encoding module comprises a data allocation unit, an intra-sequence interleaving unit, a sequence sub-interleaving unit, a sub-encoder and a data temporary storage unit, wherein the data temporary storage unit is connected to the data allocation unit, the intra-sequence interleaving unit and the sequence sub-interleaving unit, and the data allocation unit and the intra-sequence interleaving unit are also connected to the sub-encoder; the sub-encoder comprises a pre-encoding unit and an actual encoding unit.

[0021] Preferably, the data temporary storage unit is divided into seven storage blocks according to the type of stored information, wherein the first and second storage blocks store the original information sequence and configuration information, the third storage block stores the interleaved address within the sequence, the fourth storage block stores the sequence sub-interleaved address, the fifth and sixth storage blocks store the encoded intermediate results, and the seventh storage block stores the sequence sub-interleaved results.

[0022] The present invention provides a high-performance CTC encoder with low area consumption based on a pipeline structure, which can effectively improve the encoding consumption clock, reduce hardware resource overhead, and better meet the needs of practical applications.

[0023] A CTC encoding method based on a pipeline structure, using the CTC encoder based on a pipeline structure, the processing flow includes the following steps:

[0024] Step 1: Initialize the encoder, and the control module reads the configuration information stored in the data temporary storage unit;

[0025] Step 2: The control module controls the data allocation unit to enable the precoding unit to precode the original information sequence to obtain the cyclic state Sc1, and the sequence sub-interleaving unit performs a sequence sub-interleaving operation on the original information sequence, and the sequence sub-interleaving operation result (As, Bs) is stored in the data temporary storage unit;

[0026] Step 3: The pre-coding unit inputs the cyclic state Sc1 into the actual coding unit for actual coding, and the actual coding unit operation result (Y1, W1) is stored in the data temporary storage unit as the coding intermediate result; the intra-sequence interleaving unit inputs the sequence information read according to the intra-sequence interleaving address to the pre-coding unit for pre-coding to obtain the cyclic state Sc2;

[0027] Step 4: The pre-coding unit inputs the loop state Sc2 into the actual coding unit for actual coding, and the actual coding unit operation result (Y2, W2) is stored in the data temporary storage unit as the coding intermediate result;

[0028] Step 5: The sequence sub-interleaving unit reads the intermediate coding results (Y1, W1) and (Y2, W2) in the data temporary storage unit, and then performs inner interleaving on the sequence sub-interleaving operation result (Y1s, W1s) and the sub-interleaving sequence (Y2s, W2s) of the inner interleaved coding sequence, and stores the operation results (X1, X2) and (X3, X4) in the data temporary storage unit, where (X1, X2) corresponds to the result of sub-interleaving Y1 and Y2 first and then inner interleaving, and (X3, X4) corresponds to the result of sub-interleaving W1 and W2 first and then inner interleaving.

[0029] Preferably, the intra-sequence interleaving unit reads the sequence corresponding to the intra-sequence interleaving address of the original information sequence in the data temporary storage unit, and sends the read sequence data as the intra-interleaving sequence of the original information sequence to the sub-encoder. The intra-sequence interleaving unit reads the intra-sequence interleaving address in the data temporary storage unit, and reads the corresponding information from the original information sequence in the data temporary storage unit according to the address, and transmits it to the pre-coding unit and the actual coding unit for operation.

[0030] Preferably, the sequence sub-interleaving unit reads the sequence sub-interleaving address corresponding sequence of the original information sequence or the coding intermediate result in the data temporary storage unit, and performs inner interleaving again if the read sequence is the coding intermediate result. The sequence sub-interleaving unit distinguishes whether the input is the original information sequence and the inner interleaved coding sequence, wherein an additional step of sequence inner interleaving is required after the sub-interleaving of the coding intermediate result, and if it is read from the original information sequence, no additional operation is required.

[0031] The CTC encoder of the present invention can be flexibly configured by externally inputting sub-interleaving addresses and inner interleaving addresses, and reads information from the data temporary storage module according to the sub-interleaving addresses and inner interleaving addresses input from the outside in the read data temporary storage unit according to the address information sequence, performs sub-interleaving and inner interleaving, saves the complex calculation part inside the encoder, and reduces the area consumption of the CTC encoder.

[0032] Preferably, when the precoding unit operates, the register of the precoding unit is first initialized to zero, the information sequence is sequentially input to the precoding unit, the register state of the precoding unit is updated, and the cycle state Sc is calculated according to the final value of the register of the precoding unit.

[0033] Preferably, when the actual coding unit operates, the register inside the actual coding unit is first initialized according to the loop state Sc calculated by the pre-coding unit; the information sequence is sequentially input to the actual coding unit, the register state of the actual coding unit is updated, and the actual coding operation result is obtained.

[0034] Preferably, the precoding unit starts precoding the inner interleaved sequence when the actual coding unit actually codes the original information sequence. The precoding unit starts precoding the inner interleaved sequence when the actual coding unit actually codes the original information sequence, so as to realize a pipeline structure, shorten the coding cycle and improve coding efficiency.

[0035] Preferably, the configuration information read by the encoder during initialization includes the sequence logarithm and the number of encodings. The sequence logarithm in the configuration parameter represents one-half of the encoding code length each time, and the number of encodings in the configuration parameter represents the number of encodings to be performed for the input original information sequence length.

[0036] Preferably, the data distribution unit reads the original information sequence of the data temporary storage unit and sends it to the sub-encoder. After reading the original information sequence in the data temporary storage unit, the data distribution unit converts part of the parallel mode into a serial mode and transmits it to the pre-coding unit and the actual encoding unit in the form of two-bit information pairs.

[0037] The present invention uses a control unit to read configuration information and control the operation flow of a convolutional turbo code (CTC) encoding algorithm, calls a precoding unit and an actual encoding unit through a pipeline structure to implement original information sequence encoding and inner interleaving sequence encoding, and implements sub-interleaving of original information sequence encoding and sub-interleaving of inner interleaving sequence encoding by multiplexing sequence sub-interleaving units, thereby reducing the encoding operation cycle and improving algorithm efficiency and hardware utilization.

[0038] 3. Beneficial effects

[0039] Compared with the prior art, the advantages of the present invention are:

[0040] The present invention discloses a high-performance CTC encoder with low area consumption based on a pipeline structure. The sub-encoder of the pipeline structure is used to pre-encode the inner interleaved sequence while encoding the original information sequence, thereby reducing the encoding operation cycle and improving the algorithm efficiency. During the encoding operation, a sequence sub-interleaving unit is reused, and the original information sequence A and B are sequentially interleaved with the original information sequence coding sequence Y1, W1 and the inner interleaved sequence coding sequence Y2, W2 by the multiplexing sequence sub-interleaving unit, thereby improving the hardware utilization rate.

[0041] The encoder of the present invention performs the inner interleaving and sub-interleaving operations in the algorithm by externally inputting the inner interleaving address of the sequence and the sub-interleaving address of the sequence, thereby reducing the internal complex calculation of the CTC encoder. The main calculation units of the architecture are all adders, and no multiplier is required for calculation. Under the condition of ensuring performance, it has low calculation complexity and low hardware cost. The present invention effectively improves the performance and flexibility of the system, reduces the hardware cost, has good practical application value, and is very suitable for hardware implementation. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 It is a module schematic diagram of a CTC encoder based on a pipeline structure of the present invention;

[0043] Figure 2 is a schematic diagram of a sequence sub-interleaving unit of the present invention;

[0044] Figure 3 It is a schematic diagram of the algorithm implementation flow of the CTC encoder of the present invention. DETAILED DESCRIPTION

[0045] The present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0046] Example 1

[0047] The structural module of the high-performance CTC encoder based on pipeline structure described in the present invention is as follows Figure 1 As shown, it includes a control module and an encoding module, the control module is connected to the encoding module, and controls the encoding module to perform calculations.

[0048] The control module includes a control unit, which reads configuration information including the number of sequence logarithms N and the number of encoding times n, controls the operation flow of the CTC encoder through logic, and implements the sequence sub-interleaving operation of the original information sequence, the original information coding sequence and the inner interleaved sequence coding sequence by multiplexing the sequence sub-interleaving unit.

[0049] like Figure 1 As shown, the encoding module includes a data allocation unit, an intra-sequence interleaving unit, a sequence sub-interleaving unit, a sub-encoder and a data temporary storage unit. The data temporary storage unit is connected to the data allocation unit, the intra-sequence interleaving unit and the sequence sub-interleaving unit. The data allocation unit and the intra-sequence interleaving unit are also connected to the sub-encoder.

[0050] The following is a detailed description of each part of the CTC encoder.

[0051] The data temporary storage unit is divided into 7 storage blocks according to the type of information stored, which are used to store the original information sequence, the interleaving address within the sequence, the sub-interleaving address of the sequence, the intermediate result of the encoding and the sub-interleaving result. The original information sequence and configuration information are repeatedly stored in the first and second storage blocks (the original information sequence is divided into A and B according to parity, that is, (A0, B0, A1, B1, ..., An, Bn) to realize that when the sequence sub-interleaving unit is occupied for encoding the original information sequence in the first storage block, the second storage block is used to read in sequence according to the sub-interleaving address sequence to achieve conflict-free memory access; the interleaving address within the sequence is stored in the third storage block; the sequence sub-interleaving address is stored in the fourth storage block; the encoding intermediate result is stored in the fifth and sixth storage blocks to realize that the sub-interleaving of Y1 and Y2 or W1 and W2 can be performed simultaneously by reading the sub-interleaving address once to achieve conflict-free memory access, and the sub-interleaving result is stored in the seventh storage block, wherein the actual coding sequence of the interleaving sequence in the original information, that is, the check bit 1, is composed of Y1 and W1, and the actual coding sequence of the interleaving sequence in the original information, that is, the check bit 2, is composed of Y2 and W2.

[0052] The data allocation unit is used to read the original information sequence, i.e., the source data, output in parallel from the data temporary storage unit; according to the output signal of the precoding unit or the actual coding unit of the sub-encoder, the parallel sequence is correspondingly changed to output only two bits of information (A, B) at a time, and output serially to the precoding unit or the actual coding unit.

[0053] The intra-sequence interleaving unit is used to read the intra-sequence interleaving address of the data temporary storage unit, and read a new sequence from the original information sequence in the data temporary storage unit according to this address as the inner interleaving sequence of the original information. The control unit controls the obtained N double-bit information to be sent sequentially to the precoding unit or the actual coding unit.

[0054] The sequence sub-interleaving unit is used to read the sequence sub-interleaving address of the data temporary storage unit, and read out a new sequence according to this address from the original information sequence or the actual encoding intermediate result sequence in the data temporary storage unit. If it is read from the original information sequence, no additional operation is required; if it is read from the encoding intermediate result sequence, it is necessary to perform inner interleaving between the actual encoding sequence Y1 of the original information and the actual encoder sequence Y2 of the interleaved sequence within the original information, and inner interleaving between the actual encoding sequence W1 of the original information and the actual encoder sequence W2 of the interleaved sequence within the original information.

[0055] The sub-encoder includes a pre-encoding unit and an actual encoding unit, the pre-encoding unit is connected to the actual encoding unit, and the pre-encoding unit sends a loop state to the actual encoding unit. The pre-encoding unit and the actual encoding unit of the sub-encoder are both connected to the data allocation unit and the intra-sequence interleaving unit.

[0056] The precoding unit first performs precoding of the original information sequence, and after completion, continues to perform precoding operations on the inner interleaved sequence according to the signal output by the inner interleaving unit.

[0057] The actual encoding unit first performs actual encoding of the original information sequence according to the cyclic state obtained by precoding and the output of the data allocation unit. After completion, the actual encoding operation of the inner interleaved sequence is continued according to the cyclic state obtained by precoding and the signal output by the sequence inner interleaving unit.

[0058] The specific operation process of the precoding unit in this embodiment is as follows:

[0059] S101: Initialize three registers in the precoding unit to all zeros.

[0060] S102: N two-bit information is sequentially sent to the precoding unit. Sequential sending means sending (A0, B0) at time t0, sending (A1, B1) at time t1, and so on. At the same time, logical operations are performed internally to update the status of the three internal registers. The specific logical operations are shown below.

[0061]

[0062] Among them, (A, B) is the double-bit information input by the precoding unit, that is, the information input into the precoding unit at the same time, S11, S12, S13 are three registers inside the precoding unit, S11 0 ,S12 0 ,S13 0 Indicates the register status of the precoding register at the current moment, S11 1 ,S12 1 ,S13 1 Indicates the register state of the precoding register at the next moment.

[0063] S103: After completing the input of the double-bit information, the cycle state Sc is calculated by looking up the table according to the final values ​​of the three registers of the precoding unit. The corresponding relationship between the final values ​​of the three registers and the cycle state Sc is shown in Table 1.

[0064] Table 1

[0065]

[0066] If there are 48 double-bit information sent to the precoding unit, then N = 48. After the precoding is completed, the final value of its register is (0, 1, 0). After calculation, mod (N, 7) = 6. The horizontal coordinate in the corresponding table is (0, 1, 0) and the vertical coordinate is 6. The table shows that Sc = (1, 1, 0).

[0067] In this embodiment, the specific operation process of the actual encoding unit is as follows:

[0068] S201: Initialize the S21, S22 and S23 registers in the actual encoding unit according to the loop state Sc obtained by the pre-encoding unit;

[0069] S202: N two-bit information is sequentially sent to the actual encoding unit, and a logic operation is performed internally to update the register state, and finally return to the loop state Sc. The specific logic operation is as follows.

[0070]

[0071] Among them, (A, B) is the double-bit information input by the actual encoding unit, which is consistent with the input information (A, B) of the pre-coding unit. During the operation, (A, B) is first input to the pre-coding unit for pre-coding, and then (A, B) is re-input into the actual encoding unit for actual encoding. S21, S22, and S23 are three registers inside the pre-coding unit. S21 0 ,S22 0 ,S23 0 Indicates the register status of the precoding register at the current moment, S21 1 ,S22 1 ,S23 1 Indicates the register state of the precoding register at the next moment.

[0072] S203: Calculate and obtain the check bit (Y, W) of the actual coding unit.

[0073] Among them, (Y, W) is the double-bit information output by the actual coding unit, that is, the output of the actual coding unit at the same time.

[0074] The encoder performs inner interleaving and sub-interleaving operations in the algorithm by externally inputting the inner interleaving address of the sequence and the sub-interleaving address of the sequence, thereby reducing the internal complex calculations of the CTC encoder. Most of the operations are addition operations, and no multiplier is required for calculation. While ensuring performance, it has low computational complexity and low hardware overhead.

[0075] The CTC encoder based on pipeline structure described in this example has a specific implementation flow chart as shown in the following figure: Figure 3 As shown, the specific steps are as follows, where the CTC encoder algorithm implementation flow chart is as follows Figure 2 shown.

[0076] Step 1: Encoder initialization;

[0077] The control unit reads the configuration information stored in the data temporary storage unit, wherein the configuration information includes the sequence logarithm N and the number of encodings n. The configuration information is transmitted to the control unit. The sequence logarithm N in the configuration parameter represents one-half of the length of each encoding code. The number of encodings n in the configuration parameter represents the number of encodings to be performed for the length of the input original information sequence, which is determined according to the size of the storage module and cannot exceed the storage upper limit.

[0078] Step 2: original information sequence precoding and sequence sub-interleaving;

[0079] Step 2-1: Precoding of original information sequence:

[0080] The control module calls the data allocation unit to read the original information sequence in the first storage block in the data temporary storage unit, and transmits N double-bit information (A1, B1) to the precoding unit for precoding operation to obtain the cyclic state Sc1;

[0081] Step 2-2: Sequence sub-interleaving operation:

[0082] While the original information sequence is pre-coded, the control module enables the sequence sub-interleaving unit to read the sequence sub-interleaving address saddr in the data temporary storage unit. After receiving the sequence sub-interleaving address, the sequence sub-interleaving unit reads the original information sequence and the inner interleaved coding sequence in the second storage block in the data temporary storage unit according to the address, and transfers the obtained N double-bit information sequences (As, Bs) into the sequence sub-interleaving result part in the data temporary storage unit for storage, that is, stores them in the seventh storage block.

[0083] Step 3: Encoding of the original information sequence and precoding of the inner interleaved sequence;

[0084] Step 3-1: Encoding of the original information sequence:

[0085] The actual encoding unit of the sub-encoder performs actual encoding operation according to the loop state Sc1 received from the pre-encoding unit, and stores the N two-bit information sequences (Y1, W1) of the encoding result into the encoding intermediate result part in the data temporary storage unit, that is, stored in the fifth storage block of the data temporary storage unit;

[0086] Step 3-2: Precoding of inner interleaved sequence:

[0087] While precoding the original information sequence, a pipeline structure is used. The controller enables the intra-sequence interleaving unit to read the intra-sequence interleaving address iaddr in the data temporary storage unit. After receiving the intra-sequence interleaving address iaddr, the intra-sequence interleaving unit reads the original information sequence in the data temporary storage unit according to this address, and passes the obtained N double-bit information sequences (Ai1, Bi1) into the precoding unit for precoding to obtain the cyclic state Sc2.

[0088] This embodiment adopts a pipeline structured sub-encoder to pre-encode the inner interleaved sequence while encoding the original information sequence, thereby reducing the encoding operation cycle and improving the algorithm efficiency and hardware utilization.

[0089] Step 4: Actual encoding of the inner interleaved sequence;

[0090] The control module enables the intra-sequence interleaving unit to read the intra-sequence interleaving address iaddr in the data temporary storage unit. After receiving the intra-sequence interleaving address, the intra-sequence interleaving unit reads the original information sequence in the data temporary storage unit according to the address, and then transmits the N double-bit information (Ai2, Bi2) to the actual encoding unit. At the same time, the pre-coding unit transmits the loop state Sc2 to the actual encoding unit for actual encoding, and then stores the actual encoding result (Y2, W2) of the inner interleaved sequence into the encoding intermediate result part in the data temporary storage unit, that is, stored in the sixth storage block of the data temporary storage unit;

[0091] Step 5: sub-interleaving of the original information coding sequence and sub-interleaving of the inner interleaved coding sequence;

[0092] The control module enables the sequence sub-interleaving unit to read the sequence sub-interleaving address saddr in the data temporary storage unit. After receiving the sequence sub-interleaving address, the sequence sub-interleaving unit reads the original information coding sequence (Y1, W1) and the inner interleaving coding sequence (Y2, W2) of the encoding intermediate result in the data temporary storage unit according to the address, and then performs inner interleaving on the obtained sub-interleaving sequence (Y1s, W1s) of the original information coding sequence and the sub-interleaving sequence (Y2s, W2s) of the inner interleaving coding sequence to obtain the final sequence (X1, X2) corresponding to the result of sub-interleaving and inner interleaving of Y1 and Y2 respectively, and (X3, X4) corresponding to the result of sub-interleaving and inner interleaving of W1 and W2 respectively, and the sub-interleaving result part in the data temporary storage unit is stored, that is, stored in the seventh storage block of the data temporary storage unit.

[0093] The present invention multiplexes sequence sub-interleaving units during encoding operations, and sequentially performs sequence sub-interleaving on original information sequences A and B with original information sequence coding sequences Y1, W1 and inner interleaving sequence coding sequences Y2, W2 by multiplexing sequence sub-interleaving units, thereby improving hardware utilization.

[0094] In summary, the CTC encoder based on the pipeline structure of this embodiment adopts a sub-encoder with a pipeline structure for encoding. It eliminates the internal complex calculations by receiving the internal interleaving address and sub-interleaving address input from the outside, and reuses the sequence sub-interleaving unit to perform sub-interleaving twice. It has low computational complexity, low hardware overhead and high hardware utilization, showing great potential for practical applications.

[0095] The above schematically describes the invention and its implementation methods, which is not restrictive. Without departing from the spirit or basic features of the invention, the invention can be implemented in other specific forms. What is shown in the accompanying drawings is only one of the implementation methods of the invention. The actual structure is not limited to this, and any figure mark in the claims should not limit the claims involved. Therefore, if a person of ordinary skill in the art is inspired by it, without departing from the purpose of the invention, a structural method and an embodiment similar to the technical solution are designed without creativity, which should all fall within the scope of protection of this patent. In addition, the word "including" does not exclude other elements or steps, and the word "one" before the element does not exclude the inclusion of "multiple" elements. The multiple elements stated in the product claim can also be implemented by one element through software or hardware. The words first, second, etc. are used to indicate names, and do not indicate any specific order.

Claims

1. A CTC encoder based on a pipeline structure, characterized in that: It includes a control module and an encoding module, the control module is connected to the encoding module; the control module includes a control unit; the encoding module includes a data allocation unit, an intra-sequence interleaving unit, a sequence sub-interleaving unit, a sub-encoder and a data temporary storage unit, the data temporary storage unit is connected to the data allocation unit, the intra-sequence interleaving unit and the sequence sub-interleaving unit, the data allocation unit and the intra-sequence interleaving unit are also connected to the sub-encoder; the sub-encoder includes a pre-encoding unit and an actual encoding unit; The pre-coding unit is connected to the actual coding unit, and the pre-coding unit sends a loop state to the actual coding unit; the pre-coding unit and the actual coding unit of the sub-encoder are both connected to the data allocation unit and are also connected to the intra-sequence interleaving unit; The precoding unit first precodes the original information sequence, and then continues to precode the inner interleaved sequence according to the signal output by the inner interleaving unit. The actual encoding unit first performs actual encoding of the original information sequence according to the cyclic state obtained by pre-coding and the output of the data allocation unit, and then continues to perform actual encoding operation of the inner interleaved sequence according to the cyclic state obtained by pre-coding and the signal output by the sequence inner interleaving unit. The control unit reads the configuration information including the number of sequence logarithms N and the number of encoding times n, controls the operation flow of the CTC encoder through logic, and implements the sequence sub-interleaving operation of the original information sequence, the original information coding sequence and the inner interleaved sequence coding sequence by multiplexing the sequence sub-interleaving unit; The sequence sub-interleaving unit is used to read the sequence sub-interleaving address of the data temporary storage unit, and read out a new sequence according to this address from the original information sequence or the actual encoding intermediate result sequence in the data temporary storage unit. If it is read from the original information sequence, no additional operation is required; if it is read from the encoding intermediate result sequence, it is necessary to perform inner interleaving between the actual encoding sequence Y1 of the original information and the actual encoder sequence Y2 of the interleaved sequence within the original information, and inner interleaving between the actual encoding sequence W1 of the original information and the actual encoder sequence W2 of the interleaved sequence within the original information.

2. A CTC encoder based on a pipeline structure according to claim 1, characterized in that: The data temporary storage unit is divided into seven storage blocks according to the type of stored information, wherein the first and second storage blocks store the original information sequence and configuration information, the third storage block stores the interleaved address within the sequence, the fourth storage block stores the sequence sub-interleaved address, the fifth and sixth storage blocks store the encoding intermediate results, and the seventh storage block stores the sequence sub-interleaved results.

3. A CTC encoding method based on a pipeline structure, characterized in that: Using a CTC encoder based on a pipeline structure as described in claim 1 or 2, the processing flow includes the following steps: Step 1: Initialize the encoder, and the control module reads the configuration information stored in the data temporary storage unit; Step 2: The control module controls the data allocation unit to enable the precoding unit to precode the original information sequence to obtain the cyclic state Sc1, and the sequence sub-interleaving unit performs a sequence sub-interleaving operation on the original information sequence, and the sequence sub-interleaving operation result (As, Bs) is stored in the data temporary storage unit; Step 3: The pre-coding unit inputs the cyclic state Sc1 into the actual coding unit for actual coding, and the actual coding unit operation result (Y1, W1) is stored in the data temporary storage unit as the coding intermediate result; the intra-sequence interleaving unit inputs the sequence information read according to the intra-sequence interleaving address to the pre-coding unit for pre-coding to obtain the cyclic state Sc2; Step 4: The pre-coding unit inputs the loop state Sc2 into the actual coding unit for actual coding, and the actual coding unit operation result (Y2, W2) is stored in the data temporary storage unit as the coding intermediate result; Step 5: The sequence sub-interleaving unit reads the intermediate coding results (Y1, W1) and (Y2, W2) in the data temporary storage unit, and then performs inner interleaving on the sub-interleaved sequence (Y1s, W1s) of the original information coding sequence and the sub-interleaved sequence (Y2s, W2s) of the inner interleaved coding sequence, and stores the calculation results (X1, X2) and (X3, X4) into the data temporary storage unit, where (X1, X2) corresponds to the result of sub-interleaving Y1 and Y2 first and then inner interleaving, and (X3, X4) corresponds to the result of sub-interleaving W1 and W2 first and then inner interleaving.

4. The CTC encoding method based on pipeline structure according to claim 3, characterized in that: The intra-sequence interleaving unit reads the sequence corresponding to the intra-sequence interleaving address from the original information sequence in the data temporary storage unit, and sends the read sequence data as the intra-sequence interleaving sequence of the original information sequence to the sub-encoder.

5. The CTC encoding method based on pipeline structure according to claim 4, characterized in that: The sequence sub-interleaving unit reads the sequence sub-interleaving address corresponding to the original information sequence or the encoding intermediate result in the data temporary storage unit, and performs inner interleaving again if the read sequence is the encoding intermediate result.

6. The CTC encoding method based on pipeline structure according to claim 3, characterized in that: When the precoding unit operates, the register of the precoding unit is first initialized to zero, the information sequence is sequentially input to the precoding unit, the register state of the precoding unit is updated, and the cycle state Sc is calculated according to the final value of the register of the precoding unit.

7. The CTC encoding method based on pipeline structure according to claim 6, characterized in that: When the actual coding unit operates, the register inside the actual coding unit is first initialized according to the loop state Sc calculated by the pre-coding unit; the information sequence is sequentially input to the actual coding unit, the register state of the actual coding unit is updated, and the actual coding operation result is obtained.

8. The CTC encoding method based on pipeline structure according to claim 7, characterized in that: The precoding unit starts to precode the inner interleaved sequence when the actual coding unit actually codes the original information sequence.

9. The CTC encoding method based on pipeline structure according to claim 3, characterized in that: The configuration information read when the encoder is initialized includes the number of sequence pairs and the number of encodings.

10. The CTC encoding method based on pipeline structure according to claim 3, characterized in that: The data distribution unit reads the original information sequence from the data temporary storage unit and sends it to the sub-encoder.

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