Functional test circuit and test method of I2S interface

Abstract

The present invention discloses a functional test circuit and a test method of an I2S interface, wherein the test circuit connects the I2S protocol signal interface of an I2SO INTF module and an I2SIN INTF module inside a chip, wherein the signal interface includes a bit clock signal interface, a left and right channel selection signal interface, and an input / output signal interface. Meanwhile, a data selector is provided between the I2SO INTF module and the I2SIN INTF module to control the chip to enter a self-test mode or a normal mode. The test method of the present invention is simple and fast, can ensure correct functions, has a short cycle, a high accuracy rate, and does not require an external verification board, thereby saving verification resources.

Description

Technical Field

[0001] The present invention relates to the field of audio chip function testing, and in particular to a function testing circuit and a testing method for an I2S interface. Background Art

[0002] I2S (Inter-IC Sound) protocol is a bus standard developed by Philips for audio data transmission between digital audio devices. It is mainly used for transmission between ICs, such as audio codec and DSP or digital filter. Generally, the I2S interface circuit design is verified by FPGA external audio daughter board verification or testchip external chip verification to ensure that the design can be applied normally, but this method requires additional verification resources and a long verification cycle. Summary of the invention

[0003] To solve the above problems, the present invention provides a functional test circuit and test method of an I2S interface, which greatly improves the simplicity and test efficiency of the I2S interface test method. The specific technical solutions of the present invention are as follows:

[0004] A functional test circuit of an I2S interface comprises a PDMA module, an I2SO AFIFO module, an I2SINAFIFO module, an I2SO INTF module, an I2SIN INTF module, a data selector, a signal switch and two memories, MEM1 and MEM2, wherein the PDMA module is connected with the I2SO AFIFO module, the I2SIN AFIFO module, the MEM1 memory and the MEM2 memory, and is used for transmitting data of the MEM1 memory to the I2SO AFIFO module and transmitting data of the I2SIN AFIFO module to the MEM2 memory; the I2SO AFIFO module is also connected with the I2SO INTF module, and the I2SIN AFIFO module is also connected with the I2SIN INTF module; the I2SO AFIFO module and the I2SIN AFIFO module are asynchronous FIFOs, and are used for data caching and asynchronous processing of APB bus clock and chip working clock; the I2SO INTF module is used for parallel-to-serial conversion processing of data, and the I2SIN INTF module is used for serial-to-parallel conversion processing of data; the data selector is arranged on the I2SO INTF module and I2SIN INTF module are used to control the chip to enter self-test mode or normal mode; the signal switch is connected to the data selector, which is used to control the data selector to receive the output data of the I2SO INTF module or receive external input data to switch the working mode of the chip. The test circuit of the present invention completes the signal connection between the I2SO INTF module and the I2SININTF module inside the chip, and designs a data selector and cooperates with the software program to complete the internal self-test of the I2S interface circuit. This test method is simple and fast, can ensure the correct function, short cycle, high accuracy, and no external verification board is required, saving verification resources.

[0005] Furthermore, the I2S protocol signal interfaces of the I2SO INTF module and the I2SIN INTF module are connected inside the chip, and the signal interface includes a bit clock signal interface, a left and right channel selection signal interface, and an input and output signal interface. Connecting the I2SO INTF module and the I2SIN INTF module can form a test loop for the signal inside the chip, so as to complete the test of the I2S interface circuit simply and quickly.

[0006] Furthermore, the signal switch is a register of the chip, and the configuration information of the register can enable the data selector to switch the working mode of the chip. Using the register of the chip as the signal switch simplifies the circuit design and facilitates the control of the chip to switch the use mode.

[0007] Furthermore, the data selector has four interfaces, wherein the data input interface of the data selector is connected to the I2SO INTF module and the external device respectively, the data output interface is connected to the I2SIN INTF module, and the data selection switch interface is connected to the signal switch. The design of the data selector facilitates the chip to switch between the self-test mode and the normal mode.

[0008] Furthermore, the I2SO AFIFO module includes a WDATA register for checking whether data enters the I2SO AFIFO module. The address of the WDATA register is a fixed address for caching data and serves as a target address for writing data by the PDMA module.

[0009] Furthermore, the I2SINAFIFO module includes an RDATA register for checking whether data is read out from the I2SINAFIFO module. The address of the RDATA register is a fixed address of cached data and serves as a source address for the PDMA module to read out data.

[0010] A functional test method for an I2S interface comprises the following steps: S1, a chip transmits configuration information of a signal switch to a data selector and determines the working mode of the chip. If it is a normal mode, the chip receives external input data for processing and outputs. If it is a self-test mode, the chip enters step S2; S2, the chip sends parallel data in a MEM1 memory to an I2SO AFIFO module for buffering through a PDMA module; S3, the chip sends the buffered data in the I2SO AFIFO module to an I2SO INTF module for conversion into serial data; S4, the chip sends the serial data in the I2SO INTF module to an I2SIN INTF module and converts it into parallel data; S5, the chip sends the parallel data to an I2SIN AFIFO module for buffering, and then sends it to a MEM2 memory through a PDAM module; S6, the chip compares the data in the MEM1 memory and the MEM2 memory. If they are the same, the chip outputs PASS information; if they are different, the chip outputs ERROR information. The present invention completes the signal connection between the I2SOINTF module and the I2SIN INTF module inside the chip, and designs a data selector and cooperates with the software program to complete the internal self-test of the I2S interface circuit. This test method is simple and fast, can ensure the correct function, has a short cycle, a high accuracy, and does not require an external verification board, saving verification resources.

[0011] Furthermore, in the step S1, the method for determining the working mode of the chip is to compare the configuration information input by the user with the preset information pre-stored in the data selector to obtain the working mode of the chip.

[0012] Furthermore, in the steps S2 and S5, the PDMA module transfers the parallel data in the MEM1 memory to the I2SO AFIFO module and transfers the parallel data in the I2SIN AFIFO module to the MEM2 memory via the APB bus. The APB bus provides a low-power interface, reduces the complexity of the interface, and saves the time required for testing.

[0013] Furthermore, in the steps S3 and S4, the mutual conversion between serial data and parallel data is completed under the clock signal of the I2S protocol, and the clock signal includes a bit clock signal and a left and right channel selection signal.

[0014] Further, the step S4 specifically includes the following steps: S41, the chip performs I2S protocol docking of the I2SO INTF module and the I2SIN INTF module through the bit clock signal and the left and right channel selection signal; S42, the chip sends data to the I2SIN INTF module through the output signal interface of the I2SO INTF module; S43, the chip receives data through the input signal interface of the I2SIN INTF module; S44, the chip performs serial-to-parallel conversion processing on the data in the I2SIN INTF module through the bit clock signal and the left and right channel selection signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 The figure is a schematic diagram of a functional test circuit of an I2S interface according to an embodiment of the present invention.

[0016] Figure 2 The present invention is a flowchart of a method for testing the functionality of an I2S interface according to an embodiment of the present invention. DETAILED DESCRIPTION

[0017] The technical solutions in the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings in the embodiments of the present invention. It should be understood that the specific embodiments described below are only used to explain the present invention and are not used to limit the present invention.

[0018] In the following description, specific details are given to provide a thorough understanding of the embodiments. However, one of ordinary skill in the art will appreciate that the embodiments may be practiced without these specific details. For example, circuits may be shown in block diagrams so as not to obscure the embodiments in unnecessary detail. In other cases, well-known circuits, structures, and techniques may not be shown in detail in order not to obscure the embodiments.

[0019] like Figure 1As shown, a functional test circuit of an I2S interface includes a PDMA module (Programmable Direct Memory Access), which can transfer data within the system; an I2SO AFIFO module (Asynchronous First Input First Output), which is used to cache data; an I2SIN AFIFO module (Asynchronous FIFO memory of an I2S protocol input port), which is used to cache data; an I2SO INTF module (Interface, an I2S protocol output interface module), which is used for parallel-to-serial conversion of data; an I2SIN INTF module (I2S protocol input interface module), which is used for serial-to-parallel conversion of data; a data selector, which is used to switch the working mode of a chip; a signal switch, which is used to control the data selector to switch the working mode of the chip; and two memories, MEM1 (Memory1) and MEM2 (Memory2), which are used to store data before and after conversion for comparison. Wherein, the PDMA module is connected with the I2SO AFIFO module, the I2SIN AFIFO module, the MEM1 memory and the MEM2 memory, and is used for transferring data of the MEM1 memory to the I2SO AFIFO module and transferring data of the I2SIN AFIFO module to the MEM2 memory; the I2SO AFIFO module is also connected with the I2SO INTF module, and the I2SIN AFIFO module is also connected with the I2SIN INTF module; the I2SO AFIFO module and the I2SIN AFIFO module are asynchronous FIFOs, and are used for data caching and asynchronous processing of the APB bus clock and the chip working clock; the data selector is arranged between the I2SO INTF module and the I2SIN INTF module, and is used for controlling the chip to enter the self-test mode or the normal mode; the signal switch is connected with the data selector, and is used for controlling the data selector to receive the output data of the I2SO INTF module or receive the external input data to switch the working mode of the chip. The test circuit of the present invention completes the signal connection between the I2SO INTF module and the I2SININTF module inside the chip, and designs a data selector and cooperates with the software program to complete the internal self-test of the I2S interface circuit. This test method is simple and fast, can ensure the correct function, has a short cycle, a high accuracy, and does not require an external verification board, saving verification resources.

[0020] As one of the implementation modes, the I2S protocol signal interface of the I2SO INTF module and the I2SIN INTF module is connected inside the chip, and the signal interface includes a bit clock signal interface, a left and right channel selection signal interface and an input and output signal interface. The I2SO INTF module and the I2SIN INTF module are connected inside the chip to form an internal test loop to simply and quickly complete the test of the I2S interface circuit. A data selector is set between the I2SO INTF module and the I2SIN INTF module to realize the data exchange between the I2SO INTF module and the I2SIN INTF module. The data selector has 4 interfaces, wherein the data input interface of the data selector is respectively connected to the I2SO INTF module and the external device, the data output interface is connected to the I2SIN INTF module, and the data selection switch interface is connected to the signal switch. The signal switch is a register of the chip, and the data selector can switch the working mode of the chip through the configuration information of the register. For example, when the signal switch is set to 1, the chip enters the self-test mode, and the signal flows from the I2SO INTF module to the I2SIN INTF module through the data selector to complete the internal circuit test of the chip. In normal mode, the I2SIN INTF module is connected to an analog-to-digital converter ADC and a microphone to complete the input of external audio signals, and the I2SO INTF module is connected to a digital-to-analog converter DAC and a power amplifier to complete the output of audio signals. Through this external verification daughter board method, the I2S interface circuit design can also be tested. Alternatively, the I2S protocol signal interface of the I2SO INTF module and the I2SIN INTF module can be connected and tested by jumper connection. However, this requires the tester to manually find the signal interface of the I2S protocol, and this test is based on the design being completed to the testchip stage, and the cycle is very long.

[0021] As one implementation mode, the I2SO AFIFO module includes a WDATA register, which is used to check whether there is data entering the I2SO AFIFO module, and the address of the WDATA register is a fixed address of the cached data, which is used as the target address of the PDMA module to write data. The I2SIN AFIFO module includes an RDATA register, which is used to check whether there is data read out from the I2SIN AFIFO module, and the address of the RDATA register is a fixed address of the cached data, which is used as the source address of the PDMA module to read out data.

[0022] like Figure 2As shown, a functional test method of an I2S interface comprises the following steps: S1, the chip transmits the configuration information of the signal switch to the data selector and judges the working mode of the chip. If it is in the normal mode, the chip receives the external input data for processing and completes the output. If it is in the self-test mode, it enters step S2; S2, the chip sends the parallel data in the MEM1 memory to the I2SO AFIFO module for buffering through the PDMA module; S3, the chip sends the data buffered in the I2SO AFIFO module to the I2SO INTF module for conversion into serial data; S4, the chip sends the serial data in the I2SO INTF module to the I2SIN INTF module and converts it into parallel data; S5, the chip sends the parallel data to the I2SIN AFIFO module for buffering, and then sends it to the MEM2 memory through the PDAM module; S6, the chip compares the data in the MEM1 memory and the MEM2 memory. If they are the same, the chip outputs the PASS information, and if they are different, the chip outputs the ERROR information. The present invention completes the signal connection of I2SO INTF module and I2SIN INTF module inside the chip, designs a data selector and cooperates with software program to complete the internal self-test of I2S interface circuit, this test mode is simple and fast, can ensure the correct function, short cycle, high accuracy, and no external verification board is needed, saving verification resources. In order to enable the chip to switch between self-test mode and normal mode, a data selector and a signal switch are set between I2SO INTF module and I2SIN INTF module, and the chip reads the configuration information input by the user to switch the working mode. If the signal switch is set to 1, the self-test of I2S interface is performed using the method described in the present embodiment, and if the signal switch is set to 0, the chip can normally receive external signals and output signals to the outside. Under normal mode, the chip can also be tested by an external test sub-board, such as an FPGA external audio sub-board or an audio codec chip, etc. This method belongs to the prior art and is not repeated here.

[0023] As one of the embodiments, in the steps S3 and S4, the mutual conversion between serial data and parallel data is completed under the clock signal of the I2S protocol, and the clock signal includes a bit clock signal and a left and right channel selection signal. The step S4 specifically includes the following steps: S41, the chip performs I2S protocol docking of the I2SO INTF module and the I2SIN INTF module through the bit clock signal and the left and right channel selection signal; S42, the chip sends data to the I2SIN INTF module through the output signal interface of the I2SO INTF module; S43, the chip receives data through the input signal interface of the I2SIN INTF module; S44, the chip performs serial-to-parallel conversion processing on the data in the I2SIN INTF module through the bit clock signal and the left and right channel selection signal. There are many methods for serial-to-parallel conversion. According to the order and quantity requirements of the data, registers, dual-port RAM, Dual RAM, SRAM, SDRAM, FIFO, etc. can be selected for implementation. For designs with relatively small numbers, shift register design can be adopted. The serial-to-parallel conversion of this embodiment is realized on the basis of the shift register, and the input serial data is "assembled" into new parallel data in the form of 24 bits per group. Specifically, the input bit stream is sent to the shift register bit by bit, and then the serial-to-parallel converter reads the data at the output end of the shift register once every 24 clock cycles and outputs the data in the form of parallel 24 bits.

[0024] As one of the embodiments, in the steps S2 and S5, the PDMA module transfers the parallel data in the MEM1 memory to the I2SO AFIFO module and transfers the parallel data in the I2SIN AFIFO module to the MEM2 memory through the APB bus. The APB bus provides a low-power interface, reduces the complexity of the interface, and saves the time required for testing. The PDMA module needs to transfer the data in the MEM1 memory to the I2SO AFIFO module. Therefore, for the PDMA module, the source address (MEM1 memory) can be set arbitrarily by the software, but the destination address must be fixed, that is, the I2SO AFIFO module needs to have a register. It has two uses. One is that the software checks the value of this register in real time to see if there is data entering the I2SO AFIFO module during the test, and the other is that as the target address of the write data of the PDMA module, the data in the MEM1 memory is transferred to the register address corresponding to the write data in the I2SO AFIFO module (such as 0x400B_8024 is the I2SO AFIFO WDATA register address). Then, the hardware design circuit of the chip will transfer the data in the I2SO AFIFO module to the I2SO INTF module in real time. Similarly, the I2SIN AFIFO module also needs a register to store the read data of the I2SIN AFIFO module. There are two functions. One is to use the software to check the value of this register in real time to see if there is data read from the I2SIN AFIFO module during the test. The second is to serve as the source address of the PDMA module to read the data and transfer the data in the source address (such as 0x400B_8024 is the I2SIN AFIFO RDATA register address) to the address space corresponding to the MEM2 memory opened by the software.

[0025] In the embodiments provided by the present invention, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the scheme of this embodiment.

[0026] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A functional test circuit for an I2S interface, characterized in that: The circuit includes a PDMA module, an I2SO AFIFO module, an I2SIN AFIFO module, an I2SO INTF module, an I2SIN INTF module, a data selector, a signal switch and two memories MEM1 and MEM2, wherein: The PDMA module is connected to the I2SO AFIFO module, the I2SIN AFIFO module, the MEM1 memory and the MEM2 memory, and is used to transfer data from the MEM1 memory to the I2SO AFIFO module and to transfer data from the I2SIN AFIFO module to the MEM2 memory; The I2SO AFIFO module is also connected to the I2SO INTF module, and the I2SIN AFIFO module is also connected to the I2SIN INTF module; the I2SO AFIFO module and the I2SIN AFIFO module are asynchronous FIFOs, which are used for data caching and asynchronous processing of the APB bus clock and the chip working clock; The I2SO INTF module is used for parallel-to-serial conversion of data, and the I2SIN INTF module is used for serial-to-parallel conversion of data; The data selector is arranged between the I2SO INTF module and the I2SIN INTF module, and is used to control the chip to enter the self-test mode or the normal mode; The signal switch is connected to the data selector and is used to control the data selector to receive output data of the I2SO INTF module or receive external input data to switch the working mode of the chip.

2. A functional test circuit of an I2S interface according to claim 1, characterized in that: The I2S protocol signal interfaces of the I2SO INTF module and the I2SIN INTF module are connected inside the chip, and the signal interface includes a bit clock signal interface, a left and right channel selection signal interface, and an input and output signal interface.

3. A functional test circuit of an I2S interface according to claim 1, characterized in that: The signal switch is a register of the chip, and the configuration information of the register can enable the data selector to switch the working mode of the chip.

4. The functional test circuit of the I2S interface according to claim 1, characterized in that: The data selector has four interfaces, wherein the data input interface of the data selector is connected to the I2SO INTF module and the external device respectively, the data output interface is connected to the I2SIN INTF module, and the data selection switch interface is connected to the signal switch.

5. A functional test circuit of an I2S interface according to claim 1, characterized in that: The I2SO AFIFO module includes a WDATA register for checking whether data enters the I2SO AFIFO module. The address of the WDATA register is a fixed address for caching data and serves as a target address for writing data by the PDMA module.

6. The functional test circuit of the I2S interface according to claim 1, characterized in that: The I2SIN AFIFO module includes an RDATA register for checking whether there is data read out from the I2SIN AFIFO module. The address of the RDATA register is a fixed address of cached data and serves as a source address for the PDMA module to read out data.

7. A functional testing method for an I2S interface, characterized in that: The method comprises the following steps: S1, the chip transmits the configuration information of the signal switch to the data selector and determines the working mode of the chip. If it is in normal mode, the chip receives external input data for processing and completes the output. If it is in self-test mode, it enters step S2; S2, the chip sends the parallel data in the MEM1 memory to the I2SO AFIFO module for buffering through the PDMA module; S3, the chip sends the data cached in the I2SO AFIFO module to the I2SO INTF module and converts it into serial data; S4, the chip sends the serial data in the I2SO INTF module to the I2SIN INTF module and converts it into parallel data; S5, the chip sends the parallel data to the I2SIN AFIFO module for buffering, and then sends it to the MEM2 memory through the PDAM module; S6, the chip compares the data in the MEM1 memory and the data in the MEM2 memory. If they are the same, a PASS message is output; if they are different, an ERROR message is output.

8. A functional testing method for an I2S interface according to claim 7, characterized in that: In the step S1, the method for determining the working mode of the chip is to compare the configuration information input by the user with the preset information pre-stored in the data selector to obtain the working mode of the chip.

9. A method for testing the function of an I2S interface according to claim 7, characterized in that: In the steps S2 and S5, the PDMA module transfers the parallel data in the MEM1 memory to the I2SO AFIFO module and transfers the parallel data in the I2SIN AFIFO module to the MEM2 memory through the APB bus.

10. A method for testing the function of an I2S interface according to claim 7, characterized in that: In the steps S3 and S4, the mutual conversion between serial data and parallel data is completed under the clock signal of the I2S protocol, and the clock signal includes a bit clock signal and a left and right channel selection signal.

11. A method for testing the function of an I2S interface according to claim 7, characterized in that: The step S4 specifically includes the following steps: S41, the chip performs I2S protocol docking of the I2SO INTF module and the I2SIN INTF module through the bit clock signal and the left and right channel selection signals; S42, the chip sends data to the I2SIN INTF module through the output signal interface of the I2SO INTF module; S43, the chip receives data through the input signal interface of the I2SIN INTF module; S44, the chip performs serial-to-parallel conversion processing on the data in the I2SIN INTF module through the bit clock signal and the left and right channel selection signals.

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