Display device and method for driving the same

Abstract

A display device and a method for driving the display device are provided. The display device includes a first display area, a second display area, a first back gate signal application line connected to a plurality of back gate electrodes of a plurality of pixels in the first display area, and a second back gate signal application line connected to a plurality of back gate electrodes of a plurality of pixels in the second display area; a back gate signal generator configured to generate a first back gate signal applied to a plurality of back gate electrodes of a plurality of pixels in the first display area and a second back gate signal applied to a plurality of back gate electrodes of a plurality of pixels in the second display area; a gate driver configured to output a gate signal; a data driver configured to output a data voltage; and a drive controller configured to control a drive timing, wherein the drive controller, the data driver, and the back gate signal generator form an integrated driver.

Description

Technical Field

[0001] Aspects of some exemplary embodiments of the inventive concepts relate to a display device and a method of driving the display device. Background Art

[0002] Typically, a display device includes a display panel and a display panel driver. The display panel includes a plurality of gate lines, a plurality of data lines, a plurality of emission lines, and a plurality of pixels. The display panel driver includes a gate driver, a data driver, an emission driver, and a drive controller. The gate driver outputs a gate signal to the gate line. The data driver outputs a data voltage to the data line. The emission driver outputs an emission signal to the emission line. The drive controller controls the gate driver, the data driver, and the emission driver.

[0003] A foldable display device has been developed by using a flexible display panel. The foldable display device may have at least two display areas. Multiple display areas may be formed in a single flexible display panel.

[0004] Depending on whether the display device is in a folded state or an unfolded state or a condition, various display areas among the plurality of display areas may be invalid or valid. When a display area is invalid, a black image may be displayed in the invalid area. Although a black image may be displayed in the invalid area, some power may still be consumed.

[0005] The above information disclosed in this Background section is only for enhancement of understanding of the background, and therefore, the information discussed in this Background section does not necessarily constitute prior art. Summary of the invention

[0006] Aspects of some exemplary embodiments of the present inventive concept relate to a display device and a method of driving the display device. For example, some exemplary embodiments of the present inventive concept relate to a foldable display device and a method of driving the display device.

[0007] Aspects of some exemplary embodiments of the inventive concept include a display device that may be capable of reducing power consumption.

[0008] Aspects of some exemplary embodiments of the present inventive concepts may also include a method of driving a display device.

[0009] According to some exemplary embodiments of the display device conceived according to the present invention, the display device includes a display panel, a back gate signal generator, a gate driver, a data driver and a drive controller. The display panel includes a first display area, a second display area, a first back gate signal application line connected to a plurality of back gate electrodes of a plurality of pixels in the first display area, and a second back gate signal application line connected to a plurality of back gate electrodes of a plurality of pixels in the second display area. The back gate signal generator is configured to generate a first back gate signal applied to a plurality of back gate electrodes of a plurality of pixels in the first display area and a second back gate signal applied to a plurality of back gate electrodes of a plurality of pixels in the second display area. The gate driver is configured to output a gate signal to a gate line of the display panel. The data driver is configured to output a data voltage to a data line of the display panel. The drive controller is configured to control the drive timing of the gate driver and the drive timing of the data driver. The drive controller, the data driver and the back gate signal generator form an integrated driver.

[0010] According to some exemplary embodiments, the integrated driver may include a back gate reference voltage generator and a first digital-to-analog converter, the back gate reference voltage generator being configured to generate a back gate reference voltage, and the first digital-to-analog converter being configured to convert a back gate digital signal received from a driving controller into a first back gate signal having an analog type and a second back gate signal having an analog type based on the back gate reference voltage.

[0011] According to some exemplary embodiments, the integrated driver may further include a gamma reference voltage generator configured to generate the gamma reference voltages, and a second digital-to-analog converter configured to convert the data signal received from the driving controller into a data voltage having an analog type.

[0012] According to some example embodiments, the first back gate signal and the second back gate signal may be adjusted in units of horizontal lines of input image data.

[0013] According to some exemplary embodiments, the integrated driver may include a reference voltage generator and a digital-to-analog converter, the reference voltage generator being configured to generate a back gate reference voltage and a gamma reference voltage, the digital-to-analog converter being configured to convert a back gate digital signal received from a driving controller into a first back gate signal having an analog type and a second back gate signal having an analog type based on the back gate reference voltage, and to convert a data signal received from the driving controller into a data voltage having an analog type.

[0014] According to some example embodiments, the first back gate signal and the second back gate signal may be adjusted in units of horizontal lines of input image data.

[0015] According to some exemplary embodiments, the integrated driver may include a gamma reference voltage generator configured to generate a gamma reference voltage. The data driver may be configured to convert a data signal into a data voltage based on the gamma reference voltage and output the data voltage to the display panel. The integrated driver may further include a voltage regulator configured to receive information about a level of the first back gate signal and a level of the second back gate signal and generate the first back gate signal and the second back gate signal.

[0016] According to some exemplary embodiments, the display device may further include a power supply voltage generator configured to generate a high power supply voltage and a low power supply voltage applied to pixels of the display panel. The power supply voltage generator may be formed independently of the voltage regulator.

[0017] According to some example embodiments, the first back gate signal and the second back gate signal may be adjusted in units of frames of input image data.

[0018] According to some example embodiments, the integrated driver may include an output pad configured to output the first back gate signal to the first back gate signal applying line and output the second back gate signal to the second back gate signal applying line.

[0019] According to some exemplary embodiments of the display device conceived according to the present invention, the display device includes a display panel, a gate driver, a data driver, a drive controller and a power supply voltage generator. The display panel includes a first display area, a second display area, a first back gate signal application line connected to a plurality of back gate electrodes of a plurality of pixels in the first display area, and a second back gate signal application line connected to a plurality of back gate electrodes of a plurality of pixels in the second display area. The gate driver is configured to output a gate signal to the gate line of the display panel. The data driver is configured to output a data voltage to the data line of the display panel. The drive controller is configured to control the drive timing of the gate driver and the drive timing of the data driver. The power supply voltage generator is configured to generate a first back gate signal applied to a plurality of back gate electrodes of a plurality of pixels in the first display area, a second back gate signal applied to a plurality of back gate electrodes of a plurality of pixels in the second display area, and a high power supply voltage and a low power supply voltage applied to the pixels of the display panel. The drive controller and the data driver form an integrated driver. The power supply voltage generator is formed independently of the integrated driver.

[0020] According to some example embodiments, the first back gate signal and the second back gate signal may be adjusted in units of frames of input image data.

[0021] According to some exemplary embodiments, the integrated driver may include a control pad, an input pad, and an output pad, the control pad being configured to output information about a level of a first back gate signal and a level of a second back gate signal to a power supply voltage generator, the input pad being configured to receive the first back gate signal and the second back gate signal from the power supply voltage generator, and the output pad being configured to output the first back gate signal to a first back gate signal applying line, and to output the second back gate signal to a second back gate signal applying line.

[0022] According to some exemplary embodiments of the display device according to the concept of the present invention, the display device includes a display panel, a power supply voltage generator, a gate driver and a data driver. The display panel includes a first display area, a second display area, a first back gate signal application line connected to a plurality of back gate electrodes of a plurality of pixels in the first display area, and a second back gate signal application line connected to a plurality of back gate electrodes of a plurality of pixels in the second display area. The power supply voltage generator is configured to generate a first back gate signal applied to the first back gate signal application line and a second back gate signal applied to the second back gate signal application line. The gate driver is configured to output a gate signal to the gate line of the display panel. The data driver is configured to output a data voltage to the data line of the display panel. The data driver is configured to output a black data voltage to the data line once when the display panel is folded. The second back gate signal increases from a normal level to an invalid level greater than the normal level, and when the display panel is folded and after the black data voltage is output once, at least one of the gate driver, the data driver and the emission driver does not output a drive signal to the second display area.

[0023] According to some exemplary embodiments, when the display panel maintains the folded state, the current of the pixel of the display panel may be sensed, and the data driver may be configured to output the black data voltage to the data line again when the sensed current does not maintain the black data voltage.

[0024] According to some example embodiments, the data driver may include a plurality of main buffers respectively connected to the plurality of data lines and auxiliary buffers commonly connected to the plurality of data lines.

[0025] According to some exemplary embodiments, the data driver may further include a plurality of switches. The plurality of switches may be configured to selectively connect one of the plurality of main buffers and the auxiliary buffer to the data line.

[0026] According to some exemplary embodiments, the data driver may be configured to output the black data voltage to the data line again by using an auxiliary buffer when the sensed current does not maintain the black data voltage.

[0027] According to some exemplary embodiments, when the display panel maintains a folded state, a current of a pixel of the display panel may be sensed, and the back gate signal generator may be configured to increase a second back gate signal when the sensed current does not maintain a black data voltage.

[0028] According to some exemplary embodiments, the data driver may be configured to output the black data voltage to the data line again when the second back gate signal increases and the increased second back gate signal exceeds the maximum back gate voltage.

[0029] According to some exemplary embodiments, when the display panel is unfolded from the folded state, the second back gate signal may be reduced from the inactive level to the normal level.

[0030] According to some exemplary embodiments of a method for driving a display device according to the concept of the present invention, the method includes outputting a first back gate signal to a first back gate signal application line connected to a plurality of back gate electrodes of a plurality of pixels in a first display area of ​​a display panel; outputting a second back gate signal to a second back gate signal application line connected to a plurality of back gate electrodes of a plurality of pixels in a second display area of ​​the display panel, outputting a gate signal to a gate line of the display panel, and outputting a data voltage to a data line of the display panel. The data driver is configured to output a black data voltage to the data line once when the display panel is folded. The second back gate signal increases from a normal level to an invalid level greater than the normal level, and when the display panel is folded and after outputting the black data voltage once, at least one of the gate driver, the data driver, and the emission driver does not output a drive signal to the second display area.

[0031] In a display device and a method of driving a display device according to some exemplary embodiments, an independent back gate signal may be applied to a first back gate electrode located in a first display area and a second back gate electrode located in a second display area, so that pixels in an invalid area may be controlled without emitting light. In addition, in a folded state of the display device, a gate driver may not output a gate signal to the invalid area, a data driver may not output a data voltage to the invalid area, and an emission driver may not output an emission signal to the invalid area. Therefore, the power consumption of the display device may be reduced.

[0032] In addition, in the folded state of the display panel, the current of the pixel may be sensed, and when the brightness of the pixel increases due to the leakage of the pixel current, the black data voltage may be output to the inactive area.

[0033] In addition, an auxiliary buffer commonly connected to the plurality of data lines may be used to output a black data voltage to an inactive area, so that the power consumption of the display device may be further reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The above and other features of the present inventive concept will become more apparent by describing in more detail aspects of some exemplary embodiments of the present inventive concept with reference to the accompanying drawings, in which:

[0035] Figure 1 is a perspective view showing a display device according to some exemplary embodiments of the inventive concept;

[0036] Figure 2 It is shown Figure 1 A plan view of a display device;

[0037] Figure 3 It is shown Figure 1 A block diagram of a display device;

[0038] Figure 4 It is shown Figure 3 A circuit diagram of a pixel of a display panel;

[0039] Figure 5 is shown applied to Figure 4 A timing diagram of an input signal of a pixel;

[0040] Figure 6 It is shown Figure 3 A conceptual diagram of a first display area, a second display area, a first back gate signal applying line, and a second back gate signal applying line of a display panel;

[0041] Fig. 7A is shown applied to Figure 3 A timing diagram of an input signal of a display panel;

[0042] Figure 7B is shown applied to Figure 3 A timing diagram of an input signal of a display panel;

[0043] Figure 7C is shown applied to Figure 3 A timing diagram of an input signal of a display panel;

[0044] Fig.7D is shown applied to Figure 3 A timing diagram of an input signal of a display panel;

[0045] Fig. 8A Is shown driving Figure 1 A flowchart of a method for displaying a device;

[0046] Figure 8B Is shown driving Figure 1 A flowchart of a method for displaying a device;

[0047] Fig. 9 It is shown Figure 1A conceptual diagram of a timing controller embedded data driver for a display device;

[0048] Fig.10 It is shown Fig. 9 A block diagram of a timing controller embedded data driver;

[0049] Fig.11 is a block diagram illustrating a timing controller embedded data driver of a display device according to some exemplary embodiments of the inventive concept;

[0050] Fig.12 is a block diagram illustrating a timing controller embedded data driver of a display device according to some exemplary embodiments of the inventive concept;

[0051] Fig.13 is a conceptual diagram illustrating a timing controller embedded data driver of a display device according to some exemplary embodiments of the inventive concept;

[0052] Fig.14 It is shown Fig.13 A block diagram of a timing controller embedded data driver;

[0053] Fig.15 is a perspective view showing a display device according to some exemplary embodiments of the inventive concept;

[0054] Fig.16 It is shown Fig.15 A plan view of a display device;

[0055] Fig.17 It is shown Fig.15 A conceptual diagram of a first display area, a second display area, a third display area, a first back gate signal applying line, a second back gate signal applying line and a third back gate signal applying line of a display panel;

[0056] Fig.18 is a flowchart illustrating a method of driving a display device according to some exemplary embodiments of the inventive concept;

[0057] Fig.19 is shown partially driven Fig.18 A conceptual diagram of a method for displaying a display panel of a display device;

[0058] Fig. 20 It is shown Fig.18 A circuit diagram of a data driver of a display device; and

[0059] Fig.21 is a flowchart illustrating a method of driving a display device according to some exemplary embodiments of the inventive concept. DETAILED DESCRIPTION

[0060] Hereinafter, aspects of some exemplary embodiments of the inventive concept will be explained in more detail with reference to the accompanying drawings.

[0061] Figure 1 2 is a perspective view illustrating a display device in a folded condition or state according to some exemplary embodiments of the inventive concept. Figure 2 It is to show the state or condition of being unfolded. Figure 1 A plan view of a display device.

[0062] Reference Figure 1 and Figure 2 The display device may include a flexible display panel. The display device may be a foldable display device. The display device may be foldable along a folding line FL.

[0063] The display device may include a first display area DA1 located at a first side of the folding line FL and a second display area DA2 located at a second side of the folding line FL.

[0064] When Figure 1 When the display device is folded as shown, the first display area DA1 may display an image, and the second display area DA2 may not display an image. Figure 1 When the display device is folded as shown, the second display area DA2 may display an image and the first display area DA1 may not display an image according to user settings. That is, according to some embodiments, when the display device is in a folded state or condition, one of the first display area DA1 and the second display area DA2 may be configured not to display an image according to a user-defined setting of the display device.

[0065] Figure 3 It is shown Figure 1 A block diagram of a display device.

[0066] Reference Figures 1 to 3 The display device includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, an emission driver 600, and a power supply voltage generator 700.

[0067] The display panel 100 has a display area displaying an image and a peripheral area adjacent to the display area.

[0068] The display panel 100 includes a plurality of groups of gate lines GWL, GIL and GBL, a plurality of data lines DL, a plurality of emission lines EL, and a plurality of pixels electrically connected to the plurality of groups of gate lines GWL, GIL and GBL, the plurality of data lines DL and the plurality of emission lines EL. The plurality of groups of gate lines GWL, GIL and GBL extend in a first direction D1, the plurality of data lines DL extend in a second direction D2 intersecting the first direction D1, and the plurality of emission lines EL extend in the first direction D1. Although Figure 3 A single data line DL, a single emission line EL, and a single set of a plurality of gate lines GWL, GIL, and GBL are illustrated, but embodiments of the present invention are not limited thereto, and the number of lines may vary according to the design and characteristics of the display panel 100 .

[0069] According to some exemplary embodiments, the display panel 100 may include a first display area DA1, a second display area DA2, a first back gate signal applying line connected to a back gate electrode of a pixel in the first display area DA1, and a second back gate signal applying line connected to a back gate electrode of a pixel in the second display area DA2.

[0070] The driving controller 200 receives input image data IMG and input control signal CONT from an external device or an external source. For example, the input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may include white image data. The input image data IMG may include magenta image data, cyan image data, and yellow image data. The input control signal CONT may include a main clock signal and a data enable signal. The input control signal CONT may further include a vertical synchronization signal and a horizontal synchronization signal.

[0071] The driving controller 200 generates a first control signal CONT1 , a second control signal CONT2 , a third control signal CONT3 , a fourth control signal CONT4 , a fifth control signal CONT5 , and a data signal DATA based on input image data IMG and an input control signal CONT.

[0072] The driving controller 200 generates a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT, and outputs the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0073] The driving controller 200 generates a second control signal CONT2 for controlling the operation of the data driver 500 based on the input control signal CONT, and outputs the second control signal CONT2 to the data driver 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0074] The driving controller 200 generates a data signal DATA based on the input image data IMG. The driving controller 200 outputs the data signal DATA to the data driver 500.

[0075] The driving controller 200 generates a third control signal CONT3 for controlling the operation of the gamma reference voltage generator 400 based on the input control signal CONT, and outputs the third control signal CONT3 to the gamma reference voltage generator 400 .

[0076] The driving controller 200 generates a fourth control signal CONT4 for controlling the operation of the emission driver 600 based on the input control signal CONT, and outputs the fourth control signal CONT4 to the emission driver 600 .

[0077] The driving controller 200 generates a fifth control signal CONT5 for controlling the operation of the power voltage generator 700 based on the input control signal CONT, and outputs the fifth control signal CONT5 to the power voltage generator 700 .

[0078] The gate driver 300 generates a plurality of gate signals for driving the plurality of gate lines GWL, GIL, and GBL in response to the first control signal CONT1 received from the driving controller 200. The gate driver 300 may sequentially output the plurality of gate signals to the plurality of gate lines GWL, GIL, and GBL. For example, the gate driver 300 may be installed in the peripheral area of ​​the display panel 100. For example, the gate driver 300 may be integrated in the peripheral area of ​​the display panel 100.

[0079] The gamma reference voltage generator 400 generates a gamma reference voltage VGREF in response to the third control signal CONT3 received from the driving controller 200. The gamma reference voltage generator 400 provides the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF has a value corresponding to a level of the data signal DATA.

[0080] According to some exemplary embodiments, the gamma reference voltage generator 400 may be located in the driving controller 200 or in the data driver 500 .

[0081] The data driver 500 receives the second control signal CONT2 and the data signal DATA from the driving controller 200 and receives the gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 converts the data signal DATA into a data voltage of an analog type by using the gamma reference voltage VGREF. The data driver 500 outputs the data voltage to the data line DL.

[0082] The emission driver 600 generates an emission signal to drive the emission line EL in response to the fourth control signal CONT4 received from the driving controller 200. The emission driver 600 may output the emission signal to the emission line EL.

[0083] The power supply voltage generator 700 may generate a first back gate signal BS1 applied to the first back gate signal applying line and a second back gate signal BS2 applied to the second back gate signal applying line in response to the fifth control signal CONT5 received from the driving controller 200. Hereinafter, according to some exemplary embodiments, the power supply voltage generator 700 may be referred to as a back gate signal generator and a voltage regulator.

[0084] In addition, the power voltage generator 700 may generate a high power voltage and a low power voltage of the organic light emitting element of the display panel 100 and output the high power voltage and the low power voltage to the display panel 100 .

[0085] Figure 4 It is shown Figure 3 1 is a circuit diagram of a pixel of the display panel 100. Figure 5 is shown applied to Figure 4 Timing diagram of the pixel input signal.

[0086] Reference Figures 1 to 5 The display panel 100 includes a plurality of pixels. Each pixel includes an organic light emitting element OLED.

[0087] The pixel receives the data writing gate signal GW, the data initialization gate signal GI, the organic light emitting element initialization gate signal GB, the data voltage VDATA and the emission signal EM, and the organic light emitting element OLED of the pixel emits light corresponding to the level of the data voltage VDATA to display an image.

[0088] At least one of the plurality of pixels may include first to seventh pixel switching elements T1 to T7 , a storage capacitor CST, and an organic light emitting element OLED.

[0089] The first pixel switching element T1 includes a control electrode connected to the first node N1, an input electrode connected to the second node N2, and an output electrode connected to the third node N3.

[0090] For example, the first pixel switch element T1 may be a P-type thin film transistor. The control electrode of the first pixel switch element T1 may be a gate electrode. The input electrode of the first pixel switch element T1 may be a source electrode. The output electrode of the first pixel switch element T1 may be a drain electrode.

[0091] According to some exemplary embodiments, the first pixel switching element T1 may further include a back gate electrode BML1 receiving the first back gate signal BS1 or the second back gate signal BS2. The first pixel switching element T1 may have a back gate structure. The pixel switching element of the back gate structure may include a gate electrode and an additional gate electrode (back gate electrode).

[0092] Although the first pixel switching element T1 further includes a back gate electrode BML1 according to some exemplary embodiments, embodiments according to the inventive concept are not limited thereto. At least one of the first to seventh pixel switching elements T1 to T7 may include a back gate electrode.

[0093] For example, when the pixel is located in the first display area DA1, the first back gate signal BS1 may be applied to the back gate electrode BML1 of the first pixel switching element T1. When the pixel is located in the second display area DA2, the second back gate signal BS2 may be applied to the back gate electrode BML1 of the first pixel switching element T1.

[0094] The second pixel switch element T2 includes a control electrode, an input electrode, and an output electrode. The control electrode receives a data write gate signal GW, the input electrode receives a data voltage VDATA, and the output electrode is connected to the second node N2.

[0095] For example, the second pixel switch element T2 may be a P-type thin film transistor. The control electrode of the second pixel switch element T2 may be a gate electrode. The input electrode of the second pixel switch element T2 may be a source electrode. The output electrode of the second pixel switch element T2 may be a drain electrode.

[0096] The third pixel switching element T3 includes a control electrode receiving the data write gate signal GW, an input electrode connected to the first node N1, and an output electrode connected to the third node N3.

[0097] For example, the third pixel switch element T3 may be a P-type thin film transistor. The control electrode of the third pixel switch element T3 may be a gate electrode. The input electrode of the third pixel switch element T3 may be a source electrode. The output electrode of the third pixel switch element T3 may be a drain electrode.

[0098] The fourth pixel switching element T4 includes a control electrode, an input electrode, and an output electrode. The control electrode receives the data initialization gate signal GI, the input electrode receives the initialization voltage VI, and the output electrode is connected to the first node N1.

[0099] For example, the fourth pixel switch element T4 may be a P-type thin film transistor. The control electrode of the fourth pixel switch element T4 may be a gate electrode. The input electrode of the fourth pixel switch element T4 may be a source electrode. The output electrode of the fourth pixel switch element T4 may be a drain electrode.

[0100] The fifth pixel switching element T5 includes a control electrode receiving the emission signal EM, an input electrode receiving the high power voltage ELVDD, and an output electrode connected to the second node N2.

[0101] For example, the fifth pixel switch element T5 may be a P-type thin film transistor. The control electrode of the fifth pixel switch element T5 may be a gate electrode. The input electrode of the fifth pixel switch element T5 may be a source electrode. The output electrode of the fifth pixel switch element T5 may be a drain electrode.

[0102] The sixth pixel switching element T6 includes a control electrode receiving the emission signal EM, an input electrode connected to the third node N3, and an output electrode connected to the anode electrode of the organic light emitting element OLED.

[0103] For example, the sixth pixel switch element T6 may be a P-type thin film transistor, the control electrode of the sixth pixel switch element T6 may be a gate electrode, the input electrode of the sixth pixel switch element T6 may be a source electrode, and the output electrode of the sixth pixel switch element T6 may be a drain electrode.

[0104] The seventh pixel switch element T7 includes a control electrode, an input electrode and an output electrode. The control electrode receives an organic light emitting element initialization gate signal GB, the input electrode receives an initialization voltage VI, and the output electrode is connected to the anode electrode of the organic light emitting element OLED.

[0105] For example, the seventh pixel switch element T7 may be a P-type thin film transistor, the control electrode of the seventh pixel switch element T7 may be a gate electrode, the input electrode of the seventh pixel switch element T7 may be a source electrode, and the output electrode of the seventh pixel switch element T7 may be a drain electrode.

[0106] The storage capacitor CST includes a first electrode receiving the high power voltage ELVDD and a second electrode connected to the first node N1.

[0107] The organic light emitting element OLED includes an anode electrode and a cathode electrode receiving a low power voltage ELVSS.

[0108] like Figure 5As shown in the figure, during the first duration DU1, the first node N1 and the storage capacitor CST are initialized in response to the data initialization gate signal GI. During the second duration DU2, the threshold voltage |VTH| of the first pixel switch element T1 is compensated, and in response to the data write gate signal GW, the data voltage VDATA compensated by the threshold voltage |VTH| is written to the first node N1. During the second duration DU2, in response to the organic light emitting element initialization gate signal GB, the anode electrode of the organic light emitting element OLED is initialized. During the third duration DU3, the organic light emitting element OLED emits light in response to the emission signal EM, so that the display panel 100 displays an image.

[0109] During the first duration DU1, the data initialization gate signal GI may have an effective level. For example, the effective level of the data initialization gate signal GI may be a low level. When the data initialization gate signal GI has an effective level, the fourth pixel switching element T4 is turned on so that the initialization voltage VI can be applied to the first node N1. The data initialization gate signal GI[N] of the current stage may be generated based on the scan signal SCAN[N-1] of the previous stage.

[0110] During the second duration DU2, the data write gate signal GW may have an effective level. For example, the effective level of the data write gate signal GW may be a low level. When the data write gate signal GW has an effective level, the second pixel switch element T2 and the third pixel switch element T3 are turned on. In addition, the first pixel switch element T1 is turned on in response to the initialization voltage VI. The data write gate signal GW[N] of the current stage may be generated based on the scan signal SCAN[N] of the current stage.

[0111] Along a path generated by turning on the first, second, and third pixel switching elements T1, T2, and T3, a voltage equal to the data voltage VDATA minus an absolute value |VTH| of the threshold voltage of the first pixel switching element T1 may be charged at the first node N1.

[0112] During the second duration DU2, the organic light emitting element initialization gate signal GB may have an effective level. For example, the effective level of the organic light emitting element initialization gate signal GB may be a low level. When the organic light emitting element initialization gate signal GB has an effective level, the seventh pixel switch element T7 is turned on so that the initialization voltage V1 can be applied to the anode electrode of the organic light emitting element OLED. The organic light emitting element initialization gate signal GB[N] of the current stage may be generated based on the scan signal SCAN[N] of the current stage.

[0113] Although according to some exemplary embodiments, the effective timing of the organic light emitting element initialization gate signal GB is the same as the effective timing of the data write gate signal GW, the embodiments according to the inventive concept are not limited thereto. Alternatively, the effective timing of the organic light emitting element initialization gate signal GB may be different from the effective timing of the data write gate signal GW.

[0114] During the third duration DU3, the emission signal EM may have an effective level. The effective level of the emission signal EM may be a low level. When the emission signal EM has an effective level, the fifth pixel switch element T5 and the sixth pixel switch element T6 are turned on. In addition, the first pixel switch element T1 is turned on by the data voltage VDATA.

[0115] The driving current flows through the fifth pixel switching element T5, the first pixel switching element T1, and the sixth pixel switching element T6 to drive the organic light emitting element OLED. The intensity of the driving current can be determined by the level of the data voltage VDATA. The brightness of the organic light emitting element OLED is determined by the intensity of the driving current. The driving current ISD flowing through the path from the input electrode to the output electrode of the first pixel switching element T1 is determined by the following equation 1.

[0116] Equation 1:

[0117]

[0118] In Equation 1, μ is the mobility of the first pixel switch element T1. Cox is the capacitance per unit area of ​​the first pixel switch element T1. W / L is the width-to-length ratio of the first pixel switch element T1. VSG is the voltage between the input electrode of the first pixel switch element T1 and the control electrode of the first pixel switch element T1. |VTH| is the threshold voltage of the first pixel switch element T1.

[0119] During the second duration DU2 , after the threshold voltage |VTH| is compensated, the voltage VG of the first node N1 may be expressed as Equation 2 below.

[0120] Equation 2:

[0121] VG=VDATA-|VTH|

[0122] When the organic light emitting element OLED emits light during the third duration DU3, the driving voltage VOV and the driving current ISD may be expressed as the following Equations 3 and 4. In Equation 3, VS is the voltage of the second node N2.

[0123] Equation 3:

[0124] VOV=VS-VG-|VTH|=EL VDD-(VDATA-|VTH|)-|VTH|=EL VVD-VDATA

[0125] Equation 4:

[0126]

[0127] The threshold voltage |VTH| is compensated during the second duration DU2 so that when the organic light emitting element OLED emits light during the third duration DU3 , the driving current ISD may be determined regardless of the threshold voltage |VTH| of the first pixel switching element T1 .

[0128] Figure 6 It is shown Figure 3 A conceptual diagram of a first display area DA1, a second display area DA2, a first back gate signal applying line BSL1, and a second back gate signal applying line BSL2 of a display panel 100.

[0129] Reference Figures 1 to 6 , the display panel 100 may include a first display area DA1, a second display area DA2, a back gate electrode (eg, Figure 4 The first back gate signal applying line BSL1 (for example, BML1 in the display area 400) and the back gate electrode (for example, Figure 4 A second back gate signal applying line BSL2 of BML1 in FIG.

[0130] The plurality of back gate electrodes (eg, Figure 4 The back gate electrodes (eg, BML1 in the second display area DA2) of the plurality of pixels are connected to each other to form a grid. Figure 4 The back gate electrodes of the pixels in the first display area DA1 may not be connected to the back gate electrodes of the pixels in the second display area DA2.

[0131] The first back gate signal BS1 applied to the back gate electrodes of the pixels in the first display area DA1 may be generated independently of the second back gate signal BS2 applied to the back gate electrodes of the pixels in the second display area DA2.

[0132] Fig. 7A is shown applied to Figure 3 1 is a timing diagram of input signals of the display panel 100. Figure 7B is shown applied to Figure 3 1 is a timing diagram of input signals of the display panel 100. Figure 7C is shown applied to Figure 31 is a timing diagram of input signals of the display panel 100. Fig.7D is shown applied to Figure 3 1 is a timing diagram of input signals of the display panel 100. Fig. 8A Is shown driving Figure 1 A flowchart of a method for displaying an apparatus. Figure 8B Is shown driving Figure 1 A flowchart of a method for displaying an apparatus.

[0133] Reference Figures 1 to 8B , the display device can be operated in a normal driving mode and a partial driving mode.

[0134] When the display panel 100 is in the unfolded state, the display device may operate in the normal driving mode. When the display panel 100 is in the folded state, the display device may operate in the partial driving mode.

[0135] In the normal driving mode, the first display area DA1 and the second display area DA2 can display an image. In the normal driving mode, the first display area DA1 and the second display area DA2 can be fully scanned. 7A to 7D As shown in , in the normal driving mode, when driving the first display area DA1, the gate signal SCAN and the data voltage DATA can be normally applied to the first display area DA1 during the first period TA1, and when driving the second display area DA2, the gate signal SCAN and the data voltage DATA can be normally applied to the second display area DA2 during the second period TA2.

[0136] In addition, in the normal driving mode, the first back gate signal BS1 may have a normal level, and the second back gate signal BS2 may have a normal level. The normal level may mean that the level of the pixel switching element is not turned off by the first back gate signal BS1 and the second back gate signal BS2, so that the pixel switching element can be normally operated by the normal level of the first back gate signal BS1 and the second back gate signal BS2.

[0137] For example, the normal level may be a high power voltage ELVDD of the organic light emitting element OLED.

[0138] For example, in the normal driving mode, the first back gate signal BS1 may be substantially the same as the second back gate signal BS2.

[0139] In the partial driving mode, the first display area DA1 may display an image, while the second display area DA2 may not display an image.

[0140] exist Fig. 7AIn the partial driving mode, the gate signal SCAN and the data voltage DATA may be normally applied to the first display area DA1 and the second display area DA2 during a first period TA1 of driving the first display area DA1 and a second period TA2 of driving the second display area DA2.

[0141] In addition, in the partial driving mode, the first back gate signal BS1 may have a normal level (e.g., ELVDD), and the second back gate signal BS2 may have an inactive level VPOFF greater than the normal level (e.g., ELVDD). The inactive level VPOFF may mean a level at which the pixel switching element is turned off by the first back gate signal BS1 and the second back gate signal BS2.

[0142] For example, the inactive level VPOFF may be greater than Fig. 7A The pixel-off voltage of the high power supply voltage ELVDD of the organic light emitting element OLED.

[0143] When the pixel is turned off, voltage is applied to Figure 4 When the back gate electrode BML1 of the first pixel switch element T1 is turned off, the first pixel switch element T1 is turned off. When the first pixel switch element T1 is turned off, the current path generated by the fifth pixel switch element T5, the first pixel switch element T1, the sixth pixel switch element T6 and the organic light emitting element OLED is cut off so that the pixel does not emit light.

[0144] For example, in the partial driving mode, the first back gate signal BS1 may be different from the second back gate signal BS2. Fig. 7A In the partial driving mode, the second back gate signal BS2 may be greater than the first back gate signal BS1.

[0145] The normal driving mode and the partial driving mode may be determined in units of a frame, and the frame is defined by a vertical synchronization signal VSYNC.

[0146] exist Figure 7B In the partial driving mode, during the first period TA1 of driving the first display area DA1, the gate signal SCAN and the data voltage DATA may be normally applied to the first display area DA1, and during the second period TA2 of driving the second display area DA2, the gate signal SCAN and the data voltage DATA may not be applied to the second display area DA2 to reduce power consumption.

[0147] In addition, in the partial driving mode, the first back gate signal BS1 may have a normal level (eg, ELVDD), and the second back gate signal BS2 may have an inactive level VPOFF greater than the normal level (eg, ELVDD).

[0148] exist Figure 7C and Fig.7D In the embodiment, the switching element (eg, the first pixel switching element T1 ) receiving the first back gate signal BS1 or the second back gate signal BS2 is an N-type switching element.

[0149] exist Figure 7C In the partial driving mode, the gate signal SCAN and the data voltage DATA may be normally applied to the first display area DA1 and the second display area DA2 during a first period TA1 of driving the first display area DA1 and a second period TA2 of driving the second display area DA2.

[0150] In addition, in the partial driving mode, the first back gate signal BS1 may have a normal level NL, and the second back gate signal BS2 may have an inactive level VPOFF less than the normal level NL. The inactive level VPOFF may mean a level at which the pixel switching element is turned off by the first back gate signal BS1 and the second back gate signal BS2.

[0151] For example, in the partial driving mode, the first back gate signal BS1 may be different from the second back gate signal BS2. Figure 7C In the partial driving mode, the second back gate signal BS2 may be smaller than the first back gate signal BS1.

[0152] exist Fig.7D In the partial driving mode, during the first period TA1 of driving the first display area DA1, the gate signal SCAN and the data voltage DATA may be normally applied to the first display area DA1, and during the second period TA2 of driving the second display area DA2, the gate signal SCAN and the data voltage DATA may not be applied to the second display area DA2 to reduce power consumption.

[0153] In addition, in the partial driving mode, the first back gate signal BS1 may have the normal level NL, and the second back gate signal BS2 may have the inactive level VPOFF which is less than the normal level NL.

[0154] When the display panel 100 is in the unfolded state (eg, unfolded state or status), the display panel 100 may be driven in a normal driving mode (operation S10 ).

[0155] A folding condition (eg, folding condition or state) of the display panel 100 may be determined (operation S20). When the display panel 100 is not folded, the normal driving mode may be maintained. When the display panel 100 is folded, the display panel 100 may be driven in a partial driving mode.

[0156] When the display panel 100 is folded, a black data voltage ( Fig. 8AThe operation S30 of writing the black data voltage in the off area (eg, the second display area DA2) is an operation for stabilizing the display image so that Figure 8B As shown in , operation S30 may be omitted.

[0157] When the display panel 100 is folded, a back gate signal (eg, the second back gate signal BS2 ) corresponding to the off region may increase from a normal level to an inactive level VPOFF greater than the normal level (operation S40 ).

[0158] When the display panel 100 is folded, at least one of the gate driver 300, the data driver 500, and the emission driver 600 may not output a driving signal to the off region (operation S50).

[0159] For example, when the display panel 100 is folded, the carry signal is not transmitted to a portion of the gate driver 300 corresponding to the off region, so that the gate driver 300 may not output the plurality of gate signals GW, GI, and GB to the off region.

[0160] For example, when the display panel 100 is folded, the output buffer of the data driver 500 is disabled when outputting the data voltage VDATA to the off region, so that the data driver 500 may not output the data voltage VDATA to the off region.

[0161] For example, when the display panel 100 is folded, the carry signal is not transmitted to a portion of the emission driver 600 corresponding to the off region, so that the emission driver 600 may not output the emission signal EM to the off region.

[0162] As explained above, when the display panel 100 is folded, through the plurality of operations S30 , S40 , and S50 , the display device may be operated in the partial driving mode (operation S60 ).

[0163] In the folded state of the display panel 100, an unfolding action of the display panel 100 may be determined (operation S70). When the display panel 100 is not unfolded, the partial driving mode may be maintained. When the display panel 100 is unfolded, the display panel 100 may be driven in the normal driving mode.

[0164] When the display panel 100 is unfolded, the deactivated elements among the gate driver 300, the data driver 500, and the emission driver 600 may be activated. Therefore, when the display panel 100 is unfolded, the gate driver 300, the data driver 500, and the emission driver 600 may output driving signals to the first display area DA1 and the second display area DA2 of the display panel 100 (operation S80).

[0165] When the display panel 100 is unfolded from the folded state, a back gate signal (eg, the second back gate signal BS2 ) corresponding to the off region in the folded state may be reduced from the inactive level VPOFF to a normal level (eg, ELVDD) (operation S90 ).

[0166] When the display panel 100 is unfolded, the black data voltage may be temporarily written into the closed area (e.g., the second display area DA2) of the folded state (operation S100) to prevent an undesired image from being displayed to the user immediately after the display panel 100 is unfolded. Operation S100 of temporarily writing the black data voltage into the closed area (e.g., the second display area DA2) is an operation for stabilizing the displayed image so that the display panel 100 is displayed as shown in FIG. Figure 8B As shown in , operation S100 may be omitted.

[0167] As explained above, when the display panel 100 is unfolded, the display device may be operated in the normal driving mode (operation S10) through the plurality of operations S80, S90, and S100.

[0168] Fig. 9 It is shown Figure 1 Conceptual diagram of a timing controller embedded data driver (integrated driver) TED of a display device. Fig.10 It is shown Fig. 9 Block diagram of the timing controller embedded data driver TED.

[0169] Reference Figures 1 to 10 , the driving controller 200 , the data driver 500 and the back gate signal generator 700 may form a timing controller embedded data driver (integrated driver) TED.

[0170] The timing controller embedded data driver TED may include a driving controller 200 or 810 , a back gate reference voltage generator 820 , a first digital-to-analog converter ( DAC1 ) 830 , a gamma reference voltage generator 400 or 840 , and a second digital-to-analog converter ( DAC2 ) 850 .

[0171] The back gate reference voltage generator 820 may generate a back gate reference voltage VBREF. The back gate reference voltage generator 820 may correspond to the level of the first back gate signal BS1 and the level of the second back gate signal BS2. The driving controller 810 may transmit the setting of the minimum and maximum values ​​of the level of the first back gate signal BS1 and the minimum and maximum values ​​of the level of the second back gate signal BS2. The back gate reference voltage generator 820 may include a resistor string, and the resistor string includes a plurality of resistors. The back gate reference voltage generator 820 may generate the back gate reference voltage VBREF based on the minimum and maximum values ​​in the voltage division method.

[0172] The first digital-to-analog converter 830 may convert the back gate digital signal DBS received from the driving controller 810 into a first back gate signal BS1 having an analog type and a second back gate signal BS2 having an analog type based on the back gate reference voltage VBREF. The first digital-to-analog converter 830 may output the first back gate signal BS1 and the second back gate signal BS2 to the first back gate signal applying line BSL1 and the second back gate signal applying line BSL2.

[0173] The gamma reference voltage generator 840 may generate a gamma reference voltage VGREF. The gamma reference voltage VGREF may correspond to the level of the data voltage. The driving controller 810 may transmit detailed settings about the minimum value of the gamma reference voltage, the maximum value of the gamma reference voltage, the gamma value, and the gamma curve to the gamma reference voltage generator 840. The gamma reference voltage generator 840 may include a resistor string, and the resistor string includes a plurality of resistors. The gamma reference voltage generator 840 may generate the gamma reference voltage VGREF based on the detailed settings about the minimum value of the gamma reference voltage, the maximum value of the gamma reference voltage, the gamma value, and the gamma curve.

[0174] The second digital-to-analog converter 850 may convert the data signal DATA having a digital type and received from the driving controller 810 based on the gamma reference voltage VGREF into a plurality of data voltages VD1, VD2, ..., VDN-1, and VDN having an analog type. The second digital-to-analog converter 850 may output the plurality of data voltages VD1, VD2, ..., VDN-1, and VDN to the data lines.

[0175] The first back gate signal BS1 and the second back gate signal BS2 are controlled in units of horizontal lines of the input image data IMG by the driving controller 810, so that the first back gate signal BS1 and the second back gate signal BS2 can be adjusted in units of horizontal lines of the input image data IMG. Therefore, the first back gate signal BS1 and the second back gate signal BS2 can be controlled in a short cycle.

[0176] The timing controller embedded data driver TED may include a plurality of output pads OB1 and OB2, and the plurality of output pads OB1 and OB2 output the first back gate signal BS1 and the second back gate signal BS2 to the first back gate signal applying line BSL1 and the second back gate signal applying line BSL2. Fig. 9 In the example, FPDO[2:0] may mean a plurality of back gate signals output through a plurality of output pads OB1 and OB2.

[0177] According to some exemplary embodiments, independent first back gate signals BS1 and second back gate signals BS2 are applied to the first back gate electrode located in the first display area DA1 and the second back gate electrode located in the second display area DA2, so that the pixels in the invalid second display area DA2 can be controlled not to emit light. In addition, in the folded state of the display panel, the gate driver 300 does not output the gate signal to the invalid second display area DA2, the data driver 500 does not output the data voltage to the invalid second display area DA2, and the emission driver 600 does not output the emission signal to the invalid second display area DA2. Therefore, the power consumption of the display device can be reduced.

[0178] Fig.11 is a block diagram illustrating a timing controller embedded data driver TED of a display device according to some exemplary embodiments of the inventive concept.

[0179] Except for the structure of the timing controller embedded data driver TED, the display device and the method of driving the display device according to the present exemplary embodiment are similar to those of the reference Figures 1 to 10 The display device and the method of driving the display device of the previously explained exemplary embodiments are substantially the same. Therefore, the same reference numerals will be used to indicate the same Figures 1 to 10 The same or similar parts as those described in the previous exemplary embodiments of the present invention are described herein, and repeated explanations about the above elements may be omitted for the sake of brevity.

[0180] Reference Figures 1 to 9 and Fig.11 , the driving controller 200 , the data driver 500 and the back gate signal generator 700 may form a timing controller embedded data driver TED.

[0181] The timing controller embedded data driver TED may include a driving controller 200 or 810 , a reference voltage generator 820 , and a digital-to-analog converter (DAC) 830 .

[0182] The reference voltage generator 820 may generate a gamma reference voltage VGREF. The gamma reference voltage VGREF may correspond to the level of the data voltage, the level of the first back gate signal BS1, and the level of the second back gate signal BS2. The driving controller 810 may transmit detailed settings about the minimum value of the gamma reference voltage, the maximum value of the gamma reference voltage, the gamma value, and the gamma curve to the reference voltage generator 820. The reference voltage generator 820 may include a resistor string, and the resistor string includes a plurality of resistors. The reference voltage generator 820 may generate the gamma reference voltage VGREF based on the detailed settings about the minimum value of the gamma reference voltage, the maximum value of the gamma reference voltage, the gamma value, and the gamma curve.

[0183] The digital-to-analog converter 830 may convert the back gate digital signal DBS received from the driving controller 810 into a first back gate signal BS1 having an analog type and a second back gate signal BS2 having an analog type based on the gamma reference voltage VGREF. The digital-to-analog converter 830 may output the first back gate signal BS1 and the second back gate signal BS2 to the first back gate signal applying line BSL1 and the second back gate signal applying line BSL2. The digital-to-analog converter 830 may convert the data signal DATA having a digital type and received from the driving controller 810 based on the gamma reference voltage VGREF into a plurality of data voltages VD1, VD2, ..., VDN-1 and VDN having an analog type. The digital-to-analog converter 830 may output the plurality of data voltages VD1, VD2, ..., VDN-1 and VDN to a plurality of data lines.

[0184] According to some exemplary embodiments, the gamma reference voltage VGREF used to generate the plurality of data voltages VD1 , VD2 , . . . , VDN- 1 , and VDN is used to generate the first back gate signal BS1 and the second back gate signal BS2 .

[0185] The first and second back gate signals BS1 and BS2 and the plurality of data voltages VD1 , VD2 , . . . , VDN- 1 , and VDN may be generated by a single digital-to-analog converter 830 .

[0186] The first back gate signal BS1 and the second back gate signal BS2 are controlled in units of horizontal lines of the input image data IMG by the driving controller 810, so that the first back gate signal BS1 and the second back gate signal BS2 can be adjusted in units of horizontal lines of the input image data IMG. Therefore, the first back gate signal BS1 and the second back gate signal BS2 can be controlled in a short cycle.

[0187] According to some exemplary embodiments, independent first back gate signals BS1 and second back gate signals BS2 are applied to the first back gate electrode located in the first display area DA1 and the second back gate electrode located in the second display area DA2, so that the pixels in the invalid second display area DA2 can be controlled not to emit light. In addition, in the folded state of the display panel, the gate driver 300 does not output the gate signal to the invalid second display area DA2, the data driver 500 does not output the data voltage to the invalid second display area DA2, and the emission driver 600 does not output the emission signal to the invalid second display area DA2. Therefore, the power consumption of the display device can be reduced.

[0188] Fig.12 is a block diagram illustrating a timing controller embedded data driver TED of a display device according to some exemplary embodiments of the inventive concept.

[0189] Except for the structure of the timing controller embedded data driver TED, the display device and the method of driving the display device according to the present exemplary embodiment are similar to those of the reference Figures 1 to 10 The display device and the method of driving the display device of the previously explained exemplary embodiments are substantially the same. Therefore, the same reference numerals will be used to indicate the same Figures 1 to 10 The same or similar parts as those described in the previous exemplary embodiments of the present invention may be described, and some repeated explanations regarding the above elements may be omitted.

[0190] Reference Figures 1 to 9 and Fig.12 , the driving controller 200 , the gamma reference voltage generator 400 , and the data driver 500 may form a timing controller embedded data driver TED.

[0191] The timing controller embedded data driver TED may include a driving controller 200 or 810 , a gamma reference voltage generator 400 or 840 , a data driver 500 or 860 , and a voltage regulator 870 .

[0192] The gamma reference voltage generator 840 generates a gamma reference voltage VGREF and outputs the gamma reference voltage VGREF to the data driver 860 .

[0193] The data driver 860 converts the data signal into a data voltage VD based on the gamma reference voltage VGREF and outputs the data voltage VD to the display panel 100 .

[0194] The voltage regulator 870 may receive information about the level of the first back gate signal BS1 and the level of the second back gate signal BS2 from the driving controller 810 and generate the first back gate signal BS1 and the second back gate signal BS2.

[0195] According to some exemplary embodiments, the power supply voltage generator 700 may be formed independently of the timing controller embedded data driver TED. The power supply voltage generator 700 may be formed independently of the voltage regulator 870.

[0196] The power voltage generator 700 may generate a high power voltage ELVDD and a low power voltage ELVSS applied to pixels of the display panel 100 .

[0197] According to some exemplary embodiments, the first back gate signal BS1 and the second back gate signal BS2 may be controlled in units of frames of the input image data IMG.

[0198] According to some exemplary embodiments, independent first back gate signals BS1 and second back gate signals BS2 are applied to the first back gate electrode located in the first display area DA1 and the second back gate electrode located in the second display area DA2, so that the pixels in the invalid second display area DA2 can be controlled not to emit light. In addition, in the folded state of the display panel 100, the gate driver 300 does not output the gate signal to the invalid second display area DA2, the data driver 500 does not output the data voltage to the invalid second display area DA2, and the emission driver 600 does not output the emission signal to the invalid second display area DA2. Therefore, the power consumption of the display device can be reduced.

[0199] Fig.13 is a conceptual diagram illustrating a timing controller embedded data driver TED of a display device according to some exemplary embodiments of the inventive concept. Fig.14 It is shown Fig.13 Block diagram of the timing controller embedded data driver TED.

[0200] Except for the structure of the timing controller embedded data driver TED, the display device and the method of driving the display device according to the present exemplary embodiment are similar to those of the reference Figures 1 to 10 The display device and the method of driving the display device of the previously explained exemplary embodiments are substantially the same. Therefore, the same reference numerals will be used to indicate the same Figures 1 to 10 The same or similar parts as those described in the previous exemplary embodiments of the present invention may be described, and some repeated explanations regarding the above elements may be omitted.

[0201] Reference Figure 1 To Figure 8, Fig.13 and Fig.14 The timing controller embedded data driver TED may include a driving controller 200 or 810 , a gamma reference voltage generator 400 or 840 , a power supply voltage generator 700 , and a data driver 500 or 860 .

[0202] The gamma reference voltage generator 840 generates a gamma reference voltage VGREF and outputs the gamma reference voltage VGREF to the data driver 860 .

[0203] The data driver 860 converts the data signal into a data voltage VD based on the gamma reference voltage VGREF and outputs the data voltage VD to the display panel 100 .

[0204] The power supply voltage generator 700 may receive information about the level of the first back gate signal BS1 and the level of the second back gate signal BS2 from the driving controller 810, and generate the first back gate signal BS1 and the second back gate signal BS2. In addition, the power supply voltage generator 700 may generate a high power supply voltage ELVDD and a low power supply voltage ELVSS applied to the pixels of the display panel 100.

[0205] The power supply voltage generator 700 may be formed independently of the timing controller embedded data driver TED.

[0206] According to some example embodiments, the first back gate signal BS1 and the second back gate signal BS2 may be controlled in units of frames of the input image data IMG.

[0207] The timing controller embedded data driver TED may include a control pad CB1, a plurality of input pads IB1 and IB2, and a plurality of output pads OB1 and OB2, the control pad CB1 outputting information about the level of the first back gate signal BS1 and the level of the second back gate signal BS2 to the power supply voltage generator 700, the plurality of input pads IB1 and IB2 receiving the first back gate signal BS1 and the second back gate signal BS2 from the power supply voltage generator 700, and the plurality of output pads OB1 and OB2 outputting the first back gate signal BS1 to the first back gate signal applying line BSL1 and the second back gate signal BS2 to the second back gate signal applying line BSL2. Fig.13 In , FPDO[2:0] may mean that a plurality of back gate signals are output through a plurality of output pads OB1 and OB2. Fig.13 In FIG. 7 , FPDI[2:0] may mean that a plurality of back gate signals are input from the power supply voltage generator 700 through a plurality of input pads IB1 and IB2. Fig.13 , FPDCTL[2:0] may mean that a plurality of back gate control signals are output from the timing controller embedded data driver TED to the power supply voltage generator 700 through the control pad CB1.

[0208] According to some exemplary embodiments, independent first back gate signals BS1 and second back gate signals BS2 are applied to the first back gate electrode located in the first display area DA1 and the second back gate electrode located in the second display area DA2, so that the pixels in the invalid second display area DA2 can be controlled not to emit light. In addition, in the folded state of the display panel, the gate driver 300 does not output the gate signal to the invalid second display area DA2, the data driver 500 does not output the data voltage to the invalid second display area DA2, and the emission driver 600 does not output the emission signal to the invalid second display area DA2. Therefore, the power consumption of the display device can be reduced.

[0209] Fig.15are perspective views illustrating display devices according to some exemplary embodiments of the inventive concept. Fig.16 It is shown Fig.15 A plan view of a display device. Fig.17 It is shown Fig.15 Conceptual diagram of a first display area DA1, a second display area DA2, a third display area DA3, a first back gate signal applying line BSL1, a second back gate signal applying line BSL2, and a third back gate signal applying line BSL3 of a display panel.

[0210] In addition to the display panel including three display areas, the display device and the method of driving the display device according to the present exemplary embodiment are different from those of the reference Figures 1 to 10 The display device and the method of driving the display device of the previously explained exemplary embodiments are substantially the same. Therefore, the same reference numerals will be used to indicate the same Figures 1 to 10 The same or similar parts as those described in the previous exemplary embodiments of the present invention may be described, and some repeated explanations regarding the above elements may be omitted.

[0211] Reference Figures 3 to 5 Figure 7a to Fig.10 as well as Figures 15 to 17 The display device may include a flexible display panel. The display device may be a foldable display device. The display device may be foldable along a first folding line and a second folding line.

[0212] The display device may include a first display area DA1 at a first side of a first folding line, a second display area DA2 at a second side of the first folding line and at a first side of a second folding line, and a third display area DA3 at a second side of the second folding line.

[0213] When Fig.15 When the display device is folded as shown, the first display area DA1 may display an image, and the second display area DA2 and the third display area DA3 may not display an image. Alternatively, when the display device is folded, according to user settings, the third display area DA3 may display an image, and the first display area DA1 and the second display area DA2 may not display an image.

[0214] The display panel 100 may include a plurality of back gate electrodes (eg, Figure 4 A first back gate signal applying line BSL1 (BML1 in the display area), a plurality of back gate electrodes (eg, Figure 4 The back gate signal applying line BSL2 of the display area DA1 and the back gate electrodes (eg, BML1 in the display area DA2) connected to the pixels in the third display area DA3 may be connected to the back gate electrodes. Figure 4 The third back gate signal applying line BSL3 of BML1 in FIG.

[0215] The plurality of back gate electrodes (eg, Figure 4 The back gate electrodes (eg, BML1 in the second display area DA2) of the plurality of pixels are connected to each other to form a grid. Figure 4 The back gate electrodes (eg, BML1 in the third display area DA3) of the plurality of pixels are connected to each other to form a grid. Figure 4 The back gate electrodes of the plurality of pixels in the first display area DA1, the back gate electrodes of the plurality of pixels in the second display area DA2, and the back gate electrodes of the plurality of pixels in the third display area DA3 may not be connected to each other.

[0216] A first back gate signal BS1 applied to multiple back gate electrodes of multiple pixels in the first display area DA1, a second back gate signal BS2 applied to multiple back gate electrodes of multiple pixels in the second display area DA2, and a third back gate signal BS3 applied to multiple back gate electrodes of multiple pixels in the third display area DA3 can be generated independently of each other.

[0217] According to some exemplary embodiments, independent first back gate signals BS1, second back gate signals BS2, and third back gate signals BS3 are applied to a plurality of first back gate electrodes located in the first display area DA1, a plurality of second back gate electrodes located in the second display area DA2, and a plurality of third back gate electrodes located in the third display area DA3, so that a plurality of pixels in the invalid second display area DA2 and the third display area DA3 can be controlled not to emit light. In addition, in the folded state of the display panel, the gate driver 300 does not output the gate signal to the invalid second display area DA2 and the third display area DA3, the data driver 500 does not output the data voltage to the invalid second display area DA2 and the third display area DA3, and the emission driver 600 does not output the emission signal to the invalid second display area DA2 and the third display area DA3. Therefore, the power consumption of the display device can be reduced.

[0218] Fig.18 is a flowchart illustrating a method of driving a display device according to some exemplary embodiments of the inventive concept. Fig.19 is shown partially driven Fig.18 Conceptual diagram of a method for displaying a display panel of a display device. Fig. 20 It is shown Fig.18 A circuit diagram of a data driver of a display device.

[0219] The display device and the method of driving the display device according to the present exemplary embodiment are similar to those of the reference device except that the method of driving the display device further includes sensing the current of the pixel and re-outputting the black data voltage. Figures 1 to 10 The display device and the method of driving the display device of the previously explained exemplary embodiments are substantially the same. Therefore, the same reference numerals will be used to indicate the same Figures 1 to 10 The same or similar parts as those described in the previous exemplary embodiments of the present invention may be described, and some repeated explanations regarding the above elements may be omitted.

[0220] Reference Figures 1 to 7D and Figures 18 to 20 , when the display panel 100 is in the unfolded state, the display panel 100 may be driven in a normal driving mode (operation S10 ).

[0221] The folding state of the display panel 100 may be determined (operation S20). When the display panel 100 is not folded, the normal driving mode may be maintained. When the display panel 100 is folded, the display panel 100 may be driven in the partial driving mode.

[0222] When the display panel 100 is folded, a black data voltage ( Fig.18 Operation S30 of writing the black data voltage into the turn-off area (eg, the second display area DA2) is an operation for stabilizing a display image.

[0223] For example, when the display panel 100 is folded, the data driver 500 may output a black data voltage once (eg, in a single output) to a turn-off area (eg, the second display area DA2) where an image should not be displayed.

[0224] When the display panel 100 is folded and after the black data voltage is output once to the off area, a back gate signal (eg, second back gate signal BS2 ) corresponding to the off area may increase from a normal level to an inactive level VPOFF greater than the normal level (operation S40 ).

[0225] When the display panel 100 is folded, at least one of the gate driver 300, the data driver 500, and the emission driver 600 may not output a driving signal to the off region (operation S50).

[0226] For example, when the display panel 100 is folded, the carry signal is not transmitted to a portion of the gate driver 300 corresponding to the off region, so that the gate driver 300 may not output the plurality of gate signals GW, GI, and GB to the off region.

[0227] For example, when the display panel 100 is folded, the output buffer of the data driver 500 is disabled when outputting the data voltage VDATA to the off region, so that the data driver 500 may not output the data voltage VDATA to the off region.

[0228] For example, when the display panel 100 is folded, the carry signal is not transmitted to a portion of the emission driver 600 corresponding to the off region, so that the emission driver 600 may not output the emission signal EM to the off region.

[0229] As explained above, when the display panel 100 is folded, through the plurality of operations S30 , S40 , and S50 , the display device may be operated in the partial driving mode (operation S60 ).

[0230] When the display device is operated in the partial driving mode, a current of a pixel of the display panel 100 is sensed, and it is determined whether the sensed current maintains a black data voltage (operation S65 ).

[0231] When the sensed current does not maintain the black data voltage, the data driver 500 may output the black data voltage to the data line again (operation S30).

[0232] After the black data voltage is written to the invalid area of ​​the display panel 100, when a portion of the display panel driver is turned off, the brightness of the invalid area of ​​the display panel 100 may increase due to current leakage of the pixel, so that the invalid area may not display a black image, display defects may be shown to the user, and power consumption may increase.

[0233] Therefore, when the sensed current does not maintain the black data voltage, the data driver 500 may output the black data voltage to the data line again, so that a display defect may be prevented and power consumption may be reduced.

[0234] According to some exemplary embodiments, the data driver 500 may include a plurality of main buffers (main AMPs) MA1, MA2, MA3, MA4, ... respectively connected to a plurality of data lines and an auxiliary buffer PA (partial AMP) commonly connected to the plurality of data lines. The data driver 500 may further include a plurality of switches S11, S12, S21, S22, S31, S32, S41, and S42. The plurality of switches S11, S12, S21, S22, S31, S32, S41, and S42 may selectively connect one of the plurality of main buffers MA1, MA2, MA3, MA4, ... and the auxiliary buffer PA to the data lines.

[0235] When the data driver 500 outputs the black data voltage to the data line again, the data driver 500 may use the auxiliary buffer PA. The data driver 500 may use a plurality of main buffers MA1, MA2, MA3, MA4, . . . except that the data driver 500 outputs the black data voltage to the data line again.

[0236] exist Fig.19When the display panel 100 is folded, the data voltage may be output to the active area by using a plurality of main buffers MA1, MA2, MA3, MA4, ... When the display panel 100 is folded and the black data voltage is to be output to the inactive area again, the black data voltage may be output to the inactive area by using the auxiliary buffer PA.

[0237] According to some exemplary embodiments, independent first back gate signals BS1 and second back gate signals BS2 are applied to the first back gate electrode located in the first display area DA1 and the second back gate electrode located in the second display area DA2, so that a plurality of pixels in the invalid second display area DA2 can be controlled not to emit light. In addition, in the folded state of the display panel, the gate driver 300 does not output the gate signal to the invalid second display area DA2, the data driver 500 does not output the data voltage to the invalid second display area DA2, and the emission driver 600 does not output the emission signal to the invalid second display area DA2. Therefore, the power consumption of the display device can be reduced.

[0238] In addition, the current of the pixel is sensed in the folded state of the display panel 100. When the brightness of the pixel increases due to the leakage of the pixel current, the black data voltage may be output to the inactive area again.

[0239] In addition, the auxiliary buffer PA commonly connected to the plurality of data lines is used to output the black data voltage to the inactive area, so that the power consumption of the display device can be further reduced.

[0240] Fig.21 is a flowchart illustrating a method of driving a display device according to some exemplary embodiments of the inventive concept.

[0241] In addition to the method of driving a display device further comprising increasing a second back gate signal by sensing a current of a pixel and determining whether the increased second back gate signal exceeds a maximum back gate voltage, the display device and the method of driving a display device according to the present exemplary embodiment are different from those of the reference Figures 18 to 20 The display device and the method of driving the display device of the previously explained exemplary embodiments are substantially the same. Therefore, the same reference numerals will be used to indicate the same Figures 18 to 20 The same or similar parts as those described in the previous exemplary embodiments of the present invention may be described, and some repeated explanations regarding the above elements may be omitted.

[0242] Reference Figures 1 to 7D and Figures 19 to 21 , when the display panel 100 is in the unfolded state, the display panel 100 may be driven in a normal driving mode (operation S10 ).

[0243] The folding state of the display panel 100 may be determined (operation S20). When the display panel 100 is not folded, the normal driving mode may be maintained. When the display panel 100 is folded, the display panel 100 may be driven in the partial driving mode.

[0244] When the display panel 100 is folded, a black data voltage ( Fig.21 Operation S30 of writing the black data voltage into the turn-off area (eg, the second display area DA2) is an operation for stabilizing a display image.

[0245] For example, when the display panel 100 is folded, the data driver 500 may once output a black data voltage to a turn-off area (eg, the second display area DA2 ) where an image should not be displayed.

[0246] When the display panel 100 is folded and after the black data voltage is output once to the off area, a back gate signal (eg, second back gate signal BS2 ) corresponding to the off area may increase from a normal level to an inactive level VPOFF greater than the normal level (operation S40 ).

[0247] When the back gate signal (eg, the second back gate signal BS2 ) increases from the normal level to the inactive level VPOFF, it is determined whether the increased back gate signal (eg, the second back gate signal BS2 ) exceeds the maximum back gate voltage (Spec IN) (operation S45 ).

[0248] When the display panel 100 is folded and the increased back gate signal (eg, the second back gate signal BS2 ) does not exceed the maximum back gate voltage, at least one of the gate driver 300 , the data driver 500 , and the emission driver 600 may not output a driving signal to the off region (operation S50 ).

[0249] As explained above, when the display panel 100 is folded, through the plurality of operations S30 , S40 , and S50 , the display device may be operated in the partial driving mode (operation S60 ).

[0250] When the display device operates in the partial driving mode, a current of a pixel of the display panel 100 is sensed, and it is determined whether the sensed current maintains a black data voltage (operation S65 ).

[0251] When the sensed current does not maintain the black data voltage, the inactive level of the back gate signal (e.g., the second back gate signal BS2) may be further increased (operation S67). When the sensed current increases, the level of the back gate signal (e.g., the second back gate signal BS2) may be controlled to display a black image in the display panel 100 instead of writing the black data voltage.

[0252] When the back gate signal (eg, the second back gate signal BS2 ) further increases, it is determined whether the increased back gate signal (eg, the second back gate signal BS2 ) exceeds the maximum back gate voltage (operation S45 ).

[0253] When the back gate signal (e.g., the second back gate signal BS2) further increases and the increased back gate signal (e.g., the second back gate signal BS2) exceeds the maximum back gate voltage, the display defect of the display panel 100 may not be controlled by controlling the level of the back gate signal (e.g., the second back gate signal BS2) so that the data driver 500 can output the black data voltage to the data line again (operation S30).

[0254] When the back gate signal (eg, the second back gate signal BS2 ) further increases and the increased back gate signal (eg, the second back gate signal BS2 ) does not exceed the maximum back gate voltage, the partial driving method (operations S60 and S65 ) may be maintained.

[0255] According to some exemplary embodiments, independent first back gate signals BS1 and second back gate signals BS2 are applied to the first back gate electrode located in the first display area DA1 and the second back gate electrode located in the second display area DA2, so that a plurality of pixels in the invalid second display area DA2 can be controlled not to emit light. In addition, in the folded state of the display panel, the gate driver 300 does not output the gate signal to the invalid second display area DA2, the data driver 500 does not output the data voltage to the invalid second display area DA2, and the emission driver 600 does not output the emission signal to the invalid second display area DA2. Therefore, the power consumption of the display device can be reduced.

[0256] In addition, the current of the pixel is sensed in the folded state of the display panel 100. When the brightness of the pixel increases due to the leakage of the pixel current, the second back gate signal may increase, or the black data voltage may be output to the inactive area again.

[0257] In addition, the auxiliary buffer PA commonly connected to the plurality of data lines is used to output the black data voltage to the inactive area, so that the power consumption of the display device can be further reduced.

[0258] According to the inventive concept as explained above, the power consumption of the foldable display device can be reduced.

[0259] The electronic or electrical device and / or any other related device or component according to the embodiments of the present invention described herein can be implemented by utilizing any suitable hardware, firmware (e.g., application specific integrated circuit), software, or a combination of software, firmware, and hardware. For example, the various components of these devices can be formed on an integrated circuit (IC) chip or on a separate IC chip. In addition, the various components of these devices can be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on a substrate. In addition, the various components of these devices can be processes or threads running on one or more processors in one or more computing devices, which execute computer program instructions and interact with other system components for performing the various functions described herein. Computer program instructions are stored in a memory, which can be implemented in a computing device by using a standard storage device (such as, for example, a random access memory (RAM)). Computer program instructions can also be stored in other non-temporary computer-readable media (such as, for example, a CD-ROM, a flash drive, or the like). Furthermore, those skilled in the art will recognize that the functionality of various computing devices may be combined or integrated into a single computing device, or that the functionality of a particular computing device may be distributed across one or more other computing devices without departing from the spirit and scope of the exemplary embodiments of the present invention.

[0260] The foregoing is an explanation of an embodiment according to the inventive concept and will not be construed as being limited thereto. Although some exemplary embodiments of the inventive concept have been described, it will be readily understood by those skilled in the art that many modifications may be made in the exemplary embodiments without substantially departing from the novel teachings and features of the inventive concept. Accordingly, all such modifications are intended to be included within the scope of the inventive concept as defined in the following claims and their equivalents. In the claims, the device-plus-function clause is intended to cover the structures described herein as performing the enumerated functions, and not only structural equivalents, but also equivalent structures. Therefore, it will be understood that the foregoing is an explanation of the inventive concept and will not be construed as being limited to the specific exemplary embodiments disclosed, and modifications to the disclosed exemplary embodiments and other exemplary embodiments are intended to be included within the scope of the appended claims and their equivalents. In the case where the equivalents of the claims are included therein, the inventive concept is defined by the following claims.

Claims

1. A display device, comprising: A display panel comprising a first display area, a second display area, a first back gate signal applying line connected to a plurality of back gate electrodes of a plurality of pixels in the first display area, and a second back gate signal applying line connected to a plurality of back gate electrodes of a plurality of pixels in the second display area; a back gate signal generator configured to generate a first back gate signal and a second back gate signal, the first back gate signal being applied to the plurality of back gate electrodes of the plurality of pixels in the first display area, and the second back gate signal being applied to the plurality of back gate electrodes of the plurality of pixels in the second display area; a gate driver configured to output a gate signal to a gate line of the display panel; a data driver configured to output a data voltage to a data line of the display panel; as well as a driving controller configured to control a driving timing of the gate driver and a driving timing of the data driver, wherein the driving controller, the data driver and the back gate signal generator are formed as an integrated driver, and When the display panel is folded, the second back gate signal is changed from a normal level to an invalid level, and at least one of the gate driver, the data driver and the emission driver does not output a driving signal to the second display area.

2. The display device according to claim 1, wherein: The integrated driver comprises: a back-gate reference voltage generator configured to generate a back-gate reference voltage; and a first digital-to-analog converter configured to convert the back-gate digital signal received from the driving controller into the first back-gate signal having an analog type and the second back-gate signal having an analog type based on the back-gate reference voltage.

3. The display device according to claim 2, wherein: The integrated driver further comprises: a gamma reference voltage generator configured to generate a gamma reference voltage; and a second digital-to-analog converter configured to convert a data signal received from the driving controller into the data voltage having an analog type.

4. The display device according to claim 2, wherein: The first back gate signal and the second back gate signal are adjusted in units of horizontal lines of input image data.

5. The display device according to claim 1, wherein: The integrated driver comprises: a reference voltage generator configured to generate a back-gate reference voltage and a gamma reference voltage; and A digital-to-analog converter is configured to convert the back gate digital signal received from the driving controller into the first back gate signal having an analog type and the second back gate signal having an analog type based on the back gate reference voltage, and to convert the data signal received from the driving controller into the data voltage having an analog type.

6. The display device according to claim 5, wherein: The first back gate signal and the second back gate signal are adjusted in units of horizontal lines of input image data.

7. The display device according to claim 1, wherein: The integrated driver comprises: a gamma reference voltage generator configured to generate a gamma reference voltage; wherein the data driver is configured to convert the data signal into the data voltage based on the gamma reference voltage and output the data voltage to the display panel, and The integrated driver further includes a voltage regulator configured to receive information about the level of the first back gate signal and the level of the second back gate signal and generate the first back gate signal and the second back gate signal.

8. The display device according to claim 7, further comprising: a power supply voltage generator configured to generate a high power supply voltage and a low power supply voltage applied to the pixels of the display panel, Wherein, the power supply voltage generator is formed independently of the voltage regulator.

9. The display device according to claim 7, wherein: The first back gate signal and the second back gate signal are adjusted in units of frames of input image data.

10. The display device according to claim 1, wherein: The integrated driver comprises: An output pad configured to output the first back gate signal to the first back gate signal applying line and to output the second back gate signal to the second back gate signal applying line.

11. A display device, comprising: A display panel comprising a first display area, a second display area, a first back gate signal applying line connected to a plurality of back gate electrodes of a plurality of pixels in the first display area, and a second back gate signal applying line connected to a plurality of back gate electrodes of a plurality of pixels in the second display area; a gate driver configured to output a gate signal to a gate line of the display panel; a data driver configured to output a data voltage to a data line of the display panel; A driving controller configured to control a driving timing of the gate driver and a driving timing of the data driver; as well as a power supply voltage generator configured to generate a first back gate signal applied to the plurality of back gate electrodes of the plurality of pixels in the first display area, a second back gate signal applied to the plurality of back gate electrodes of the plurality of pixels in the second display area, and a high power supply voltage and a low power supply voltage applied to the pixels of the display panel, wherein the drive controller and the data driver form an integrated driver, wherein the supply voltage generator is formed independently of the integrated driver, and When the display panel is folded, the second back gate signal is changed from a normal level to an inactive level, and at least one of the gate driver, the data driver, and the emission driver does not output a driving signal to the second display area.

12. The display device according to claim 11, wherein: The first back gate signal and the second back gate signal are adjusted in units of frames of input image data.

13. The display device according to claim 11, wherein: The integrated driver comprises: a control pad configured to output information about a level of the first back gate signal and a level of the second back gate signal to the power supply voltage generator; an input pad configured to receive the first back-gate signal and the second back-gate signal from the power supply voltage generator; and An output pad configured to output the first back gate signal to the first back gate signal applying line and to output the second back gate signal to the second back gate signal applying line.

14. A display device, comprising: A display panel comprising a first display area, a second display area, a first back gate signal applying line connected to a plurality of back gate electrodes of a plurality of pixels in the first display area, and a second back gate signal applying line connected to a plurality of back gate electrodes of a plurality of pixels in the second display area; a back gate signal generator configured to generate a first back gate signal applied to the first back gate signal applying line and a second back gate signal applied to the second back gate signal applying line; a gate driver configured to output a gate signal to a gate line of the display panel; as well as a data driver configured to output a data voltage to a data line of the display panel; wherein the data driver is configured to output a black data voltage to the data line at a single time when the display panel is folded, and Wherein, when the display panel is folded and after the black data voltage is outputted once, the second back gate signal increases from a normal level to an invalid level greater than the normal level, and at least one of the gate driver, the data driver and the emission driver does not output a driving signal to the second display area.

15. The display device according to claim 14, wherein: When the display panel maintains the folded state, sensing the current of the pixel of the display panel, and The data driver is configured to output the black data voltage to the data line again in response to the sensed current not maintaining the black data voltage.

16. The display device according to claim 15, wherein: The data driver comprises: a plurality of main buffers, the plurality of main buffers being connected to the plurality of data lines respectively; and An auxiliary buffer is commonly connected to the plurality of data lines.

17. The display device according to claim 16, wherein: The data driver further includes a plurality of switches, and The plurality of switches are configured to selectively connect one of the plurality of primary buffers and the auxiliary buffer to the data line.

18. The display device according to claim 16, wherein: The data driver is configured to output the black data voltage to the data line again by using the auxiliary buffer when the sensed current does not maintain the black data voltage.

19. The display device according to claim 14, wherein: When the display panel maintains the folded state, sensing the current of the pixel of the display panel, and The back gate signal generator is configured to increase the second back gate signal when the sensed current does not maintain the black data voltage.

20. The display device according to claim 19, wherein: The data driver is configured to output the black data voltage to the data line again when the second back gate signal increases and the increased second back gate signal exceeds a maximum back gate voltage.

21. The display device according to claim 14, wherein: When the display panel is unfolded from the folded state, the second back gate signal decreases from the inactive level to the normal level.

22. A method for driving a display device, the method comprising: outputting a first back gate signal to a first back gate signal applying line connected to a plurality of back gate electrodes of a plurality of pixels in a first display area of ​​the display panel; outputting a second back gate signal to a second back gate signal applying line connected to a plurality of back gate electrodes of a plurality of pixels in a second display area of ​​the display panel; Outputting a gate signal to a gate line of the display panel; as well as outputting a data voltage to a data line of the display panel, wherein the data driver is configured to output a black data voltage to the data line at a single time when the display panel is folded, and wherein the second back gate signal increases from a normal level to an invalid level greater than the normal level, and when the display panel is folded and after outputting the black data voltage in the single time, at least one of the gate driver, the data driver and the emission driver does not output a driving signal to the second display area.

23. The method according to claim 22, wherein: When the display panel maintains the folded state, sensing the current of the pixel of the display panel, and The data driver is configured to output the black data voltage to the data line again in response to the sensed current not maintaining the black data voltage.

24. The method according to claim 22, wherein: The display device includes a back gate signal generator configured to generate the first back gate signal applied to the first back gate signal applying line and the second back gate signal applied to the second back gate signal applying line, Wherein, when the display panel maintains the folded state, the current of the pixel of the display panel is sensed, and The back gate signal generator is configured to increase the second back gate signal when the sensed current does not maintain the black data voltage.

25. The method according to claim 24, wherein: The data driver is configured to output the black data voltage to the data line again when the second back gate signal increases and the increased second back gate signal exceeds a maximum back gate voltage.

26. The method of claim 22, wherein: When the display panel is unfolded from the folded state, the second back gate signal decreases from the inactive level to the normal level.

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