Encapsulated power electronics and method of assembling the same

Abstract

Embodiments of the present disclosure relate to a packaged power electronic device and a method of assembling the same, the device having: a first support element forming a first heat dissipation surface and carrying first power components; a second support element forming a second heat dissipation surface and carrying second power components; a first contact element superposed to the first power components; a second contact element superposed to the second power components; a plurality of leads electrically coupled with the power components through the first support element and / or the second support element; and a thermally conductive body arranged between the first contact element and the second contact element. The first and second support elements and the first and second contact elements are formed by a plurality of layers that are electrically insulating and thermally conductive.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a packaged power electronic device, in particular to a circuit comprising a power transistor and to a method for assembling thereof. BACKGROUND

[0002] For example, the circuit can comprise a power device operating at high voltage (even up to 600-700 V) with a current that can be quickly switched, such as a silicon carbide or silicon device, such as a super-junction metal-oxide-semiconductor field-effect transistor (MOSFET), an insulated-gate bipolar transistor (IGBT), and the like.

[0003] For such circuits and power electronic devices, a specific packaging is desired, which allows a high thermal dissipation. Such a packaging is usually formed by an insulating rigid body, typically of parallelepiped shape (for example of resin), in which the electronic component(s) are embedded, as well as a dissipation structure, arranged between the electronic component(s), facing the packaging surface and typically occupying most of the long base of the parallelepiped shape. The dissipation structure is sometimes formed by the same metal support, called "leadframe", which carries one or more dies, integrating one or more electronic components as well as a plurality of leads for external connection. Typically, in this case, the leadframe has a surface arranged to directly face the outer side of the packaging.

[0004] For example, in the case where the packaged device comprises a MOSFET transistor, the die integrating the MOSFET transistor typically has a drain pad on a first large surface, as well as at least two contact pads (a source pad and a gate pad, respectively) on a second large surface opposite the first large surface. The transistor contact pads (typically, the drain pad) are attached to the leadframe support portion, which is in direct contact with one or more leads. The other contact pads (typically, the gate pad and the source pad) are coupled to the other leads through a bonding wire or a clip. Such a standard packaging typically has leads arranged on the same side of the dissipation structure, and thus typically allows a downward dissipation.

[0005] Due to the appropriate configuration of the leads and the leadframe support portion, the Applicant has further developed a packaging allowing an upward cooling. For example, Figure 1 An integrated device 1 is shown, which comprises two electronic components integrated in respective dies 2A, 2B and embedded in a substantially parallelepiped-shaped packaging insulating mass 3, shown in dashed lines. The integrated device 1 comprises a leadframe 4 formed by a DBC (Direct Bonded Copper) multilayer, which comprises a first metal conductive layer, an insulating layer of ceramic and a second metal conductive layer. One of the metal conductive layers (in this case, the first metal conductive layer) is arranged to directly face the outer side of the packaging.Figure 1 The conductive portions 5A, 5B are shaped and formed so as to be electrically separated, form respective support portions for the dies 2A, 2B, and be directly coupled to two respective gate pads (not visible) of the dies 2A, 2B and to own lead 6. The other leads 7 are connected to the source pads and gate pads of the dies 2A, 2B and any other contact pads by means of the conductive areas 9 forming part of the lead frame 4 and possibly by means of the wiring 8.

[0006] The conductive portions 5A, 5B and 9 are thermally coupled to a heat dissipation area 10 Figure 2A and are electrically separated from the heat dissipation area 10, which faces outwards and is flush with the upper surface of the encapsulation insulating substance 3.

[0007] With this type of encapsulation, different circuit and component topologies can be formed, as Figures 3A-3I shown in the example of Fig. 2.

[0008] However, this solution is not optimal in the case of electronic devices formed by larger components, such as high-power and high-switching-current MOSFET transistors, and / or having different topologies.

[0009] For example, reference can be made to the full-bridge circuit diagram, indicated by 15, formed by four MOSFET transistors 16-19, for example N-channel. The MOSFET transistors 16-19 can be power transistors of the vertical type, each integrated in own die (similar to the dies 2A and 2B of Figure 4 Fig. 1), with a drain electrode on a first face of the respective die and a source electrode and a gate electrode on the opposite face of the respective die. Figure 1 In a manner known per se, two of the MOSFET transistors 16-19, hereinafter referred to as first and second MOSFET transistors 16, 17, are connected in series with each other between first and second supply nodes 21, 22, and two other MOSFET transistors, hereinafter referred to as third and fourth MOSFET transistors 18, 19, are connected in series with each other between the same supply terminals 21, 22. A first intermediate node 23 between the first and second MOSFET transistors 16, 17 forms a first output terminal, and a second intermediate node 24 between the third and fourth MOSFET transistors 18, 19 forms a second output terminal.

[0010] In a manner known per se, two of the MOSFET transistors 16-19, hereinafter referred to as first and second MOSFET transistors 16, 17, are connected in series with each other between first and second supply nodes 21, 22, and two other MOSFET transistors, hereinafter referred to as third and fourth MOSFET transistors 18, 19, are connected in series with each other between the same supply terminals 21, 22. A first intermediate node 23 between the first and second MOSFET transistors 16, 17 forms a first output terminal, and a second intermediate node 24 between the third and fourth MOSFET transistors 18, 19 forms a second output terminal.

[0011] In the illustrated example, the first and third MOSFET transistors 16, 18 have drain terminals D coupled to each other and to a first supply node 21, source terminals S coupled to first and second intermediate nodes 23, 24, respectively, and gate terminals G coupled to first and third control terminals 25, 26, respectively. The second and fourth MOSFET transistors 17, 19 have source terminals S coupled to each other and to a second supply node 22, drain terminals D coupled to first and second intermediate nodes 23, 24, respectively, and gate terminals G coupled to second and fourth control terminals 27, 28, respectively.

[0012] Additionally, in the illustrated example, in order to have a better on and off cycle control of the MOSFET transistors 16-19, such that the control voltage applied to the respective gate terminal is not referenced to ground, the MOSFET transistors 16-19 all have a further source terminal SD, referred to as driver source terminal 30-33, which is described in detail, for example, in Italian patent application 102017000113926 and US patent application 16 / 154,411 (US 2019 / 0109225).

[0013] In the design of a packaged device integrating the bridge circuit 15, the supply nodes 21, 22, the intermediate nodes 23, 24, the control terminals 25-28 and the driver source terminals 30-33 are coupled to the outside through respective contact pads and respective leads. Then in the following, the same reference numerals will be used to refer to the terminals / nodes or contact pads 21-28 and 30-33 in different ways. SUMMARY

[0014] One purpose of the present disclosure is to provide a packaged solution that overcomes at least some of the drawbacks of the prior art.

[0015] According to the present disclosure, a packaged electronic device and a method for assembling the same are provided. BRIEF DESCRIPTION OF DRAWINGS

[0016] For a better understanding of the present disclosure, embodiments thereof will now be described, by way of non-limiting example only, with reference to the attached drawings, wherein:

[0017] Figure 1 is a top perspective view of a known packaged electronic device with virtual parts;

[0018] Figure 2A and Figure 2B are, respectively, Figure 1 a top perspective view and a bottom perspective view of the packaged electronic device of

[0019] Figures 3A-3I showing that the packaged electronic device of Figure 1circuit topology of an encapsulated electronic device;

[0020] Figure 4 a full-bridge circuit of the known type is shown;

[0021] Figure 5 is Figure 4 a top view of a possible embodiment of a full-bridge circuit of the known type, formed similarly to the encapsulated electronic device of Figure 1 ;

[0022] Figure 6 a possible embodiment of Figure 5 is shown in cross-section;

[0023] Figure 7 a full-bridge circuit of the type obtainable with the present device is shown;

[0024] Figure 8 a simplified cross-section of a portion of a die that integrates known power MOSFET devices usable in the bridge circuit of Figure 7 ;

[0025] Figure 9 is a cross-section of a possible embodiment of the present encapsulated electronic device taken along the line IX-IX of Figure 10A ;

[0026] Figure 10A and Figure 10B are plan views of two portions of the device of Figure 9 in an intermediate manufacturing step;

[0027] Figure 11 and Figure 12 are plan and perspective views, respectively, of different embodiments of the mutual arrangement of some portions of the encapsulated device of Figure 9 ;

[0028] Figure 13 is an exploded view of the encapsulated device of Figure 9 ;

[0029] Figure 14A and Figure 14B are bottom and top perspective views, respectively, of the encapsulated device of Figure 9 ;

[0030] Figures 15A-15D is a simplified perspective representation of a portion of the device of Figure 9 ;

[0031] Figures 16-19 are cross-sections of different embodiments of a detail of the device of Figure 9 ; and

[0032] Figures 20A-20D are plan and perspective views, respectively, of a portion of the device ofFigures 15A-15D simplified perspective representation of a portion of different packaged electronic devices. DETAILED DESCRIPTION

[0033] In order to use an upward cooling package similar to Figure 1 , Figure 2A and Figure 2B it is conceivable to arrange the MOSFET transistors 16-19 in the manner shown in Figure 5 , in which the MOSFET transistors 16-19 are carried by a leadframe 35 provided with leads. Figure 5 Possible electrical connections between the terminals / nodes 21-28 and 30-33 of the bridge circuit 15 and the leads are also shown. In Figure 5 , for the sake of clarity, the leads are identified with the same reference numerals as the respective terminals / nodes of the bridge circuit 15, and, apart from the supply nodes 21, 22, which are each coupled to two different leads 21', 21"; 22', 22", they are identified with a superscript (leads 23'-28' and 30'-33').

[0034] In Figure 5 , the leadframe 35, which is formed as a DBC multilayer, comprises first, second and third conductive areas 36, 37 and 38, which are arranged side by side but are electrically insulated from one another, to carry the MOSFET transistors 16-19. In particular, the first conductive area 36 carries the first and third MOSFET transistors 16, 18 arranged side by side, so that the respective drain terminals D are in contact with the first conductive area 36; the second conductive area 37 carries the second MOSFET transistor 17, so that its drain terminal D is in contact with the second conductive area 37; and the third conductive area 38 carries the fourth MOSFET transistor 19, so that its drain terminal D is in contact with the third conductive area 38.

[0035] The driver source pads 30-33 and the gate pads 25-28 are arranged on the upper surface of the MOSFET transistors 16-19, exposed through corresponding openings (also not numbered) in the respective passivation layer (not numbered). Bonding wires 40 connect the driver source pads 30-33 and the gate pads 25-28 to the respective leads 30'-33' and 25'-28'.

[0036] The first and second clips 41, 42, which are L-shaped in a top view, couple the source terminals S of the first and third MOSFET transistors 16, 18 to the second and third conductive areas 37, 38, respectively, which in turn are coupled to the leads 23' and 24', and thus form the first and second intermediate nodes 23, 24. In the configuration shown, since the MOSFET transistors 16-19 have source terminals S arranged on different levels with respect to the conductive areas 36-38, the first and second clips 41, 42 have a non-planar shape, as shown in cross-section with respect to the first clip 41. Figure 6 The same considerations apply, however, also to the second clip 42.

[0037] In particular, the first clip 41 has a first horizontal portion 41A in contact with the source pad of the first MOSFET transistor 16. Additionally, the first clip 41 has a vertical portion 41B extending laterally to the first MOSFET transistor 16, insulated from the first MOSFET transistor 16 by an insulating layer, not shown, or by the passivation of the die in which the MOSFET transistor 16 is integrated; and a second horizontal portion 41C extending on the lead frame 35, joined to the third conductive area 37 and to the lead 23'.

[0038] Similarly, the third clip 43 couples the source terminals S of the second and fourth MOSFET transistors 17, 19 (electrically connected to each other, Figure 4 ) to the leads 22', 22", which are connected to the second supply node 22 of the Figure 5 . To this end, see also Figure 6 , the third clip 43 has a first horizontal portion 43A extending above the upper surface of the second and fourth MOSFET transistors 17, 19, in contact with the sources of the second and fourth MOSFET transistors 17, 19; a vertical portion 43B and a horizontal portion 43C joined to the coupling areas 47' and 47" of conductive material, which extend between the horizontal portion 43C and the respective leads 22', 22".

[0039] However, this solution, while allowing cooling from the top, is not optimal.

[0040] In fact, as the size of the MOSFET transistors 16-19 increases, the packaged device (with Figure 2A and Figure 2BThe external shape (as shown in the cross-section) would occupy a lot of space, and in some applications would reach unacceptable overall dimensions. Additionally, in the case of high voltages and fast switchable currents, the heat dissipation can be insufficient.

[0041] Figures 7-15D A device 50 is shown implementing a full-bridge circuit 100, which is similar to Figure 4 the full-bridge circuit 15 of Figure 7 and is shown again in

[0042] In particular, the device 50 comprises four integrated components, here four MOSFET transistors 51-54, and are indicated below as first, second, third and fourth MOSFET transistors 51-54. Each MOSFET transistor 51-54 is integrated in its own die, and can be made as shown in Figure 8

[0043] In particular, Figure 8 The structure of a charge balance (also known as super junction) MOSFET device is shown, and for better understanding is briefly described in the following.

[0044] Referring to Figure 8 (wherein the various regions are not to scale for clarity), a MOSFET transistor, here, the first MOSFET transistor 51 (and the other MOSFET devices 52-54) is integrated in a die 220, which comprises a body 202 of semiconductor material (typically silicon) having an upper surface 202A, a back surface 202B and having a first conductivity type (e.g. N). The body 202 defines an active region 203 and a border region 204, and is disposed with a plurality of pillars 206 of a second conductivity type (here, P-type), in which an N-type epitaxial layer region extends. A body region 207 (here, P-type) extends from the upper surface 202A of the body 202 to the upper ends of the pillars 206 arranged in the active region 203, and accommodates a source region 208 of N-type.

[0045] Between pairs of adjacent pillars 206, a gate region 211 extends over the upper surface 202A of the body 202 in laterally offset fashion from the source region 208, the gate region 211 being electrically insulated from the body 202 and surrounded by an insulating region 212. A source metallization 213 extends over the active region 203 of the body 202, over the gate regions 211 (but electrically insulated therefrom), and has a contact portion which extends between pairs of adjacent gate regions 211 towards the upper surface of the body 202, in direct electrical contact with the source region 208. A portion of the source metallization 213 (one in the case of the first MOSFET transistor 51) is arranged to be electrically connected to a source terminal 214 of the MOSFET transistor 51, and a portion of the source metallization 213 (one in the case of the first MOSFET transistor 51) is arranged to be electrically connected to a gate terminal 215 of the MOSFET transistor 51.​Figure 8 The source pad 213A is accessible from the outside through the window 214 and forms a source pad for external electrical connections.

[0046] The gate metallization 216, which is electrically connected to the gate region 211, extends over the dielectric layer 215 and forms a gate pad 216A for external electrical connections. The upper passivation layer 217 covers the dielectric layer 215, exposing the source pad 213A and the gate pad 216A. The drain metallization 218 extends over the back surface 202B of the body 202, directly in electrical contact with the body 202, covers the entire back surface 202B, and forms the drain terminal D of the MOSFET transistor 51.

[0047] Referring again to Figure 7 , the first and second MOSFET transistors 51, 52 are connected in series with each other between the first and second supply terminals 101, 102 of the bridge circuit 100; the third and fourth MOSFET transistors 53, 54 are connected in series with each other between the same supply terminals 101, 102. A first intermediate node 103 between the first and second MOSFET transistors 51, 52 forms a first output terminal, and a second intermediate node 104 between the third and fourth MOSFET transistors 53, 54 forms a second output terminal 104 of the bridge circuit 100.

[0048] In Figure 7 , the gate terminals of the MOSFET transistors 51-54 are further indicated with 105-108, and the driver source terminals of the MOSFET transistors 51-54 are further indicated with 110-113.

[0049] Figure 9 , Figure 10A and Figure 10B , Figures 15A-15D possible implementation of the device 50 is shown. It should be noted that Figure 10A and Figure 10B two parts of the device 50 are shown, and the complete device 50 is obtained by flipping one part onto the other part (for example, Figure 10B the structure of the device 50 is flipped around a vertical axis of the drawing that extends between the two Figure 10A , Figure 10B larger surfaces 50A, 50B). In the following, additionally, the device 50 will be described with reference to the spatial position shown in Figure 9 , i.e. the first larger surface 50A of the device 50 (typically parallelepiped-shaped) is facing downwardly arranged (and is therefore also defined below as lower surface 50A) and the second larger surface 50B is facing upwardly arranged (and is therefore also defined below as upper surface 50B). Thus, the indications "upper", "lower", "high", "low", etc. refer only to the spatial position of Figure 9 , in particular,Figures 9-15D The embodiment refers to a solution in which external connection leads protrude from the housing of device 50 in the lower region of the device and are substantially aligned with the lower surface 50A.

[0050] refer to Figure 9 , Figure 10A and Figure 10B MOSFET transistors 51-54 are arranged two-by-two on two overlapping levels. In the considered example, the first MOSFET transistor 51 and the third MOSFET transistor 53 (forming the upper transistor of bridge circuit 100) are arranged side-by-side on the upper level, with their respective drain metallizations 218 facing upwards. The second and fourth MOSFET transistors 52 and 54 are arranged on the lower level, with their respective drain metallizations 218 facing downwards. The second and fourth MOSFET transistors 52 and 54 are supported by a first support element 56; the first MOSFET transistor 51 and the third MOSFET transistor 53 are supported by a second support element 57. Figure 9 In the cross-section, only the first and second MOSFET transistors 51 and 52 are visible.

[0051] The first and second alignment and spacing structures 89, and the third and fourth alignment and spacing structures 90 extend between the first and second support elements 56 and 57, near their respective longitudinal ends.

[0052] like Figure 13 As shown, the first support element 56 has a first surface 56' and a second surface 56', the first surface 56' being coplanar with the first larger surface 50A of the device 50; the second support element 57 has a first surface 57' and a second surface 57', the first surface 57' being coplanar with the second larger surface 50B of the device 50.

[0053] like Figure 9 As can be seen, the first support element 56 is formed of a DBC (Direct Bonded Copper) multilayer, which comprises a stack of a first conductive layer 56A (typically copper), a ceramic insulating layer 56B (typically alumina), and a second conductive layer 56C (typically copper). Similarly, the second support element 57 is formed of a DBC multilayer, which comprises a stack of a first conductive layer 57A (typically copper), a ceramic insulating layer 57B (typically alumina), and a second conductive layer 57C (typically copper).

[0054] existFigure 9 In the first support element 56, the first conductive layer 56A is arranged at the bottom, and the second conductive layer 56C is arranged at the top. In the second support element 57, the first conductive layer 57A is arranged at the top, and the second conductive layer 57C is arranged at the bottom.

[0055] MOSFET transistors 51 and 53 are bonded to the second conductive layer 57C of the support element 57 via electrically conductive bonding regions 61C and 61D, and MOSFET transistors 52 and 54 are bonded to the second conductive layer 56C of the support element 56 via electrically conductive bonding regions 61A and 61B (see also...). Figure 13 ).

[0056] like Figure 10A As can be seen, the second conductive layer 56C of the first support element 56 is shaped and forms ten separate conductive regions 58A-58J, as discussed in detail below, forming two first drain conductive regions 58A and 58B, two first gate conductive regions 58C and 58D, two driver source conductive regions 58E and 58F, two first source regions 58G and 58H, and two insulating conductive regions 58I and 58J. As detailed below, corresponding output leads 59A-59H are bonded to conductive regions 58A-58H.

[0057] Specifically, the drain metallization 218 of the second and fourth MOSFET transistors 52 and 54 is respectively bonded to the two first drain conductive regions 58A and 58B. Similarly, the drain leads 59A and 59B of the first and second output terminals 103 and 104 of the bridge circuit 100 are also respectively bonded to the two first drain conductive regions 58A and 58B. In addition, first and second connecting posts 67 and 68 of conductive material (e.g., copper) extend from the first drain conductive regions 58A and 58B toward the second support element 57.

[0058] The first contact element 60 extends over the second and fourth MOSFET transistors 52 and 54, and places its source pad 213A ( Figure 8 They are electrically connected to each other. A first contact element 60 is arranged across the second and fourth MOSFET transistors 52 and 54, and has dimensions such that it covers only a portion of their area (e.g., approximately two-thirds here). Figure 10A This is also the DBC multi-layer (in) Figure 12 (As can also be seen in the image) and includes a stack formed by a first conductive layer 60A (typically copper), an intermediate insulating layer 60B (typically alumina), such as ceramic, and a second conductive layer 60C (typically copper).

[0059] The first conductive layer 60A of the first contact element 60 is arranged at the bottom, and the second conductive layer 60C of the first contact element 60 is arranged at the top. As shown in Figures 16-19 and described in the following, the first conductive layer 60A of the first contact element 60 is in direct electrical contact with the source pads 213A of the second and fourth MOSFET transistors 52, 54. Figure 8 ) and the gate pads 213B of the second and fourth MOSFET transistors 52, 54.

[0060] The first contact element 60 has a length (in a direction parallel to the first Cartesian axis X) which is larger than the second and fourth MOSFET transistors 52, 54, and the first contact element 60 protrudes on a side (the left side in Figure 9 and Figure 10A ) to the second and fourth MOSFET transistors 52, 54. The portion of the first conductive layer 60A which protrudes beyond the first and third transistors 51, 53 is in direct electrical contact with the coupling areas 64G, 64H, as indicated by the dashed lines in Figure 10A , which both extend from the respective first source conductive areas 58G, 58H and are thus electrically coupled to the first source leads 59G, 59H. In this way, the source regions 207 of the second and fourth MOSFET transistors 52, 54 are electrically coupled to each other and to the first source leads 59G, 59H by the first conductive layer 60A of the first contact element 60, and these form the second supply terminal 102 of the bridge circuit 100. Figure 8 ). Figure 7

[0061] The further source pad 213E’ is not covered by the first contact element 60 and is visible in Figure 10A , the further source pad 213E’ is connected to the first driver source conductive area 58E by the first driver source wire 62E. Likewise, another further source pad 213F’ is also not covered by the first contact element 60 and is visible in Figure 10A , the further source pad 213F’ is connected to the other first driver source conductive area 58F by the other first driver source wire 62F. The first driver source leads 59E, 59F are bonded to the first driver source conductive areas 58E, 58F and form the driver source terminals 111, 113 of the bridge circuit 100. Figure 7 ).

[0062] ​The gate pads 216A of the second and fourth MOSFET transistors 52, 54 also face the upper surface of the transistors 52, 54, are lateral to the first contact element 60, and are connected to the first gate conductive areas 58C, 58D by the first gate wires 65C, 65D. The first gate leads 59C, 59D are bonded to the first gate conductive areas 58C, 58D and form the gate terminals 106, 108 of the bridge circuit 100 Figure 7

[0063] As mentioned above, the second support element 57 carries the first and third MOSFET transistors 51, 53 Figure 9 and Figure 10B .

[0064] With particular reference to Figure 10B , the first conductive layer 57A of the second support element 57 here forms five conductive areas 76A, 76C-76F (see also Figure 13 ), including a single second drain conductive area 76A, two second gate conductive areas 76C, 76D, and two second driver source conductive areas 76E, 76F. Output leads 77A-77F are bonded to the conductive areas 76A, 76C-76F, as explained in detail below.

[0065] Here, the drain metallizations 218 of the first and third MOSFET transistors 51, 53 Figure 8 are directly bonded to the second drain conductive area 76A and are then electrically coupled. In addition, the second drain leads 77A, 77B are bonded to the second drain conductive area 76A and are thus electrically coupled to each other and form the first supply terminal 101 of the bridge circuit 100 Figure 7 .

[0066] The second and third contact elements 80, 81 are coupled to the first and third MOSFET transistors 51, 53, respectively, and extend in Figure 9 under the first and third MOSFET transistors 51, 53. The second and third contact elements 80, 81 are arranged side by side at the same level, but are electrically insulated, as explained below. In Figure 9 , Figure 10A , Figure 10B the embodiment, the second and third contact elements 80, 81 are also substantially parallelepiped-shaped, elongated in the direction of the first Cartesian axis X, the second and third contact elements 80, 81 being offset in the width direction (parallel to the second Cartesian axis Y) with respect to the first contact element 60, but as Figure 9 ​As can be seen, the second and third contact elements 80 and 81 are exactly superimposed relative to the first contact element 60 in the length direction (parallel to the first Cartesian axis X).

[0067] According to Figure 11 and Figure 12 In the different embodiments shown, the second and third contact elements 80, 81 are also offset symmetrically relative to the first contact element 60 in the length direction.

[0068] Here, the second and third contact elements 80 and 81 are also formed of DBC multilayers. Specifically, both the second and third contact elements 80 and 81 include a stack formed of a first conductive layer 80A, (correspondingly) 81A (typically copper), a corresponding intermediate insulating layer 80B, (correspondingly) 81B (typically alumina), such as ceramic, and a second conductive layer 80C, (correspondingly) 81C (typically copper). Figure 9 In the first contact element 60, the first and second conductive layers 80A, 81A, 80C, and 81C have a thickness less than that of the corresponding conductive layers 60A and 60C of the first contact element 60, because they do not have electrical conduction function but have thermal conduction function.

[0069] The first conductive layers 80A and 81A of the second and third contact elements 80 and 81 are arranged on the top, and the second conductive layers 80C and 81C of the second and third contact elements 80 and 81 are arranged on the bottom. The first conductive layer 80A of the second contact element 80 is connected to the source pad 213A of the first MOSFET transistor 51 via a first clip element 82. Figure 8 Direct electrical contact. Similarly, the first conductive layer 81A of the third contact element 81 is connected to the source pad 213A of the third MOSFET transistor 53 via the second clamping element 83. Figure 8 Direct electrical contact.

[0070] Specifically, Figure 10B The clamping elements 82 and 83 are formed from elongated regions of a conductive material such as copper (in a direction parallel to the first Cartesian axis X). The first clamping element 82 is disposed between the second contact element 80 and the first MOSFET transistor 51. The first clamping element 82 is longer than the first MOSFET transistor 51, such that a portion 82' of it (in...) Figure 10B The left side of the middle and in Figure 9 The second clamping element 83 protrudes laterally relative to the MOSFET transistor 51 (on its right side). Similarly, the second clamping element 83 is disposed between the third contact element 81 and the third MOSFET transistor 53. The second clamping element 83 is longer than the second MOSFET transistor 51, such that a portion 83' (on its right side) protrudes laterally relative to the MOSFET transistor 51.Figure 10B the left) protrudes laterally with respect to the MOSFET transistor 53 side.

[0071] The protruding portions 82', 83' of the clip elements 82, 83 extend as far as, and are engaged with and electrically connected to, the respective first and second connection posts 67, 68.

[0072] In this way, the source terminal 213A of the first MOSFET transistor 51 is coupled to the first drain conductivity region 58A, drain lead 59A and thus to the first output terminal 103 of the bridge circuit 100 (Fig. 1) by the first clip element 82 and the first connection post 67, and the source terminal 213A of the third MOSFET transistor 53 is coupled to the second drain conductivity region 58B and drain lead 59B and thus to the second output terminal 104 of the bridge circuit 100 by the second clip element 83 and the second connection post 68. Figure 7

[0073] In the embodiment of Fig. 1, the first support regions 85 formed by the DBC substrate are arranged between each clip element 82, 83 and the respective first and second support elements 57. Figure 9 The connection post 67 (shown in dashed lines in Fig. 1 for clarity), the protruding portion 82' and one of the first support regions 85 form a third alignment and spacing structure 89; and the connection post 68 (shown in dashed lines in Fig. 1), the protruding portion 83' and the other of the support regions 85 form a fourth alignment and spacing structure 89.

[0074] Figure 10B Again with reference to Fig. 1, the further source pad 213E" of the first MOSFET transistor 51 which is not covered by the second contact element 80 is connected to one of the second driver source conductivity regions 76E by the second driver source wire 87E. Similarly, the other further source pad 213F" of the first MOSFET transistor 53 which is not covered by the third contact element 81 is connected to the other of the second driver source conductivity regions 76F by the other second driver source wire 87F. The second driver source leads 77E, 77F are engaged to the second driver source conductivity regions 76E, 76F and form the driver source terminals 110, 112 of the bridge circuit 100. Figure 10B

[0075] Figure 10B

[0076] ​​​​​The gate pads 216A of the first and third MOSFET transistors 51, 53 also face the upper surfaces of these transistors 51, 53, laterally to the second and third contact elements 80, 81, and are connected to the second gate conductive regions 76C, 76D by the second gate wires 87C, 87D, respectively. The second gate leads 77C, 77D are bonded to the second gate conductive regions 76C, 76D and form the gate terminals 105, 107 of the bridge circuit 100.

[0077] On the side opposite the connection posts 67, 68 with respect to the MOSFET transistors 51-54, a third and fourth alignment and spacing structure 90 extends between the first and second support elements 56, 57. For example, as shown in Figure 9 、 Figure 10A and Figure 10B , the third and fourth alignment and spacing structure 90 each comprise a carrier post 91 extending from a second drain conductive region 76A (see Figure 10B ) on the second support element 57, towards the first support element 56 (in Figure 9 , downwards) and a second support region 92 formed on a respective insulating conductive region 58I, 58J. In the illustrated example, each second support region 92 is formed by a DBC multilayer.

[0078] A block 94 of thermally conductive material (e.g. copper) extends between the second conductive layer 60C of the first contact element 60 and the second conductive layers 80C, 81C of the second and third contact elements 80, 81 (see also Figure 13 ). Thus, the second conductive layers 60C, 80C, 81C are electrically and thermally connected to each other, but electrically insulated from the rest of the structure thanks to the insulating intermediate layers 60B, 80B, 81B. In this way, the assembly formed by the contact elements 60, 80, 81 and the block 94 forms a thermal distribution structure 95 inside the device 50, which is able to provide a smooth thermal distribution without discontinuities and avoids local hot spots.

[0079] An encapsulation substance 96 (see Figure 9 ) surrounds and contains the structure formed by the first support element 56, the second support element 57 and the alignment and spacing structures 89 and 90, the encapsulation substance 96 being flush with the first conductive layers 56A and 57A of the support elements 56 and 57, thus forming the device 50.

[0080] In the device 50, since both the first conductive layers 56A and 57A of the support elements 56 and 57 are exposed (in good thermal contact with the drain metallization 218 of the MOSFET transistors 51-54 through the DBC multilayer), the device 50 has thermal dissipation surfaces on both sides and therefore a high thermal dissipation capacity.

[0081] The alignment and spacing structures 89 and 90 in turn provide an optimal thermal conduction path, facilitating the transfer of heat from the MOSFET transistors 51-54 inside the device 50 to the outside.

[0082] As particularly indicated in the view of Figure 14A , Figure 14B Due to the arrangement of the two levels of integrated electronic components (here, MOSFET transistors 51-54), the structure is particularly compact.

[0083] The device 50 is assembled as follows. Initially, the first and second support elements 56, 57 are formed, and the components of the device 50 are joined on the first and second support elements 56, 57.

[0084] In particular, and not necessarily in the indicated order, the first support element 56 is shaped to form in the second conductive layer 56C the conductive regions 58A-58J of Figure 10A ; the second and third MOSFET transistors 52, 54 are joined by means of the adhesive regions 61A, 61B; the leads 59A-59H are soldered; the wiring 65C-65F is soldered; the second support region 92 is attached and the growth support column 91 is grown.

[0085] In addition, and not necessarily in the indicated order, the second support element 57 is shaped to form in the second conductive layer 57C the conductive regions 76A-76F of Figure 10B ; the first and second MOSFET transistors 51, 53 are joined by means of the adhesive regions 61C, 61D; the leads 77A-77F are soldered; the wiring 87C-87F is soldered; the first support region 85 is joined; the clamp elements 82, 83 are joined; and the growth connection columns 67, 68 are grown.

[0086] At the same time or earlier or later, the thermal distribution structure 95 (of Figure 9 ) is formed by joining the block 94 to the contact elements 60, 80, 81, respectively. As an indicated alternative, the clamp elements 82, 83 and the connection columns 67, 68 can be formed as part of the thermal distribution structure 95, instead of being joined in advance to the first and second MOSFET transistors 51, 53 and to the first support region 85.

[0087] Then, in the assembly example considered, the first support element 56 (and the relative structures attached thereto), the second support element 57 (and the relative structures attached thereto) and the heat distribution structure 95 are attached to each other by joining the carrier pillars 91 to the second support region 92, and joining the connection pillars 67, 68 to the clip elements 82, 83.

[0088] Finally, in a manner known per se, an encapsulating substance 96 is formed (e.g. molded) so that the leads 59A-59H and 77A-77F protrude beyond the encapsulating substance 96.

[0089] On one side of the first and third MOSFET transistors 51, 53, a "heat sink" (not shown) can be attached to the thus completed device 50, and the device 50 can be mounted on a carrier plate (not shown), with the second and fourth transistors 52, 54 arranged close to the carrier plate.

[0090] Figures 16-19 Details of the electrical connection between the contact pads 213A are shown.

[0091] In Figure 16 , the source windows 214 of the exposed source pads 213A (on the source passivation layer 213) Figure 8 are indicated with dashed lines. The windows 214 accommodate a filling region 70 of conductive material, which fills the source windows 214 and can slightly protrude beyond the source windows 214 before the attachment of the clip elements 82, 83 (only the first clip element 82 of the clip elements 82, 83 is visible in Figure 16 ). In particular, the attachment of the clip elements 82, 83 is obtained by a soldering process, for example by dispensing solder paste on an upper portion of the filling region 70 (a portion formed in a concave manner to avoid solder paste leakage), or, in case the clip elements 82, 83 are pre-joined to the contact elements 80, 81 to form the heat distribution structure 95, by dispensing solder paste on the faces of the clip elements 82 and 83 facing the first and second MOSFET transistors 51, 53. In this case, the metal material of the clip elements 82, 83 and the first source regions 58G, 58H are in direct contact with the filling region 70, forming the electrical connection of the source regions 213.

[0092] Figure 17 Details of the connection of the source pads 213A of the MOSFET transistors 51-54 using contact elements also for the first and third MOSFET transistors 51, 53 are shown. Thus, in this embodiment, there are no clip elements 82, 83, the first support region 85 is formed wider, extending beyond the second and third contact elements 80, 81, and the connection pillars 67, 68 (in Figure 17The first contact elements 60, 80, 81 are formed in the first support element 56, which is pre-bonded to the first support region 85 during manufacturing.

[0093] Additionally, in this embodiment, the first conductive layers 60A, 80A, 81A of the contact elements 60, 80, 81 are shaped so as to form a plurality of electrically connected protrusions 71 that enter the source windows 214 of the MOSFET transistors 51-54 (for the first and second MOSFET transistors 51, 52, as visible in Figure 17 ) and are bonded in direct electrical contact with the source pads 213A (as visible in Figure 8 ).

[0094] In this solution, the first conductive layers 60A, 80A, 81A of the contact elements 60, 80, 81 have a protrusion 72 at the protruding part of the first conductive layers 60A, 80A, 81A, wherein the first contact element 60 is in electrical contact with the coupling regions 64G, 64H, and the second and third contact elements 80, 81 are bonded to the first support region 85.

[0095] Additionally, here, the first and second conductive layers 80A, 81A, 80C, 81C of the second and third contact elements 80, 81 have the same thickness as the first and second conductive layers 60A, 61A of the first contact element 60.

[0096] In this way, in Figure 17 , the connection pillars 67, 68 form an electrical contact over the intermediate insulating layers 80B, 81B to create electrical continuity between the source metallization 213 (as visible in Figure 8 ) of the first and third MOSFET transistors 51, 53 and the drain leads 59A, 59B through the source windows 214, the protrusions 72, the connection pillars 67, 68, the first drain conductive regions 58A, 58B of the first support element 56.

[0097] Figure 18 A connection structure of the source pads 213A of the MOSFET transistors 51-54 is shown, similar to Figure 17 , wherein the first conductive layers 60A, 80A, 81A of all contact elements 60, 80, 81 are shaped to form protrusions 71, but the blocks 94 are replaced by an adhesive substance 93 (e.g. solder).

[0098] Figure 19 A connection structure of the source pads 213A of the MOSFET transistors 51-54 is shown, without the clamping elements, with the connection to the source metallization 213 directly formed by the contact elements 60, 80, 81 (as visible in Figure 18as in the case of the device 50), but the first conductive layer 60A, 80A, 81 A, which does not contact the elements 60, 80, 81, is shaped and comes into contact with the filling area 70 formed in the source window 214 (as in the case of the device 150). Figure 16

[0099] Figures 20A-20D Different packaged electronic devices are shown, indicated with 150. The device 150 has a structure and components similar to those of the device 50, except for the leads 59A-59H and the leads 77A-77F, which protrude beyond the housing of the device 150 to an upper region thereof, substantially aligned with the upper surface 150B (as in the case of the device 150). Figure 9 Figure 10A Figure 10B The device 150 has a structure and components similar to those of the device 50, except for the leads 59A-59H and the leads 77A-77F, which protrude beyond the housing of the device 150 to an upper region thereof, substantially aligned with the upper surface 150B (as in the case of the device 150). Figure 20D Therefore, in this case, when the device 150 is mounted on a carrier plate (not shown), the first and third MOSFET transistors 51, 53 (upper transistors of the bridge circuit 100) will be arranged close to the carrier plate, while the second and fourth transistors 52, 54 (lower transistors of the bridge circuit 100) will be arranged at a higher level with respect to the plane of the carrier plate, and can be in more direct thermal contact with any heat sink that can be arranged on the device 150.

[0100] Finally, it is clear that modifications and changes can be made to the packaged electronic devices described and illustrated herein and to the method of assembling them, without departing from the scope of the present disclosure. For example, the different embodiments described can be combined in order to provide further solutions.

[0101] For example, the above also applies to so-called "leadless" embodiments, in which the leads do not protrude to the outside, and only a small portion of the leads is not covered by the packaging substance 96 and is flush with the housing, to allow the device 50 to be mounted with "surface mounting" technology.

[0102] Additionally, clip elements can additionally or alternatively be provided between the source terminals of the second and third transistors 52, 54 and the first contact elements.

[0103] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above- described specific embodiments. In general, the selected terms used in the following claims are not to be construed as limiting the claims to the specific embodiments disclosed in the specification and claims. Rather, the claims should be construed in accordance with the full scope of equivalents, permissible under the patent laws, of all claims. Accordingly, the claims are not limited to the disclosed embodiments.​​​

Claims

1. A packaged power electronic device, comprising: a first support element having a first face and a second face, the first face of the first support element comprising a first heat dissipation surface of the device; a second support element having a first face and a second face, the first face of the second support element comprising a second heat dissipation surface of the device, the first and second support elements being stacked on each other with the respective second faces facing each other; a first power component attached to the second face of the second support element; a second power component attached to the second face of the first support element; a third power transistor attached to the second face of the second support element and alongside the first power component; a first contact element on the second power component; a second contact element on the first power component; a third contact element overlapping the third power transistor, the third contact element being arranged alongside and electrically insulated from the second contact element; a first lead electrically coupled with the first power component through the second support element; a second lead electrically coupled with the second power component through the first support element; and a thermally conductive body arranged between the first and second contact elements; wherein the first and second support elements, and the first and second contact elements, comprise multilayers that are electrically insulating and thermally conductive.

2. The device of claim 1, wherein the first and second support elements, and the first and second contact elements, are direct bonded copper (DBC) multilayers.

3. The device of claim 1, wherein the thermally conductive body comprises a block of conductive material.

4. The device of claim 1, wherein the thermally conductive body comprises an adhesive substance.

5. The device of claim 1, wherein the first and second support elements each comprise a first conductive layer, an intermediate layer, and a second conductive layer, the first conductive layers of the first and second support elements comprising the first and second heat dissipation surfaces of the device, respectively, and the second conductive layers of the first and second support elements comprising electrical contact areas for the first and second power components, respectively.

6. The device of claim 1, wherein the first and second power components are first and second power transistors, the device further comprising a fourth power transistor, and the fourth power transistor is attached to the second face of the first support element, wherein: the first contact element overlaps and electrically contacts the second and fourth power transistors; the second contact element overlaps and electrically contacts the first power transistor; the third contact element electrically contacts the third power transistor, the third contact element comprising multilayers that are electrically insulating and thermally conductive. ​ 7. The device of claim 6, wherein: the first, second, third, and fourth power transistors are electrically connected to form a full bridge, and each have a first conduction terminal, a second conduction terminal, and a control terminal; the first contact element comprises a first conductive layer in direct electrical contact with the first conduction terminals of the second and fourth power transistors; the second contact element comprises a first conductive layer electrically coupled to the first conduction terminal of the first power transistor; and the third contact element comprises a first conductive layer electrically coupled to the first conduction terminal of the third power transistor.

8. The device of claim 7, further comprising: first and second wiring lines; and first and second coupling regions extending between the first support element and the first contact element, wherein: the first and second support elements each comprise a first conductive layer, an intermediate layer, and a second conductive layer; the first conductive layers of the first and second support elements comprise first and second heat dissipation surfaces of the device, respectively; the second conductive layers of the first and second support elements comprise electrical contact regions for the first and second power components; and the second conductive layer of the first support element comprises: first and second conductive regions in electrical contact with the second conduction terminals of the second and fourth power transistors, respectively, third and fourth conductive regions coupled to the control terminals of the second and fourth power transistors, respectively, through the first and second wiring lines, respectively, and fifth and sixth conductive regions coupled to the first conductive layer of the first contact element through the first and second coupling regions, respectively.

9. The device of claim 8, further comprising: third and fourth wiring lines; and first and second post elements of conductive material, wherein: the second conductive layer of the second support element comprises seventh, eighth, and ninth conductive regions, the seventh conductive region in electrical contact with the second conduction terminals of the first and third power transistors, and the eighth and ninth conductive regions coupled to the control terminals of the first and third power transistors through the third and fourth wiring lines, respectively; and the first conductive layers of the second and third contact elements are coupled to the fifth and sixth conductive regions of the first support element through the first and second post elements, respectively.

10. The apparatus of claim 9, wherein the apparatus further comprises first and second clip element of electrically conductive material, the first clip element extending between the first conductive layer of the second contact element and the first power transistor, the second clip element extending between the first conductive layer of the third contact element and the third power transistor, the first clip element having a first protruding portion extending beyond the first power transistor and electrically coupled to the first post element, and the second clip element having a second protruding portion extending beyond the third power transistor and electrically coupled to the second post element.

11. The apparatus of claim 10, wherein the second and third contact elements are longer than the first and third power transistors, the second contact element comprises a first protruding portion coupled to the first post element, and the third contact element comprises a second protruding portion coupled to the second post element.

12. The apparatus of claim 10, further comprising: a first support post portion extending between the first protruding portion of the first clip element and the second support element and aligned with the first post element; a second support post portion extending between the second protruding portion of the second clip element and the second support element and aligned with the second post element, wherein the first and second support post portions each comprise a plurality of layers that are electrically insulating and thermally conductive, and the first support post portion and the first post element form a first alignment and spacing structure, and the second support post portion and the second post element form a second alignment and spacing structure.

13. The apparatus of claim 12, wherein the first and second support elements each have an elongated shape having a first longitudinal end and a second longitudinal end, wherein the first and second alignment and spacing structures are disposed proximate the first longitudinal end of the first and second support elements, respectively, the apparatus comprising: a third alignment and spacing structure extending proximate the second longitudinal end of the first support element and comprising a third support post portion and a first support post element aligned with each other; and a fourth alignment and spacing structure extending proximate the second longitudinal end of the second support element and comprising a fourth support post portion and a second support post element aligned with each other, the third and fourth support post portions each comprising a plurality of layers that are electrically insulating, the first and second support post elements being of conductive material.

14. The apparatus of claim 9, comprising: a first plurality of leads attached to the first, second, third, fourth, fifth, and sixth conductive regions of the first support element; a second plurality of leads attached to the first, second, third, fourth, fifth, and sixth conductive regions of the second support element. and a second plurality of leads attached to the seventh conductive region, the eighth conductive region, and the ninth conductive region of the second support element.

15. A method for assembling a packaged power electronic device, comprising: arranging a first support element and a second support element, the first support element and the second support element each having a first face and a second face, and being formed of a plurality of layers that are electrically insulating and thermally conductive; bonding a first electronic component to the second face of the second support element, and bonding a second electronic component to the second face of the first support element; bonding a first lead on the second face of the second support element, and bonding a second lead on the second face of the first support element; forming a thermal distribution structure, the thermal distribution structure comprising a first contact element and a second contact element, and an intermediate substance, the first contact element and the second contact element each comprising a plurality of layers that are electrically insulating and thermally conductive, the first contact element being arranged on a first side of the intermediate substance, and the second contact element being arranged on a second side of the intermediate substance, wherein forming the thermal distribution structure comprises: attaching a third contact element to the second side of the intermediate substance, the third contact element being adjacent to and electrically insulating from the second contact element, the third contact element being formed of a plurality of layers that are electrically insulating and thermally conductive; bonding a third power transistor to the second face of the second support element, bonding the first contact element of the thermal distribution structure to the second electronic component, bonding the second contact element of the thermal distribution structure to the first electronic component, and coupling the third contact element to the third power transistor; and forming an encapsulation substance, the encapsulation substance surrounding the thermal distribution structure, and the first support element and the second support element, the first face of the first support element forming a first thermal dissipation surface of the device, the first face of the second support element forming a second thermal dissipation surface of the device.

16. The method of claim 15, wherein disposing the first support element and the second support element comprises: shaping the second faces of the first support element and the second support element to form electrically conductive regions.

17. The method of claim 15, wherein the first electronic component is a first power transistor, and the second electronic component is a second power transistor; the method further comprising: bonding a fourth power transistor to the second face of the first support element, prior to bonding the first contact element and the second contact element to the first electronic component and the second electronic component.

18. A packaged power electronic device, comprising: a first support element having a first face and a second face, the first face of the first support element comprising a first thermal dissipation surface of the device; a second support element having a first face and a second face, the first face of the second support element comprising a second thermal dissipation surface of the device, the first support element and the second support element being superposed to each other with the respective second faces facing each other; a first power component attached to the second face of the second support element; a second power component attached to the second face of the first support element; a third power transistor attached to the second face of the second support element and alongside the first power component; a first contact element on the second power component; a second contact element on the first power component; a third contact element overlapping the third power transistor, the third contact element being arranged alongside and electrically insulated from the second contact element; and a thermally conductive body arranged between the first and second contact elements; wherein the first and second support elements, and the first and second contact elements, comprise multiple layers that are electrically insulating and thermally conductive.

19. The device of claim 18, wherein the first and second support elements each comprise a first conductive layer, an intermediate layer, and a second conductive layer, the first conductive layers of the first and second support elements comprising the first and second heat dissipation surfaces of the device, respectively, and the second conductive layers of the first and second support elements forming electrical contact areas for the first and second power components, respectively.

20. The device of claim 18, wherein the first and second power components are first and second power transistors, the device comprises a fourth power transistor, and the fourth power transistor is attached to the second face of the first support element, wherein: the first contact element overlaps and is in electrical contact with the second and fourth power transistors; the second contact element overlaps and is in electrical contact with the first power transistor; the third contact element overlaps and is in electrical contact with the third power transistor, the third contact element comprising multiple layers that are electrically insulating and thermally conductive.

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