Non-volatile memory device

Abstract

A nonvolatile memory device having improved operating performance and reliability is provided. The nonvolatile memory device includes a substrate, a peripheral circuit structure on the substrate, a mold structure including a plurality of insulating patterns and a plurality of gate electrodes alternately stacked on the peripheral circuit structure, a channel structure passing through the mold structure, a first impurity pattern contacting a first portion of the channel structure on the mold structure and having a first conductivity type, and a second impurity pattern contacting a second portion of the channel structure on the mold structure and having a second conductivity type different from the first conductivity type.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0093632, filed on August 1, 2019, with the Korean Intellectual Property Office, the contents of which are incorporated herein by reference. Technical Field

[0003] This invention relates to a non-volatile memory device and a method for manufacturing the same. More specifically, this invention relates to a non-volatile memory device having a COP (Cell on Peripheral) structure and a method for manufacturing the same. Background Technology

[0004] To meet consumer demands for high performance and low cost, the integration density of non-volatile memory devices is continuously increasing. In the case of two-dimensional or planar memory devices, the integration density is determined by the area occupied by a single memory cell. Therefore, three-dimensional memory devices with vertically arranged single memory cells have been developed.

[0005] To further improve the integration density of non-volatile memory devices, a COP (cell on peripheral) structure with cell arrays located on peripheral circuitry has been studied. Summary of the Invention

[0006] Some embodiments of the present invention provide a non-volatile memory device with improved operational performance and reliability.

[0007] Some embodiments of the present invention provide a method for manufacturing a non-volatile memory device with improved operational performance and reliability.

[0008] However, some embodiments of the inventive concept are not limited to those described herein. The above and other aspects of the inventive concept will become more apparent to one skilled in the art from the following detailed description of the inventive concept.

[0009] According to some embodiments of the present invention, a non-volatile memory device is provided, the non-volatile memory device comprising: a substrate; a peripheral circuit structure on the substrate; a molding structure including a plurality of insulating patterns and a plurality of gate electrodes alternately stacked on the peripheral circuit structure; a channel structure passing through the molding structure; a first impurity pattern on the molding structure contacting a first portion of the channel structure and having a first conductivity type; and a second impurity pattern on the molding structure contacting a second portion of the channel structure and having a second conductivity type different from the first conductivity type.

[0010] According to some embodiments of the present invention, a non-volatile memory device is provided, comprising: a substrate; an interlayer insulating layer on the substrate; a bit line extending in the interlayer insulating layer in a first direction; a molding structure including a plurality of insulating patterns and a plurality of gate electrodes alternately stacked on the interlayer insulating layer; a channel structure passing through the molding structure and connected to the bit line; and a source structure contacting the upper portion of the channel structure on the molding structure. The source structure includes a first impurity pattern overlapping a first region of the channel structure, a second impurity pattern overlapping a second region of the channel structure, and a separation pattern overlapping a third region of the channel structure and separating the first impurity pattern from the second impurity pattern.

[0011] According to some embodiments of the present invention, a non-volatile memory device is provided, the non-volatile memory device comprising: a substrate; a peripheral circuit structure on the substrate; a bit line extending in a first direction on the peripheral circuit structure; a molding structure including a plurality of insulating patterns and a plurality of gate electrodes alternately stacked on the bit line; a plurality of channel structures passing through the molding structure, the lower portion of each of the channel structures being connected to the bit line; and a source structure connected to the upper portion of each of the channel structures on the molding structure, wherein the source structure includes a first impurity pattern overlapping a first region of each of the channel structures, a second impurity pattern overlapping a second region of each of the channel structures, and a separation pattern overlapping a third region of each of the channel structures and separating the first impurity pattern from the second impurity pattern, the first impurity pattern comprising an n-type impurity, and the second impurity pattern comprising a p-type impurity. Attached Figure Description

[0012] These and / or other aspects will become clearer and more readily understood from the following description of embodiments taken in conjunction with the accompanying drawings, in which:

[0013] Figure 1 This is a layout diagram used to explain a non-volatile memory device according to some embodiments;

[0014] Figure 2 It is along Figure 1 A sectional view taken by line AA;

[0015] Figure 3 yes Figure 2 A magnified view of region R1;

[0016] Figures 4A to 4E It is enlarged. Figure 2 Various magnified images of region R2;

[0017] Figure 5 It is along Figure 1 A sectional view taken by line BB;

[0018] Figure 6 It is along Figure 1 A cross-sectional view taken by line CC;

[0019] Figure 7 This is a layout diagram used to explain a non-volatile memory device according to some embodiments;

[0020] Figure 8 This is a layout diagram used to explain a non-volatile memory device according to some embodiments;

[0021] Figure 9 This is a layout diagram used to explain a non-volatile memory device according to some embodiments;

[0022] Figure 10 This is a layout diagram used to explain a non-volatile memory device according to some embodiments;

[0023] Figures 11 to 16 This is an intermediate stage diagram used to explain an example method for manufacturing a non-volatile memory device according to some embodiments. Detailed Implementation

[0024] In a COP (Cellular Plug-in) structure, more cell arrays can be integrated within the same region by positioning the peripheral circuitry already arranged around the cell array between the cell array and the substrate. The following will refer to... Figures 1 to 10 Describes a non-volatile memory device according to some embodiments.

[0025] Figure 1 This is a layout diagram used to explain a non-volatile memory device according to some embodiments. Figure 2 It is along Figure 1 The sectional view taken by line AA. Figure 3 yes Figure 2 An enlarged view of region R1. Figures 4A to 4E It is enlarged. Figure 2 Various magnified images of region R2. Figure 5 It is along Figure 1 The sectional view taken by line BB. Figure 6 It is along Figure 1 The sectional view taken by the CC line.

[0026] Reference Figures 1 to 6 A non-volatile memory device according to some embodiments includes a substrate 10, a peripheral circuit structure PS, a molded structure MS, a plurality of channel structures CS, a plurality of bit lines BL, and a source structure 200.

[0027] For example, substrate 10 may include a semiconductor substrate such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate. In some embodiments, substrate 10 may include a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, etc. For example, substrate 10 may be (but is not limited to) a p-type semiconductor substrate.

[0028] The substrate 10 may include a cell array region CAR and a contact region CTR.

[0029] A memory cell array comprising multiple memory cells can be formed in a cell array region (CAR). The memory cell array may include multiple memory cells and multiple word lines and multiple bit lines electrically connected to each memory cell. For example, the bit line BL, molding structure MS, channel structure CS, and source structure 200, described below, can be formed in the cell array region (CAR).

[0030] The contact area (CTR) can be located around the cell array area (CAR). For example, memory cell contacts 310 and through-hole vias (THVs) can be formed in the contact area (CTR).

[0031] The peripheral circuit structure PS can be formed on the substrate 10. The peripheral circuit structure PS may include peripheral circuitry that controls the operation of each memory cell. For example, the peripheral circuit structure PS may include a row decoder, a column decoder, a page buffer, control circuitry, etc. Figure 5 As shown, the peripheral circuit structure PS may include peripheral circuit elements PT and wiring structure PW.

[0032] In some embodiments, the peripheral circuit element PT may include a transistor. For example, the peripheral circuit element PT may include a peripheral circuit gate electrode 12, a peripheral circuit gate insulating layer 14, a source / drain region 16, and a gate spacer 18.

[0033] The peripheral circuit gate electrode 12 may be formed on the substrate 10. For example, the peripheral circuit gate electrode 12 may include (but is not limited to) at least one of silicon (e.g., polycrystalline silicon), metal silicide (e.g., tungsten silicide (WSi), nickel silicide (NiSi), cobalt silicide (CoSi), titanium silicide (TiSi), tantalum silicide (TaSi)), or metal (e.g., tungsten (W) or aluminum (Al)). In some embodiments, the peripheral circuit gate electrode 12 may be formed of multiple conductive layers.

[0034] The peripheral circuit gate insulating layer 14 may be disposed between the substrate 10 and the peripheral circuit gate electrode 12. For example, the peripheral circuit gate insulating layer 14 may extend along the upper surface of the substrate 10. For example, the peripheral circuit gate insulating layer 14 may include (but is not limited to) at least one of silicon oxide, silicon nitride, silicon oxynitride, and / or a high dielectric constant material with a dielectric constant higher than that of silicon oxide.

[0035] The source / drain region 16 can be formed in the substrate 10 on both sides of the gate electrode 12 of the peripheral circuit. The source / drain region 16 can be doped with impurities. For example, when the peripheral circuit element PT is an n-type (or p-type) transistor, the source / drain region 16 can be doped with n-type (or p-type) impurities.

[0036] Gate spacers 18 may be formed on both sides of the peripheral circuit gate electrode 12. For example, the peripheral circuit gate electrode 12 and the peripheral circuit gate insulating layer 14 may be formed to fill or at least partially fill the trench formed through the upper surface of the substrate 10 and the inner surface of the gate spacers 18.

[0037] In some embodiments, the peripheral circuit element PT may be a high-voltage transistor. While the peripheral circuit element PT is described only as a transistor, this is merely an example, and the technical concept of the invention is not limited thereto. For example, the peripheral circuit element PT includes not only various active elements such as transistors, but also various passive elements such as capacitors, resistors, and inductors.

[0038] In some embodiments, the peripheral circuit element PT may include a well bias driver. The well bias driver can provide the erase voltage required for the erase operation of each memory cell to the channel structure CS.

[0039] In some embodiments, a first interlayer insulating layer 20 may be formed on the substrate 10. The first interlayer insulating layer 20 may be formed to cover or overlap with peripheral circuit elements PT on the substrate 10. Although the first interlayer insulating layer 20 is shown as a single layer, this is only for ease of explanation, and the first interlayer insulating layer 20 may of course be a multilayer in which multiple insulating layers are stacked. For example, the first interlayer insulating layer 20 may include (but is not limited to) silicon oxide.

[0040] The wiring structure PW may include peripheral circuit wiring 22 and peripheral circuit contacts 24. For example, the peripheral circuit wiring 22 and peripheral circuit contacts 24 may be formed in the first interlayer insulating layer 20. The peripheral circuit wiring 22 can be connected to the peripheral circuit element PT through the peripheral circuit contacts 24.

[0041] For example, peripheral circuit wiring 22 may include (but is not limited to) metal (e.g., copper (Cu) or aluminum (Al)). For example, peripheral circuit contact 24 may include (but is not limited to) silicon (e.g., polysilicon) or metal (e.g., tungsten (W) or copper (Cu)).

[0042] A molded structure MS can be formed on a peripheral circuit structure PS. For example, the molded structure MS can be formed on a first interlayer insulating layer 20. That is, the peripheral circuit structure PS can be situated between the substrate 10 and the molded structure MS. The molded structure MS may include a plurality of gate electrodes SSL, DM1, WL1 to WLn, DM2 and GSL stacked on the peripheral circuit structure PS, as well as a plurality of insulating patterns 110. Each of the gate electrodes SSL, DM1, WL1 to WLn, DM2 and GSL, and each insulating pattern 110 may be a stacked structure extending in a first direction X and a second direction Y intersecting the first direction X.

[0043] The corresponding gate electrodes SSL, DM1, WL1 to WLn, DM2, and GSL can be stacked alternately with the corresponding insulating pattern 110. For example, the gate electrodes SSL, DM1, WL1 to WLn, DM2, and GSL are spaced apart from each other along a third direction Z intersecting the upper surface of the substrate 10, and can be stacked sequentially. In this case, the insulating pattern 110 can be located between the gate electrodes SSL, DM1, WL1 to WLn, DM2, and GSL. That is, the gate electrodes SSL, DM1, WL1 to WLn, DM2, and GSL can be electrically separated from each other by the insulating pattern 110.

[0044] exist Figure 2 , Figure 5 and Figure 6 In this example, although gate electrodes SSL, DM1, WL1 to WLn, DM2, and GSL are shown to have the same thickness, this is merely an example. For instance, gate electrodes SSL, DM1, WL1 to WLn, DM2, and GSL can have different thicknesses than each other.

[0045] In some embodiments, the gate electrodes SSL, DM1, WL1 to WLn, DM2, and GSL may include a serial select line SSL, multiple word lines WL1 to WLn, and a ground select line GSL. The serial select line SSL, multiple word lines WL1 to WLn, and ground select line GSL may be stacked sequentially on the substrate 10.

[0046] The serial select line SSL can be used as the gate electrode of the serial select transistor that controls the electrical connection between the bit line BL and each channel structure CS. Multiple word lines WL1 to WLn can be used as the gate electrodes of the memory cell transistors that control the corresponding memory cells. That is, multiple word lines WL1 to WLn, together with the channel structures CS, can form multiple memory cells. The ground select line GSL can be used as the gate electrode of the ground select transistor that controls the electrical connection between the source structure 200 and each channel structure CS.

[0047] Although three word lines are shown between the Serial Select line (SSL) and the Ground Select line (GSL), this is only for ease of explanation. For example, eight, sixteen, thirty-two, sixty-four, or more word lines can certainly be stacked between the Serial Select line (SSL) and the Ground Select line (GSL).

[0048] Additionally, although the molded structure MS is simply shown as having one string select line SSL and one ground select line GSL, this is for ease of explanation. For example, of course, the molded structure MS can have two or more string select lines SSL or two or more ground select lines GSL.

[0049] In some embodiments, the molded structure MS may further include a first dummy line DM1 and / or a second dummy line DM2. For example, the first dummy line DM1 may be located between the string select line SSL and multiple word lines WL1 to WLn. For example, the second dummy line DM2 may be located between the ground select line GSL and multiple word lines WL1 to WLn. In a non-volatile memory device according to some embodiments, the first dummy line DM1 and the second dummy line DM2 may not be used as string select lines, word lines, or ground select lines.

[0050] Each of the gate electrodes SSL, DM1, WL1 through WLn, DM2, and GSL may include a conductive material. For example, each of the gate electrodes SSL, DM1, WL1 through WLn, DM2, and GSL may include (but is not limited to) metals such as tungsten (W), cobalt (Co), and nickel (Ni) or semiconductor materials such as silicon.

[0051] Each insulating pattern 110 may include an insulating material. For example, each insulating pattern 110 may include (but is not limited to) silicon oxide.

[0052] In some embodiments, the second interlayer insulating layer 30 may be formed on the first interlayer insulating layer 20. The second interlayer insulating layer 30 may be formed to cover at least a portion of the molded structure MS or to overlap at least a portion of the molded structure MS. Although the second interlayer insulating layer 30 is shown as a single layer, this is only for ease of explanation, and the second interlayer insulating layer 30 may of course be a multilayer in which multiple insulating layers are stacked. For example, the second interlayer insulating layer 30 may include (but is not limited to) silicon oxide.

[0053] In some embodiments, such as Figure 2 As shown, memory cell contacts 310 and first upper wiring 315 can be formed to connect to the respective gate electrodes SSL, DM1, WL1 to WLn, DM2 and GSL. The memory cell contacts 310 can be formed on the ends of each of the gate electrodes SSL, DM1, WL1 to WLn, DM2 and GSL. For example, the memory cell contacts 310 can be formed on the contact area CTR.

[0054] The memory cell contact 310 can be configured to connect to the respective gate electrodes SSL, DM1, WL1 to WLn, DM2 and GSL. For example, the memory cell contact 310 can pass through the second interlayer insulating layer 30 and connect to the respective gate electrodes SSL, DM1, WL1 to WLn, DM2 and GSL.

[0055] The first upper wiring 315 can be formed on the memory cell contact 310. For example, the first upper wiring 315 can be formed in the third interlayer insulating layer 40 on the second interlayer insulating layer 30. Therefore, the first upper wiring 315 can be electrically connected to the corresponding gate electrodes SSL, DM1, WL1 to WLn, DM2 and GSL to apply a gate voltage to the corresponding gate electrodes SSL, DM1, WL1 to WLn, DM2 and GSL.

[0056] In some embodiments, a through-hole THV and a second upper wiring 325 may be formed to connect to the peripheral circuit structure PS. For example, the through-hole THV may pass through the second interlayer insulating layer 30 and connect to the wiring structure PW. The second upper wiring 325 may be formed on the through-hole THV. For example, the second upper wiring 325 may be formed in the third interlayer insulating layer 40.

[0057] For example, the first upper wiring 315 and the second upper wiring 325 may include (but are not limited to) metals (e.g., copper (Cu) or aluminum (Al)). For example, the memory cell contact 310 and the through-hole THV may include (but are not limited to) silicon (e.g., polysilicon) or metals (e.g., tungsten (W) or copper (Cu)).

[0058] In some embodiments, the molded structure MS can be cut by the word line cutting region WLc. For example, as Figure 1 , Figure 5 and Figure 6 As shown, the word line cutting area WLc can extend in the second direction Y and cut the molded structure MS.

[0059] In some embodiments, an insulating structure 150 may be formed in the word line cutting region WLc. The insulating structure 150 may be formed to fill the word line cutting region WLc. For example... Figure 5 and Figure 6 As shown, the insulating structure 150 can penetrate the molded structure MS and extend to the first interlayer insulating layer 20. Therefore, the insulating structure 150 extends in the second direction Y and can cut through the molded structure MS.

[0060] For example, the insulating structure 150 may include (but is not limited to) at least one of silicon oxide, silicon nitride, silicon oxynitride, and / or a high dielectric constant material with a dielectric constant higher than that of silicon oxide.

[0061] Multiple channel structures CS can extend through the molded structure MS. Furthermore, the multiple channel structures CS can extend in directions intersecting with multiple gate electrodes SSL, DM1, WL1 to WLn, DM2, and GSL. For example, each channel structure CS can have a cylindrical shape (e.g., a cylinder) extending in a third direction Z. Each channel structure CS can include a semiconductor pattern 120 and an information storage layer 130.

[0062] Semiconductor pattern 120 may extend through the molded structure MS. For example, semiconductor pattern 120 may extend in the third direction Z. Although semiconductor pattern 120 is shown as cup-shaped, this is only an example. For example, semiconductor pattern 120 may have various shapes such as cylindrical, square, and solid column.

[0063] For example, semiconductor pattern 120 may include (but is not limited to) semiconductor materials such as monocrystalline silicon, polycrystalline silicon, organic semiconductor materials, and carbon nanostructures.

[0064] Information storage layer 130 may be located between semiconductor pattern 120 and each of gate electrodes SSL, DM1, WL1 to WLn, DM2 and GSL. For example, information storage layer 130 may extend along the side surface of semiconductor pattern 120.

[0065] For example, the information storage layer 130 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a high dielectric constant material with a dielectric constant higher than that of silicon oxide. The high dielectric constant material may include at least one of aluminum oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, lanthanum hafnium oxide, lanthanum aluminum oxide, dysprosium scandium oxide, and / or combinations thereof.

[0066] In some embodiments, the information storage layer 130 may include multiple layers. For example, such as Figure 3 As shown, the information storage layer 130 may include a tunnel insulating layer 132, a charge storage layer 134 and a first barrier insulating layer 136 sequentially stacked on the semiconductor pattern 120.

[0067] For example, tunnel insulation layer 132 may include silicon oxide or a high dielectric constant material with a dielectric constant higher than that of silicon oxide (e.g., aluminum oxide (Al2O3) and hafnium oxide (HfO2)). For example, charge storage layer 134 may include silicon nitride. For example, first barrier insulation layer 136 may include silicon oxide or a high dielectric constant material with a dielectric constant higher than that of silicon oxide (e.g., aluminum oxide (Al2O3) and hafnium oxide (HfO2)).

[0068] In some embodiments, each channel structure CS may further include a second barrier insulating layer 138. The second barrier insulating layer 138 may be located between the information storage layer 130 and the respective gate electrodes SSL, DM1, WL1 to WLn, DM2 and GSL. For example, the second barrier insulating layer 138 may extend along the side surface of each of the gate electrodes SSL, DM1, WL1 to WLn, DM2 and GSL.

[0069] In some embodiments, the second barrier insulating layer 138 may extend along the upper and lower surfaces of each of the gate electrodes SSL, DM1, WL1 to WLn, DM2 and GSL. Therefore, the second barrier insulating layer 138 may be located between each of the gate electrodes SSL, DM1, WL1 to WLn, DM2 and GSL and the respective insulating pattern 110.

[0070] In some embodiments, each channel structure CS may further include a filled insulating pattern 140. The filled insulating pattern 140 may be formed to fill the interior of a cup-shaped semiconductor pattern 120. For example, the semiconductor pattern 120 may extend along the side and bottom surfaces of the filled insulating pattern 140. For example, the filled insulating pattern 140 may include (but is not limited to) silicon oxide.

[0071] In some embodiments, a plurality of channel structures CS can be repeatedly arranged along a first direction X and a second direction Y. For example, as Figure 1 As shown, some portions of the multiple channel structures CS can be arranged along the first direction X to form a first channel group CG1. Furthermore, some other portions of the multiple channel structures CS can be arranged along the first direction X to form a second channel group CG2. The first channel group CG1 and the second channel group CG2 can be arranged side-by-side to be adjacent to each other. For example, the second channel group CG2 can be adjacent to the first channel group CG1 in the second direction Y.

[0072] In some embodiments, multiple channel structures CS can be arranged in a zigzag pattern. For example, as Figure 1 As shown, the channel structures CS constituting the first channel group CG1 and the channel structures CS constituting the second channel group CG2 can be arranged to intersect each other in the second direction Y. A plurality of channel structures CS arranged in a zigzag pattern can further improve the integration density of the non-volatile memory device according to some embodiments.

[0073] exist Figure 1In this example, although the number of channel structures CS constituting or forming the first channel group CG1 (e.g., four) is shown to be less than the number of channel structures CS constituting or forming the second channel group CG2 (e.g., five), this is merely an example. For instance, even if multiple channel structures CS are arranged in a zigzag pattern, the number of channel structures CS constituting or forming the first channel group CG1 can be equal to the number of channel structures CS constituting or forming the second channel group CG2.

[0074] Multiple bit lines BL can be arranged in two dimensions. For example, corresponding bit lines BL can be spaced apart from each other and extend side by side in a first direction X. Since the word line cut-off region WLc can extend in a second direction Y, each bit line BL can intersect with the word line cut-off region WLc.

[0075] The channel structure CS can be connected to each bit line BL. For example, each bit line BL can be connected to each channel structure CS through bit line contact Blc.

[0076] In some embodiments, bit lines BL can be formed below the molded structure MS. That is, bit lines BL can be located between the substrate 10 and the molded structure MS. For example, bit lines BL and bit line contacts BLc can be formed in the first interlayer insulating layer 20. Bit line contacts BLc can be located between the channel structure CS and the bit lines BL and connect the semiconductor pattern 120 to the bit lines BL. Therefore, each bit line BL can be connected to the lower part of the semiconductor pattern 120.

[0077] In some embodiments, the pillar 105 may be formed between the channel structure CS and the bit line BL. For example, the pillar 105 may be formed in the first interlayer insulating layer 20. The pillar 105 can connect the channel structure CS and the bit line BL. For example, the upper surface of the pillar 105 may contact the lower surface of the semiconductor pattern 120, and the lower surface of the pillar 105 may contact the upper surface of the bit line contact BLc. For example, the pillar 105 may include (but is not limited to) polysilicon.

[0078] In some embodiments, the width of the post 105 may be greater than the width of the channel structure CS and the width of the bit line contact BLc. Therefore, the post 105 can stably connect the semiconductor pattern 120 to the bit line contact BLc.

[0079] The source structure 200 can be formed on the molded structure MS. Alternatively, the source structure 200 can be formed on the cell array region CAR and can be connected to the upper part of each channel structure CS.

[0080] The source structure 200 may include a first impurity pattern 210 and a second impurity pattern 220. The first impurity pattern 210 may be connected to some portions of the respective channel structures CS, and the second impurity pattern 220 may be connected to other portions of the respective channel structures CS. In some embodiments, the first impurity pattern 210 and the second impurity pattern 220 may be in contact with the upper surface of the semiconductor pattern 120.

[0081] In some embodiments, the first impurity pattern 210 may have a first conductivity type, and the second impurity pattern 220 may have a second conductivity type different from the first conductivity type. Hereinafter, for ease of explanation, it is assumed that the first impurity pattern 210 includes n-type impurities and the second impurity pattern 220 includes p-type impurities. However, this is merely an example, and the technical concept of the invention is not limited thereto. For example, it is natural that the first impurity pattern 210 may include p-type impurities, and the second impurity pattern 220 may include n-type impurities.

[0082] In some embodiments, the upper surface of the first impurity pattern 210 may be disposed on the same plane as the upper surface of the second impurity pattern 220. In this specification, the term "identical" means not only completely identical, but also that there may be minor differences due to factors such as processing allowance. In other words, the term "identical" may include substantially identical or similar elements.

[0083] In some examples, source structure 200 may also include a separation pattern 230. The separation pattern 230 may be located between the first impurity pattern 210 and the second impurity pattern 220 to separate the first impurity pattern 210 and the second impurity pattern 220.

[0084] The separation pattern 230 may include an insulating material. For example, the separation pattern 230 may include (but is not limited to) at least one of silicon oxide, silicon nitride, and / or silicon oxynitride.

[0085] In some embodiments, the upper surface of the first impurity pattern 210 and the upper surface of the second impurity pattern 220 may be disposed on the same plane as the upper surface of the separation pattern 230.

[0086] In some embodiments, the first impurity pattern 210 may overlap with some portions of the respective channel structures CS, and the second impurity pattern 220 may overlap with some other portions of the respective channel structures CS. Here, the term "overlap" means overlap in a third direction Z intersecting with the upper surface of the substrate 10.

[0087] For example, such as Figure 1 and Figure 4AAs shown, each channel structure CS may include a first region CSa, a second region CSb, and a third region CSc, which are distinct from each other from a planar perspective. The third region CSc may lie between the first region CSa and the second region CSb. In this case, the first impurity pattern 210 may overlap with the first region CSa of each channel structure CS, and the second impurity pattern 220 may overlap with the second region CSb of each channel structure CS. The separation pattern 230 may overlap with the third region CSc of each channel structure CS.

[0088] In some embodiments, a first impurity pattern 210 having a first conductivity type (e.g., n-type) can be used as a common source line (CSL). For example, during a read or write operation of a non-volatile memory device according to some embodiments, a ground voltage can be applied to the first impurity pattern 210.

[0089] In some embodiments, a second impurity pattern 220 having a second conductivity type (e.g., p-type) can be used for erase operations of a non-volatile memory device according to some embodiments. For example, during an erase operation of a non-volatile memory device according to some embodiments, an erase voltage can be applied to the second impurity pattern 220.

[0090] In a non-volatile memory device according to some embodiments, since the second impurity pattern 220 has a second conductivity type (e.g., p-type) different from the first conductivity type (e.g., n-type) of the first impurity pattern 210, it is possible to reduce the power consumption of the erase operation of the non-volatile memory device and improve the erase reliability. For example, during the erase operation of the non-volatile memory device according to some embodiments, holes can be smoothly supplied to each channel structure CS by means of the second impurity pattern 220 including p-type impurities. As a result, a non-volatile memory device with improved operating performance and reliability can be provided.

[0091] In a non-volatile memory device according to some embodiments, the separation pattern 230 can prevent the formation of a PN junction between a first impurity pattern 210 and a second impurity pattern 220 that have different conductivity types. That is, the separation pattern 230 can prevent junction leakage current from occurring between the first impurity pattern 210 and the second impurity pattern 220, thereby reducing the impedance of the second impurity pattern 220. For example, during the erase operation of the non-volatile memory device according to some embodiments, holes can be rapidly supplied to each channel structure CS through the second impurity pattern 220, which includes p-type impurities. As a result, a non-volatile memory device with improved operating performance and reliability can be provided.

[0092] In some embodiments, the side surfaces of the first impurity pattern 210 may have curved surfaces. For example, as... Figure 4BAs shown, the first impurity pattern 210 may include a first side surface 210S, which includes a curved surface. In some embodiments, the first side surface 210S may be a concave surface.

[0093] In some embodiments, the separation pattern 230 and the second impurity pattern 220 may have shapes corresponding to the first side surface 210S. For example, the separation pattern 230 may extend along the contour of the concave first side surface 210S and have a curved shape. Alternatively, for example, the second impurity pattern 220 may include a second side surface 220S facing the first side surface 210S. The second side surface 220S may extend along the contour of the concave first side surface 210S and have a convex shape.

[0094] In some embodiments, the side surface of the first impurity pattern 210 may have a bevel. For example, as... Figure 4C As shown, the first side surface 210S of the first impurity pattern 210 may have a slope relative to the upper surface of the channel structure CS. In some embodiments, the first side surface 210S may form an acute angle relative to the upper surface of the channel structure CS.

[0095] In some embodiments, the separation pattern 230 and the second impurity pattern 220 may have a shape corresponding to the first side surface 210S. For example, the separation pattern 230 may extend along the contour of the first side surface 210S having a slope and have a slope. Alternatively, for example, the second side surface 220S may extend along the contour of the first side surface 210S forming an acute angle with respect to the upper surface of the channel structure CS, and form an obtuse angle with respect to the upper surface of the channel structure CS.

[0096] In some embodiments, the size of the region where the first impurity pattern 210 overlaps with the channel structure CS can be different from the size of the region where the second impurity pattern 220 overlaps with the channel structure CS. For example, as Figure 4D and Figure 4E As shown, the size of the first region CSa that overlaps with the first impurity pattern 210 can be different from the size of the second region CSb that overlaps with the second impurity pattern 220.

[0097] For example, such as Figure 4D As shown, in the second direction Y, the first overlap length OL1 of the first impurity pattern 210 and the channel structure CS can be less than the second overlap length OL2 of the second impurity pattern 220 and the channel structure CS.

[0098] Or, for example, such as Figure 4E As shown, in the second direction Y, the first overlap length OL1 of the first impurity pattern 210 overlapping with the channel structure CS can be greater than the second overlap length OL2 of the second impurity pattern 220 overlapping with the channel structure CS.

[0099] In some embodiments, such as Figure 5 and Figure 6 As shown, a first upper contact 48, a third upper wiring 46, a second upper contact 44, and a fourth upper wiring 42 can be formed to connect to the source structure 200.

[0100] The first upper contact 48 may be formed to connect to the first impurity pattern 210. For example, the first upper contact 48 may penetrate the third interlayer insulating layer 40 and connect to the first impurity pattern 210. The third upper wiring 46 may be formed on the first upper contact 48. For example, the third upper wiring 46 may be formed in the third interlayer insulating layer 40.

[0101] In some embodiments, the first upper contact 48 may be formed on the word line cutting region WLc. However, the position of the first upper contact 48 is not limited, as long as it is connected to the first impurity pattern 210.

[0102] In some embodiments, a first high-concentration impurity region 215 may be formed between the first impurity pattern 210 and the first upper contact 48. For example, the first high-concentration impurity region 215 is formed in the first impurity pattern 210 and may be in contact with the first upper contact 48. The first high-concentration impurity region 215 may have the same first conductivity type (e.g., n-type) as the first impurity pattern 210, and may have a higher impurity concentration than the first impurity pattern 210.

[0103] In some embodiments, the third upper wiring 46 can be connected to Figure 2 The second upper wiring 325. Therefore, the first impurity pattern 210 can be connected to Figure 2 The peripheral circuit structure PS. During read or write operations of the non-volatile memory device according to some embodiments, the peripheral circuit structure PS can apply a ground voltage to the first impurity pattern 210 through the first upper contact 48 and the third upper wiring 46.

[0104] The second upper contact 44 can be formed to connect to the second impurity pattern 220. For example, the second upper contact 44 can pass through the third interlayer insulating layer 40 and connect to the second impurity pattern 220. A fourth upper wiring 42 can be formed on the second upper contact 44. For example, the fourth upper wiring 42 can be formed in the third interlayer insulating layer 40.

[0105] In some embodiments, the second upper contact 44 may be formed on the central portion of the second impurity pattern 220. However, the position of the second upper contact 44 is not limited, as long as it is connected to the second impurity pattern 220.

[0106] In some embodiments, a second high-concentration impurity region 225 may be formed between the second impurity pattern 220 and the second upper contact 44. For example, the second high-concentration impurity region 225 is formed in the second impurity pattern 220 and may contact the second upper contact 44. The second high-concentration impurity region 225 may have the same second conductivity type (e.g., p-type) as the second impurity pattern 220, and may have a higher impurity concentration than the second impurity pattern 220.

[0107] In some embodiments, the fourth upper wiring 42 can be connected to Figure 2 The second upper wiring 325. Therefore, the second impurity pattern 220 can be connected to Figure 2 The peripheral circuit structure PS. During the erase operation of the non-volatile memory device according to some embodiments, the peripheral circuit structure PS can apply an erase voltage to the second impurity pattern 220 through the second upper contact 44 and the fourth upper wiring 42.

[0108] For example, the third upper wiring 46 and the fourth upper wiring 42 may include (but are not limited to) metals (e.g., copper (Cu) or aluminum (Al)). For example, the first upper contact 48 and the second upper contact 44 may include (but are not limited to) silicon (e.g., polysilicon) or metals (e.g., tungsten (W) or copper (Cu)).

[0109] Refer to Figure 1 In some embodiments, at least a portion of the separation pattern 230 may extend in the first direction X and intersect with a plurality of channel structures CS in a plan view. Additionally, as described above, each channel structure CS may be cylindrical. In this case, both the first region CSa of the channel structure CS that overlaps with the first impurity pattern 210 and the second region CSb of the channel structure CS that overlaps with the second impurity pattern 220 may be semi-circular (or arc-shaped).

[0110] In some embodiments, the second impurity pattern 220 may be formed over a portion of the first channel group CG1 and a portion of the second channel group CG2. For example, the second impurity pattern 220 extends in the first direction X and may overlap with both the second region CSb of the first channel group CG1 and the second region CSb of the second channel group CG2. In this case, erasure operations for the first channel group CG1 and erasure operations for the second channel group CG2 can be performed simultaneously.

[0111] In some embodiments, the separation pattern 230 may surround the second impurity pattern 220 from a planar view. For example, the separation pattern 230 may extend along the side surface of the second impurity pattern 220. Therefore, the second impurity pattern 220 may be isolated by the separation pattern 230 from a planar view. In some embodiments, the second impurity pattern 220 may form a plurality of isolation regions.

[0112] In some embodiments, the first impurity pattern 210 may surround the separation pattern 230 from a planar view. For example, the first impurity pattern 210 may extend along the side surface of the separation pattern 230. In some embodiments, the first impurity pattern 210 may be formed to fill the remaining area of ​​the cell array region CAR other than the second impurity pattern 220 and the separation pattern 230.

[0113] In some embodiments, the single separation pattern 230 forming the isolation zone may intersect with both the first channel group CG1 and the second channel group CG2 in a plan view. For example, as Figure 1 As shown, a separation pattern 230 can form a rectangular isolation area between the word line cutting areas WLc. The separation pattern 230 forming the rectangular isolation area can intersect with both the channel structure CS constituting the first channel group CG1 and the channel structure CS2 constituting the second channel group CG2.

[0114] Figure 7 This is a layout diagram used to explain a non-volatile memory device according to some embodiments. For ease of explanation, the above utilization will be briefly described or omitted. Figures 1 to 6 The repeated parts of the explanation.

[0115] Reference Figure 7 In a non-volatile memory device according to some embodiments, the separation pattern 230 may extend in a first direction X and intersect with a plurality of channel structures CS in a plan view.

[0116] For example, multiple separation patterns 230 can be formed that are spaced apart from each other and extend side by side in the first direction X. At this time, one separation pattern 230 may intersect with the channel structure CS that constitutes the first channel group CG1, and another separation pattern 230 may intersect with the channel structure CS that constitutes the second channel group CG2.

[0117] In some embodiments, a plurality of separate patterns 230 extending in the first direction X may intersect with the word line cutting area WLc.

[0118] Figure 8 This is a layout diagram used to explain a non-volatile memory device according to some embodiments. For ease of explanation, the above utilization will be briefly described or omitted. Figures 1 to 6 The repeated parts of the explained content.

[0119] Reference Figure 8 In a non-volatile memory device according to some embodiments, at least a portion of the separation pattern 230 may intersect with a plurality of channel structures CS in a zigzag pattern.

[0120] For example, the third region CSc of the channel structure CS, which overlaps with the separation pattern 230, can be V-shaped. In this case, the second region CSb of the channel structure CS, which overlaps with the second impurity pattern 220, can be arc-shaped. Although the central angle of the arc is only shown as less than 180°, this is only an example. For example, the central angle of the arc can be greater than 180°.

[0121] In some embodiments, the size of the region where the first impurity pattern 210 overlaps with the channel structure CS may be different from the size of the region where the second impurity pattern 220 overlaps with the channel structure CS.

[0122] Figure 9 This is a layout diagram used to explain a non-volatile memory device according to some embodiments. For ease of explanation, the above utilization will be briefly described or omitted. Figures 1 to 6 The repeated parts of the explained content.

[0123] Reference Figure 9 In a non-volatile memory device according to some embodiments, a second impurity pattern 220 may be formed only above one of the first channel group CG1 and the second channel group CG2.

[0124] For example, one of the multiple second impurity patterns 220 forming the multiple isolation zones may overlap with a portion of the first channel group CG1, but may not overlap with the second channel group CG2.

[0125] Alternatively, for example, one of the multiple second impurity patterns 220 forming the multiple isolation zones may overlap with a portion of the second channel group CG2, but may not overlap with the first channel group CG1.

[0126] In this case, the erasure operation for the first channel group CG1 and the erasure operation for the second channel group CG2 can be performed separately.

[0127] Figure 10 This is a layout diagram used to explain a non-volatile memory device according to some embodiments. For ease of explanation, the above utilization will be briefly described or omitted. Figures 1 to 6 The repeated parts of the explained content.

[0128] Reference Figure 10 In a non-volatile memory device according to some embodiments, a second impurity pattern 220 may overlap with three adjacent channel structures CS.

[0129] For example, the separation pattern 230 can be triangular when viewed from a planar perspective. In this case, the third region CSc of the channel structure CS that overlaps with the separation pattern 230 can be V-shaped. Furthermore, the second region CSb of the channel structure CS that overlaps with the second impurity pattern 220 can be arc-shaped.

[0130] In some embodiments, erasure operations can be performed simultaneously on three channel structures CS that overlap with a second impurity pattern 220.

[0131] The following will refer to Figures 11 to 16 Describes a non-volatile memory device according to some embodiments.

[0132] Figures 11 to 16 This is an intermediate stage diagram used to explain an example method for manufacturing a non-volatile memory device according to some embodiments. For ease of explanation, the above utilization will be briefly described or omitted. Figures 1 to 10 The repeated parts of the explanation.

[0133] Reference Figure 11 A peripheral circuit structure PS, a molded structure MS, and multiple channel structures CS are formed on the substrate 10.

[0134] For example, a peripheral circuit structure PS can be formed in the first interlayer insulating layer 20 on the substrate 10. The peripheral circuit structure PS may include a wiring structure PW.

[0135] In some embodiments, a bit line BL extending in the first direction X and a bit line contact BLc connected to the bit line BL may also be formed in the first interlayer insulating layer 20. In some embodiments, a post 105 connected to the bit line contact BLc may also be formed in the first interlayer insulating layer 20.

[0136] Next, a molded structure MS can be formed on the peripheral circuit structure PS. For example, the molded structure MS can be formed on the first interlayer insulating layer 20. The molded structure MS may include a plurality of gate electrodes SSL, DM1, WL1 to WLn, DM2 and GSL stacked on the peripheral circuit structure PS, as well as a plurality of insulating patterns 110. The plurality of insulating patterns 110 may be arranged alternately (i.e., interleaved) with the plurality of gate electrodes SSL, DM1, WL1 to WLn, DM2 and GSL.

[0137] Next, multiple channel structures CS can be formed through the molded structure MS. In some embodiments, each channel structure CS may include a semiconductor pattern 120 and an information storage layer 130.

[0138] In some embodiments, a second interlayer insulating layer 30 may be formed on the first interlayer insulating layer 20. The second interlayer insulating layer 30 may be formed to cover at least a portion of the molded structure MS or to overlap with at least a portion of the molded structure MS.

[0139] Reference Figure 12 A first impurity layer 210L is formed on the molded structure MS.

[0140] A first impurity layer 210L is formed on the cell array region CAR and can be connected to the upper part of each channel structure CS. In some embodiments, the first impurity layer 210L can be in contact with the upper surface of the semiconductor pattern 120.

[0141] In some embodiments, the first impurity layer 210L may have a first conductivity type. Hereinafter, for ease of description, the first impurity layer 210L will be described as including n-type impurities.

[0142] Reference Figure 13 The first impurity layer 210L is patterned to form the first impurity pattern 210.

[0143] The first impurity pattern 210 can be patterned to expose a portion of the respective channel structure CS. That is, the first impurity pattern 210 can overlap with a portion of the channel structure CS and can expose another portion of the channel structure CS. In some embodiments, the first impurity pattern 210 can be formed to expose a portion of the upper surface of the semiconductor pattern 120.

[0144] For example, the formation of the first impurity pattern 210 can be performed by (but not limited to) a photolithography process.

[0145] Reference Figure 14 Separation pattern 230 is formed on the side surface of the first impurity pattern 210.

[0146] For example, a separation layer can be formed extending along the contours of the first impurity pattern 210, the molded structure MS, and the second interlayer insulating layer 30. Then, a portion of the separation layer formed on the upper surface of the first impurity pattern 210, the upper surface of the molded structure MS, and the second interlayer insulating layer 30 can be removed. For example, the removal of a portion of the separation layer can be performed by (but is not limited to) anisotropic etching processes. Therefore, a separation pattern 230 can be formed on the side surface of the first impurity pattern 210.

[0147] In some embodiments, the separation pattern 230 may be formed to expose a portion of the respective channel structure CS. That is, the first impurity pattern 210 and the separation pattern 230 may overlap with a portion of the channel structure CS and may expose another portion of the channel structure CS. In some embodiments, the separation pattern 230 may be formed to expose a portion of the upper surface of the semiconductor pattern 120.

[0148] The separation pattern 230 may include an insulating material. For example, the separation pattern 230 may include (but is not limited to) at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0149] Reference Figure 15 A second impurity layer 220L is formed on the first impurity pattern 210 and the separation pattern 230.

[0150] For example, a second impurity layer 220L may be formed extending along the contours of the first impurity pattern 210, the separation pattern 230, the molding structure MS, and the second interlayer insulating layer 30.

[0151] The second impurity layer 220L may be connected to the respective channel structures CS exposed through the first impurity pattern 210 and the separation pattern 230. In some embodiments, the second impurity layer 220L may be in contact with a portion of the upper surface of the semiconductor pattern 120 exposed through the first impurity pattern 210 and the separation pattern 230.

[0152] In some embodiments, the second impurity layer 220L may have a second conductivity type different from the first conductivity type. For example, the second impurity layer 220L may include p-type impurities.

[0153] Reference Figure 16 A planarization process is performed to form a second impurity pattern 220.

[0154] For example, a planarization process can be performed until the upper part of the separation pattern 230 is removed. Therefore, the second impurity pattern 220 can be separated from the first impurity pattern 210 through the separation pattern 230. Furthermore, a source structure 200 including the first impurity pattern 210, the second impurity pattern 220, and the separation pattern 230 can be formed accordingly.

[0155] For example, planarization processes may include (but are not limited to) chemical mechanical polishing (CMP) processes.

[0156] Next, refer to Figures 1 to 6A third interlayer insulating layer 40 is formed on the source structure 200 and the second interlayer insulating layer 30. Furthermore, memory cell contacts 310 and through-holes THV are formed in the contact region CTR. Additionally, a first upper contact 48 connected to the first impurity pattern 210 and a second upper contact 44 connected to the second impurity pattern 220 are formed.

[0157] In some embodiments, such as Figure 2 As shown, a first upper wiring 315 connected to the memory cell contact 310 and a second upper wiring 325 connected to the through-hole THV can be formed in the third interlayer insulating layer 40.

[0158] Additionally, in some embodiments, such as Figure 5 and Figure 6 As shown, a third upper wiring 46 connected to the first upper contact 48 and a fourth upper wiring 42 connected to the second upper contact 44 can be formed in the third interlayer insulating layer 40.

[0159] While the inventive concept has been specifically shown and described with reference to exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of the inventive concept as defined by the appended claims. Therefore, the exemplary embodiments described above should be viewed only in an illustrative sense and not for limiting purposes.

Claims

1. A non-volatile memory device, comprising: Substrate; The peripheral circuit structure on the substrate; A molded structure comprising multiple insulating patterns and multiple gate electrodes alternately stacked on the peripheral circuit structure; A channel structure that passes through the molded structure; A first impurity pattern, which contacts a first portion of the channel structure on the molded structure, and has a first conductivity type; A second impurity pattern is formed on the molded structure and contacts a second portion of the channel structure, and has a second conductivity type different from the first conductivity type. as well as A separation pattern is formed, which contacts a third portion of the channel structure located between the first and second portions on the molded structure, and separates the first impurity pattern and the second impurity pattern. The separation pattern is in contact with the first impurity pattern and the second impurity pattern.

2. The non-volatile memory device according to claim 1, wherein, The upper surface of the first impurity pattern is coplanar with the upper surface of the second impurity pattern.

3. The non-volatile memory device according to claim 1, in, From a planar perspective, the first impurity pattern overlaps with a first portion of the channel structure, and the second impurity pattern overlaps with a second portion of the channel structure.

4. The non-volatile memory device according to claim 3, wherein, The first region of the channel structure that overlaps with the first impurity pattern and the second region of the channel structure that overlaps with the second impurity pattern each have a semi-circular or arc shape.

5. The non-volatile memory device according to claim 3, wherein, The size of the first region of the channel structure that overlaps with the first impurity pattern is different from the size of the second region of the channel structure that overlaps with the second impurity pattern.

6. The non-volatile memory device according to claim 1, wherein, The channel structure includes a semiconductor pattern passing through the molded structure and an information storage layer located between the semiconductor pattern and the gate electrodes among the plurality of gate electrodes.

7. The non-volatile memory device according to claim 6, wherein, The first impurity pattern and the second impurity pattern are in contact with the upper surface of the semiconductor pattern.

8. The non-volatile memory device according to claim 6, wherein, The information storage layer includes a tunnel insulating layer, a charge storage layer, and a barrier insulating layer stacked on the semiconductor pattern.

9. A non-volatile memory device, comprising: Substrate; The interlayer insulating layer on the substrate; Bit lines that extend in the interlayer insulating layer in a first direction; A molded structure comprising multiple insulating patterns and multiple gate electrodes alternately stacked on the interlayer insulating layer; A channel structure that passes through the molded structure and connects to the bit line; as well as The source structure contacts the upper part of the channel structure on the molded structure. The source structure includes a first impurity pattern, a second impurity pattern, and a separation pattern. The first impurity pattern overlaps with a first region of the channel structure, the second impurity pattern overlaps with a second region of the channel structure, and the separation pattern overlaps with a third region of the channel structure and separates the first impurity pattern from the second impurity pattern.

10. The non-volatile memory device according to claim 9, wherein, The separation pattern extends in a second direction that intersects with the first direction.

11. The non-volatile memory device according to claim 9, further comprising: A column, which is connected to the lower part of the channel structure; as well as The position line contact element connects the post to the position line.

12. The non-volatile memory device according to claim 11, wherein, The pillars are made of polycrystalline silicon.

13. The non-volatile memory device according to claim 9, further comprising: The peripheral circuit structure in the interlayer insulation layer. The peripheral circuit structure includes peripheral circuit elements on the substrate and wiring structures that connect the peripheral circuit elements to the bit lines.

14. The non-volatile memory device according to claim 9, wherein, The upper surface of the first impurity pattern, the upper surface of the second impurity pattern, and the upper surface of the separation pattern are coplanar.

15. The non-volatile memory device according to claim 9, in, The channel structure is cylindrical, and The first region that overlaps with the first impurity pattern has a semi-circle or arc shape in the planar view.

16. A non-volatile memory device, comprising: Substrate; The peripheral circuit structure on the substrate; Bit lines that extend in a first direction on the peripheral circuit structure; A molded structure comprising multiple insulating patterns and multiple gate electrodes alternately stacked on the bit line; Multiple channel structures passing through the molding structure, wherein the lower portion of each of the channel structures is connected to the bit line; as well as The source structure is connected to the upper part of each of the channel structures on the molded structure. The source structure includes a first impurity pattern, a second impurity pattern, and a separation pattern. The first impurity pattern overlaps with a first region of each of the channel structures, the second impurity pattern overlaps with a second region of each of the channel structures, and the separation pattern overlaps with a third region of each of the channel structures and separates the first impurity pattern and the second impurity pattern. Wherein, the first impurity pattern includes n-type impurities, and The second impurity pattern includes p-type impurities.

17. The non-volatile memory device according to claim 16, in, The first portion of the plurality of channel structures forms a first channel group along a second direction intersecting the first direction. The second portion of the plurality of channel structures forms a second channel group along the second direction. Wherein, the second channel group is adjacent to the first channel group in the first direction, and The second impurity pattern overlaps with the second region of the first channel group and the second region of the second channel group.

18. The non-volatile memory device according to claim 17, wherein, In the plan view, the separation pattern surrounds the second impurity pattern and the first impurity pattern surrounds the separation pattern.

19. The non-volatile memory device of claim 16, further comprising: An interlayer insulating layer that overlaps with the source structure; The first upper contact extends through the interlayer insulation layer and is connected to the first impurity pattern; as well as The second upper contact extends through the interlayer insulation layer and is connected to the second impurity pattern.

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