Circuits and layouts for resistive random access memory arrays

Abstract

The present invention discloses a ReRAM memory array, which includes rows and columns of ReRAM cells. Each ReRAM cell in the rows and columns of the array includes a ReRAM device, which has an ion source terminal coupled to a bias line associated with the row of the array containing the ReRAM device. A first transistor is coupled between a solid electrolyte terminal of the ReRAM device and a bit line associated with the column of the array containing the ReRAM cell. The first transistor has a gate coupled to a first word line associated with the row containing the ReRAM cell. A second transistor is coupled between a solid electrolyte terminal of the ReRAM device and a bit line associated with the column of the array containing the ReRAM cell. The second transistor has a gate coupled to a second word line associated with the row containing the ReRAM cell.

Description

Technical Field

[0001] The present invention relates to integrated circuit technology and resistive random access memory (ReRAM) technology. More specifically, the present invention relates to integrated circuit layouts of addressable arrays of ReRAM memory cells using small geometry transistor devices such as FinFET transistor devices. ReRAM memory cells have been used as configuration memory for user programmable integrated circuits by driving switch transistors that configure programmable circuits. ReRAM memory cells have also been used as random access memory (RAM) in integrated circuits. The present invention relates to ReRAM memory cells used as random access memory (RAM) cells in integrated circuits that must be addressed and coupled to sense amplifiers to read the data contained in these memory cells. Background Art

[0002] Since small geometry transistor devices such as FinFET transistors alone cannot support the voltages required to program and erase ReRAM devices, two FinFET transistors have been placed in series in an addressable ReRAM memory cell.

[0003] See first Figure 1 , Figure 2A and Figure 2B , respectively showing a schematic diagram of a portion 10 of a prior art ReRAM memory array, Figure 1 A top view of the layout of a portion 10 of the memory array is shown, and a view taken through line 2B-2B. Figure 2A A cross-sectional view of the layout of a portion of a memory array is shown. Figure 1 , a portion 10 of a prior art ReRAM memory array includes six ReRAM memory cells (indicated by dashed lines at reference numerals 12a to 12f, respectively). ReRAM memory cells 12a, 12b, and 12c are located in a first column of the array, and ReRAM memory cells 12d, 12e, and 12f are located in a second column of the array. One of ordinary skill in the art will observe that the layout of memory cells 12a to 12f is a mirror configuration. Thus, in the first column of the array, memory cells 12a and 12b mirror each other, and memory cells 12b and 12c mirror each other. Similar mirroring exists in the second column of the array.

[0004] Each memory cell 12a to 12f includes a ReRAM device and two series transistor devices. These circuit elements will be designated using letter suffixes corresponding to the memory cells in which they are disposed. As an example, the ReRAM memory cell 12a includes a ReRAM device 14a and two n-channel FinFET transistor devices 16a and 18a, all of which are connected in series between a first common bias node 20-1 and a first bit line BL0 associated with the first column of the portion 10 of the array at the reference numeral 22-1. The convention used in the reference numerals of the ReRAM devices herein is that the wider end of the ReRAM device is the ion source side of the device, and the narrower end is the opposite electrode separated from the ion source by a solid electrolyte layer. In order to program the ReRAM device, that is, to set it to a lower resistance, a programming voltage is applied to the wider end of the ReRAM device at a maximum positive potential. In order to erase the ReRAM device, that is, to set it to a high resistance, a programming voltage is applied to the narrower end of the ReRAM device at a maximum positive potential.

[0005] The ReRAM memory cell 12b includes a ReRAM device 14b and two n-channel FinFET transistor devices 16b and 18b, all of which are connected in series between a second common bias node 20-2 and a first bit line 22-1. The ReRAM memory cell 12c includes a ReRAM device 14c and two n-channel FinFET transistor devices 16c and 18c, all of which are connected in series between a second common bias node 20-2 and a first bit line 22-1. The ReRAM cells 12d, 12e, and 12f are similarly connected, except that they are connected between common bias nodes 20-1 and 20-2, respectively, and a second bit line 22-2 associated with a second column of the portion 10 of the array.

[0006] The gates of the two FinFET transistors in each row of the array are connected together to the word line. Thus, FinFET transistors 16a and 18a and 16d and 18d are connected together to word line WL0 at reference numeral 24. Word line 24 is shown in two segments, each of which represents a gate line formed of, for example, a metal or metal silicide that extends the length of the row in the array containing ReRAM memory cells 12a and 12d. These gate lines are joined together as shown by connection 26. Similarly, the gates of FinFET transistors 16b and 18b and 16e and 18e are connected together to word line WL1 at reference numeral 28. These gate lines are joined together as shown by connection 30. The gates of FinFET transistors 16c and 18c and 16f and 18f are connected together to word line WL2 at reference numeral 32. These gate lines are joined together as shown by connection 34.

[0007] See now Figure 2A and Figure 2B Both, schematic diagrams show the use of ReRAM memory cells (such as Figure 1 A typical layout 40 of a specific implementation in an integrated circuit of those). Figure 2A and Figure 2B The portion of the ReRAM array depicted in Figure 1 Thus, a person skilled in the art will note that Figure 2A and Figure 2B The layout depicted does not include Figure 1 The ReRAM cells 12c and 12f are depicted in FIG. Figure 2A and Figure 2B Depicted in Figure 1 The components in Figure 1 The same reference numerals are used to designate these elements in the drawings.

[0008] For simplicity, Figure 2A The first fin set 42, shown as a diffusion in FIG, forms the source, drain and channel of the FinFET transistors 16a, 18a, 16b and 18b of the first column of the array, and the second fin set 44 forms the source, drain and channel of the FinFET transistors 16d, 18d, 16e and 18e in the second column of the array. Figure 2A The dashed lines indicated at the reference numerals 12a, 12b, 12d and 12e in FIG. Figure 1 The locations of the ReRAM memory cells 12a, 12b, 12d and 12e.

[0009] Gate electrode line 46 forms the gates of FinFET transistors 16a and 16d and serves as word line WL0. Gate line 48 forms the gates of FinFET transistors 18a and 18d and also serves as word line WL0 (eg, Figure 1 and Figure 2A Gate electrode line 50 forms the gates of FinFET transistors 16b and 16e and serves as word line WL1. Gate electrode line 52 forms the gates of FinFET transistors 18b and 18e and also serves as word line WL1 (as shown in FIG. Figure 1 and Figure 2A Gate electrode lines 46, 48, 50 and 52 are formed of metal, as is known in the art of FinFET fabrication.

[0010] FinFET technology requires a virtual gate electrode to terminate the end of the diffusion region to isolate it from the adjacent diffusion region. The virtual gate electrode is formed simultaneously and in the same manner as the gate electrode lines 46, 48, 50 and 52, and is referred to as a virtual gate electrode because no transistor is formed under these gate electrodes. The virtual gate electrode line 54 provides isolation between the ReRAM devices 14a, 14d and the ReRAM device (not shown) disposed above the virtual gate electrode line 54. Similarly, the virtual gate electrode line 56 provides isolation between the ReRAM devices 14b, 14e and the ReRAM device (not shown) disposed below the gate electrode line 56.

[0011] Figure 2B Reference numeral 58 in FIG. 5 indicates a gate dielectric layer beneath gate electrode lines 46, 48, 50, 54, and 56. Contacts 60 and 62 connect gate electrode lines 46 and 48 to a metal level 0 (M0) segment 64 (in FIG. 1 ) that connects the gates of FinFETs 16a and 18a together. Figure 1 Contacts 66 and 68 connect gate lines 50 and 52 to M0 segment 70 (in FIG. 1 ) that connects the gates of FinFETs 16b and 18b together. Figure 1 denoted as wiring connection 30).

[0012] Metal level 0 (M0) segment 72-1 passes Figure 2B Contact 74 is shown connected to fin set 42. Contact 76 connects M0 segment 72-1 to metal level 1 (M1) segment 78. Contact 80 connects M1 segment 78 to metal level 2 (M2) segment 82. Figure 2A and Figure 2B The contacts 84 shown in both connect the M2 segment 82 to the Figure 1 To avoid overly complicating the drawing, metal sections 78 and 82 and contacts 76 and 80 are not shown. Figure 2A Shown in.

[0013] The metal layer 2 section 88 is used as Figure 1 The contact 90-1 connects the M2 segment 88 to the first common bias node 20-1 in FIG. Figure 1 ReRAM 14a, such as Figure 2A shown, and in Figure 2B It is also shown as including an ion source layer 92 and a solid electrolyte layer 94. Those skilled in the art will appreciate that ReRAM devices are known and are more Figure 2B As shown in Figure 1, it is more complicated. Figure 2B As shown, the ReRAM device 14 a is connected to the M1 layer segment 98 via contact 96 , to the M0 segment 102 - 1 via contact 100 , and to the FinFET transistor 16 a via contact 104 .

[0014] The metal layer 2 section 106 is used as Figure 1 The contact 90-2 connects the M2 segment 106 to the second common bias node 20-2 in Figure 1 ReRAM 14b, such as Figure 2A shown, and in Figure 2B 1 and 10. It is also shown as including an ion source layer 108 and a solid electrolyte layer 110. Those skilled in the art will appreciate that ReRAM devices are known and are more Figure 2B As shown in Figure 1, it is more complicated. Figure 2B As shown, the ReRAM device 14 b is connected to the M1 layer segment 114 via contact 112 , to the M0 segment 102 - 2 via contact 116 , and to the FinFET transistor 16 b via contact 118 .

[0015] For programming Figure 1 In the ReRAM device 14a in the memory cell 12a in FIG. 1, a positive voltage is applied to the word line WL0 24 to turn on the transistors 16a and 18a, and a voltage is applied between the bias line 20-1 and the bit line 0 22-1, wherein a more positive potential is applied to the bias line 20-1. To erase Figure 1 To disable programming / erasing of the ReRAM devices 14a in the memory cell 12a in the memory cell 12b, a positive voltage is applied to the word line WL0 24 to turn on the transistors 16a and 18a, and a voltage is applied between the bias line 20-1 and the bit line 0 22-1, wherein a more positive potential is applied to the bit line 0 22-1. To disable programming / erasing of the ReRAM devices 14b and 14c in the memory cells 12b and 12c, the word lines WL1 28 and WL2 32 are disconnected. To disable programming / erasing of the ReRAM devices 14d, 14e, and 14f in the memory cells 12d, 12e, and 12f, the voltage at the bit line 1 22-2 is set to the same voltage as the bias line 0 20-1.

[0016] Under the bias conditions used to program the ReRAM memory cell (using memory cell 12a as an example), transistors 16a and 18a are in a common source configuration that provides current limiting. In addition, since both transistors 16a and 18a are turned on, the voltage across them is close to zero, resulting in little or no stress on these transistors. There is no current limiting in the opposite direction for erasing the ReRAM device (using memory cell 12a as an example) because none of the FinFET transistors of the selected ReRAM cell are grounded (i.e., in a common source configuration), and the varying resistance of the ReRAM device 14a places a source bias on transistors 16a and 18a, thereby reducing the current handling capability of the transistors. In addition, there is a higher voltage across transistors 16a and 18a than during programming, requiring a greater number of FinFET transistors to support the voltage. This requirement limits the area minimization of the ReRAM memory cell.

[0017] Furthermore, ReRAM memory cells require programming and erasing currents of approximately 100 μA or more. To provide such currents, the programming and erasing paths must have sufficiently low impedance to allow programming and erasing currents of this magnitude to flow. As device dimensions decrease, the transistors used become smaller and weaker, and wider metal lines are required to provide the necessary programming potentials. Furthermore, as discussed above with respect to Figure 2A As described above, prior art ReRAM memory arrays (ie, FinFET transistor devices) that employ ReRAM memory cells fabricated using deep sub-micron lines require the use of additional dummy gate lines (eg, Figure 2A The virtual gate lines 54 and 56 in FIG. 5 are used to terminate the quantitative layout rules of the diffusion regions between cells. Summary of the invention

[0018] According to one aspect of the present invention, a ReRAM memory array is disclosed, the ReRAM memory array comprising rows and columns of ReRAM cells. Each ReRAM cell in the rows and columns of the ReRAM cells comprises a ReRAM device, a first transistor, and a second transistor; the ReRAM device has an ion source terminal and a solid electrolyte terminal, the ion source terminal is coupled to a bias line associated with the row of the array containing the ReRAM device; the first transistor is coupled between the solid electrolyte terminal of the ReRAM device and a bit line associated with the column of the array containing the ReRAM cell, the first transistor having a gate coupled to a first word line associated with the row containing the ReRAM cell; the second transistor is coupled between the solid electrolyte terminal of the ReRAM device and the bit line associated with the column of the array containing the ReRAM cell, the second transistor having a gate coupled to a second word line associated with the row containing the ReRAM cell.

[0019] According to another aspect of the present invention, a layout for a ReRAM memory array including rows and columns of ReRAM cells is disclosed. Fin groups are formed in a semiconductor substrate for each column of the array and extend in a first direction. A bit line is formed for each column of the array in the form of a metal interconnect line extending in the first direction. A separated first inter-word line and a second word line are formed for each row in the array extending in a second direction perpendicular to the first direction. The first word line passes over each fin group and is electrically insulated from each fin group, and forms the gate of a first transistor in a ReRAM memory cell in a row of the array. The second word line passes over each fin group and is electrically insulated from each fin group, and forms the gate of a second transistor in a ReRAM memory cell in the row of the array. There is a bias line extending in the second direction in the form of a metal interconnect line for each row of the array. A plurality of ReRAM memory cells are formed, each ReRAM memory cell is located at the intersection of a row and a column of the array, each memory cell includes a ReRAM device, the ReRAM device is formed on the fin group between the first word line and the second word line, the ReRAM device has a solid electrolyte terminal and an ion source terminal, the solid electrolyte terminal of each ReRAM device is electrically connected to a region of the fin group of the array containing the column of the memory cell at a position between the first word line and the second word line of the row containing the memory cell, and the ion source terminal of each ReRAM device is electrically connected to the bias line of the row containing the memory cell. The region of the fin group electrically connected to the solid electrolyte terminal of each ReRAM device forms a common drain of the first transistor and the second transistor in the ReRAM cell. The region of the fin group outside the pair of spaced-apart word lines forms a separate source region of the first transistor and the second transistor in the ReRAM cell, and the separate source region is electrically connected to the bias line of the row containing the ReRAM memory cell.

[0020] According to another aspect of the present invention, in addition to the end area of ​​the fin group, an area of ​​the fin group outside a pair of spaced-apart word lines is disclosed, and the area of ​​the fin group outside the pair of spaced-apart word lines also forms a common source region for one of the first transistor and the second transistor in another memory cell in the column of the ReRAM memory cell adjacent to the memory cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The invention will be explained in more detail below with reference to embodiments and the accompanying drawings, in which:

[0022] Figure 1is a schematic diagram of a prior art ReRAM memory array portion;

[0023] Figure 2A yes Figure 1 A top view of the layout of a portion of a memory array is shown;

[0024] Figure 2B It was intercepted along line 2B-2B Figure 2A A cross-sectional view of a layout of a portion of a memory array is shown;

[0025] Figure 3 is a schematic diagram of a portion of a ReRAM memory array according to one aspect of the present invention;

[0026] Figure 4A yes Figure 3 A top view of the layout of a portion of a memory array is shown;

[0027] Figure 4B It was taken along route 4B-4B Figure 4A A cross-sectional view of a layout of a portion of a memory array is shown; and

[0028] Figure 5 is a block diagram illustrating a typical ReRAM memory array and associated read, write, and erase control circuits according to one aspect of the present invention. DETAILED DESCRIPTION

[0029] Those skilled in the art will recognize that the following description of the present invention is exemplary only and not limiting in any way. Other embodiments of the present invention will be readily suggested to those skilled in the art.

[0030] See now Figure 3 , a schematic diagram illustrates a portion 120 of a ReRAM memory array according to one aspect of the present invention. Figure 3 The various circuit elements of the embodiments correspond to Figure 1 circuit elements in the prior art array and will use the same Figure 1 1 and 2. The memory cells 12a and 12b are referred to by the same reference numerals as those circuit elements in the memory cells 12a and 12c. Each memory cell includes a ReRAM device and a first FinFET transistor device and a second FinFET transistor device. The circuit elements will be designated using a letter suffix corresponding to the memory cell in which they are disposed. As an example, a ReRAM memory cell 12a includes a ReRAM device 14a and a first n-channel FinFET transistor device 16a and a second n-channel FinFET transistor device 18a.

[0031] exist Figure 31 , a portion 120 of a ReRAM memory array according to this exemplary embodiment of the invention includes twelve ReRAM memory cells (indicated by dashed lines at reference numerals 12a to 121, respectively). ReRAM memory cells 12a, 12b, and 12c are in a first column of the array, ReRAM memory cells 12d, 12e, and 12f are in a second column of the array, ReRAM memory cells 12g, 12h, and 12i are in a third column of the array, and ReRAM memory cells 12j, 12k, and 121 are in a fourth column of the array.

[0032] exist Figure 3 In an exemplary embodiment of the present invention, the ReRAM devices in each row of the array have their ion source terminals coupled to the bias line associated with the corresponding row of the array. The ion source terminals of the ReRAM devices 14a, 14d, 14g, and 14j in the first row of the array portion are connected to the first bias line BIAS0 122. The ion source terminals of the ReRAM devices 14b, 14e, 14h, and 14k in the second row of the array portion are connected to the second bias line BIAS1 124. The ion source terminals of the ReRAM devices 14c, 14f, 14i, and 14l in the third row of the array portion are connected to the third bias line BIAS2 126.

[0033] In each memory cell in the array, drains of the first FinFET transistor and the second FinFET transistor are connected together to the solid electrolyte terminal of the ReRAM device. Sources of the first FinFET transistor and the second FinFET transistor in each memory cell are connected together to a bit line associated with the column of the array in which the memory cell is located. Gates of all of the first FinFET transistors in a row are connected to a first word line associated with the row, and gates of all of the second FinFET transistors in a row are connected to a second word line associated with the row.

[0034] exist Figure 3 In the first column of the first row of the portion 120 of the depicted array, both FinFET transistors 16a and 18a are connected between the solid electrolyte terminal of the ReRAM device 14a and a first bit line (BL0) 128 associated with the first column of the portion 120 of the array. Figure 3 In the second column of the first row of the depicted portion 120 of the array 120, both FinFET transistors 16d and 18d are connected between the solid electrolyte terminal of the ReRAM device 14d and a second bit line (BL1) 130 associated with the second column of the portion 120 of the array. Figure 3In the third column of the first row of the depicted portion 120 of the array, both FinFET transistors 16g and 18g are connected between the solid electrolyte terminal of the ReRAM device 14g and a third bit line (BL2) 132 associated with the third column of the portion 120 of the array. Figure 3 In the fourth column of the first row of the depicted portion 120 of the array, FinFET transistors 16j and 18j are both connected between the solid electrolyte terminal of ReRAM device 14j and a fourth bit line (BL3) 134 associated with the fourth column of the portion 120 of the array.

[0035] 144. The gates of the second FinFET transistors 18c, 18f, 18i and 18l are connected to word line WL2A 146. In the second row of the array, the gates of the first FinFET transistors 16b, 16e, 16h and 16k are connected to word line WL1 140. The gates of the second FinFET transistors 18b, 18e, 18h and 18k are connected to word line WL1A 142. In the third row of the array, the gates of the first FinFET transistors 16c, 16f, 16i and 16l are connected to word line WL2 144. The gates of the second FinFET transistors 18c, 18f, 18i and 18l are connected to word line WL2A 146.

[0036] exist Figure 4A and Figure 4B The top view and cross-sectional view show Figure 3 An exemplary layout of a portion 120 of a memory array is shown. Figure 4B Taken along line 4B-4B Figure 4A A cross-sectional view of the layout of a portion of a memory array is shown. Figure 4A and Figure 4B Some of the circuit elements in the embodiment correspond to Figure 2A and Figure 2B circuit elements in the prior art array and will use the same Figure 2A and Figure 2B All of the columns of array portion 120 are identical, and only the first column will be described in detail.

[0037] Figure 4A and Figure 4BOnly a portion of the ReRAM memory cells 12a, 12d, 12g, and 12j are shown in FIG. The ion source terminal 148 of the ReRAM device 14a is connected to the metal level 2 (M2) segment 150, which serves as the bias 0 line 122, through a contact 152. The ion source terminal 154 of the ReRAM device 14a is connected to the metal level 1 (M1) segment 156 through a contact 158. The metal level 1 (M1) segment 156 is connected to the metal level 0 (M0) segment 160 through a contact 162. The metal level 0 (M0) segment 160 is connected to the portion of the fin 164a that forms the drain of both the FinFET transistor 18a and the FinFET transistor 16a through a contact 166.

[0038] The ion source terminal 168 of the ReRAM device 14b is connected to a metal level 2 (M2) segment 170, which serves as a bias 1 line 124, through a contact 172. The ion source terminal 174 of the ReRAM device 14a is connected to a metal level 1 (M1) segment 176 through a contact 178. The metal level 1 (M1) segment 176 is connected to a metal level 0 (M0) segment 180 through a contact 182. The metal level 0 (M0) segment 180 is connected to a portion of the fin set 164c that forms the drains of both the FinFET transistor 16b and the FinFET transistor 18b through a contact 184.

[0039] The sources of FinFET transistors 16b and 18a are formed by the portion of fin set 164b connected to metal level 0 (M0) segment 186 through contact 188. Metal level 0 (M0) segment 186 is connected to metal level 1 (M1) segment 190 through contact 192. Metal level 1 (M1) segment 190 is connected to metal level 2 (M2) segment 194 through contact 196. Metal level 2 (M2) segment 194 is connected to metal 3 segment 198 forming bit line BL0 128 through contact 200. Gate electrode 138 is the gate of FinFET transistor 18a and is also word line WL0A. Gate electrode 140 is the gate of FinFET transistor 16b and is also word line WL1.

[0040] The ion source end 202 of the ReRAM device 14c is connected to the metal level 2 (M2) segment 204, which serves as the bias 2 line 126, through a contact 206. The ion source end 208 of the ReRAM device 14a is connected to the metal level 1 (M1) segment 210 through a contact 212. The metal level 1 (M1) segment 210 is connected to the metal level 0 (M0) segment 214 through a contact 216. The metal level 0 (M0) segment 214 is connected to the portion of the fin set 164e that forms the drains of both the FinFET transistor 16c and the FinFET transistor 18c through a contact 218.

[0041] The sources of FinFET transistors 16c and 18b are formed by the portion of fin set 164d connected to metal level 0 (M0) segment 220 through contact 222. Metal level 0 (M0) segment 220 is connected to metal level 1 (M1) segment 224 through contact 226. Metal level 1 (M1) segment 224 is connected to metal level 2 (M2) segment 228 through contact 230. Metal level 2 (M2) segment 228 is connected to metal 3 segment 198 forming bit line BL0 128 through contact 232. Gate electrode 142 is the gate of FinFET transistor 18b and is also word line WL1A. Gate electrode 144 is the gate of FinFET transistor 16c and is also word line WL2.

[0042] The sources of FinFET transistors 16d and 18c are formed by the portion of fin set 164f connected to metal level 0 (M0) segment 234 through contact 236. Metal level 0 (M0) segment 234 is connected to metal level 1 (M1) segment 238 through contact 240. Metal level 1 (M1) segment 238 is connected to metal level 2 (M2) segment 242 through contact 244. Metal level 2 (M2) segment 242 is connected to metal 3 segment 198 forming bit line BL0 128 through contact 246. Gate electrode 146 is the gate of FinFET transistor 18c and is also word line WL2A.

[0043] As previously mentioned, word line pairs WL0 and WL0A, WL1 and WL1A, and WL2 and WL2A are connected together. Figure 4A Metal segment 256 is connected to word line WL0A 138 through contact 258 and to word line WL0 (neither of which is shown in FIG. Figure 4A 140). Metal segment 260 is connected to word line WL1 140 through contact 262 and to word line WL1A 142 through contact 264. Metal segment 266 is connected to word line WL2 144 through contact 268 and to word line WL2A 146 through contact 270.

[0044] like Figure 4A 1, there are shown three additional columns of memory cells, the second column in array portion 120 being formed on the fin group identified by reference numeral 248 and including memory cells 12d, 12e, and 12f, the third column in array portion 120 being formed on the fin group identified by reference numeral 250 and including memory cells 12g, 12h, and 12i, and the fourth column in array portion 120 being formed on the fin group identified by reference numeral 252 and including memory cells 12j, 12k, and 12l. The layout of these additional columns of array portion 120 is similar to Figure 4B The layout of the first column, which is shown in detail in cross section in FIG, is identical and will not be discussed in detail.

[0045] Table 1 shows the connections applied to the ReRAM cell to program, erase, and read Figure 3 The operating voltage of the ReRAM device 14b in the ReRAM memory cell 12b. Figure 3 The other ReRAM memory cells in are shown in Table 1 as not selected.

[0046] exist Figure 3 In the embodiment of FIG. 1, and as reflected in Table 1, word line pair WL0 / WL0A is connected together, word line pair WL1 / WL1A is connected together, and word line pair WL2 / WL2A is connected together. This can be easily accomplished by bonding the gate lines forming these word line pairs together at certain intervals along each row, as is known in the art.

[0047]

[0048]

[0049] Table 1

[0050] A person skilled in the art will observe that it is possible to program or erase Figure 3 More than one ReRAM memory cell in a row of an array, up to all ReRAM memory cells in a row of the array. For example, if bit line BL3 134 reaches 0V together with bit line BL0 128, then ReRAM device 14h in ReRAM memory cell 12h can be programmed at the same time as ReRAM device 14b in ReRAM memory cell 12b. Because bias lines BIAS 0 122, BIAS1 124, and BIAS 2 126 are global to a row, the ReRAM memory cells in a row can be read at the same time because all of bit lines BL0 128, BL1 130, BL2 132, and BL3 134 are connected to the sense amplifier when the memory array is in read mode.

[0051] An advantage of the ReRAM cell and memory array of the present invention is that it eliminates the need for a dummy gate line, as in prior art ReRAM memory cells employing FinFET transistor devices, allowing the cell to occupy the same space on the integrated circuit die as the dummy gate line. Figure 1The prior art shown in FIG. 1 shows a smaller area. In addition, because the FinFET transistor devices 16 and 18 of each cell are connected in parallel with each other, more drive current can be provided during programming and erasing. Those skilled in the art will recognize that increased stress is presented to the metal bit lines and bias lines during programming and erasing, so wider metal lines and / or shorter lengths of metal bias lines and bit lines are required compared to the prior art. In addition, the bias line driver device must be a current drive device in order to prevent overdrive during programming, so the bias line driver device is required to be a larger device than a normal word line driver.

[0052] See now Figure 5 , a block diagram illustrates a typical ReRAM memory array system and associated read, write, and erase control circuits according to one aspect of the present invention. The ReRAM memory array system 280 includes a ReRAM memory array 282 that drives a sense amplifier circuit 284 via a bit line 286. The sense amplifier circuit can be any type of sense amplifier circuit, depending on the output voltage / current present on the bit line 286 during the read mode operation of the ReRAM memory array 282. The design of a specific sense amplifier circuit is well within the scope of ordinary skill in the art. The output of the sense amplifier is presented on output line 288.

[0053] Reading, programming (writing), and erasing memory cells in the ReRAM memory array 282 are controlled by the program / erase / read bias generation circuit 290. The program / erase / read bias generation circuit 290 generates the potentials shown in Table 1 to operate the program, erase, and read modes of the ReRAM memory array 282. The design of the specific circuit will depend on the specific potentials required and is well within the level of ordinary technicians in the art. The potentials required to operate the program, erase, and read modes of the ReRAM memory array 282 are driven into the ReRAM memory array 282 to operate the program, erase, and read modes of the ReRAM memory array 282 through the word line driver 292, the bias line driver 294, and the bit line driver 296. Word line driver, bias line driver, and bit line driver circuits are known in the art, and specific instances of these circuits are easily designed for specific ReRAM memory arrays with specific voltage and current requirements.

[0054] The program / erase controller 298 directs the operation of the program / erase / read bias generation circuit 290 through control lines 300 by providing timing and other controls in a manner known in the art. Those skilled in the art will appreciate that the sense amplifier 284 is disabled during program and erase operations by asserting a signal from the program / erase controller 298 on a disable line 302.

[0055] Although the embodiments and applications of the present invention have been shown and described, it will be apparent to those skilled in the art that more modifications than those described above may be made without departing from the inventive concept herein. Therefore, the present invention is not to be restricted except in the spirit of the appended claims.

Claims

1. A ReRAM memory array comprising rows and columns of ReRAM cells, each ReRAM cell in the rows and columns of ReRAM cells comprising: a ReRAM device having an ion source terminal and a solid electrolyte terminal, the ion source terminal coupled to a bias line associated with the row of the array containing the ReRAM device; a first n-channel transistor coupled between the solid electrolyte terminal of the ReRAM device and a bit line associated with the column of the array containing the ReRAM cell, the first n-channel transistor having a gate coupled to a first word line associated with the row containing the ReRAM cell; as well as a second n-channel transistor coupled between the solid electrolyte terminal of the ReRAM device and a bit line associated with the column of the array containing the ReRAM cell, the second n-channel transistor having a gate coupled to a second word line associated with the row containing the ReRAM cell, The first word line and the second word line associated with the row including the ReRAM cell are electrically connected together. 2 . The ReRAM memory array of claim 1 , further comprising a sense amplifier coupled to the bit line of each column in the array. 3 . The ReRAM memory array of claim 1 , wherein the first n-channel transistor and the second n-channel transistor are both FinFET transistors. 4 . The ReRAM memory array of claim 3 , wherein the first n-channel transistor and the n-channel second transistor for each memory cell in a column of the array are formed on the same fin set.

5. A product comprising a ReRAM memory array of rows and columns of ReRAM cells, the product comprising a layout of the ReRAM memory array, the layout comprising: a fin group formed in the semiconductor substrate for each column of the array and extending in a first direction; a bit line extending in the first direction for each column of the array in the form of a metal interconnect line; spaced apart first and second word lines, the first and second word lines extending in a second direction perpendicular to the first direction for each row in the array, the first word line passing over and electrically insulated from each fin set and forming a gate of a first transistor in a ReRAM memory cell in a row of the array, and the second word line passing over and electrically insulated from each fin set and forming a gate of a second transistor in a ReRAM memory cell in the row of the array; a bias line extending in the second direction for each row of the array in the form of a metal interconnect line; A plurality of ReRAM memory cells, each ReRAM memory cell being formed at an intersection of a row and a column of the array, each memory cell comprising: a ReRAM device formed on the fin set between the first word line and the second word line, the ReRAM device having a solid electrolyte terminal and an ion source terminal, the solid electrolyte terminal of each ReRAM device being electrically connected to a region of the fin set of the array containing the column of the memory cell at a location between the first word line and the second word line containing the row of the memory cell, the ion source terminal of each ReRAM device being electrically connected to the bias line containing the row of the memory cell; The region of the fin group is electrically connected to the solid electrolyte terminal of each ReRAM device, the region of the fin group forms a common drain of the first transistor and the second transistor in the ReRAM cell, and the region of the fin group outside the spaced-apart first word line and the second word line forms a separate source region of the first transistor and the second transistor in the ReRAM cell, the separate source region is electrically connected to the bias line of the row containing the ReRAM memory cell.

6. The product of claim 5, wherein: In addition to the end regions of the fin group, the region of the fin group outside the pair of spaced-apart word lines also forms a common source region for one of a first transistor and a second transistor in another memory cell adjacent to the memory cell in the column of the ReRAM memory cell.

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