Power semiconductor devices and their manufacturing processes

Abstract

The present application relates to the technical field of power semiconductor devices, and more specifically, to a power semiconductor device and its manufacturing process. The manufacturing process of the power semiconductor device includes the following steps: depositing an epitaxial layer on the front side of the substrate and completing the manufacturing of the front structure of the power semiconductor device; etching the back side of the substrate, etching through the entire substrate until the epitaxial layer, and forming a lead hole; filling the lead hole with metal and accumulating it on the back side of the substrate to form a back metal layer, and annealing the alloy, connecting the epitaxial layer to the back metal layer through metal leads. This process does not require thinning the substrate, but uses lead hole technology to lead out the back electrode. On the basis of not affecting the welding process and the electrical properties of the power semiconductor device, the thinning process is abolished, and the substrate is retained as a support, avoiding the risk of fragmentation caused by the thinning process and the subsequent thin film manufacturing process, and saving costs.

Description

Technical Field

[0001] The present application relates to the technical field of power semiconductor devices, and in particular to a power semiconductor device and a manufacturing process thereof. Background Art

[0002] In order to ensure the on-resistance or voltage drop of the chip, the chip manufacturing process in the prior art will perform back thinning on the wafer after the front process is completed. With the continuous development of chip manufacturing technology, the thickness of the chip is constantly thinning, and the thinner and thinner chip thickness will cause damage to the wafer, resulting in abnormal problems such as wafer fragments and missing corners, and bring an increasingly high fragmentation rate. In particular, as the wafer size continues to increase, the wafer fragmentation rate also rises sharply, resulting in a large amount of cost waste; in addition, the thinning process will cause changes in wafer stress, and insufficient stress release will lead to reliability problems in subsequent packaging. Summary of the invention

[0003] In order to solve the above technical problem or at least partially solve the above technical problem, the present application provides a method for manufacturing a power semiconductor device and a power semiconductor device manufactured by the method.

[0004] In order to achieve the above-mentioned purpose, according to one aspect of the present technical solution, the present technical solution provides a manufacturing process of a power semiconductor device.

[0005] According to the manufacturing process of the power semiconductor device of the embodiment of the present application, it includes the following steps:

[0006] Depositing an epitaxial layer on the front side of the substrate and completing the fabrication of the front side structure of the power semiconductor device;

[0007] Etching the back side of the substrate, etching through the entire substrate to the epitaxial layer, and forming a lead hole;

[0008] The lead holes are filled with metal and a back metal layer is formed on the back side of the substrate. The alloy is annealed and the epitaxial layer is connected to the back metal layer through metal leads.

[0009] Furthermore, the manufacturing process of the power semiconductor device also includes: before etching the back side of the substrate, cleaning the back side of the substrate to remove contamination and excess film layers on the back side of the substrate.

[0010] Furthermore, the manufacturing process of the power semiconductor device also includes: before etching the back side of the substrate, attaching a protective film to the front side of the power semiconductor device, and removing the protective film after etching to form the lead hole.

[0011] Furthermore, the protective film is a blue film, a UV film, a white film or a dry film.

[0012] Furthermore, the method for forming the lead hole includes:

[0013] coating a photoresist on the back side of the substrate;

[0014] Removing the photoresist at the position of the lead hole by a photolithography process to form a window to expose the substrate;

[0015] Removing the substrate in the area not covered by the photoresist by an etching method to form the lead hole;

[0016] After the etching of the substrate is completed, the remaining photoresist is removed.

[0017] Furthermore, the etching process for forming the lead hole is a dry etching process or a wet etching process.

[0018] Furthermore, the substrate includes one of a SiC substrate, a Si substrate, a sapphire substrate and a GaN substrate.

[0019] Furthermore, the manufacturing process of the power semiconductor device also includes: after the epitaxial layer is connected to the back metal layer through metal leads, the preparation of the power semiconductor device is completed through a packaging process.

[0020] In order to achieve the above-mentioned purpose, according to the second aspect of the present technical solution, the present technical solution also provides a power semiconductor device.

[0021] The power semiconductor device according to the embodiment of the present application is prepared by the above-mentioned power semiconductor device manufacturing process provided by the present application.

[0022] The power semiconductor device comprises a back metal layer, a substrate, an epitaxial layer and a front structure which are stacked in sequence from bottom to top, and the back metal layer is connected to the epitaxial layer through a metal arranged in the substrate.

[0023] Furthermore, a through lead hole is formed in the substrate, and a metal for connecting the back metal layer and the epitaxial layer is filled in the lead hole.

[0024] Furthermore, the front structure includes at least one of a source, a drain, a gate, an oxide layer, a field plate and a passivation layer.

[0025] The manufacturing process of the power semiconductor device provided by the technical solution of this application does not need to thin the substrate, but uses the lead hole technology to lead out the back electrode. On the basis of not affecting the welding process and the electrical properties of the power semiconductor device, the thinning process is abolished, the substrate is retained as a support, the risk of fragmentation caused by the thinning process and the subsequent thin-sheet manufacturing process is avoided, and the cost is saved. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The drawings constituting a part of this application are used to provide a further understanding of this application, so that other features, purposes and advantages of this application become more obvious. The schematic embodiment drawings and their descriptions of this application are used to explain this application and do not constitute an improper limitation on this application. In the drawings:

[0027] Figure 1 It is a schematic diagram of the structure of a power semiconductor device in the prior art;

[0028] Figure 2 A schematic diagram of the structure of a power semiconductor device provided in an embodiment of the present application;

[0029] Figure 3-8 A schematic structural diagram corresponding to each step of the method for manufacturing a GaN power semiconductor device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0030] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0031] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0032] In the present application, the directions or positional relationships indicated by the terms "upper", "lower", "inner", "middle", "outer", "front", "back", etc. are based on the directions or positional relationships shown in the drawings. These terms are mainly used to better describe the present application and its embodiments, and are not used to limit the indicated devices, elements or components to have a specific direction, or to be constructed and operated in a specific direction.

[0033] In addition, some of the above terms may be used to express other meanings in addition to indicating orientation or positional relationship. For example, the term "on" may also be used to express a certain dependency or connection relationship in some cases. For those of ordinary skill in the art, the specific meanings of these terms in this application can be understood according to specific circumstances.

[0034] In addition, the terms "disposed", "connected", and "fixed" should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be an internal connection between two devices, elements, or components. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0035] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0036] In production practice, technicians have found that in order to ensure the on-resistance or voltage drop of the chip, the power semiconductor device manufacturing process in the prior art will perform back-thinning on the wafer after the front-side process is completed. Figure 1 As shown, the substrate of the thinned power semiconductor device is removed and is directly connected to the epitaxial layer through the back metal layer. Figure 1 The thinning process of the power semiconductor device shown in the figure will cause damage to the wafer, resulting in abnormal problems such as wafer fragments and chipped corners, resulting in an increasingly high fragmentation rate. In particular, as the wafer size continues to increase, the wafer fragmentation rate also rises sharply, resulting in a large amount of cost waste. In addition, the thinning process will cause changes in wafer stress, and insufficient stress release will lead to reliability problems in subsequent packaging.

[0037] The exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the figures, the thickness of the layers and regions are magnified for the convenience of explanation, and the sizes shown do not represent the actual sizes. Although these figures do not completely and accurately reflect the actual size of the device, they still fully reflect the relative positions between the regions and the component structures, especially the upper and lower and adjacent relationships between the component structures. The reference figures are schematic diagrams of idealized embodiments of the present invention, and the embodiments shown in the present invention should not be considered to be limited to the specific shapes of the regions shown in the figures, but include the resulting shapes, such as deviations caused by manufacturing. At the same time, in the following description, the term substrate used can be understood to include semiconductor substrates that are being processed, and may include other thin film layers prepared thereon.

[0038] like Figure 3-8As shown, this embodiment discloses a method for manufacturing a power semiconductor device, which includes the following steps:

[0039] Step 1: Figure 3 As shown, a substrate 2 is provided, an epitaxial layer 3 is formed on the substrate 2, and the front structure 4 of the power semiconductor device is completed.

[0040] Wherein, the substrate 2 includes but is not limited to a SiC substrate, a Si substrate, a sapphire substrate or a GaN substrate. Wherein, the method for forming the epitaxial layer 3 includes but is not limited to a chemical vapor deposition process, such as MOCVD. The epitaxial layer 3 can be n-type or p-type, which is specifically set according to needs. In addition, the thickness of the epitaxial layer 3 can also be specifically set according to needs. For example, the typical thickness of the epitaxial layer of a power semiconductor device used in a high-speed digital circuit is 0.5 to 5 microns, and the typical thickness of the epitaxial layer used in a silicon power device is 50 to 100 microns.

[0041] Step 2: Etching the back side of the substrate 2 to etch through the entire substrate 2 until the epitaxial layer 3 to form a lead hole 5.

[0042] This step may specifically include:

[0043] First, if Figure 3 As shown, a protective film is attached to the front side of the power semiconductor device with the front side structure 4 completed, so as to protect the front side structure 4 of the power semiconductor device and prevent scratches and contamination of the front side when operating the back side of the power semiconductor device. Preferably, the protective film includes but is not limited to a blue film, a UV film, a white film or a dry film.

[0044] Then, yes Figure 3 In the structure shown in FIG. 1 , the back side of the substrate 2 is cleaned to remove the contamination and excess film layer on the back side of the substrate 2, and the structure shown in FIG. 1 is shown in FIG. Figure 4 The structure shown.

[0045] Then, a photoresist is coated on the back of the substrate 2, and the photoresist at the position of the lead hole is removed by a photolithography process to form a window to expose the substrate 2, so as to obtain a Figure 5 The structure shown.

[0046] Then, the substrate 2 in the area not covered by the photoresist is removed by etching, and the entire substrate 2 is etched through until the epitaxial layer 3 is formed to form the lead hole 6, and the following is obtained: Figure 6 The etching process for forming the lead hole 6 can be a dry etching process or a wet etching process.

[0047] Finally, after the etching of the substrate 2 is completed, the remaining photoresist and the protective film attached to the front surface are removed to obtain the following Figure 7 The structure shown.

[0048] In this step, the positions of the lead holes 6 are evenly distributed within the cell area of ​​the die to ensure that there is no potential difference on the back side. The number of lead holes 6 is preferably such that the total area of ​​the lead holes 6 on the back side is greater than or equal to the lead holes on the front side, so that it does not become a bottleneck for the conduction current.

[0049] Step 3: If Figure 8 As shown, metal 5 is filled in the lead hole 6 and a back metal layer 1 is formed on the back of the substrate 2, and the alloy is annealed, and the epitaxial layer 3 is wired to the back metal layer 1 through the metal 5. Since the substrate 2 is usually thick, the metal 6 in the lead hole 6 is preferably filled with metal tungsten using a tungsten plug process, and the material that can be used for the back metal layer 1 includes but is not limited to at least one of Al, Ti, Ni and Ag.

[0050] Step 4: Package the device through a packaging process to complete the preparation of the power semiconductor device.

[0051] The processing method of the power semiconductor device according to the above embodiment may further include other necessary steps, and the corresponding step implementation methods and sequences may refer to the prior art, which are known to ordinary technicians in this field and will not be described in detail here.

[0052] like Figure 2 and 8 As shown, the embodiment of the present application provides a power semiconductor device manufactured by the manufacturing process provided by the above embodiment, which is stacked from bottom to top in sequence with a back metal layer 1, a substrate 2, an epitaxial layer 3 and a front structure 4, and the back metal layer 1 is connected to the epitaxial layer 3 through a metal 5 provided in the substrate 2. As shown in the figure, a through lead hole 6 is formed in the substrate 2, and the metal 5 for connecting the back metal layer 1 and the epitaxial layer 3 is filled in the lead hole 6.

[0053] The front structure 4 includes but is not limited to at least one of a source, a drain, a gate, an oxide layer, a field plate and a passivation layer.

[0054] The power semiconductor device according to the above embodiment may also include other necessary components or structures, and the corresponding layout positions and connection relationships can refer to the power semiconductor devices in the prior art. The connection relationships, operations and working principles of the structures not mentioned are known to ordinary technicians in the field and will not be described in detail here.

[0055] Some embodiments in this specification are described in a progressive or parallel manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referenced to each other.

[0056] The above is only a specific embodiment of the present invention, so that those skilled in the art can understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but will conform to the widest range consistent with the principles and novel features applied herein.

Claims

1. A process for manufacturing a power semiconductor device, characterized in that: The following steps are involved: forming an epitaxial layer on the front side of the substrate and completing the fabrication of the front side structure of the power semiconductor device; Etching the back side of the substrate, etching through the entire substrate to the epitaxial layer, and forming a lead hole; Fill the lead holes with metal and form a back metal layer on the back of the substrate, anneal the alloy, and connect the epitaxial layer to the back metal layer through metal leads. The total area of ​​the lead holes on the back of the device is greater than or equal to the total area of ​​the lead holes on the front of the device.

2. The process for manufacturing a power semiconductor device according to claim 1, characterized in that: Also includes: Before etching the back side of the substrate, the back side of the substrate is cleaned to remove contamination and excess film layers on the back side of the substrate.

3. The process for manufacturing a power semiconductor device according to claim 1, characterized in that: Also includes: Before etching the back side of the substrate, a protective film is attached to the front side of the power semiconductor device, and the protective film is removed after etching to form the lead hole.

4. The process for manufacturing a power semiconductor device according to claim 3, characterized in that: The protective film is a blue film, a UV film, a white film or a dry film.

5. The process for manufacturing a power semiconductor device according to claim 1, characterized in that: The method of forming the lead hole comprises: coating a photoresist on the back side of the substrate; Removing the photoresist at the position of the lead hole by a photolithography process to form a window to expose the substrate; Removing the substrate in the area not covered by the photoresist by an etching method to form the lead hole; After the etching of the substrate is completed, the remaining photoresist is removed.

6. The process for manufacturing a power semiconductor device according to claim 1, characterized in that: The etching process for forming the lead hole is a dry etching process or a wet etching process.

7. The process for manufacturing a power semiconductor device according to claim 1, characterized in that: The substrate includes one of a SiC substrate, a Si substrate, a sapphire substrate and a GaN substrate.

8. The process for manufacturing a power semiconductor device according to claim 1, characterized in that: Also includes: After the epitaxial layer is connected to the back metal layer through metal leads, the power semiconductor device is prepared through a packaging process.

9. The process for manufacturing a power semiconductor device according to any one of claims 1 to 8, characterized in that: The manufactured power semiconductor device comprises a back metal layer (1), a substrate (2), an epitaxial layer (3) and a front structure (4) stacked in sequence from bottom to top, wherein the back metal layer (1) is connected to the epitaxial layer (3) via a metal (5) arranged in the substrate (2).

10. The process for manufacturing a power semiconductor device according to claim 9, characterized in that: A through lead hole (6) is formed in the substrate (2), and a metal (5) for connecting the back metal layer (1) and the epitaxial layer (3) is filled in the lead hole (6).

11. The process for manufacturing a power semiconductor device according to claim 9, characterized in that: The front structure (4) comprises at least one of a source electrode, a drain electrode, a gate electrode, an oxide layer, a field plate and a passivation layer.

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