Semiconductor power device and method of manufacturing the same

Abstract

The invention is entitled "Semiconductor power device and method of manufacturing the same". A device is disclosed comprising a first doped semiconductor region and a second oppositely doped semiconductor region separated by an undoped or lightly doped semiconductor drift region. The device further comprises a first electrode structure forming an ohmic contact with the first doped semiconductor region and a second electrode structure forming a universal contact with the second doped semiconductor region. The universal contact of the second electrode structure allows both electrons and holes to flow into and out of the device.

Description

[0001] Related applications

[0002] This application claims priority and benefit to U.S. Patent Application 16 / 667,631, filed October 29, 2019, and U.S. Provisional Patent Application 62 / 887,759, filed August 16, 2019, both of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to devices for power electronic devices, such as freewheeling or flyback diodes that can be connected across an inductor and used to eliminate flyback, which is a sudden voltage spike seen across an inductor when the supply current to the inductor suddenly decreases or is interrupted. Background Technology

[0004] Freewheeling or flyback diodes (also referred to herein as fast recovery diodes (FRDs)) are used to prevent damage to circuits that typically include loads with inductors and switching potentials. Inductors cannot change current instantaneously. Attempting to change the current rapidly, such as when a switch opens after energy has already accumulated in the inductor, will cause the inductor to generate a large electromotive force (EMF). A freewheeling diode placed in anti-parallel to the inductor provides a short-circuit path for the flow of decaying current in the inductor and thus dissipates the energy stored in the inductor.

[0005] In power electronics circuits used in many switching applications (e.g., industrial and automotive inverter applications), semiconductor devices (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistors (IGBTs), etc.) are used as switches to apply power to inductive loads. In power electronic circuits, a freewheeling diode (FRD) is placed in antiparallel with the switch (e.g., the IGBT) to provide a return path for the inductor discharge current. The FRD can contribute to significant power losses in switching circuits (e.g., in power inverter applications with IGBTs). Importantly, the FRD is designed for oscillatory, stable operation and low electromagnetic interference (EMI) in switching circuits. The desired FRD characteristics are low loss, fast switching, and soft reverse current recovery. Achieving these FRD characteristics involves trade-offs between diode parameters such as low forward voltage (VF), low reverse recovery charge (Qrr), and between high operating voltage and soft reverse current recovery. Summary of the Invention

[0006] In one general aspect, a device includes a first doped semiconductor region and a second oppositely doped semiconductor region separated by an undoped or lightly doped semiconductor drift region. The device also includes a first electrode structure forming an ohmic contact with the first doped semiconductor region and a second electrode structure forming a universal contact with the second doped semiconductor region. The universal contact of the second electrode structure allows both electrons and holes to flow into and out of the device.

[0007] In one aspect, an alternating array of P+ and N+ doped semiconductor regions in the second electrode structure forms the universal contact with the second doped semiconductor region.

[0008] In one general aspect, a device includes a first doped semiconductor region and a second oppositely doped semiconductor region separated by an undoped or lightly doped semiconductor drift region. The device also includes a first electrode structure forming an ohmic contact with the first doped semiconductor region and a second electrode structure including an alternating array of P+ and N+ doped semiconductor regions in contact with the second doped semiconductor region. The second electrode structure includes an oxide layer disposed between a metal layer and the P+ and N+ doped semiconductor regions of the alternating array.

[0009] In one aspect, in the second electrode structure, the oxide layer covers the P+ doped semiconductor regions and extends partially over the N+ doped semiconductor regions of the alternating array.

[0010] In one general aspect, a method includes growing an n-type epitaxial layer on an N-type semiconductor substrate; forming an anode structure on a top surface of the n-type epitaxial layer; backgrinding the N-type semiconductor substrate to reduce its thickness; and forming a cathode structure on a back surface of the backgrounded N-type semiconductor substrate. Forming the cathode structure includes forming a universal contact structure on the back surface of the backgrounded semiconductor substrate, and depositing a back metal on the back surface of the universal contact structure. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1A and Figure 1B is a schematic diagram showing an electrode structure of a p-i-n diode consistent with the present disclosure.

[0012] Figure 2 shows reverse recovery current of a p-i-n diode consistent with the present disclosure Figure 1A in FIG. 4.

[0013] Figure 3 shows a diode consistent with the present disclosure having an exemplary cathode structure including a universal contact to the diode.

[0014] Figure 4is a graphical illustration of an exemplary method for fabricating a diode having soft recovery characteristics in accordance with the present disclosure.

[0015] Figures 5A to 5F is a cross-sectional view of a portion of a semiconductor substrate being processed in different stages or steps of a method for fabricating a diode. Figure 4

[0016] Figure 6A and Figure 6B shows exemplary dopant concentrations in a rectangular cross-section of an exemplary diode having a common contact in its cathode structure.

[0017] Figure 7A and Figure 7B shows exemplary dopant concentrations in a rectangular cross-section of an exemplary diode having a common contact in its cathode structure.

[0018] Figure 8 is a graph showing simulated reverse recovery current and voltage for an exemplary diode having no backside p-n junction and for an exemplary diode having a backside p-n junction in its cathode structure.

[0019] Figure 9A is a graph showing simulated reverse recovery current for a set of diodes having different p-n area ratios in the common contact of the diodes.

[0020] Figure 9B is a portion of the graph of Figure 9A is an expanded view of a portion of the graph of

[0021] Figure 10 is a graph showing simulated forward current (IF) as a function of forward voltage (VF) for a set of diodes having different p-n area ratios in the common contact of the diodes.

[0022] Figure 11 is a graph showing simulated reverse load current (IR) as a function of load voltage (VR) for the same set of diodes as Figure 10

[0023] Figure 12 is a graph showing simulated reverse recovery current for a diode not including an oxide layer in its common contact and for a diode having an oxide layer covering the p-region of its common contact.

[0024] Figure 13 is a graph showing simulated forward current for the diodes of Figure 12 DETAILED DESCRIPTION

[0025] ​​​A p-i-n diode includes two oppositely doped semiconductor regions separated by an undoped or lightly doped semiconductor drift region. Each of the two oppositely doped semiconductor regions is in electrical contact (ohmic contact) with a respective electrode (i.e., an anode or a cathode) of the device, which allows charge carriers (i.e., holes or electrons) to flow into and out of the respective doped semiconductor region of the diode.

[0026] According to the principles of the present disclosure, at least one of the electrodes is configured to allow both holes and electrons to flow into and out of the respective doped semiconductor region of the diode.

[0027] The universal contact to the doped semiconductor region of the diode can have a structure that includes both a P-doped semiconductor region and an N-doped semiconductor region in contact with the respective doped semiconductor region of the diode. The P-doped semiconductor region and the N-doped semiconductor region can be present in different areas of the universal contact. A p-n area ratio can be used as a figure of merit to describe the ratio of the area of the universal contact occupied by the P-doped semiconductor region to the area of the universal contact occupied by the N-doped semiconductor region. The p-n area ratio is selected taking into account the reverse current recovery time of the device, and taking into account the forward current of the device.

[0028] Figure 1A An exemplary structure of an example freewheeling diode (e.g., FRD 100) according to the principles of the present disclosure is shown. The FRD 100 can have soft recovery characteristics for a power switching circuit.

[0029] Reference is made to Figure 1A The FRD 100 can have a p-i-n diode-like structure that includes two oppositely doped semiconductor regions (110, 130) separated by a semiconductor drift region 120. The semiconductor region 110 can be, for example, a p-doped semiconductor region, and the semiconductor region 130 can be an n-doped semiconductor region. The semiconductor drift region 120 can be, for example, an undoped or lightly doped semiconductor region compared to the two oppositely doped semiconductor regions 110, 130. The two oppositely doped semiconductor regions 110, 130 can be heavily doped as they are used to make the electrode structure (e.g., an anode structure 112 and a cathode structure 132, respectively) of the FRD 100.

[0030] The anode structure 112 can be, for example, a layer of metal or metal alloy that forms an ohmic contact with the semiconductor region 110 (e.g., a p-doped semiconductor region), thereby allowing the transport of holes into the semiconductor region 110.

[0031] Furthermore, in accordance with the principles of the present disclosure, a device electrode structure (e.g., cathode structure 132) can include a universal contact structure 133 interposed between a metal or metal alloy layer 134 and a semiconductor region 130 (e.g., an n-doped semiconductor region). The universal contact structure 133 can include a semiconductor region (e.g., a semiconductor region 133A of opposite polarity to the semiconductor region 130) that forms a p-n junction 135A along at least a portion of an interface 135 between the universal contact structure 133 and the semiconductor region 130. In an example implementation, the universal contact structure 133 can include at least a pair of semiconductor regions (133A, 133B) that alternate in a lateral direction (along the interface 135 between the universal contact structure 133 and the semiconductor region 130). The semiconductor region 133A can be, for example, a heavily P+ doped semiconductor region, while the semiconductor region 133B can be, for example, a heavily N+ doped semiconductor region. The semiconductor region 133A (backside p-doped region) forms a p-n junction 135A (backside p-n junction) along a portion of a lateral area or extent of the semiconductor region 130 along the interface 135.

[0032] In an example implementation, the semiconductor regions (133A, 133B) of the universal contact structure 133 can occupy different areas along the interface 135.

[0033] Figure 1B The figure is an exploded partial cross-sectional view of the FRD 100 shown in FIG. Figure 1A shows the semiconductor region 133A present along a length LI of the interface 135, while the semiconductor region 133B is present along a different length L2 of the interface 135. Thus, in the example shown in FIG. Figure 1B In the example shown in FIG. 1, the semiconductor region 133A and the semiconductor region 133B of the universal contact structure 133 are present along the interface 135 in an area ratio of LI :L2 (assuming the same depth of the semiconductor regions perpendicular to the plane of the figure). The area ratio of the semiconductor region 133A and the semiconductor region 133B along the interface 135 can be referred to hereinafter as the p-n area ratio of the universal contact structure 133. Figure 1B

[0034] The universal contact structure 133 can be in contact with the semiconductor region 130, allowing both holes and electrons to be transported into the semiconductor region 130. These holes can be transported into the semiconductor region 130, for example, via the P+ doped semiconductor region 133A, and these electrons can be transported into the semiconductor region 130, for example, via the N+ doped semiconductor region 133B.

[0035] When switching from the conducting state to the blocking state, the FRD 100 has stored charges (e.g., reverse recovery charges (Qrr)) in, for example, the semiconductor drift region 120, which must be discharged before the FRD 100 blocks reverse current. This discharge takes a finite amount of time, referred to as the reverse recovery time or t rr ​By allowing holes to be transported into the FRD 100 via the P+ doped semiconductor region 133A in addition to holes being transported into the semiconductor region 110 via the ohmic contact formed by the anode structure 112, the cathode structure 132 increases the reverse recovery time of the FRD 100, which exceeds the reverse recovery time of a conventional p-i-n diode structure (not shown) having a conventional ohmic anode and cathode contact (i.e., a non-universal contact) by increasing the tail of the reverse recovery current.

[0036] The increased reverse recovery time t rr of the FRD 100 can contribute to the soft recovery characteristics of the FRD 100. Figure 2 The reverse recovery current 210 of the FRD 100 is shown schematically, the reverse recovery current having a reverse recovery time t rr For comparison, Figure 2 The reverse recovery current 220 of a conventional p-i-n diode is also shown schematically, the reverse recovery current having a comparable reverse recovery time t rr .

[0037] As Figure 2 shown, the reverse recovery current 210 of the FRD 100 has a smooth curve that gradually returns to zero, and thus can be characterized as a “soft” recovery. In contrast, the reverse recovery current 220 of the conventional p-i-n diode has a noisy (i.e., fast, unsmooth) return to zero, and thus can be characterized as a “hard” recovery.

[0038] Figure 3 An FRD 100 having another exemplary cathode structure for universal contact with a diode in accordance with the principles of the present disclosure is shown. As Figure 3 shown, the FRD 100 can include a different cathode structure 332 in addition to the cathode structure 132 shown in Figure 1A .

[0039] The cathode structure 332, while generally similar to the cathode structure 132 of the FRD 100 (shown in Figure 1A ), further includes an oxide layer 336 interposed between the universal contact structure 133 and the metal layer 134. In an exemplary implementation, the oxide layer 336 can cover the P+ semiconductor region 133A and can extend partially over the N+ semiconductor region 133B. The oxide layer 336 covering the P+ semiconductor region 133A can act as a barrier to hole flow, preventing holes from leaking out of the FRD 100 through the cathode 332, and further improving the diode characteristics.

[0040] Figure 4 A method 400 for manufacturing an FRD (e.g., the FRD 100) having soft recovery characteristics is shown. Figures 5A to 5Fmay be combined Figure 1A and Figure 1B (And Figure 3 ) can be observed, which schematically illustrate cross-sectional views of portions of a semiconductor substrate as it is processed at different stages or steps of the method 400 to fabricate the FRD 100.

[0041] As shown in Figure 4 , the method 400 includes growing an n-type epitaxial layer (410) on an N-type semiconductor substrate (e.g., an N+ doped silicon substrate). The n-type epitaxial layer (which forms a drift region, e.g., the semiconductor region 120 of the FRD 100) can be un-doped or lightly doped at a concentration lower than that of the N-type semiconductor substrate.

[0042] The method 400 also includes forming an anode structure of the FRD (420). Forming the anode structure can include forming a P+ layer on a top surface of the n-type epitaxial layer and depositing a metal layer on the P+ layer to form the anode structure of the FRD 100. The P+ layer can be formed by thermal diffusion and / or implantation of p-dopant species into the top surface of the n-type epitaxial layer.

[0043] The method 400 also includes backgrinding the semiconductor substrate to reduce its thickness (430). The reduced thickness of the backgrinded semiconductor substrate can correspond to the thickness of the buffer layer of the FRD 100.

[0044] The method 400 also includes forming a universal contact (e.g., the universal contact structure 133) on a back surface of the backgrinded semiconductor substrate (440). Forming the universal contact can involve a buffer implant (e.g., implanting n-dopant such as phosphorous), followed by implantation of p-dopant (e.g., boron) into the back surface of the backgrinded semiconductor substrate. Forming the universal contact can also involve a photolithographic patterning step to delineate the P+ region 134A and the N+ region 134B of the universal contact structure 133, followed by implantation of n-dopant (e.g., phosphorous) to form the N+ region 134B. A laser anneal step can be performed to activate the aforementioned dopants in the universal contact structure 133.

[0045] The method 400 also includes depositing a backside metal on a back surface of the universal contact structure 133 to form a cathode structure of the FRD 100 (450).

[0046] In an example implementation in which the FRD 100 includes the cathode structure 332 Figure 3 as shown in, forming the universal contact on the back surface of the backgrinded semiconductor substrate 440 in the method 400 can include patterning and depositing an oxide layer (e.g., the oxide layer 336) over the P+ region 134A and partially over the N+ region 134B. The oxide layer can be deposited prior to depositing the backside metal on the back surface of the universal contact structure 133.

[0047] As previously described, Figures 5A to 5F A cross-sectional view of a portion of a semiconductor substrate as it is processed at different stages or steps of the method 400 to fabricate the FRD 100 is schematically illustrated.

[0048] Figure 5A A portion of a semiconductor substrate 510 that is processed, e.g., by the method 400, to fabricate the FRD 100 is illustrated. In example implementations, the semiconductor substrate 510 can be an N+ silicon wafer having a resistivity in a range of about 0.001 W-cm to 50 W-cm.

[0049] Figure 5B An epitaxial layer 520 grown on the semiconductor substrate 510, e.g., at step 410 of the method 400, is illustrated. In example implementations, the epitaxial layer 520 can be an un-doped or lightly doped epitaxial layer having a resistivity in a range of, e.g., 20 W-cm to 200 W-cm and having a thickness in a range of, e.g., about 10 pm to 100 pm.

[0050] Figure 5C An anode structure 530 of the FRD 100 is formed, e.g., at step 420 of the method 400. The anode structure 530 can include, e.g., a P+ layer 532 on a top surface of the epitaxial layer 520 and a metal layer 534 deposited on the P+ layer 532.

[0051] Figure 5D The semiconductor substrate 510 is illustrated as having a reduced thickness T after backgrinding, e.g., at step 430 of the method 400.

[0052] Figure 5E A universal contact 533 (having alternating P-doped and N-doped regions) is formed on a backside of the semiconductor substrate 510 having the reduced thickness T, e.g., at step 440 of the method 400.

[0053] Figure 5F A backside metal 535 is deposited on a back surface of the universal contact 533 to form a cathode structure 537 of the FRD 100, e.g., at step 450 of the method 400.

[0054] Figure 6A is an X-Y plot of a cross-section of the diode 610, with trace CI extending from a top of the diode 610 to a bottom of the diode 610. An example diode 610 can have a vertical die thickness t of about 0.114 millimeters and a lateral die area of about 11 square millimeters (e.g., in a plane perpendicular to Figure 6A the diode 610 has a conventional cathode structure (i.e., does not have a backside p-n junction).Figure 6B This is an XY graph showing the dopant concentration in diode 610 along trace C1.

[0055] Figure 7A This is an XY plot of a cross-section of diode 710, where trace C1 extends from the top of diode 710 to the bottom of diode 710. An exemplary diode 710 may have a universal contact comprising an N+ semiconductor region 712A and a P+ semiconductor region 722 forming a back-side pn junction 732. Diode 710 may have a vertical die thickness t of approximately 0.114 mm and a lateral die area of ​​approximately 11 square millimeters (e.g., in a direction perpendicular to...). Figure 7A (in a plane, not shown). Figure 7B This is an XY graph showing the dopant concentration in the general contact region of diode 710 along trace C1.

[0056] Figure 8 This is a graph showing the simulated reverse recovery current 810 and voltage 830 for diode 610 (without a back-side pn junction), and the reverse recovery current 820 and voltage 840 for diode 710 (with a universal contact including a back-side pn junction in its cathode structure). The simulation was performed using a Technology Computer-Aided Design (TCAD) tool, where the diodes were placed in an inductor-resistor circuit with the following parameters: diode area 11 mm²; die thickness 0.114 mms; reverse voltage (VR) = 800 V; and forward current (IF) = 40 A.

[0057] like Figure 8 As observed, when comparing reverse recovery current 820 and reverse recovery current 810, diode 710 (with a universal contact including a back-side p-junction) exhibits a softer recovery than diode 610 (without a universal contact).

[0058] Figure 9A The simulated reverse recovery currents of a group of diodes with different pn area ratios in their common contact are shown. Reverse recovery current 910 corresponds to a diode with a common contact pn area ratio of 0:200 (i.e., a diode without a common contact); reverse recovery current 920 corresponds to a diode with a common contact pn area ratio of 50:100; reverse recovery current 930 corresponds to a diode with a common contact pn area ratio of 100:100; and reverse recovery current 940 corresponds to a diode with a common contact pn area ratio of 150:100.

[0059] Figure 9A A portion of it is enclosed within a dashed rectangle 97. Figure 9B It shows Figure 9A An exploded view of the portion enclosed in the dashed rectangle 97.

[0060] In Figure 9A and Figure 9B , the arrow 91 is overlaid on the reverse recovery current curve as a visual aid to indicate the direction of increasing p-n area ratio in the common contact of the diode (i.e., 0:100 to 150:100).

[0061] The length of the tail of the reverse current curve approaching zero is a measure of the softness of the reverse current recovery of the diode. As seen in Figure 9A and Figure 9B , the length of the tail 93 of the reverse recovery current increases as the p-n area ratio in the common contact of the diode increases. Thus, increasing the p-n area ratio in the common contact of the diode can increase the softness of the reverse current recovery of the diode.

[0062] Figure 10 Simulated forward current (IF) as a function of forward voltage (VF) is shown for a set of diodes having different p-n area ratios in the common contact of the diodes. Forward current 1010 corresponds to a diode without a common contact (i.e., a diode without a common contact); forward current 1020 corresponds to a diode with a common contact p-n area ratio of 50:150 (i.e., 0.33:1); forward current 1030 corresponds to a diode with a common contact p-n area ratio of 100:100 (i.e., 1:1); and forward current 1040 corresponds to a diode with a common contact p-n area ratio of 150:100 (i.e., 1.5:1).

[0063] Figure 11 Simulated reverse load current (IR) as a function of load voltage (VR) is shown for the same set of diodes as Figure 10 . Reverse load current 1110 corresponds to a diode without a common contact p-n area ratio (i.e., a diode without a common contact); reverse load current 1120 corresponds to a diode with a common contact p-n area ratio of 50:150 (i.e., 0.33:1); reverse recovery current 1130 corresponds to a diode with a common contact p-n area ratio of 100:100 (i.e., 1:1); and reverse recovery current 1140 corresponds to a diode with a common contact p-n area ratio of 150:100 (i.e., 1.5:1).

[0064] The arrow 92 is overlaid on the forward current curves in Figure 10 (and the reverse load current curves in Figure 11 ) as a visual aid to indicate the direction of increasing p-n area ratio in the common contact of the diode (i.e., 0:200 to 150:100).

[0065] As seen in Figure 10As seen, the forward voltage of the diode increases with an increase in the p-n area ratio in the common contact of the diode (e.g., from 0:200 to 150:50). However, as Figure 11 As seen, the reverse load current curves (1110, 1120, 1130, and 1140) for different p-n area ratios are clustered together and substantially overlap each other in the voltage range of 1500 V to 170 V. An increase in the p-n area ratio in the common contact of the diode appears to have no effect on the breakdown voltage (Vbr) of the diode (in other words, the breakdown voltage Vbr of the diode appears to be independent of the p-n area ratio).

[0066] As previously described (with reference to Figure 3 ), the characteristics of the diode can be further improved by including an oxide layer in the common contact. Figure 12 The simulated reverse recovery current 1210 of a diode is shown that does not include an oxide layer in its common contact (e.g., having a p-n area ratio of 75:25 (i.e., 3: 1)). For comparison, Figure 12 The simulated reverse recovery current 1220 of a diode is also shown that has an oxide layer covering the p-region of its common contact (e.g., having a p-n area ratio of 50:50 (i.e., 1: 1)).

[0067] Figure 13 The simulated forward current 1310 of a diode is shown that does not include an oxide layer in its common contact (e.g., having a p-n area ratio of 75:25 (i.e., 3: 1)). For comparison, Figure 13 The simulated forward current 1320 of a diode is also shown that has an oxide layer covering the p-region of its common contact (e.g., having a p-n area ratio of 50:50 (i.e., 1: 1)).

[0068] As Figure 12 seen (compare current 1210 and current 1220), the introduction of an oxide layer in the common contact results in a softer reverse current recovery in the diode. As Figure 13 shown (compare current 1310 and current 1320), the introduction of an oxide layer in the common contact results in a smaller forward current in the diode.

[0069] The simulated currents and voltages described above with reference to Figures 6A to 13 indicate that the incorporation of a common contact including a backside p-n junction in a cathode structure improves the soft reverse current recovery characteristics of the diode. The inclusion of an oxide layer over the P region of the common contact additionally improves the reverse current recovery of the diode.

[0070] It should also be understood that when an element (such as a transistor or resistor) is referred to as being on, connected to, electrically connected to, coupled to, or electrically coupled to another element, the element may be directly on, connected to, or coupled to the other element, or one or more intermediate elements may be present. Conversely, when an element is referred to as being directly on, directly connected to, or directly coupled to another element or layer, no intermediate elements or layers are present. Although the terms "directly on," "directly connected to," or "directly coupled to" may not be used throughout the specific embodiments, elements shown as being directly on, directly connected to, or directly coupled to an element can be referred to in this manner. The claims of this application (if included) may be amended to describe the exemplary relationships described in the specification or shown in the drawings.

[0071] As used herein, the singular form may include the plural form unless the context clearly indicates otherwise. In addition to the orientations shown in the figures, spatial relative terms (e.g., above, on, above, below, under, beneath, etc.) are intended to cover different orientations of the device in use or operation. In some embodiments, the relative terms above and below may respectively include vertically above and vertically below. In some embodiments, term proximity may include lateral proximity or horizontal proximity.

[0072] Implementations of the various techniques described herein may be carried out in digital electronic circuits, computer hardware, firmware, software, or combinations thereof (e.g., included therein). Parts of the methods may also be implemented using dedicated logic circuitry such as FPGAs (Field-Programmable Gate Arrays) or ASICs (Application-Specific Integrated Circuits), and the apparatus may be implemented as such dedicated logic circuitry.

[0073] The implementation can be implemented in a computing system that includes industrial motor drives, solar inverters, ballasts, general-purpose half-bridge topologies, auxiliary and / or traction motor inverter drives, switch-mode power supplies, on-board chargers, uninterruptible power supplies (UPS), back-end components (e.g., as data servers), or middleware components (e.g., application servers), or front-end components (e.g., client computers with graphical user interfaces or web browsers through which users can interact with the implementation), or any combination of such back-end, middleware, or front-end components. Components can be interconnected via digital data communication (e.g., communication networks) of any form or medium. Examples of communication networks include local area networks (LANs) and wide area networks (WANs), such as the Internet.

[0074] While certain features of the described implementations have been illustrated as described herein, many modifications, substitutions, changes and equivalents will now occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the scope of the specific implementations. It should be understood that they have been presented by way of example only, not limitation, and various changes in form and details can be made. Any portion of the apparatus and / or methods described herein can be combined in any combination, except for combinations where one or more features are mutually exclusive with each other. Implementations described herein can include various combinations and / or sub-combinations of the functions, components and / or features of the different implementations described.

Claims

1. A diode device, the device comprising: A first doped semiconductor region and a second doped semiconductor region with opposite doping, the first doped semiconductor region and the second doped semiconductor region being separated by an undoped or lightly doped semiconductor drift region; A first electrode structure, wherein the first electrode structure forms an ohmic contact with the first doped semiconductor region; The second electrode structure includes a universal contact structure that forms a universal contact with the second doped semiconductor region. This universal contact allows the flow of both electrons and holes. The universal contact structure includes at least one P+ doped semiconductor region and at least one N+ doped semiconductor region that are in contact with and mutually contact with the second doped semiconductor region. The second electrode structure further includes a metal or metal alloy layer, and the general contact structure is disposed between the metal or metal alloy layer and the second doped semiconductor region; An oxide layer is disposed between at least a portion of the general contact structure, including the P+ doped semiconductor region, and the metal or metal alloy layer.

2. The device of claim 1, wherein the first electrode structure comprises a P+ layer formed on the top surface of the first doped semiconductor region and a metal layer deposited on the P+ layer.

3. The device of claim 1, wherein the at least one P+ doped semiconductor region has a first region in contact with the second doped semiconductor region, and the at least one N+ doped semiconductor region has a second region in contact with the second doped semiconductor region, the ratio of the first region and the second region forming the pn area ratio of the universal contact, and wherein the pn area ratio determines the reverse current recovery time of the device and the forward current of the device.

4. The device of claim 1, wherein the first doped semiconductor region is a p-doped semiconductor region, the second doped semiconductor region is an N-type semiconductor substrate region having a resistivity in the range of 0.001 Ω-cm to 50 Ω-cm, and the undoped or lightly doped semiconductor drift region is an n-type epitaxial semiconductor region having a resistivity in the range of 20 Ω-cm to 200 Ω-cm.

5. A diode device, the device comprising: A first doped semiconductor region and a second oppositely doped semiconductor region, wherein the first doped semiconductor region and the second oppositely doped semiconductor region are separated by an undoped or lightly doped semiconductor drift region; A first electrode structure, wherein the first electrode structure forms an ohmic contact with the first doped semiconductor region; The second electrode structure includes an alternating array of P+ doped semiconductor regions and N+ doped semiconductor regions in contact with the second doped semiconductor region. The second electrode structure also includes an oxide layer disposed between a metal layer and the alternating array of P+ doped semiconductor regions and N+ doped semiconductor regions.

6. The device of claim 5, wherein the oxide layer covers the P+ doped semiconductor region and extends partially over the N+ doped semiconductor regions of the alternating array.

7. A method for manufacturing a diode device, the method comprising: Growing an n-type epitaxial layer on an N-type semiconductor substrate; An anode structure is formed on the top surface of the n-type epitaxial layer; The N-type semiconductor substrate is back-ground to reduce its thickness; as well as The cathode structure is formed by: A universal contact structure with P+ and N+ regions is formed on the back surface of a back-ground semiconductor substrate; and Deposit back-side metal on the back surface of the universal contact structure. The formation of the general contact structure also includes: An oxide layer is patterned and deposited over the P+ region of the universal contact structure and partially over the N+ region of the universal contact structure; and The back metal is deposited over the oxide layer.

8. The method of claim 7, wherein forming the universal contact structure comprises: An n-type dopant is implanted into the back surface of the back-polished semiconductor substrate; A p-type dopant is implanted into the back surface of the back-polished semiconductor substrate; Photolithographic patterning is performed to outline the P+ and N+ regions of the general contact structure; Implanting n-type dopants to form the N+ region of the general contact structure; as well as Laser annealing is performed to activate the implanted p-type and n-type dopants to form the P+ and N+ regions of the general contact structure.

9. The method of claim 7, wherein the N-type semiconductor substrate has a resistivity in the range of 0.01 Ω-cm to 10 Ω-cm, and the n-type epitaxial layer has a resistivity in the range of 20 Ω-cm to 200 Ω-cm.

10. The method of claim 7, wherein forming the anode structure comprises: A P+ layer is formed on the top surface of the n-type epitaxial layer by thermal diffusion and / or implantation of p-type dopant material into the top surface of the n-type epitaxial layer; as well as A metal layer is deposited on the P+ layer.

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