Capacitance Reduction Scheme for Operational Amplifiers

Abstract

The present invention discloses an operational amplifier, comprising a first differential input pair, a first switch and a second switch. The first differential input pair comprises a first input transistor and a second input transistor. The first input transistor has a gate terminal coupled to an output terminal of the operational amplifier. The second input transistor has a gate terminal. The first switch is coupled between the gate terminal of the first input transistor and the gate terminal of the second input transistor. The second switch is coupled between a first input terminal of the operational amplifier and the gate terminal of the second input transistor.

Description

Technical Field

[0001] The invention relates to an operational amplifier, and in particular to an operational amplifier that can be used for a source driving device of a panel. Background Art

[0002] Operational amplifiers are basic circuit components commonly used in analog integrated circuits (Analog Integrated Circuit, Analog IC), which can be, for example, source driving devices or data driving devices of panels. Under the design and application of source driving integrated circuits with high resolution and low offset (i.e., small data voltage deviation), the bandwidth and speed of the single-stage design of operational amplifiers (hereinafter referred to as source amplifiers (Source Operational Amplifier, S-OP)) used as output buffers in existing source driving circuits have met the requirements. However, due to the excessive parasitic capacitance of the input pair, the output speed of the source amplifier has a bottleneck and cannot be improved. This bottleneck mainly comes from the resistance and capacitance delay (RC delay) generated from the output end of the digital-to-analog converter (Digital-to-Analog Converter, DAC) to the input end of the source amplifier.

[0003] Please refer to Figure 1 , Figure 1 is a schematic diagram of a source driving circuit 10 . Figure 1The circuit between the output buffer of the gamma voltage generating circuit and the source amplifier (S-OP) is shown. The output buffer of the gamma voltage generating circuit can usually be implemented by an operational amplifier, so it is also called an input gamma operational amplifier (IGOP). The seven tap voltages Gamma1 to Gamma7 generated by the input gamma operational amplifier are divided by the gamma resistors to generate multiple gamma voltages output to the resistor-ladder DAC (RDAC). According to the input image data (for example, an 8-bit or 10-bit data code), the resistor-ladder DAC can select a gamma voltage corresponding to the input image data from the multiple gamma voltages and transmit it to the input end of the source amplifier. The resistor-ladder DAC includes multiple switches, which are respectively controlled by control signals corresponding to the input image data. When the resistor ladder digital-to-analog converter performs voltage selection, some of the switches are turned on, and the impedance (i.e., Ron) formed by a series of conduction paths plus the parasitic capacitance of the differential input pair of the source amplifier and the parasitic capacitance on the path produce a time delay in the charging and discharging of resistors and capacitors. This resistor and capacitor time delay will seriously limit the signal transmission of the entire source driver integrated circuit system at high resolution.

[0004] In order to reduce the time delay generated by the circuit from the resistor ladder digital-to-analog converter to the source amplifier input pair, a simple solution is to reduce the impedance of the switch of the resistor ladder digital-to-analog converter or reduce the number of resistors in the resistor string. However, when the resistor ladder digital-to-analog converter or the resistor string is simplified to the extreme, a larger time delay will be generated with the application of higher resolution.

[0005] Please refer to Figure 2 , Figure 2A plurality of differential input pairs in an input stage circuit 200 of a conventional source amplifier are shown. The plurality of differential input pairs can generate more detailed input data voltage levels by interpolation to improve the data voltage resolution output by the source amplifier. For example, if an 8-bit resolution is desired, a 6-bit digital-to-analog converter can be used in combination with a 2-bit source amplifier. In a typical structure such as a differential difference amplifier (DDA), there are a plurality of differential input pairs, each of which is composed of a plurality of metal oxide semiconductor field-effect transistors (MOSFET) and coupled to a plurality of current sources (receiving a bias voltage VB), wherein different differential input pairs can receive slightly different input data voltages (e.g., input data voltages Vin1+, Vin1-, Vin2+, Vin2-, Vin3+, Vin3-... etc., such as Figure 2 As shown in the figure, the data voltage deviation is also required for interpolation. When the system has a higher color resolution requirement, such as 8-bit to 10-bit or even 12-bit, a lower data voltage deviation is also required. However, the area of ​​the differential input pair of the source amplifier increases rapidly. For example, under the differential differential amplifier architecture, when the resolution is increased by 2 bits, the circuit area of ​​the differential input pair will increase by 4 times (its parasitic capacitance also increases proportionally), resulting in a rate-dependent increase in the parasitic capacitance of the output end of the resistor ladder digital-to-analog converter, which exacerbates the input signal delay of the source amplifier. Summary of the invention

[0006] Therefore, the main purpose of the present invention is to provide a capacitance reduction solution for an operational amplifier of a source driving device to solve the above-mentioned problem.

[0007] An embodiment of the present invention discloses an operational amplifier, which includes a first differential input pair, a first switch and a second switch. The first differential input pair includes a first input transistor and a second input transistor. The first input transistor has a gate terminal coupled to an output terminal of the operational amplifier. The second input transistor has a gate terminal. The first switch is coupled between the gate terminal of the first input transistor and the gate terminal of the second input transistor. The second switch is coupled between a first input terminal of the operational amplifier and the gate terminal of the second input transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic diagram of a source driving circuit.

[0009] Figure 2 A plurality of differential input pairs in an input stage circuit of a conventional source amplifier are shown.

[0010] Figure 3 FIG. 1 is a schematic diagram of an input stage circuit of an operational amplifier according to an embodiment of the present invention.

[0011] Figure 4 An example of a source amplifier having multiple positive input terminals and multiple negative input terminals is shown.

[0012] Figure 5 Schematic diagram of voltage switching in normal driving mode and speed-up driving mode.

[0013] Figures 6 to 9 FIG. 4 is a schematic diagram of an input stage circuit of a source amplifier according to an embodiment of the present invention.

[0014] Fig. 10A and 10B FIG. 1 is a schematic diagram of an input stage circuit of a source amplifier according to an embodiment of the present invention.

[0015] Fig.11 FIG. 1 is a schematic diagram of a source driving circuit according to an embodiment of the present invention.

[0016] Fig.12 Shows Fig.11 An example schematic diagram of a capacitance reduction circuit in FIG.

[0017] Fig.13A and 13B The detailed operation of the capacitance reduction circuit during the display line period is shown.

[0018] Fig.14 A practical circuit diagram of a capacitance reduction circuit is shown.

[0019] Fig.15 Graph showing the waveform of the relevant control signal of the capacitance reduction circuit.

[0020] The reference numerals are described as follows:

[0021] 10, 110 Source drive circuit

[0022] S-OP, 40 Source Amplifier

[0023] IGOP Input Gamma Operational Amplifier

[0024] Gamma1~Gamma7 pinch voltage

[0025] RDAC Resistor Ladder Digital-to-Analog Converter

[0026] Ron Impedance

[0027] 200, 300, 600, 800, 900, 100 Input stage circuit

[0028] VB, VB1~VB3 bias voltage

[0029] Vin1+, Vin1-, Vin2+, Vin2-, Vin3+, input data voltage

[0030] Vin3-、Vink+、Vink-、Vin(k+1)+、

[0031] Vin(k-1)-、Vinx+、Vinx-、VinN+、

[0032] VinN-

[0033] DP1~DP3 differential input pair

[0034] MP1~MP3、MN1~MN3 Input transistor

[0035] MB1~MB3、CS11、CS12、CS21、 Transistor

[0036] CS22, CS31, CS32

[0037] SW2A, SW2B, SW3A, SW3B, Switches

[0038] SWB11, SWB12, SWB21, SWB22,

[0039] SWB31、SWB32

[0040] I Bias current value

[0041] C+ Positive input capacitor

[0042] C- Negative input capacitor

[0043] S1, S2, RF_CK, RF_CK', R_N, control signal

[0044] R_P、F_N、F_P

[0045] 1102 Capacitance Reduction Circuit

[0046] P_1~P_N positive input terminal

[0047] N_1~N_N Negative input terminal

[0048] ΔV Voltage difference

[0049] CD1, CD2 clamping device DETAILED DESCRIPTION

[0050] Please refer to Figure 3 , Figure 3FIG. 3 is a schematic diagram of an input stage circuit 300 of an operational amplifier according to an embodiment of the present invention. The input stage circuit 300 may include a plurality of differential input pairs. Figure 3 Three differential input pairs DP1-DP3 are shown. The differential input pair DP1 is composed of input transistors MP1 and MN1, which can operate by receiving a current supply from a current source (composed of a transistor MB1). The differential input pair DP2 is composed of input transistors MP2 and MN2, which can operate by receiving a current supply from a current source (composed of a transistor MB2). The differential input pair DP3 is composed of input transistors MP3 and MN3, which can operate by receiving a current supply from a current source (composed of a transistor MB3). By receiving a bias voltage VB, transistors MB1-MB3 can be used to supply a bias current (or tail current). In this example, each differential input pair DP1-DP3 receives the same bias current value I. Similar to the input stage circuit 200, the differential input pairs of the input stage circuit 300 are also used to receive slightly different input data voltages Vin1+, Vin1-, Vin2+, Vin2-, Vin3+, Vin3-, etc. for interpolation to output the required voltage level with higher resolution.

[0051] like Figure 3 As shown, the input stage circuit 300 also includes: a switch SW2A coupled between the gate terminal of the input transistor MP2 and the positive input terminal of the operational amplifier (which is used to receive the input data voltage Vin2+), a switch SW2B coupled between the gate terminal of the input transistor MP2 and the gate terminal of the input transistor MN2, a switch SW3A coupled between the gate terminal of the input transistor MP3 and the other positive input terminal of the operational amplifier (which is used to receive the input data voltage Vin3+), and a switch SW3B coupled between the gate terminal of the input transistor MP3 and the gate terminal of the input transistor MN3.

[0052] When the operational amplifier is used as an output buffer of the source driving device (hereinafter referred to as a source amplifier (Source Operational Amplifier, S-OP)), the operational amplifier is coupled to a resistor-ladder DAC (Resistor-ladder DAC, RDAC) in a gamma voltage generating circuit. More specifically, the positive input terminal of the source amplifier is coupled to the resistor-ladder DAC, and the negative input terminal of the source amplifier is coupled to the output terminal of the source amplifier to form a buffer structure. Figure 4An example of a source amplifier 40 having multiple positive input terminals and multiple negative input terminals is shown, wherein at least one positive input terminal is configured to be coupled to the output terminal of the resistor ladder digital-to-analog converter, and all negative input terminals are coupled to the output terminal of the source amplifier 40 itself.

[0053] Please refer back Figure 3 , the differential input pair DP2 and DP3 in the input stage circuit 300 can be operated in two different driving modes by the control of the switches. For the differential input pair DP2, under a normal driving mode (a first driving mode), the switch SW2A is turned on and the switch SW2B is turned off, so that the gate terminal of the input transistor MP2 is coupled to the input terminal of the source amplifier, so as to be further coupled to the resistance ladder digital-to-analog converter; under a speed-up driving mode (a second driving mode), the switch SW2A is turned off and the switch SW2B is turned on, so that the gate terminal of the input transistor MP2 is coupled to the gate terminal of the input transistor MN2. In addition, the operation of the switches SW3A and SW3B is similar to that of the switches SW2A and SW2B, and can be used to realize different driving modes of the differential input pair DP3, and the related operations are not repeated here.

[0054] Therefore, under the speed-up driving mode, the gate terminals of the positive input transistors in some differential input pairs (i.e., DP2 and DP3) are coupled to the gate terminals of the corresponding negative input transistors, and the connection between the gate terminals of the positive input transistors in these differential input pairs and the input terminals of the source amplifiers is disconnected. Under such an arrangement, only a few differential input pairs in the source amplifier are enabled, and the parasitic capacitance of the differential input pairs in the source amplifier can be quickly charged and discharged by the source amplifier. In this way, the parasitic capacitance at the output of the resistor ladder digital-to-analog converter can be greatly reduced to alleviate the phenomenon of resistor-capacitor delay (RC delay). Figure 3 In the diagrams of the following embodiments, the connection between the negative input terminal of the differential input pair and the output terminal of the source amplifier is omitted, but those skilled in the art should understand that the negative input terminal of the differential input pair can be commonly coupled to the output terminal to form a buffer structure, such as Figure 4 The circuit shown.

[0055] During a display line period (or display output period), a row of new display data is loaded into the operational amplifier of the source driver, so that a large number of source amplifiers are simultaneously switched to receive the selected data voltage corresponding to the new display data from the resistor ladder digital-to-analog converter. The data voltage selected by the resistor ladder digital-to-analog converter changes due to the transformation of the pixel data, so the input data voltage of the source amplifier reaches a steady state after a rise time or a fall time during the display line period. Among them, the rise time represents the period during which the input data voltage of the source amplifier rises from the current level to a higher level; the fall time represents the period during which the input data voltage of the source amplifier falls from the current level to a lower level. In this example, the switches SW2A, SW2B, SW3A and SW3B can be operated in the rising time or the falling time of the input data voltage of the source amplifier during a display line period in the rising time or the falling time. During the rising time and / or the falling time of the input data voltage of the source amplifier, the positive gate terminals of more sets of differential input pairs should be controlled to be coupled to the corresponding negative gate terminals. Specifically, the input stage circuit may arrange only one or a few of the positive gate terminals of the differential input pairs to receive the data voltage output by the resistor ladder digital-to-analog converter, while the positive gate terminals and negative gate terminals of the majority of the differential input pairs are connected to the output terminal (i.e., the feedback terminal) of the source amplifier. Figure 3 In the embodiment of the invention, in the boost driving mode, the switches SW2A and SW3A are turned off and the switches SW2B and SW3B are turned on, so that the gate terminals of the positive input transistors MP2 and MP3 are respectively coupled to the gate terminals of the corresponding negative input transistors MN2 and MN3. The disconnected switches SW2A and SW3A can reduce the parasitic capacitance of the output terminal of the resistance ladder digital-to-analog converter, thereby reducing the time delay of signal transmission.

[0056] On the other hand, in the normal driving mode, the gate terminals of the positive input transistors in all the differential input pairs DP1-DP3 are coupled to the input terminals of the source amplifiers, and further coupled to the corresponding output terminals of the resistance ladder digital-to-analog converters. For example, when the input data voltage of the source amplifier is close to being stable (i.e., close to its target voltage value), the switches SW2A and SW3A can be turned on and the switches SW2B and SW3B can be turned off to perform normal driving and control the output terminals of the source amplifiers to reach the correct voltage value.

[0057] Please continue to refer to Figure 4 Matching Figure 3As shown, except for the first differential input pair (such as DP1) for receiving the input data voltage Vin1+, the other differential input pairs (such as DP2, DP3, etc.) are all controlled by switches to select coupling to the corresponding input terminal or the corresponding negative gate terminal under different driving modes. Under the normal driving mode, all switches coupled between the gate terminal of the positive input transistor and the input terminal of the source amplifier 40 are turned on, and all switches coupled between the gate terminal of the positive input transistor and the gate terminal of the negative input transistor are turned off, so the overall capacitance seen by the positive input terminal (i.e., C+) is equal to C1+C2+C3+…, where C1, C2, C3… respectively represent the parasitic capacitance of each positive input transistor. At the same time, the overall capacitance seen by the negative input terminal (i.e., C-) is equal to C1'+C2'+C3'+…, where C1', C2', C3'… respectively represent the parasitic capacitance of each negative input transistor.

[0058] In the speed-up driving mode, all switches coupled between the gate terminal of the positive input transistor and the gate terminal of the negative input transistor are turned on, and all switches coupled between the gate terminal of the positive input transistor and the input terminal of the source amplifier 40 are turned off. Therefore, the overall capacitance seen by the positive input terminal only includes C1, and the overall capacitance seen by the negative input terminal is increased to C1'+C2'+C3'+…+C2+C3+…. Since the negative input terminal is commonly coupled to the output terminal of the source amplifier 40, the strong driving capability of the source amplifier 40 itself can be used to charge and discharge the parasitic capacitance of these differential input pairs. In this way, the parasitic capacitance at the output terminal of the resistor ladder digital-to-analog converter (which is only coupled to one or a few positive input terminals of the source amplifier 40) can be greatly reduced. As Figure 5 As shown, in the speed-up driving mode, when the capacitive load of the output terminal of the resistor ladder DAC (or the input terminal of the source amplifier 40) is reduced, the rise time and fall time of the input data voltage are also shortened, indicating that the resistor-capacitor delay is reduced.

[0059] It should be noted that the present invention is not limited to setting which set of differential input pairs is coupled to the input terminal in the boost drive mode. In one embodiment, each switch in the input stage circuit can be flexibly and independently controlled, so that any number of positive input transistors can be coupled to the input terminal. In one embodiment, in each differential input pair (together with the first set of differential input pairs), a switch can be set between the gate terminal of the positive input transistor and the gate terminal of the negative input transistor, and a switch can be set between the gate terminal of the positive input transistor and the input terminal, so that different differential input pairs can be coupled to the input terminal at different times. For example, during each display line period, one set of differential input pairs can be selected to be coupled to the input terminal while the other differential input pairs are coupled in the boost drive mode to reduce the capacitive load of the input terminal. After each N display line period (i.e., N consecutive display lines are displayed or N sets of consecutive data voltages are output from the source amplifier) ​​or after each N consecutive image frames are displayed, another set of differential input pairs can be selected to be coupled to the input terminal. The purpose of this implementation is to reduce or eliminate the offset caused by the process mismatch between the differential input pairs. Furthermore, different differential input pairs can also be set to be alternately coupled to the input terminal during a display line period.

[0060] The capacitance reduction scheme achieved by switching the differential input pair coupling method can also be applied to input stage circuits with different circuit structures. Figure 6 , Figure 6 FIG. 6 is a schematic diagram of an input stage circuit 600 of a source amplifier according to an embodiment of the present invention. Figure 6 As shown, the input stage circuit 600 includes a plurality of groups (x groups) of differential input pairs, wherein some (k groups) of differential input pairs are provided with switches while other (xk groups) of differential input pairs are not provided with switches (where k is less than x). Therefore, during the display line period when the input data voltage changes, the (xk) group of differential input pairs can be set to operate in the boost driving mode, that is, the gate terminal of the positive input transistor of the (xk) group of differential input pairs is coupled to the gate terminal of the corresponding negative input transistor. When the input data voltage is stable, the (xk) group of differential input pairs can be set to operate in the normal driving mode, that is, the gate terminal of the positive input transistor of the (xk) group of differential input pairs is coupled to the corresponding input terminal.

[0061] Since the negative input transistor is also coupled to the output of the source amplifier, the parasitic capacitance of these differential input pairs can be charged and discharged by the driving capability of the source amplifier itself. In this way, during the display line period, the number of positive input transistors coupled to the output of the resistance ladder digital-to-analog converter can be reduced, so that the parasitic capacitance of the output of the resistance ladder digital-to-analog converter is greatly reduced, thereby increasing the charging and discharging speed of the parasitic capacitance of the output of the resistance ladder digital-to-analog converter and reducing the resistance and capacitance delay.

[0062] Please refer to Figure 7 , Figure 7 FIG. 7 is a schematic diagram of an input stage circuit 700 of a source amplifier according to an embodiment of the present invention. Figure 7 The figure shows a differential input pair including a plurality of input transistor pairs respectively coupled to the same positive input terminal (all used to receive the input data voltage Vin1+), and the negative gate terminal thereof is coupled to the output terminal of the source amplifier. Among these differential input pairs, n input transistor pairs (M=n) are provided with switches and k input transistor pairs (M=k) are not provided with switches. Therefore, during the display line period when the input data voltage changes, the n input transistor pairs can be set to operate in the boost driving mode, wherein the gate terminal of the positive input transistor is coupled to the gate terminal of the corresponding negative input transistor. When the input data voltage is stable, the n input transistor pairs can be set to operate in the normal driving mode, wherein the gate terminal of the positive input transistor is coupled to the corresponding input terminal. In this example, the current value supplied to the differential input pair is distributed to each input transistor pair (i.e., kI and nI) in the same ratio as the number of input transistor pairs.

[0063] Since the negative input transistor is also coupled to the output of the source amplifier, the parasitic capacitance of these input transistor pairs can be charged and discharged by the driving capability of the source amplifier itself. In this way, during the display line period, only some input transistor pairs are coupled to the output of the resistance ladder digital-to-analog converter, so that the parasitic capacitance of the output of the resistance ladder digital-to-analog converter is greatly reduced, thereby increasing the charging and discharging speed of the parasitic capacitance of the output of the resistance ladder digital-to-analog converter and reducing the resistance and capacitance delay.

[0064] In the above embodiments, each differential input pair or each input transistor pair is used to receive the same bias current value. Those skilled in the art should understand that the bias current or tail current can be set arbitrarily. For example, please refer to Figure 8 , Figure 8 FIG. 8 is a schematic diagram of an input stage circuit 800 of a source amplifier according to an embodiment of the present invention. Figure 8As shown, the circuit structure of the input stage circuit 800 is similar to that of the input stage circuit 300, so signals or components with similar functions are represented by the same symbols. The difference between the input stage circuit 800 and the input stage circuit 300 is that in the input stage circuit 800, each differential input pair DP1-DP3 receives bias currents of different sizes (i.e., kI, nI, and xI). Different current sizes can be achieved by setting different numbers of transistors in the current sources of the differential input pairs DP1-DP3 (i.e., M=k, M=n, and M=x), and different current values ​​can be used as weight parameters for interpolation to improve the output data voltage resolution. In this example, through the control of switches SW2A, SW2B, SW3A, and SW3B, the differential input pairs DP2 and DP3 can be operated in normal drive mode or speed-up drive mode. The detailed operation method can be found in the description of the above paragraphs and will not be repeated here.

[0065] Please refer to Fig. 9 , Fig. 9 FIG. 9 is a schematic diagram of an input stage circuit 900 of a source amplifier according to an embodiment of the present invention. Fig. 9 As shown, the input stage circuit 900 includes a plurality of groups (x groups) of differential input pairs, and each differential input pair has y groups of input transistor pairs (i.e., M=y). Among the x groups of differential input pairs, the k groups of differential input pairs are not provided with switches (where k is less than x), and among the other (xk) groups of differential input pairs, the z groups of input transistor pairs (M=z) are provided with switches while the other (yz) groups of input transistor pairs (M=yz) are not provided with switches (where z is less than y). Therefore, during the display line period where the input data voltage changes, the z groups of input transistor pairs can be set to operate in a boost driving mode, wherein the gate terminal of the positive input transistor is coupled to the gate terminal of the corresponding negative input transistor. When the input data voltage is stable, the z groups of input transistor pairs can be set to operate in a normal driving mode, wherein the gate terminal of the positive input transistor is coupled to the corresponding input terminal.

[0066] Since the negative input transistor is also coupled to the output of the source amplifier, the parasitic capacitance of these differential input pairs can be charged and discharged by the driving capability of the source amplifier itself. In this way, during the display line period, only some input transistor pairs are coupled to the output of the resistance ladder digital-to-analog converter, so that the parasitic capacitance of the output of the resistance ladder digital-to-analog converter is greatly reduced, thereby increasing the charging and discharging speed of the parasitic capacitance of the output of the resistance ladder digital-to-analog converter and reducing the resistance and capacitance delay.

[0067] exist Fig. 9In the embodiment of , each current source receives the same bias voltage VB to generate the same bias current value I on each differential input pair. For the (xk) groups of differential input pairs, since some input transistor pairs are configured with switches and some input transistor pairs are not configured with switches, the bias current value I supplied to the differential input pairs can also be distributed in the same proportion (i.e., (yz) / y*I and z / y*I) to correspond to the number of input transistor pairs.

[0068] It is worth noting that the purpose of the present invention is to provide a capacitance reduction scheme for an operational amplifier. Those skilled in the art can make modifications or changes accordingly, but are not limited to this. For example, in the above embodiment, the operational amplifier can be used as a source amplifier to receive the data voltage from the resistor ladder digital-to-analog converter. However, the differential input pair of the present invention is not limited to the differential input pair in the source amplifier, and the front stage of the operational amplifier is not limited to the gamma voltage generation circuit. In fact, the operational amplifier of the present invention can be widely used in any situation where the parasitic capacitance of the differential input pair needs to be reduced, thereby avoiding the problem of excessive resistance and capacitance delay caused by the parasitic capacitance load of the differential input pair added to the passive components, active components and signal wires, or the slew rate (slew rate) is too slow due to insufficient driving capability of the front stage circuit. As long as one or more groups of differential input pairs or input transistor pairs are switched to couple the positive gate terminal to the corresponding negative gate terminal, and the positive input transistor is isolated from the input terminal to reduce the parasitic capacitance of the front stage output terminal, the relevant implementation methods, operation methods and applications belong to the scope of the present invention.

[0069] It should also be noted that when the gate terminal of the positive input transistor is disconnected from the input terminal, it should be coupled to the gate terminal of the corresponding negative input transistor. More specifically, the purpose of the embodiment of the present invention is to reduce the parasitic capacitance of the input terminal of the operational amplifier and the output terminal of the previous stage circuit, and this purpose can be achieved by disconnecting the gate terminal of the positive input transistor from the input terminal. In this case, the gate terminal may be in a floating state and not connected to any node, resulting in an unpredictable voltage at the gate terminal. If the gate terminal voltage of the positive input transistor is significantly different from the target output data voltage level of the operational amplifier, when the differential input pair returns to the normal driving mode and the gate terminal is reconnected to the input terminal, charge sharing may occur, causing abnormal voltage drops or surges at the input and output terminals of the operational amplifier. Therefore, preferably, in the speed-up driving mode, the gate terminal of the positive input transistor should be coupled to the gate terminal of the corresponding negative input transistor, so that the strong driving capability of the operational amplifier can be used to pull the voltage of the input gate terminal to the target voltage level.

[0070] In addition, it should be noted that the implementation method of controlling the positive gate terminal and the negative gate terminal of the differential input pair to be short-circuited will reduce the charging and discharging capability of the source amplifier. For example, in an embodiment where the input stage circuit has three sets of differential input pairs, each set of differential input pairs receives the same bias current. If one set of differential input pairs is coupled to the input terminal in a normal manner and the other two sets of differential input pairs are set to connect the gate terminals of the positive input transistor and the negative input transistor to each other under the boost drive mode. In this case, the charging and discharging capability of the source amplifier will be reduced to one third of the original.

[0071] In one embodiment, the bias current of the differential input pair can be set or adjusted to solve this problem. Fig. 10A and 10B , which is a schematic diagram of an input stage circuit 100 of a source amplifier according to an embodiment of the present invention. The input stage circuit 100 may include a plurality of differential input pairs, Fig. 10A and 10B Three differential input pairs DP1 to DP3 are shown. The differential input pair DP1 is composed of input transistors MP1 and MN1, and is operated without a switch, wherein the gate terminal of the input transistor MP1 is coupled to the input terminal of the source amplifier and the gate terminal of the input transistor MN1 is coupled to the output terminal of the source amplifier (omitted to simplify the diagram). The differential input pair DP2 is composed of input transistors MP2 and MN2, and the differential input pair DP3 is composed of input transistors MP3 and MN3. The differential input pairs DP2 and DP3 are both operated with a switch, similar to Figure 3 Implementation method of the switch in (omitted to simplify the illustration).

[0072] In addition, the differential input pair DP1 can receive a current supply from a current source, which is implemented by transistors CS11 and CS12 respectively coupled to switches SWB11 and SWB12, and switches SWB11 and SWB12 are controlled by control signals S1 and S2 respectively. Transistors CS11 and CS12 receive bias voltages VB1 and VB2 respectively to provide different current sizes. The differential input pair DP2 can receive a current supply from a current source, which is implemented by transistors CS21 and CS22 respectively coupled to switches SWB21 and SWB22, and switches SWB21 and SWB22 are controlled by control signals S1 and S2 respectively. Transistors CS21 and CS22 receive bias voltages VB1 and VB3 respectively to provide different current sizes. The differential input pair DP3 can receive current supply from a current source, which is implemented by transistors CS31 and CS32 respectively coupled to switches SWB31 and SWB32, which are respectively controlled by control signals S1 and S2. Transistors CS31 and CS32 respectively receive bias voltages VB1 and VB3 to provide different currents.

[0073] Fig. 10A 1 shows a normal driving mode, wherein the gate terminal of the positive input transistor of each differential input pair DP1-DP3 is coupled to the corresponding input terminal. Under the normal driving mode, the switches SWB11, SWB21 and SWB31 controlled by the control signal S1 are turned on, so that the current source supplies the same bias current value I to the differential input pairs DP1-DP3.

[0074] Fig. 10B The boost drive mode is shown, wherein the gate terminal of the positive input transistor in the differential input pair DP2-DP3 is coupled to the gate terminal of the corresponding negative input transistor. Therefore, only the gate terminal of the positive input transistor in the differential input pair DP1 is coupled to the input terminal of the source amplifier to reduce the parasitic capacitance of the input terminal. Under the boost drive mode, the switches SWB12, SWB22 and SWB32 controlled by the control signal S2 are turned on, so that the current source supplies different bias current values ​​to the differential input pairs DP1-DP3. In this example, the bias current value for the differential input pair DP1 is I*(X+N) / X, and the bias current value for the differential input pairs DP2 and DP3 is I / X, where X and N are positive integers.

[0075] Therefore, under the speed-up driving mode, the gate terminals of the two input transistors in the differential input pair DP2-DP3 are connected to each other, so that the bias current or tail current of the differential input pair DP2-DP3 cannot provide the charging and discharging capability required by the source amplifier. This is because the gate terminals of the positive input transistor and the negative input transistor are locked at the same voltage level. In other words, only one set of differential input pairs DP1 can provide the charging and discharging capability of the source amplifier. In this case, the bias current received by the differential input pair DP1 can be increased in the speed-up driving mode to provide sufficient charging and discharging capability. Correspondingly, the bias current received by the differential input pairs DP2 and DP3 can be reduced to a value less than that in the normal driving mode.

[0076] It is worth noting that the method of determining the current value according to the parameters N and X is only an example. In fact, the current value can be set or adjusted in any feasible way. As long as the bias current value received by the differential input pair DP1 in the boost drive mode is greater than the bias current value received in the normal drive mode, a higher charge and discharge capacity level can be maintained in the boost drive operation. Fig. 10A and 10B In an embodiment, different current values ​​can also be achieved by applying different bias voltages to the current sources. In another embodiment, different current values ​​can also be achieved by using different numbers of transistors in each current source or changing the size of the transistors.

[0077] In another embodiment, when the negative gate terminal and the positive gate terminal are coupled to each other, a voltage difference can be applied between the gate terminal of the positive input transistor and the gate terminal of the negative input transistor to solve the problem of decreased charging and discharging capacity caused by the connection between the positive and negative gate terminals.

[0078] Please refer to Fig.11 , Fig.11 FIG. 1 is a schematic diagram of a source driving circuit 110 according to an embodiment of the present invention. Fig.11 As shown, the source driving circuit 110 is similar to Figure 1 The source driving circuit 10 in FIG. 1 is similar to the source driving circuit 10 in FIG. 1 , so signals or components with similar functions are represented by the same symbols. The difference between the source driving circuit 110 and the source driving circuit 10 is that the source driving circuit 110 further includes a capacitance reduction circuit 1102 coupled between the resistor ladder digital-to-analog converter and the source amplifier.

[0079] Fig.12 An example schematic diagram of a capacitance reduction circuit 1102 is shown, wherein a source amplifier is also shown. Fig.12 For convenience of explanation. Fig.12As shown, the source amplifier includes N positive input terminals P_1-P_N, N negative input terminals N_1-N_N, and an output terminal. The positive input terminals P_1-P_N are coupled to the resistor ladder digital-to-analog converter through the capacitance reduction circuit 1102, and the negative input terminals N_1-N_N are coupled to the output terminal of the source amplifier through the capacitance reduction circuit 1102. The capacitance reduction circuit 1102 includes a plurality of switches and clamping devices, wherein the switches are used to control the positive input terminals P_1-P_N of the source amplifier to be coupled to the resistor ladder digital-to-analog converter or to be coupled to the corresponding negative input terminals N_1-N_N in the source amplifier, and the clamping device is used to generate a voltage difference ΔV between the positive input terminals P_1-P_N and their corresponding negative input terminals N_1-N_N.

[0080] It is worth noting that the operation of the switch in the capacitance reduction circuit 1102 is similar to the switch in the input stage circuit of the source amplifier in the above-mentioned embodiment. Fig.12 The switch is included in the capacitance reduction circuit 1102, and the capacitance reduction circuit 1102 is a module independent of the source amplifier. In this case, the source amplifier only includes a plurality of differential input pairs, so Fig.12 The positive input terminals P_1-P_N and the negative input terminals N_1-N_N respectively represent the gate terminals of the positive input transistors and the gate terminals of the negative input transistors in each differential input pair. In another embodiment, the capacitance reduction circuit 1102 may also be integrated into the source amplifier or the input stage circuit. Considering that the capacitance reduction circuit 1102 is integrated into the source amplifier, the node in the capacitance reduction circuit 1102 coupled to the resistor ladder digital-to-analog converter may be regarded as the input terminal of the source amplifier.

[0081] Fig.12 The source amplifier is shown to have N groups of differential input pairs, wherein only one group of differential input pairs is not provided with a switch while the other differential input pairs are provided with switches (i.e., coupled to the switch in the capacitance reduction circuit 1102). In detail, for the first group of differential input pairs, the positive input terminal P_1 is coupled to the resistor ladder digital-to-analog converter to receive the input data voltage Vin1+, and the negative input terminal N_1 is coupled to the output terminal of the source amplifier. For the other differential input pairs, the negative input terminals N_2 to N_N are commonly coupled to the output terminal of the source amplifier, and the positive input terminals P_2 to P_N can be selectively coupled to the resistor ladder digital-to-analog converter (for receiving the input data voltages Vin2+, Vin3+, ... VinN+) or coupled to the corresponding negative input terminals N_2 to N_N.

[0082] More specifically, under the switch setting of the capacitance reduction circuit 1102, each positive input terminal P_2~P_N can be coupled to the resistance ladder digital-to-analog converter through a switch. The negative input terminals N_2~N_N are connected to each other and then commonly coupled to the output terminal of the source amplifier through a switch. In addition, the positive input terminals P_2~P_(N-1) can be respectively coupled to the positive input terminal P_N through a switch, and the positive input terminal P_N is also coupled to the output terminal of the source amplifier through a switch, and is coupled to the common node of the negative input terminals N_2~N_N through two paths, and each of the two paths includes a switch and a clamping device CD1 or CD2. In one path, the clamp device CD1 can form a voltage difference ΔV so that the voltage of the positive input terminal P_2~P_N is greater than the voltage of the negative input terminal N_2~N_N; in another path, the clamp device CD2 can form a voltage difference ΔV so that the voltage of the negative input terminal N_2~N_N is greater than the voltage of the positive input terminal P_2~P_N. Fig.12 shown.

[0083] Therefore, during the display line period, the capacitance reduction circuit 1102 can be set to operate in the speed-up driving mode, that is, the switch coupled between the positive input terminal P_2~P_N and the negative input terminal N_2~N_N is turned on, and the switch coupled between the positive input terminal P_2~P_N and the resistance ladder digital-to-analog converter is turned off. In this case, only the positive input terminal P_1 contributes parasitic capacitance to the output terminal of the resistance ladder digital-to-analog converter, so that the resistance ladder digital-to-analog converter has a lower capacitive load. During other periods, the capacitance reduction circuit 1102 operates in the normal driving mode, that is, the switch coupled between the positive input terminal P_2~P_N and the resistance ladder digital-to-analog converter is turned on, and the switch coupled between the positive input terminal P_2~P_N and the negative input terminal N_2~N_N is turned off.

[0084] Fig.13A and 13B The detailed operation of the capacitance reduction circuit 1102 during the display line period is shown. Fig.13A shows the rise time of the input data voltage during the display line period; Fig. 13B The falling time of the input data voltage in the display line period is shown. The capacitance reduction circuit 1102 can receive a control signal, which can control the corresponding switch to be turned on or off during each rising time and falling time.

[0085] like Fig.13AAs shown, at the rising time of the input data voltage, the switch coupled to the clamp device CD1 and the switch coupled between the positive input terminals P_2-P_N and the output terminal are turned on. In this case, through the turned-on switch, a current can flow from the output terminal of the source amplifier through the positive input terminals P_2-P_N to the negative input terminals N_2-N_N. In the case where a positive voltage difference is intentionally applied between the positive input terminals P_2-P_N and the negative input terminals N_2-N_N (i.e., the voltage of the positive input terminals P_2-P_N is greater than the voltage of the negative input terminals N_2-N_N), the source amplifier can have a higher driving capability to charge the output terminal at the rising time.

[0086] like Fig. 13B As shown, at the falling time of the input data voltage, the switch coupled to the clamp device CD2 and the switch coupled between the negative input terminals N_2 to N_N and the output terminal are turned on. In this case, through the turned-on switch, a current can flow from the output terminal of the source amplifier through the negative input terminal N_2 to N_N to the positive input terminal P_2 to P_N. In the case of intentionally applying a negative voltage difference between the positive input terminal P_2 to P_N and the negative input terminal N_2 to N_N (i.e., the voltage of the positive input terminal P_2 to P_N is less than the voltage of the negative input terminal N_2 to N_N), the source amplifier can have a higher driving capability to discharge the output terminal at the falling time.

[0087] Therefore, during the rise time or fall time of the input data voltage, even if part of the differential input pair is not used to receive the input data voltage, the transconductance and slew rate of the source amplifier can still be maintained at a good level. In this way, the parasitic capacitance at the output of the resistor ladder digital-to-analog converter can be reduced, while maintaining the charging and discharging capabilities of the source amplifier, which can greatly reduce the problem of resistor and capacitor delay and improve the overall output slew rate (rise / fall time) of the system.

[0088] Fig.14An actual circuit diagram of the capacitance reduction circuit 1102 is shown. The capacitance reduction circuit 1102 can be used for a source amplifier having three positive input terminals P_1-P_3 and three negative input terminals N_1-N_3 (i.e., three differential input pairs). It should be noted that each switch can be implemented by a transmission gate composed of an N-type Metal Oxide Semiconductor Transistor (NMOS Transistor) and a P-type Metal Oxide Semiconductor Transistor (PMOS Transistor), and each clamping device CD1 and CD2 can be implemented by a diode or a diode-connected transistor, which can form a voltage difference of approximately 0.7V. Fig.15 for Fig.14 The waveform diagram of the control signal of the capacitance reduction circuit 1102 is shown in FIG. Fig.15 As shown, during the rising time and the falling time, the control signals RF_CK and RF_CK' can be used to start the rising speed driving mode, the control signals R_N and R_P turn on the corresponding switches during the rising time, and the control signals F_N and F_P turn on the corresponding switches during the falling time.

[0089] In summary, an embodiment of the present invention provides a capacitance reduction scheme for an operational amplifier, and this capacitance reduction scheme can be implemented in the input stage circuit of the operational amplifier, or in a capacitance reduction circuit coupled to the input terminal of the operational amplifier. In one embodiment, the operational amplifier can be used as an output buffer, such as a source amplifier in a source driver. Through the capacitance reduction scheme, a switch can be coupled between the gate terminal of the positive input transistor of the differential input pair and its corresponding input terminal, and another switch can be coupled between the gate terminal of the positive input transistor and its corresponding gate terminal of the negative input transistor. Therefore, the gate terminal of the positive input transistor can be selected to be coupled to the input terminal to receive an input data voltage (i.e., normal drive mode), or coupled to the gate terminal of the negative input transistor to reduce the parasitic capacitance of the positive input terminal (i.e., speed-up drive mode). In one embodiment, the speed-up drive mode can be performed during the display line period when the input data voltage of the operational amplifier changes. As a result, during a display line period, only one or a few differential input pairs are coupled to the output terminal of the previous stage, which can significantly reduce parasitic capacitance, thereby reducing resistance and capacitance delay and improving signal transmission efficiency.

[0090] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. An operational amplifier, used as an output buffer of a source driving device of a panel, the operational amplifier comprising: A plurality of differential input pairs are used to receive at least one input data voltage to generate an output data voltage to be output to the panel, wherein a first differential input pair among the plurality of differential input pairs comprises: a first input transistor having a gate terminal coupled to an output terminal of the operational amplifier; and a second input transistor having a gate terminal; a first switch coupled between the gate terminal of the first input transistor and the gate terminal of the second input transistor, for controlling the gate terminal of the first input transistor to be connected to or disconnected from the gate terminal of the second input transistor; and a second switch coupled between a first input terminal of the operational amplifier and the gate terminal of the second input transistor; Wherein, a second differential input pair among the plurality of differential input pairs comprises: a fifth input transistor having a gate terminal coupled to the output terminal of the operational amplifier; and A sixth input transistor has a gate terminal, which is coupled to the first input terminal or a second input terminal of the operational amplifier without passing through any switch.

2. The operational amplifier according to claim 1, wherein: In a first driving mode, the first switch is turned off and the second switch is turned on, and in a second driving mode, the first switch is turned on and the second switch is turned off.

3. The operational amplifier according to claim 2, wherein: In the first driving mode, the gate terminal of the second input transistor is coupled to the first input terminal of the operational amplifier, and in the second driving mode, the gate terminal of the second input transistor is coupled to the gate terminal of the first input transistor.

4. The operational amplifier according to claim 2, wherein: The first switch and the second switch operate in the second driving mode within at least one of a rising time and a falling time within a display line period.

5. The operational amplifier according to claim 1, wherein: The first differential input pair further includes: a third input transistor having a gate terminal coupled to the output terminal of the operational amplifier; and A fourth input transistor has a gate terminal coupled to the first input terminal of the operational amplifier.

6. The operational amplifier according to claim 1, wherein: The plurality of differential input pairs further include a third differential input pair, the third differential input pair including: a seventh input transistor having a gate terminal coupled to the output terminal of the operational amplifier; and an eighth input transistor having a gate terminal; The operational amplifier further includes: a third switch coupled between the gate terminal of the seventh input transistor and the gate terminal of the eighth input transistor; and A fourth switch is coupled between a third input terminal of the operational amplifier and the gate terminal of the eighth input transistor.

7. The operational amplifier according to claim 1, wherein: When the gate terminal of the second input transistor is coupled to the first input terminal of the operational amplifier, the first differential input pair is used to receive a first bias current, and when the gate terminal of the second input transistor is coupled to the gate terminal of the first input transistor, the first differential input pair is used to receive a second bias current; The value of the first bias current is greater than the value of the second bias current.

8. The operational amplifier according to claim 7, wherein: The plurality of differential input pairs further include a fourth differential input pair, the fourth differential input pair being coupled to a fourth input terminal of the operational amplifier, wherein when the gate terminal of the second input transistor is coupled to the first input terminal of the operational amplifier, the fourth differential input pair is used to receive a third bias current, and when the gate terminal of the second input transistor is coupled to the gate terminal of the first input transistor, the fourth differential input pair is used to receive a fourth bias current; The value of the fourth bias current is greater than the value of the third bias current.

9. The operational amplifier according to claim 1, wherein: The gate terminal of the second input transistor is coupled to the gate terminal of the first input transistor, and there is a voltage difference between the gate terminal of the second input transistor and the gate terminal of the first input transistor.

10. The operational amplifier according to claim 9, wherein: The gate terminal of the second input transistor is coupled to the gate terminal of the first input transistor through a clamping device.

11. The operational amplifier according to claim 10, wherein: The clamping device comprises a diode or a transistor in the form of a diode.

12. The operational amplifier according to claim 10, wherein: The clamping device is used to form the voltage difference between the gate terminal of the second input transistor and the gate terminal of the first input transistor.

13. The operational amplifier according to claim 1, wherein: The first differential input pair is coupled to a resistor ladder digital-to-analog converter in a gamma voltage generating circuit for the source driving device.

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