Phase synchronization circuit, transceiver circuit and integrated circuit

Abstract

The phase synchronization circuit of the present invention comprises: a first delay circuit (311) for delaying a first reference clock signal by a first delay amount and outputting a first delayed reference clock signal, wherein the first delay amount is adjustable; a first clock control circuit (312-314, 316) for comparing the phases of the first delayed reference clock signal and the first output clock signal and generating a first clock control signal based on the comparison result; a first clock signal generating circuit (315) for generating the first output clock signal based on the first clock control signal; and a first monitoring circuit (317, 318) for monitoring the jitter of the first output clock signal and adjusting the first delay amount based on the monitoring result of the jitter of the first output clock signal.

Description

Technical Field

[0001] The invention relates to a phase synchronization circuit, a transceiver circuit and an integrated circuit. Background Art

[0002] A clock generation circuit of a phase-locked loop is known that generates a feedback clock by dividing the output clock of a voltage-controlled oscillator into a predetermined value by a frequency divider (see Patent Document 1). A phase comparator detects the phase difference between the feedback clock and the input reference clock, generates a phase error signal for eliminating the phase difference, and controls the output clock of the voltage-controlled oscillator. When the frequency variation of the input reference clock exceeds a predetermined range, an adjustment circuit adjusts the frequency variation to within a predetermined range.

[0003] In addition, there is known a phase-locked loop circuit including a phase comparator for generating a signal representing a phase difference between a signal given to a first input of the phase comparator and a signal given to a second input of the phase comparator (see patent document 2). A first delay element delays a signal supplied to the first input of the phase comparator. A second delay element delays a signal supplied to the second input of the phase comparator. The delay given by at least one of the first delay element and the second delay element varies according to a related delay control value. A microcontroller is combined with the first delay element and the second delay element to generate a related delay control value. The phase-locked loop circuit, the first delay element, the second delay element, and the microcontroller are present on the same semiconductor substrate.

[0004] In addition, a phase-locked loop having a phase interpolation control unit that generates a phase interpolation control signal based on an input clock is known (see patent document 3). The phase / frequency detector detects the phase difference between the second reference clock and the feedback clock, and outputs a phase error signal representing the phase difference. The loop filter filters the phase error signal to generate a first control signal. The phase interpolation oscillator generates a phase-interpolated output clock based on the first reference clock controlled by the phase interpolation control signal and the oscillation condition controlled by the first control signal. The N-division circuit (N is an integer) divides the output clock by N to generate a feedback clock. The variable delay module is combined with the phase / frequency detector to delay the input clock by an amount controlled by the second control signal to generate a second reference clock.

[0005] Patent Document 1: Japanese Patent Application Publication No. 2004-153332

[0006] Patent Document 2: U.S. Patent No. 9859901

[0007] Patent Document 3: U.S. Patent No. 8253454

[0008] The phase-locked loop circuit generates an output clock signal. However, jitter may occur in the output clock signal. Jitter is a high-frequency change (fluctuation) in the time axis direction of the output clock signal. Summary of the invention

[0009] In one aspect, an object of the present invention is to provide a phase synchronization circuit, a transceiver circuit, and an integrated circuit capable of reducing jitter of an output clock signal.

[0010] The phase synchronization circuit comprises: a first delay circuit, which delays a first reference clock signal by a first delay amount and outputs a first delayed reference clock signal, wherein the first delay amount is adjustable; a first clock control circuit, which compares the phases of the first delayed reference clock signal and the first output clock signal and generates a first clock control signal based on the comparison result; a first clock signal generating circuit, which generates the first output clock signal based on the first clock control signal; and a first monitoring circuit, which monitors the jitter of the first output clock signal and adjusts the first delay amount based on the monitoring result of the jitter of the first output clock signal.

[0011] In one aspect, jitter of the first output clock signal can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a diagram showing a configuration example of an integrated circuit according to the first embodiment.

[0013] Figure 2 This is a diagram showing power supply potential nodes and ground potential nodes commonly connected to a plurality of phase-locked loop circuits.

[0014] Figure 3 It is a diagram showing a configuration example of a phase-locked loop circuit.

[0015] Figure 4 is a flow chart showing a control method of an integrated circuit.

[0016] Figure 5 It is a diagram showing a configuration example of a phase-locked loop circuit according to the second embodiment.

[0017] Figure 6 It is a diagram showing a configuration example of a phase-locked loop circuit according to a third embodiment.

[0018] Figure 7 is a flow chart showing a control method of an integrated circuit.

[0019] Figure 8 It is a diagram showing a configuration example of a transmission and reception circuit according to a fourth embodiment.

[0020] Fig. 9 FIG. 1 is a diagram showing an eye pattern before the delay amount of the delay circuit is adjusted.

[0021] Fig.10 FIG. 4 is a diagram showing an eye pattern after the delay amount of the delay circuit is adjusted. DETAILED DESCRIPTION

[0022] (First Embodiment)

[0023] Figure 1 1 is a diagram showing a configuration example of an integrated circuit 100 according to the first embodiment. The integrated circuit 100 includes a central processing unit (CPU) 101 and multi-channel transceiver circuits 111 to 114 .

[0024] The transceiver circuit 111 includes a transmission circuit (TX) 121, a phase-locked loop (PLL) circuit 131, and a receiving circuit (RX) 141. The phase-locked loop circuit 131 is a phase synchronization circuit that generates an output clock signal. The transmission circuit 121 transmits transmission data based on the output clock signal generated by the phase-locked loop circuit 131. The receiving circuit 141 receives reception data based on the output clock signal generated by the phase-locked loop circuit 131. The central processing unit 101 is an internal circuit that outputs transmission data to the transmission circuit 121 and inputs reception data from the reception circuit 141. The transmission circuit 121 converts the transmission data input from the central processing unit 101 from parallel to serial in synchronization with the output clock signal generated by the phase-locked loop circuit 131, and transmits the serial transmission data to other integrated circuits. The receiving circuit 141 includes a clock data recovery (CDR) circuit that reproduces the clock signal and reception data based on the serial reception signal received from other integrated circuits in synchronization with the output clock signal generated by the phase-locked loop circuit 131. Furthermore, the receiving circuit 141 converts the received data from serial to parallel and outputs the parallel received data to the central processing unit 101 .

[0025] The transceiver circuit 112 includes a transmission circuit 122, a phase-locked loop circuit 132, and a receiving circuit 142. The phase-locked loop circuit 132 is a phase synchronization circuit and generates an output clock signal. The transmission circuit 122 transmits transmission data based on the output clock signal generated by the phase-locked loop circuit 132. The receiving circuit 142 receives reception data based on the output clock signal generated by the phase-locked loop circuit 132. The central processing unit 101 outputs transmission data to the transmission circuit 122 and inputs reception data from the reception circuit 142. The transmission circuit 122 performs the same processing as the transmission circuit 121. The reception circuit 142 performs the same processing as the reception circuit 141.

[0026] The transceiver circuit 113 includes a transmission circuit 123, a phase-locked loop circuit 133, and a receiving circuit 143. The phase-locked loop circuit 133 is a phase synchronization circuit and generates an output clock signal. The transmission circuit 123 transmits transmission data based on the output clock signal generated by the phase-locked loop circuit 133. The receiving circuit 143 receives reception data based on the output clock signal generated by the phase-locked loop circuit 133. The central processing unit 101 outputs transmission data to the transmission circuit 123 and inputs reception data from the reception circuit 143. The transmission circuit 123 performs the same processing as the transmission circuit 121. The reception circuit 143 performs the same processing as the reception circuit 141.

[0027] The transceiver circuit 114 includes a transmission circuit 124, a phase-locked loop circuit 134, and a receiving circuit 144. The phase-locked loop circuit 134 is a phase synchronization circuit and generates an output clock signal. The transmission circuit 124 transmits transmission data based on the output clock signal generated by the phase-locked loop circuit 134. The receiving circuit 144 receives reception data based on the output clock signal generated by the phase-locked loop circuit 134. The central processing unit 101 outputs transmission data to the transmission circuit 124 and inputs reception data from the reception circuit 144. The transmission circuit 124 performs the same processing as the transmission circuit 121. The reception circuit 144 performs the same processing as the reception circuit 141.

[0028] The transmission and reception circuits 111 to 114 each include a phase-locked loop circuit 131 to 134, so that the transmission and reception speeds can be made different. However, since the plurality of phase-locked loop circuits 131 to 134 are arranged close to each other, interference from power supply noise is likely to occur.

[0029] Furthermore, five or more transceiver circuits 111 to 114 may be provided. Furthermore, a central processing unit 101 may be provided for each of the transceiver circuits 111 to 114 .

[0030] Figure 2 1 is a diagram showing a power supply potential node VDD and a ground potential node GND commonly connected to a plurality of phase-locked loop circuits 131 to 134. There are three power supply connection methods.

[0031] In the first power supply connection method, the plurality of phase-locked loop circuits 131 to 134 are connected to a common power supply potential node VDD and a common ground potential node GND in the integrated circuit 100 .

[0032] In the second power connection method, the power supply potential nodes and ground potential nodes of the plurality of PLL circuits 131 to 134 are separated in the integrated circuit 100. In this case, the plurality of PLL circuits 131 to 134 are connected to a common power supply potential node VDD and ground potential node GND through package power connections.

[0033] In the third power connection method, the power supply potential nodes and ground potential nodes of the plurality of PLL circuits 131 to 134 are separated in the integrated circuit 100 and the package. In this case, the plurality of PLL circuits 131 to 134 are connected to the common power supply potential node VDD and ground potential node GND through the board power connection.

[0034] When a plurality of transceiver circuits 111 to 114 are provided in the integrated circuit 100, it is difficult to separate the terminals (ball members) of the package for each of the transceiver circuits 111 to 114. In this case, the second power supply connection method is often used.

[0035] If the plurality of PLL circuits 131 to 134 operate simultaneously, power supply noises interfere with each other between the plurality of PLL circuits 131 to 134 via the power supply potential node VDD and the ground potential node GND.

[0036] Figure 3 1 is a diagram showing a configuration example of the phase-locked loop circuits 131 and 132 according to the present embodiment.

[0037] The phase-locked loop circuit 131 has a delay circuit 311, a phase frequency detector (PFD) 312, a supply pump (CP) 313, a low-pass filter (LPF) 314, a voltage-controlled oscillator (VCO) 315, a frequency divider (DIV) 316, an analog-to-digital converter (ADC) 317 and a delay control circuit 318 to generate an output clock signal CK1.

[0038] The delay circuit 311 delays the reference clock signal RCK by a delay amount, and outputs a delayed reference clock signal RCKa, wherein the delay amount can be adjusted. The reference clock signal RCK is, for example, 100 MHz. The frequency divider 316 divides the output clock signal CK1 generated by the voltage-controlled oscillator 315, and outputs the divided clock signal CK1a to the phase frequency detector 312. The phase frequency detector 312 compares the phase and frequency of the delayed reference clock signal RCKa and the clock signal CK1a, and outputs an up signal UP or a down signal DN to the supply pump 313 based on the result of the comparison. The supply pump 313 increases the voltage of the control signal V1 if the up signal UP is input, and decreases the voltage of the control signal V1 if the down signal DN is input. The low-pass filter 314 performs low-pass filtering on the control signal V1, and outputs the low-pass filtered clock control signal V1a to the voltage-controlled oscillator 315. The phase frequency detector 312, the charge pump 313, the low-pass filter 314, and the frequency divider 316 are an example of a clock control circuit that generates the clock control signal V1a. The voltage controlled oscillator 315 is a clock signal generating circuit that generates an output clock signal CK1 with a frequency based on the voltage of the clock control signal V1a. The output clock signal CK1 is, for example, several GHz. In addition, the analog-to-digital converter 317 and the delay control circuit 318 will be described later.

[0039] The phase-locked loop circuit 132 includes a delay circuit 321 , a phase frequency detector 322 , a charge pump 323 , a low-pass filter 324 , a voltage-controlled oscillator 325 , and a frequency divider 326 , and generates an output clock signal CK2 .

[0040] The delay circuit 321 delays the reference clock signal RCK by a predetermined delay amount and outputs a delayed reference clock signal RCKb. In addition, the delay circuit 321 can also be deleted. The frequency divider 326 divides the output clock signal CK2 generated by the voltage controlled oscillator 325, and outputs the divided clock signal CK2b to the phase frequency detector 322. The phase frequency detector 322 compares the phase and frequency of the delayed reference clock signal RCKb and the clock signal CK2b, and outputs an up signal UP or a down signal DN to the supply pump 323 based on the result of the comparison. If the up signal UP is input to the supply pump 323, the voltage of the control signal V2 is increased, and if the down signal DN is input, the voltage of the control signal V2 is decreased. The low-pass filter 324 performs low-pass filtering on the control signal V2, and outputs the low-pass filtered clock control signal V2b to the voltage controlled oscillator 325. The phase frequency detector 322, the supply pump 323, the low-pass filter 324 and the frequency divider 326 are an example of a clock control circuit that generates the clock control signal V2b. The voltage controlled oscillator 325 is a clock signal generating circuit, and generates an output clock signal CK2 having a frequency based on the voltage of the clock control signal V2b. The phase-locked loop circuit 132 may generate the output clock signal CK2 by a configuration different from that of the phase-locked loop circuit 131.

[0041] If the phase-locked loop circuits 131 and 132 operate simultaneously, power supply noise interferes with each other through the power supply potential node VDD and the ground potential node GND between the phase-locked loop circuits 131 and 132. As a result, jitter is generated in the output clock signal CK1 and the output clock signal CK2. Jitter is a high-frequency change (fluctuation) generated in the time axis direction of the output clock signals CK1 and CK2.

[0042] The magnitude of the jitter of the output clock signal CK1 depends on the power supply noise and the phase of the output clock signal CK1. Therefore, by changing the phase of the output clock signal CK1 to an appropriate phase, the jitter of the output clock signal CK1 can be reduced. The phase-locked loop circuit 131 changes the phase of the delayed reference clock signal RCKa through the delay circuit 311 to change the phase of the output clock signal CK1, as a result, the jitter of the output clock signal CK1 can be reduced. The delay control circuit 318 adjusts the delay amount of the delay circuit 311 to minimize the jitter of the output clock signal CK1.

[0043] The magnitude of the jitter of the output clock signal CK1 depends on the magnitude of the variation of the clock control signal V1a. That is, the greater the variation of the clock control signal V1a, the greater the jitter of the output clock signal CK1. Therefore, the analog-to-digital converter 317 converts the clock control signal V1a from analog to digital, and outputs the digital control signal D1 to the delay control circuit 318. The delay control circuit 318 adjusts the delay amount of the delay circuit 311 through the delay control signal CTL1 to minimize the variation of the control signal D1. Thus, the delay control circuit 318 can adjust the delay amount of the delay circuit 311 through the delay control signal CTL1 to minimize the jitter of the output clock signal CK1.

[0044] Specifically, the delay control circuit 318 changes the delay amount of the delay circuit 311 from the minimum value to the maximum value, detects the maximum value and the minimum value of the control signal D1 for each delay amount, and detects the difference between the maximum value and the minimum value of the control signal D1 as the variation amount. Furthermore, the delay control circuit 318 searches for the delay amount at which the variation amount of the control signal D1 becomes the minimum from the minimum value to the maximum value of the delay amount of the delay circuit 311, and fixes the delay amount of the delay circuit 311. Thus, the jitter of the output clock signal CK1 can be minimized.

[0045] By changing the delay amount of the delay circuit 311, the phase of the delay reference clock signal RCKa changes, and the phase of the power supply noise caused by the phase-locked loop circuit 131 changes. As a result, the jitter of the output clock signal CK2 generated by the phase-locked loop circuit 132 is also reduced.

[0046] As described above, the analog-to-digital converter 317 and the delay control circuit 318 are examples of a monitoring circuit, and monitor the jitter of the output clock signal CK1 and adjust the delay amount of the delay circuit 311 based on the monitoring result of the jitter of the output clock signal CK1.

[0047] Figure 4 4 is a flowchart showing a control method of the integrated circuit 100. In step S401, the central processing unit 101 activates the phase-locked loop circuit 131 and the phase-locked loop circuit 132. In step S402, the central processing unit 101 activates the analog-to-digital converter 317 of the phase-locked loop circuit 131.

[0048] In step S403, the delay control circuit 318 substitutes 0 (minimum value) into the delay amount del of the delay circuit 311. The delay amount del may also be a delay code. In step S404, the delay control circuit 318 substitutes 0 into the variable i.

[0049] In step S405, the delay control circuit 318 determines whether the delay amount del is less than the maximum delay amount n. The delay control circuit 318 proceeds to step S406 if the delay amount del is less than the maximum delay amount n, and proceeds to step S419 if the delay amount del is not less than the maximum delay amount n.

[0050] In step S406 , the delay control circuit 318 substitutes the value of the control signal D1 output by the analog-to-digital converter 317 into the maximum value max and the minimum value min.

[0051] In step S407, the delay control circuit 318 determines whether the variable i is less than the detection number m. The detection number m is the number of times the delay control circuit 318 detects the control signal D1. The delay control circuit 318 proceeds to step S408 when the variable i is less than the detection number m, and proceeds to step S414 when the variable i is not less than the detection number m.

[0052] In step S408, the delay control circuit 318 substitutes the value of the control signal D1 output by the analog-to-digital converter 317 into the variable out. In step S409, the delay control circuit 318 determines whether the variable out is greater than the maximum value max. The delay control circuit 318 proceeds to step S412 if the variable out is greater than the maximum value max, and proceeds to step S410 if the variable out is not greater than the maximum value max.

[0053] In step S412 , the delay control circuit 318 substitutes the maximum value max into the variable out, and proceeds to step S413 .

[0054] In step S410, the delay control circuit 318 determines whether the variable out is less than the minimum value min. If the variable out is less than the minimum value min, the delay control circuit 318 proceeds to step S411, and if the variable out is not less than the minimum value min, the delay control circuit 318 proceeds to step S413.

[0055] In step S411 , the delay control circuit 318 substitutes the minimum value min into the variable out, and proceeds to step S413 .

[0056] In step S413, the delay control circuit 318 increments the variable i by 1, and returns to step S407. By repeatedly executing the above-mentioned process m times, the maximum value max and the minimum value min of the control signal D1 can be detected.

[0057] In step S414 , the delay control circuit 318 substitutes a value obtained by subtracting the minimum value min from the maximum value max into the variation amp.

[0058] In step S415 , the delay control circuit 318 determines whether the delay amount del is 0. When the delay amount del is 0, the delay control circuit 318 proceeds to step S417 , and when the delay amount del is not 0, the delay control circuit 318 proceeds to step S416 .

[0059] In step S417 , the delay control circuit 318 substitutes the variation amount amp into the minimum variation amount amp_min, substitutes the delay amount del into the minimum variation delay amount del_min, and proceeds to step S418 .

[0060] In step S416, the delay control circuit 318 determines whether the variation amp is less than the minimum variation amp_min. If the variation amp is less than the minimum variation amp_min, the delay control circuit 318 proceeds to step S417, and if the variation amp is not less than the minimum variation amp_min, the delay control circuit 318 proceeds to step S418.

[0061] In step S418, the delay control circuit 318 increments the delay del by 1, and returns to step S404. The above process is repeated from the minimum value 0 to the maximum value n of the delay del. The minimum change amp in the change amp when the delay del changes from the minimum value 0 to the maximum value n is substituted into the minimum change amp_min. The delay del when the change amp_min is the minimum in the delay del from the minimum value 0 to the maximum value n is substituted into the minimum change delay del_min.

[0062] In step S419, the delay control circuit 318 substitutes the minimum variable delay amount del_min into the delay amount del. In step S420, the delay control circuit 318 fixes the delay amount del of the delay circuit 311, and completes the adjustment of the delay amount del. After that, the integrated circuit 100 performs normal operation.

[0063] (Second Embodiment)

[0064] Figure 5 1 is a diagram showing a configuration example of phase-locked loop circuits 131 and 132 according to the second embodiment. The following describes differences between this embodiment and the first embodiment. Figure 5 The phase-locked loop circuit 131 has Figure 3 The phase-locked loop circuit 131 has the same structure. Figure 5 The phase-locked loop circuit 132 is relative to Figure 3 The phase-locked loop circuit 132 is supplemented with an analog-to-digital converter 327.

[0065] The analog-to-digital converter 327 converts the clock control signal V2b output by the low-pass filter 324 from analog to digital, and outputs the digital control signal D2 to the delay control circuit 318. The delay control circuit 318 changes the delay amount of the delay circuit 311 from the minimum value to the maximum value, and searches for the delay amount of the delay circuit 311 with the minimum sum of the variation of the control signal D1 and the variation of the control signal D2. Then, the delay control circuit 318 adjusts the delay amount of the delay circuit 311 to the delay amount with the minimum sum of the variation of the control signal D1 and the variation of the control signal D2. The specific adjustment method is as follows: Figure 4 Thus, the jitter of the output clock signal CK1 generated by the phase-locked loop circuit 131 and the jitter of the output clock signal CK2 generated by the phase-locked loop circuit 132 can be reduced.

[0066] This embodiment can also be applied to more than three phase-locked loop circuits. An analog-to-digital converter and a variable delay circuit are provided for all phase-locked loop circuits 131 to 134, and a common delay control circuit 318 is provided for all phase-locked loop circuits 131 to 134. The delay control circuit 318 changes the delay amount of the delay circuit of each phase-locked loop circuit 131 to 134, and adjusts the delay amount of the delay circuit of all phase-locked loop circuits 131 to 134 so that the sum of the variation of the control signals D1, D2, etc. of all phase-locked loop circuits 131 to 134 is minimized.

[0067] Furthermore, even if the sum of the variations of the control signals D1, D2, etc. of all the PLL circuits 131 to 134 is the smallest, if the variation of the control signal of any PLL circuit is larger than the threshold, the delay combination may not be used.

[0068] (Third Embodiment)

[0069] Figure 6 1 is a diagram showing an example of the configuration of the phase-locked loop circuits 131 to 134 of the third embodiment. The differences between this embodiment and the first embodiment are described below. The phase-locked loop circuit 131, the phase-locked loop circuit 132, the phase-locked loop circuit 133, and the phase-locked loop circuit 134 are arranged adjacent to each other in this order. The phase-locked loop circuit 132 is arranged between the phase-locked loop circuit 131 and the phase-locked loop circuit 133. The phase-locked loop circuit 133 is arranged between the phase-locked loop circuit 132 and the phase-locked loop circuit 134.

[0070] Figure 6 The phase-locked loop circuit 131 is relative to Figure 3The analog-to-digital converter 317 and the delay control circuit 318 are deleted from the phase-locked loop circuit 131. The delay circuit 311 delays the reference clock signal RCK by a predetermined delay amount and outputs the delayed reference clock signal RCKa to the phase frequency detector 312. In addition, the delay circuit 311 may also be deleted.

[0071] Figure 6 The phase-locked loop circuit 132 is relative to Figure 3 The phase-locked loop circuit 132 is supplemented with an analog-to-digital converter 327 and a delay control circuit 328. The delay circuit 321 delays the reference clock signal RCK by a delay amount, and outputs the delayed reference clock signal RCKb to the phase frequency detector 322, wherein the delay amount can be adjusted. The analog-to-digital converter 327 converts the clock control signal V2b from analog to digital, and outputs the digital control signal D2 to the delay control circuit 328. The delay control circuit 328 adjusts the delay amount of the delay circuit 321 through the delay control signal CTL2 to minimize the variation of the control signal D2. Thus, the delay control circuit 328 can adjust the delay amount of the delay circuit 321 through the delay control signal CTL2 to minimize the jitter of the output clock signal CK2. The analog-to-digital converter 327 and the delay control circuit 328 are an example of a monitoring circuit, which monitors the jitter of the output clock signal CK2 and adjusts the delay amount of the delay circuit 321 based on the monitoring result of the jitter of the output clock signal CK2.

[0072] The phase-locked loop circuit 133 includes a delay circuit 331 , a phase frequency detector 332 , a charge pump 333 , a low-pass filter 334 , a voltage-controlled oscillator 335 , a frequency divider 336 , an analog-to-digital converter 337 , and a delay control circuit 338 , and generates an output clock signal CK3 .

[0073] The delay circuit 331 delays the reference clock signal RCK by a delay amount, and outputs a delayed reference clock signal RCKc, wherein the delay amount can be adjusted. The frequency divider 336 divides the output clock signal CK3 generated by the voltage controlled oscillator 335, and outputs the divided clock signal CK3c to the phase frequency detector 332. The phase frequency detector 332 compares the phase and frequency of the delayed reference clock signal RCKc and the clock signal CK3c, and outputs an up signal UP or a down signal DN to the supply pump 333 based on the result of the comparison. The supply pump 333 increases the voltage of the control signal V3 if the up signal UP is input, and decreases the voltage of the control signal V3 if the down signal DN is input. The low-pass filter 334 performs low-pass filtering on the control signal V3, and outputs the low-pass filtered clock control signal V3c to the voltage controlled oscillator 335. The phase frequency detector 332, the supply pump 333, the low-pass filter 334 and the frequency divider 336 are an example of a clock control circuit that generates the clock control signal V3c. The voltage controlled oscillator 335 is a clock signal generating circuit, and generates an output clock signal CK3 of a frequency based on the voltage of the clock control signal V3c. The analog-to-digital converter 337 converts the clock control signal V3c from analog to digital, and outputs the digital control signal D3 to the delay control circuit 338. The delay control circuit 338 adjusts the delay amount of the delay circuit 331 through the delay control signal CTL3 to minimize the variation of the control signal D3. Thus, the delay control circuit 338 can adjust the delay amount of the delay circuit 331 through the delay control signal CTL3 to minimize the jitter of the output clock signal CK3. The analog-to-digital converter 337 and the delay control circuit 338 are an example of a monitoring circuit, which monitors the jitter of the output clock signal CK3 and adjusts the delay amount of the delay circuit 331 based on the monitoring result of the jitter of the output clock signal CK3.

[0074] The phase-locked loop circuit 134 includes a delay circuit 341, a phase frequency detector 342, a charge pump 343, a low-pass filter 344, a voltage-controlled oscillator 345, a frequency divider 346, an analog-to-digital converter 347, and a delay control circuit 348, and generates an output clock signal CK4.

[0075] The delay circuit 341 delays the reference clock signal RCK by a delay amount, and outputs a delayed reference clock signal RCKd, wherein the delay amount can be adjusted. The frequency divider 346 divides the output clock signal CK4 generated by the voltage controlled oscillator 345, and outputs the divided clock signal CK4d to the phase frequency detector 342. The phase frequency detector 342 compares the phase and frequency of the delayed reference clock signal RCKd and the clock signal CK4d, and outputs an up signal UP or a down signal DN to the supply pump 343 based on the result of the comparison. The supply pump 343 increases the voltage of the control signal V4 if the up signal UP is input, and decreases the voltage of the control signal V4 if the down signal DN is input. The low-pass filter 344 performs low-pass filtering on the control signal V4, and outputs the low-pass filtered clock control signal V4d to the voltage controlled oscillator 345. The phase frequency detector 342, the supply pump 343, the low-pass filter 344 and the frequency divider 346 are an example of a clock control circuit that generates the clock control signal V4d. The voltage controlled oscillator 345 is a clock signal generating circuit, and generates an output clock signal CK4 of a frequency based on the voltage of the clock control signal V4d. The analog-to-digital converter 347 converts the clock control signal V4d from analog to digital, and outputs the digital control signal D4 to the delay control circuit 348. The delay control circuit 348 adjusts the delay amount of the delay circuit 341 through the delay control signal CTL4 to minimize the variation of the control signal D4. Thus, the delay control circuit 348 can adjust the delay amount of the delay circuit 341 through the delay control signal CTL4 to minimize the jitter of the output clock signal CK4. The analog-to-digital converter 347 and the delay control circuit 348 are an example of a monitoring circuit, which monitors the jitter of the output clock signal CK4 and adjusts the delay amount of the delay circuit 341 based on the monitoring result of the jitter of the output clock signal CK4.

[0076] Figure 7 1 is a flowchart showing a control method of the integrated circuit 100 according to the present embodiment. For the phase-locked loop circuits 131 to 134, the interference of power supply noise between phase-locked loop circuits that are close to each other is greater, and the interference of power supply noise between phase-locked loop circuits that are far away is smaller. Therefore, in the present embodiment, by sequentially adjusting the delay amount for minimizing the jitter between adjacent phase-locked loop circuits in the phase-locked loop circuits 131 to 134, the interference of power supply noise between all phase-locked loop circuits is suppressed. As a result, the jitter of the output clock signals CK1 to CK4 of all phase-locked loop circuits 131 to 134 can be reduced.

[0077] In step S701 , the central processing unit 101 controls the phase-locked loop circuits 131 and 132 to operate and the other phase-locked loop circuits 133 and 134 to not operate.

[0078] Next, in step S702, the delay control circuit 328 and Figure 4 Similarly to the flowchart of , the variation of the control signal D2 is observed and the delay of the delay circuit 321 is adjusted to minimize the variation of the control signal D2. Thus, the interference of the power supply noise between the adjacent phase-locked loop circuits 131 and 132 can be suppressed, and the jitter of the output clock signals CK1 and CK2 can be reduced.

[0079] Next, in step S703 , the central processing unit 101 controls the phase-locked loop circuits 131 to 133 to operate and the other phase-locked loop circuits 134 and the like to not operate.

[0080] Next, in step S704, the delay control circuit 338 and Figure 4 Similarly to the flowchart of , the variation of the control signal D3 is observed and the delay of the delay circuit 331 is adjusted to minimize the variation of the control signal D3. Thus, the interference of power supply noise between adjacent PLL circuits 131 to 133 can be suppressed and the jitter of the output clock signals CK1 to CK3 can be reduced.

[0081] Next, in step S705 , the central processing unit 101 controls the state in which the PLL circuits 131 to 134 are operated and the other PLL circuits are not operated.

[0082] Next, in step S706, the delay control circuit 348 and Figure 4 Similarly to the flowchart of , the variation of the control signal D4 is observed and the delay of the delay circuit 341 is adjusted to minimize the variation of the control signal D4. Thus, the interference of power supply noise between adjacent PLL circuits 131 to 134 can be suppressed and the jitter of the output clock signals CK1 to CK4 can be reduced.

[0083] After that, the same processing is performed on all the phase-locked loop circuits, thereby reducing the jitter of the output clock signals of all the phase-locked loop circuits.

[0084] (Fourth Embodiment)

[0085] Figure 8 1 is a diagram showing a configuration example of the transmission and reception circuits 111 and 112 according to the fourth embodiment. The following describes the differences between the present embodiment and the first embodiment.

[0086] The transceiver circuit 111 includes a transmission circuit 121 , a phase-locked loop circuit 131 , a reception circuit 141 , and an eye monitor 151 . Figure 8 The phase-locked loop circuit 131 is relative to Figure 3The analog-to-digital converter 317 is deleted from the phase-locked loop circuit 131. The transmission circuit 121 transmits the test pattern data generated by the pattern generator in synchronization with the output clock signal CK1 generated by the phase-locked loop circuit 131. The input terminal of the receiving circuit 141 can be switched. Figure 1 In the normal mode, the input terminal of the receiving circuit 141 is connected to other integrated circuits, and the receiving circuit 141 receives data sent by other integrated circuits. Figure 8 In the adjustment mode, the input terminal of the receiving circuit 141 is connected to the output terminal of the transmitting circuit 121, and the receiving circuit 141 receives the data sent by the transmitting circuit 121. Fig. 9 as well as Fig.10 As shown, the eye monitor 151 detects the openings 901 and 1001 of the eye pattern of the data received by the receiving circuit 141. The eye pattern is a pattern formed by overlapping a plurality of data transition patterns on the time axis. The delay control circuit 318 adjusts the delay amount of the delay circuit 311 based on the openings 901 and 1001 of the eye pattern detected by the eye monitor 151 so as to minimize the jitter of the output clock signal CK1.

[0087] The transceiver circuit 112 includes a transmission circuit 122 , a phase-locked loop circuit 132 , a reception circuit 142 , and an eye monitor 152 . Figure 8 The phase-locked loop circuit 132 has Figure 3 The transmitting circuit 122 transmits the test pattern data generated by the pattern generator in synchronization with the output clock signal CK2 generated by the phase-locked loop circuit 132. The input terminal of the receiving circuit 142 can be switched. Figure 1 In the normal mode, the input terminal of the receiving circuit 142 is connected to other integrated circuits, and the receiving circuit 142 receives data sent by other integrated circuits. Figure 8 In the adjustment mode, the input terminal of the receiving circuit 142 is connected to the output terminal of the transmitting circuit 122, and the receiving circuit 142 receives the data transmitted by the transmitting circuit 122. The eye monitor 152 detects the opening of the eye pattern of the data received by the receiving circuit 142.

[0088] Furthermore, since the delay amount of the delay circuit 321 is not controlled, the transmission circuit 122 may not transmit the test pattern data. The input terminal of the reception circuit 142 may not be connected to the output terminal of the transmission circuit 122. The eye monitor 152 may be deleted.

[0089] Fig. 9 1 is a diagram showing an eye pattern before the delay amount of the delay circuit 311 is adjusted. The eye monitor 151 detects the opening 901 of the eye pattern. When the delay amount of the delay circuit 311 is inappropriate, the jitter of the output clock signal CK1 increases and the opening 901 of the eye pattern decreases.

[0090] Fig.10 1 is a diagram showing an eye pattern after the delay amount of the delay circuit 311 is adjusted. The eye monitor 151 detects the opening 1001 of the eye pattern. When the delay amount of the delay circuit 311 is appropriate, the jitter of the output clock signal CK1 becomes small and the opening 1001 of the eye pattern becomes large.

[0091] The delay control circuit 318 adjusts the delay amount of the delay circuit 311 so as to maximize the opening area of ​​the eye pattern. That is, the delay control circuit 318 adjusts the delay amount of the delay circuit 311 according to the opening of the eye pattern of the transmission signal generated based on the output clock signal CK1.

[0092] For example, the eye monitor 151 performs binary determination by sampling the output signal of the receiving circuit 141 using the main sampler and the monitor sampler and comparing it with a threshold. At this time, the eye monitor 151 detects the opening of the eye pattern by comparing the value determined by the main sampler and the value determined by the monitor sampler while changing the sampling phase and threshold of the monitor sampler. The delay control circuit 318 searches for the delay amount of the delay circuit 311 that maximizes the opening area of ​​the eye pattern. In addition, the delay control circuit 318 adjusts the delay amount of the delay circuit 311 so that the opening area of ​​the eye pattern is maximized. In this way, the jitter of the output clock signals CK1 and CK2 can be reduced.

[0093] Furthermore, from the viewpoint of jitter, the delay control circuit 318 may adjust the delay amount of the delay circuit 311 so that the opening area of ​​the central portion of the eye pattern in the time axis direction is maximized.

[0094] In addition, a receiving circuit and an eye monitor in another integrated circuit may be used instead of the above-mentioned receiving circuit 141 and the eye monitor 151. In this case, the transmitting circuit 121 transmits the test pattern data to the other integrated circuit in synchronization with the output clock signal CK1. In the other integrated circuit, the receiving circuit receives the test pattern data, and the eye monitor 151 detects the opening of the eye pattern of the test pattern data. The delay control circuit 318 adjusts the delay amount of the delay circuit 311 so that the opening area of ​​the eye pattern detected by the eye monitor of the other integrated circuit is maximized.

[0095] In addition, it is possible to Figure 8 The phase-locked loop circuits 131 and 132 of the fourth embodiment shown are modified as follows.

[0096] For example, you can also Figure 5Similar to the phase-locked loop circuits 131 and 132 of the second embodiment shown, the delay control circuit 318 adjusts the delay amount of the delay circuit 311 based on the opening of the eye pattern detected by the eye monitor 152 in addition to the opening of the eye pattern detected by the eye monitor 151, so as to maximize the sum of the opening areas of the two eye patterns detected by the eye monitors 151 and 152.

[0097] In addition, you can also Figure 6 The phase-locked loop circuits 131 to 134 of the third embodiment shown are the same except that Figure 8 In addition to the phase-locked loops 131 and 132, circuits similar to the phase-locked loop circuit 131 may be provided adjacent to each other, and the delay amount for minimizing the jitter between adjacent phase-locked loop circuits may be adjusted in sequence.

[0098] In addition, the above-mentioned embodiments are merely examples of specific implementation of the present invention, and the technical scope of the present invention cannot be limitedly interpreted by these embodiments. That is, the present invention can be implemented in various forms without departing from its technical concept or its main features.

[0099] Industrial Applicability

[0100] In one aspect, jitter of an output clock signal can be reduced.

Claims

1. A phase synchronization circuit, comprising: The first delay circuit delays the first reference clock signal by a first delay amount and outputs a first delayed reference clock signal, wherein: The first delay amount is adjustable; a first clock control circuit, which compares the phases of the first delayed reference clock signal and the first output clock signal, and outputs a first clock control signal based on a result of the comparison; A first clock signal generating circuit receives the first clock control signal and generates the first output clock signal based on the received first clock control signal; as well as a first monitoring circuit that monitors jitter of the first output clock signal and adjusts the first delay amount based on a monitoring result of the jitter of the first output clock signal; The first clock signal generating circuit includes a voltage controlled oscillator circuit, and the voltage controlled oscillator circuit receives the first clock control signal as an input signal. The first monitoring circuit detects a variation of the input signal of the voltage controlled oscillator circuit, and adjusts the first delay amount based on the detected variation.

2. The phase synchronization circuit according to claim 1, wherein: The phase synchronization circuit further comprises: a second clock control circuit, which compares the phases of the second reference clock signal and the second output clock signal, and generates a second clock control signal based on a result of the comparison; as well as A second clock signal generating circuit generates the second output clock signal based on the second clock control signal. The first monitoring circuit adjusts the first delay amount based on a change in the first clock control signal and a change in the second clock control signal.

3. The phase synchronization circuit according to claim 1, wherein: The phase synchronization circuit further comprises: a second clock control circuit, which compares the phases of the second reference clock signal and the second output clock signal, and generates a second clock control signal based on a result of the comparison; A second clock signal generating circuit, generating the second output clock signal based on the second clock control signal; a second delay circuit, delaying the third reference clock signal by a second delay amount and outputting a second delayed reference clock signal, wherein the second delay amount is adjustable; a third clock control circuit, which compares the phases of the second delayed reference clock signal and the third output clock signal, and generates a third clock control signal based on the comparison result; A third clock signal generating circuit, generating the third output clock signal based on the third clock control signal; and The second monitoring circuit monitors jitter of the third output clock signal and adjusts the second delay amount based on a monitoring result of the jitter of the third output clock signal.

4. The phase synchronization circuit according to claim 3, wherein: The group of the first clock control circuit and the first clock signal generating circuit is provided between the group of the second clock control circuit and the second clock signal generating circuit and the group of the third clock control circuit and the third clock signal generating circuit. In a state where the group of the first clock control circuit and the first clock signal generating circuit and the group of the second clock control circuit and the second clock signal generating circuit are in operation and the group of the third clock control circuit and the third clock signal generating circuit are not in operation, the first monitoring circuit adjusts the first delay amount based on a change in the first clock control signal, Afterwards, while the group of the first clock control circuit and the first clock signal generating circuit, the group of the second clock control circuit and the second clock signal generating circuit, and the group of the third clock control circuit and the third clock signal generating circuit are in operation, the second monitoring circuit adjusts the second delay amount based on changes in the third clock control signal.

5. A transceiver circuit, comprising: a first phase synchronization circuit, generating a first output clock signal; A first sending circuit, which sends based on the first output clock signal; and The first receiving circuit receives based on the first output clock signal. The first phase synchronization circuit has: The first delay circuit delays the first reference clock signal by a first delay amount and outputs a first delayed reference clock signal, wherein: The first delay amount is adjustable; a first clock control circuit, which compares the phases of the first delayed reference clock signal and the first output clock signal, and outputs a first clock control signal based on a result of the comparison; A first clock signal generating circuit receives the first clock control signal and generates the first output clock signal based on the received first clock control signal; as well as a first monitoring circuit that monitors jitter of the first output clock signal and adjusts the first delay amount based on a monitoring result of the jitter of the first output clock signal; The first clock signal generating circuit includes a voltage controlled oscillator circuit, and the voltage controlled oscillator circuit receives the first clock control signal as an input signal. The first monitoring circuit detects a variation of the input signal of the voltage controlled oscillator circuit, and adjusts the first delay amount based on the detected variation.

6. The transceiver circuit according to claim 5, wherein: The above-mentioned transceiver circuit also has: a second phase synchronization circuit, generating a second output clock signal; A second sending circuit, sending based on the second output clock signal; The second receiving circuit receives based on the second output clock signal. The second phase synchronization circuit has: a second clock control circuit, which compares the phases of the second reference clock signal and the second output clock signal, and generates a second clock control signal based on the comparison result; as well as A second clock signal generating circuit generates the second output clock signal based on the second clock control signal. The first monitoring circuit adjusts the first delay amount based on a change in the first clock control signal and a change in the second clock control signal.

7. The transceiver circuit according to claim 5, wherein: The above-mentioned transceiver circuit also has: a second phase synchronization circuit, generating a second output clock signal; A second sending circuit, sending based on the second output clock signal; A second receiving circuit receives based on the second output clock signal; a third phase synchronization circuit, generating a third output clock signal; A third sending circuit, sending based on the third output clock signal; as well as A third receiving circuit receives based on the third output clock signal. The second phase synchronization circuit has: a second clock control circuit, which compares the phases of the second reference clock signal and the second output clock signal, and generates a second clock control signal based on the comparison result; as well as A second clock signal generating circuit generates the second output clock signal based on the second clock control signal. The third phase synchronization circuit has: a second delay circuit, delaying the third reference clock signal by a second delay amount and outputting a second delayed reference clock signal, wherein the second delay amount is adjustable; a third clock control circuit, which compares the phases of the second delayed reference clock signal and the third output clock signal, and generates a third clock control signal based on the comparison result; A third clock signal generating circuit, generating the third output clock signal based on the third clock control signal; as well as The second monitoring circuit monitors jitter of the third output clock signal and adjusts the second delay amount based on a monitoring result of the jitter of the third output clock signal.

8. The transceiver circuit according to claim 7, wherein: The first phase synchronization circuit is arranged between the second phase synchronization circuit and the third phase synchronization circuit. In a state where the first phase synchronization circuit and the second phase synchronization circuit are in operation and the third phase synchronization circuit is not in operation, the first monitoring circuit adjusts the first delay amount based on a change in the first clock control signal. Thereafter, while the first phase synchronization circuit, the second phase synchronization circuit, and the third phase synchronization circuit are operating, the second monitoring circuit adjusts the second delay amount based on a change in the third clock control signal.

9. An integrated circuit having: a first phase synchronization circuit, generating a first output clock signal; A first sending circuit sends first sending data based on the first output clock signal; A first receiving circuit receives first received data based on the first output clock signal; as well as The internal circuit outputs the first transmission data to the first transmission circuit and inputs the first reception data from the first reception circuit. The first phase synchronization circuit has: a first delay circuit, delaying the first reference clock signal by a first delay amount and outputting a first delayed reference clock signal, wherein the first delay amount is adjustable; a first clock control circuit, which compares the phases of the first delayed reference clock signal and the first output clock signal, and outputs a first clock control signal based on a result of the comparison; a first clock signal generating circuit, receiving the first clock control signal, and generating the first output clock signal based on the received first clock control signal; and a first monitoring circuit that monitors jitter of the first output clock signal and adjusts the first delay amount based on a monitoring result of the jitter of the first output clock signal; The first clock signal generating circuit includes a voltage controlled oscillator circuit, and the voltage controlled oscillator circuit receives the first clock control signal as an input signal. The first monitoring circuit detects a variation of the input signal of the voltage controlled oscillator circuit, and adjusts the first delay amount based on the detected variation.

10. The integrated circuit of claim 9, wherein: The above integrated circuit also has: a second phase synchronization circuit, generating a second output clock signal; A second sending circuit sends second sending data based on the second output clock signal; as well as A second receiving circuit receives second received data based on the second output clock signal. The second phase synchronization circuit has: a second clock control circuit, which compares the phases of the second reference clock signal and the second output clock signal, and generates a second clock control signal based on the comparison result; as well as A second clock signal generating circuit generates the second output clock signal based on the second clock control signal. The first monitoring circuit adjusts the first delay amount based on a change in the first clock control signal and a change in the second clock control signal.

11. The integrated circuit of claim 9, wherein: The above integrated circuit also has: a second phase synchronization circuit, generating a second output clock signal; A second sending circuit sends second sending data based on the second output clock signal; A second receiving circuit receives second received data based on the second output clock signal; a third phase synchronization circuit, generating a third output clock signal; A third sending circuit sends third sending data based on the third output clock signal; as well as A third receiving circuit receives third received data based on the third output clock signal. The second phase synchronization circuit has: a second clock control circuit, which compares the phases of the second reference clock signal and the second output clock signal, and generates a second clock control signal based on the comparison result; as well as A second clock signal generating circuit generates the second output clock signal based on the second clock control signal. The third phase synchronization circuit has: a second delay circuit, delaying the third reference clock signal by a second delay amount and outputting a second delayed reference clock signal, wherein the second delay amount is adjustable; a third clock control circuit, which compares the phases of the second delayed reference clock signal and the third output clock signal, and generates a third clock control signal based on the comparison result; A third clock signal generating circuit, generating the third output clock signal based on the third clock control signal; as well as The second monitoring circuit monitors jitter of the third output clock signal and adjusts the second delay amount based on a monitoring result of the jitter of the third output clock signal.

12. The integrated circuit of claim 11, wherein: The first phase synchronization circuit is arranged between the second phase synchronization circuit and the third phase synchronization circuit. In a state where the first phase synchronization circuit and the second phase synchronization circuit are in operation and the third phase synchronization circuit is not in operation, the first monitoring circuit adjusts the first delay amount based on a change in the first clock control signal. Thereafter, while the first phase synchronization circuit, the second phase synchronization circuit, and the third phase synchronization circuit are operating, the second monitoring circuit adjusts the second delay amount based on a change in the third clock control signal.

13. A phase synchronization circuit, comprising: The first delay circuit delays the first reference clock signal by a first delay amount and outputs a first delayed reference clock signal, wherein: The first delay amount is adjustable; a first clock control circuit, which compares the phases of the first delayed reference clock signal and the first output clock signal, and generates a first clock control signal based on a result of the comparison; A first clock signal generating circuit, generating the first output clock signal based on the first clock control signal; as well as a first monitoring circuit that monitors jitter of the first output clock signal and adjusts the first delay amount based on a monitoring result of the jitter of the first output clock signal; The first monitoring circuit adjusts the first delay amount based on an opening area of ​​an eye pattern of a transmission signal generated based on the first output clock signal. The first monitoring circuit adjusts the first delay amount so as to maximize the opening area of ​​the eye pattern.

14. A transceiver circuit, comprising: a first phase synchronization circuit, generating a first output clock signal; A first sending circuit, which sends based on the first output clock signal; and The first receiving circuit receives based on the first output clock signal. The first phase synchronization circuit has: The first delay circuit delays the first reference clock signal by a first delay amount and outputs a first delayed reference clock signal, wherein: The first delay amount is adjustable; a first clock control circuit, which compares the phases of the first delayed reference clock signal and the first output clock signal, and generates a first clock control signal based on a result of the comparison; A first clock signal generating circuit, generating the first output clock signal based on the first clock control signal; as well as a first monitoring circuit that monitors jitter of the first output clock signal and adjusts the first delay amount based on a monitoring result of the jitter of the first output clock signal; The first monitoring circuit adjusts the first delay amount based on an opening area of ​​an eye pattern of a transmission signal generated by the first transmission circuit based on the first output clock signal. The first monitoring circuit adjusts the first delay amount so as to maximize the opening area of ​​the eye pattern.

15. An integrated circuit having: a first phase synchronization circuit, generating a first output clock signal; A first sending circuit sends first sending data based on the first output clock signal; A first receiving circuit receives first received data based on the first output clock signal; as well as The internal circuit outputs the first transmission data to the first transmission circuit and inputs the first reception data from the first reception circuit. The first phase synchronization circuit has: a first delay circuit, delaying the first reference clock signal by a first delay amount and outputting a first delayed reference clock signal, wherein the first delay amount is adjustable; a first clock control circuit, which compares the phases of the first delayed reference clock signal and the first output clock signal, and generates a first clock control signal based on a result of the comparison; A first clock signal generating circuit, generating the first output clock signal based on the first clock control signal; and a first monitoring circuit that monitors jitter of the first output clock signal and adjusts the first delay amount based on a monitoring result of the jitter of the first output clock signal; The first monitoring circuit adjusts the first delay amount based on an opening area of ​​an eye pattern of a transmission signal generated by the first transmission circuit based on the first output clock signal. The first monitoring circuit adjusts the first delay amount so as to maximize the opening area of ​​the eye pattern.

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