Package and method of manufacturing the same

Abstract

The package includes a first tube core, a second tube core, an encapsulation body, and an insulating layer perforation. The first tube core has a first bonding structure. The first bonding structure includes a first dielectric layer and a first connector embedded in the first dielectric layer. The second tube core has a second bonding structure. The second bonding structure includes a second dielectric layer and a second connector embedded in the second dielectric layer. The first dielectric layer and the second dielectric layer are mixedly bonded. The first connector and the second connector are mixedly bonded. The encapsulation body laterally encapsulates the second tube core. The insulating layer perforation penetrates the encapsulation body and is connected to the first bonding structure.

Description

Technical Field

[0001] The present invention relates to a package and a method for manufacturing the same. More specifically, the present invention relates to a package with a hybrid bonding structure and a method for manufacturing the same. Background Art

[0002] Semiconductor devices and integrated circuits used in various electronic devices (e.g., mobile phones and other mobile electronic devices) are usually manufactured on a single semiconductor wafer. The die of the wafer can be processed and packaged with other semiconductor devices or dies at the wafer level, and various technologies and applications have been developed for wafer level packaging. Integrating multiple semiconductor devices has become a challenge in this field. Summary of the invention

[0003] A package includes a first tube core, a second tube core, an encapsulation body, and an insulating layer through-hole (TIV). The first tube core has a first bonding structure. The first bonding structure includes a first dielectric layer and a first connector embedded in the first dielectric layer. The second tube core has a second bonding structure. The second bonding structure includes a second dielectric layer and a second connector embedded in the second dielectric layer. The first dielectric layer is hybrid bonded with the second dielectric layer. The first connector is hybrid bonded with the second connector. The encapsulation body laterally encapsulates the second tube core. The insulating layer through-hole penetrates the encapsulation body and is connected to the first bonding structure.

[0004] A package includes a first tube core, a second tube core and an encapsulation body. The first tube core includes a first pad, a first connector and a first dielectric layer. The first connector is located on the first pad. The first dielectric layer encapsulates the first pad and the first connector. The second tube core includes a second pad, a second connector and a second dielectric layer. The second connector is located on the second pad and is in direct contact with the first connector. The second dielectric layer encapsulates the second pad and the second connector. The second dielectric layer is in direct contact with the first dielectric layer. The encapsulation body laterally encapsulates the second tube core. The encapsulation body is in direct contact with the first dielectric layer.

[0005] A method for manufacturing a package includes at least the following steps. A semiconductor wafer having a first bonding structure formed thereon is provided. A semiconductor die is bonded to the semiconductor wafer. Each of the semiconductor dies has a second bonding structure formed thereon and a semiconductor through-hole (TSV) formed therein. The first bonding structure is bonded to the second bonding structure. A through-insulation layer via (TIV) is formed to surround the semiconductor die. A first encapsulant is used to encapsulate the semiconductor die and the insulating layer through-hole. A portion of each of the semiconductor die is removed to form a groove. A second encapsulant is filled into the groove. An under-ball metal pattern and a conductive terminal are formed on the first encapsulant and the second encapsulant. The under-ball metal pattern is connected to the insulating layer through-hole and the semiconductor through-hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A to Figure 1K is a schematic cross-sectional view of a manufacturing process of a package according to some embodiments of the present disclosure.

[0008] Figure 2 are schematic cross-sectional views of packages according to some alternative embodiments of the present disclosure.

[0009] Figure 3 are schematic cross-sectional views of packages according to some alternative embodiments of the present disclosure.

[0010] Figure 4 are schematic cross-sectional views of packages according to some alternative embodiments of the present disclosure.

[0011] Description of Figure Numbers

[0012] 10, 20, 30, 40: Encapsulation

[0013] 100, 200: semiconductor die

[0014] 110: Semiconductor substrate

[0015] 120: First internal connection structure

[0016] 122: First dielectric interlayer

[0017] 124: first patterned conductive layer

[0018] 126: First via

[0019] 130: First joint structure

[0020] 132: First dielectric layer

[0021] 134: First pad

[0022] 136: First connecting piece

[0023] 136a, 138a, 236a: Through hole part

[0024] 136b, 138b, 236b: Groove part

[0025] 138: Auxiliary connector

[0026] 210: Semiconductor substrate

[0027] 212: Semiconductor drilling

[0028] 220: Second internal structure

[0029] 222: Second dielectric interlayer

[0030] 224: Second patterned conductive layer

[0031] 226: Second via

[0032] 230: Second bonding structure

[0033] 232: Second dielectric layer

[0034] 234: Second pad

[0035] 236: Second connecting piece

[0036] 300: Insulation perforation

[0037] 400: Encapsulation

[0038] 400a: first enclosure

[0039] 400a': first encapsulation material

[0040] 400b: Second packaging body

[0041] 500: Dielectric layer

[0042] 600: Metal pattern under the ball

[0043] 700: Conductive terminal

[0044] AS1, AS2: valid surface

[0045] H W , H 200 , H 200’ , H 300 :high

[0046] OP: Opening contact

[0047] R: Groove

[0048] RS1, RS2, RS2', RS2", RS2'': rear surface

[0049] T 212 、T 300 、T 300’ 、T 400a 、T 400a’ 、T 400b : Top surface

[0050] W: semiconductor wafer

[0051] W 212 , W 300 , W 600 :width

[0052] WS: Wafer substrate DETAILED DESCRIPTION

[0053] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description in which a first feature is formed on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than indicating the relationship between the various embodiments and / or configurations discussed by itself.

[0054] Additionally, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature illustrated in a figure to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0055] The present disclosure may also include other features and processes. For example, a test structure may be included to help perform verification testing on three-dimensional (3D) packages or three-dimensional integrated circuits (3DIC) devices. The test structure may include, for example, test pads formed in a redistribution layer or on a substrate to enable testing of three-dimensional packages or three-dimensional integrated circuits, use of probes and / or probe cards, etc. Verification testing may be performed on intermediate structures and final structures. In addition, the structures and methods disclosed herein may be used in conjunction with a test method that includes intermediate verification of known good dies to improve yield and reduce costs.

[0056] Figure 1A to Figure 1K is a schematic cross-sectional view of a manufacturing process of a package according to some embodiments of the present disclosure. Figure 1A , a semiconductor wafer W is provided. In some embodiments, the semiconductor wafer W includes a wafer substrate WS and a first interconnect structure 120 formed on the semiconductor wafer W. In some embodiments, a first bonding structure 130 is formed on the semiconductor wafer W, and the first bonding structure 130 is also considered as a part of the semiconductor wafer W.

[0057] In some embodiments, the wafer substrate WS may be made of the following semiconductors: a suitable elemental semiconductor, such as crystalline silicon, diamond, or germanium; a suitable compound semiconductor, such as gallium arsenide, silicon carbide, indium arsenide, or indium phosphide; or a suitable alloy semiconductor, such as silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. In some embodiments, the wafer substrate WS may include active components (such as transistors, etc.) and / or passive components (such as resistors, capacitors, inductors, etc.) formed therein. In some embodiments, the wafer substrate WS may also include a plurality of through semiconductor vias (TSVs) penetrating the wafer substrate WS for dual-side connection. However, in the wafer substrate WS, the TSVs may be optional, so these TSVs are not included in the wafer substrate WS. Figure 1A Shown in.

[0058] like Figure 1A As shown in FIG. 1 , a first interconnect structure 120 is disposed on a wafer substrate WS. In some embodiments, the first interconnect structure 120 includes a first dielectric interlayer 122, a plurality of first patterned conductive layers 124, and a plurality of first vias 126. In some embodiments, the first patterned conductive layers 124 and the first vias 126 are embedded in the first dielectric interlayer 122. For simplicity, the first dielectric interlayer 122 is Figure 1A 12 is shown as a bulk layer, but it should be understood that the first dielectric interlayer 122 may be composed of multiple dielectric layers. The first patterned conductive layers 124 are alternately stacked with the dielectric layers of the first dielectric interlayer 122. In some embodiments, two adjacent first patterned conductive layers 124 are electrically connected to each other through a via 126 sandwiched therebetween.

[0059] In some embodiments, the material of the first dielectric interlayer 122 includes polyimide, epoxy resin, acrylic resin, phenolic resin, benzocyclobutene (BCB), polybenzoxazole (PBO), or other suitable polymer dielectric materials. The first dielectric interlayer 122 can be formed, for example, by suitable manufacturing techniques (such as spin coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), etc.). In some embodiments, the material of the first patterned conductive layer 124 and the first via 126 includes aluminum, titanium, copper, nickel, tungsten, and / or alloys thereof. The first patterned conductive layer 124 and the first via 126 can be formed, for example, by electroplating, deposition, and / or photolithography and etching. It should be noted that, Figure 1A The number of the first patterned conductive layer 124, the first vias 126, and the number of dielectric layers in the first dielectric interlayer 122 shown in the figure is only for illustration, and the present disclosure is not limited thereto. In some alternative embodiments, the number of the first patterned conductive layer 124, the number of the first vias 126, and the number of dielectric layers in the first dielectric interlayer 122 can be adjusted according to wiring requirements.

[0060] In some embodiments, the first bonding structure 130 includes a first dielectric layer 132, a plurality of first pads 134, a plurality of first connectors 136, and a plurality of auxiliary connectors 138. In some embodiments, the first pads 134 are formed on the first interconnect structure 120 so that the first pads 134 directly contact the topmost first via 126 of the first interconnect structure 120. In other words, the first interconnect structure 120 is sandwiched between the first pads 134 and the wafer substrate WS. In some embodiments, the first pads 134 are electrically connected to the first interconnect structure 120 through the topmost first via 126. In some embodiments, the first pads 134 may be aluminum pads, copper pads, or other suitable metal pads. It should be noted that the number and shape of the first pads 140 may be selected based on needs. In some embodiments, the first dielectric layer 132 is formed on the first pads 134 to seal the first pads 134. In some embodiments, the material of the first dielectric layer 132 includes oxides, such as silicon oxide. Alternatively, the first dielectric layer 132 may include polyimide, epoxy resin, acrylic resin, phenolic resin, benzocyclobutene (BCB), polybenzoxazole (PBO), or any other suitable polymer-based dielectric material. The first dielectric layer 132 may be formed, for example, by a suitable fabrication technique (e.g., spin coating, CVD, PECVD, etc.).

[0061] In some embodiments, the first connector 136 and the auxiliary connector 138 can be formed by removing a portion of the first dielectric layer 132 and filling the gap with a conductive material. For example, the first connector 136 and the auxiliary connector 138 can be formed by a dual damascene process. Therefore, each first connector 136 may include a through-hole portion 136a and a groove portion 136b stacked on the through-hole portion 136a. Similarly, each auxiliary connector 138 may also include a through-hole portion 138a and a groove portion 138b stacked on the through-hole portion 138a. In some embodiments, the width of the groove portion 136b is greater than the width of the through-hole portion 136a. Similarly, the width of the groove portion 138b is greater than the width of the through-hole portion 138a. In some embodiments, the first connector 136 and the auxiliary connector 138 may be made of, for example, aluminum, titanium, copper, nickel, tungsten, and / or its alloy. In some embodiments, the first connector 136 and the auxiliary connector 138 are formed simultaneously. However, the present disclosure is not limited thereto. In some alternative embodiments, the first connector 136 and the auxiliary connector 138 may be formed separately. For example, the first connector 136 may be formed before or after the auxiliary connector 138 is formed. Figure 1AAs shown in , the first connector 136 is disposed on the first pad 134 and is in direct contact with the first pad 134. In some embodiments, the first connector 136 is electrically connected to the first interconnect structure 120 through the first pad 134. On the other hand, the auxiliary connector 138 extends into the first dielectric interlayer 122 to directly contact the topmost first patterned conductive layer 124, thereby achieving electrical connection with the first interconnect structure 120. However, the aforementioned configuration is merely illustrative, and the present disclosure is not limited thereto. In some alternative embodiments, the configuration of the first connector 136 may be the same as the configuration of the auxiliary connector 138. In other words, other additional pads may be formed directly below the auxiliary connector 138 so that the auxiliary connector 138 is electrically connected to the first interconnect structure 120 through these additional pads. As shown in FIG. Figure 1A As shown in FIG. 1 , the first connector 136 and the auxiliary connector 138 are embedded in the first dielectric layer 132 .

[0062] In some embodiments, the semiconductor wafer W has a height H of about 500 μm to about 775 μm. W In some embodiments, the top surface of the first connector 136, the top surface of the auxiliary connector 138, and the top surface of the first dielectric layer 132 may be collectively referred to as the active surface AS1 of the semiconductor wafer W. On the other hand, the surface of the semiconductor wafer W opposite to the active surface AS1 may be referred to as the back surface RS1 of the semiconductor wafer W. Figure 1A As shown in FIG. 1 , the top surface of the first connector 136 , the top surface of the auxiliary connector 138 , and the top surface of the first dielectric layer 132 are substantially located at the same level to provide a suitable active surface AS1 for hybrid bonding.

[0063] Reference Figure 1B , providing a plurality of semiconductor dies 200. In some embodiments, each semiconductor die 200 includes a semiconductor substrate 210 and a second interconnect structure 220 formed on the semiconductor substrate 210. In some embodiments, a second bonding structure 230 is formed on each semiconductor die 200, and the second bonding structure 230 is also considered to be a part of the semiconductor die 200. In some embodiments, each semiconductor die 200 also includes a plurality of semiconductor through vias (TSVs) 212 formed therein. For example, the TSVs 212 are embedded in the semiconductor substrate 210 and are electrically connected to the second interconnect structure 220. In some embodiments, each TSV 212 has a width W of about 0.9 μm to about 10 μm. 212 On the other hand, two adjacent TSVs 212 have a pitch ranging between about 3 μm and about 50 μm.

[0064] In some embodiments, the semiconductor substrate 210 of the semiconductor die 200 may be similar to the wafer substrate WS of the semiconductor wafer W, and thus a detailed description thereof is omitted herein. Figure 1B As shown in , the second interconnect structure 220 is disposed on the semiconductor substrate 210. In some embodiments, the second interconnect structure 220 includes a second dielectric interlayer 222, a plurality of second patterned conductive layers 224, and a plurality of second vias 226. The second dielectric interlayer 222, the second patterned conductive layer 224, and the second vias 226 of the second interconnect structure 220 may be similar to the first dielectric interlayer 122, the first patterned conductive layer 124, and the first vias 126 of the first interconnect structure 120, respectively, and thus a detailed description thereof is omitted herein. Figure 1B As shown in FIG. 2 , the TSV 212 directly contacts one of the second patterned conductive layers 224 . In other words, the TSV 212 is electrically connected to the second interconnect structure 220 through one of the second patterned conductive layers 224 .

[0065] In some embodiments, the second bonding structure 230 includes a second dielectric layer 232, a plurality of second pads 234, and a plurality of second connectors 236. The second dielectric layer 232, the second pads 234, and the second connectors 236 of the second bonding structure 230 may be similar to the first dielectric layer 132, the first pads 134, and the first connectors 136 of the first bonding structure 130, respectively, and therefore a detailed description thereof is omitted herein. In some embodiments, the second connectors 236 may be formed by a dual damascene process. That is, each second connector 236 may include a through-hole portion 236a and a groove portion 236b stacked on the through-hole portion 236a. In some embodiments, the width of the groove portion 236b is greater than the width of the through-hole portion 236a. Figure 1B As shown in FIG. 2 , the second connection member 236 and the second pad 234 are embedded in the second dielectric layer 232 . On the other hand, the second interconnect structure 220 is sandwiched between the second pad 234 and the semiconductor substrate 210 .

[0066] In some embodiments, each semiconductor die 200 has a height H of about 40 μm to about 200 μm. 200’ .like Figure 1B As shown in , the bottom surface of the second connector 236 and the bottom surface of the second dielectric layer 232 may be collectively referred to as the active surface AS2 of the semiconductor die 200. On the other hand, the surface of the semiconductor die 200 opposite to the active surface AS2 may be referred to as the back surface RS2 of the semiconductor die 200. Figure 1B As shown in FIG. 1 , the bottom surface of the second connector 236 is substantially at the same level as the bottom surface of the second dielectric layer 232 to provide a suitable active surface AS2 for hybrid bonding.

[0067] In some embodiments, the semiconductor die 200 may be a die capable of performing a storage function. For example, the semiconductor die 200 may be a dynamic random access memory (DRAM), a resistive random access memory (RRAM), a static random access memory (SRAM), etc. However, the present disclosure is not limited thereto. In some alternative embodiments, the semiconductor die 200 may be a central processing unit (CPU) die, a graphics processing unit (GPU) die, a field programmable gate array (FPGA), etc.

[0068] like Figure 1B As shown in , the semiconductor die 200 is bonded to the semiconductor wafer W. In some embodiments, the semiconductor die 200 may be bonded to the semiconductor wafer W by a hybrid bonding process. In some embodiments, the temperature of the hybrid bonding process ranges from about 150° C. to about 400° C. The hybrid bonding process will be described in detail below.

[0069] In some embodiments, the semiconductor die 200 may be picked up and placed onto the active surface AS1 of the semiconductor wafer W so that the semiconductor die 200 is electrically connected to the semiconductor wafer W. In some embodiments, the semiconductor die 200 is placed so that the active surface AS2 of the semiconductor die 200 contacts the active surface AS1 of the semiconductor wafer W. At the same time, the second connectors 236 of the semiconductor die 200 are substantially aligned with the first connectors 136 of the semiconductor wafer W and directly contact the first connectors 136 of the semiconductor wafer W. For example, the groove portion 136b of each first connector 136 is substantially aligned with the corresponding groove portion 236b of each second connector 236 and directly contacts the corresponding groove portion 236b of each second connector 236.

[0070] In some embodiments, in order to promote hybrid bonding between the semiconductor die 200 and the semiconductor wafer W, surface preparation may be performed on the bonding surface of the semiconductor die 200 and the bonding surface of the semiconductor wafer W (i.e., the active surface AS1 and the active surface AS2). The surface preparation may include, for example, surface cleaning and activation. The active surfaces AS1 and AS2 may be surface cleaned to remove particles on the bonding surface of the first connector 136, the bonding surface of the second connector 236, the bonding surface of the first dielectric layer 132, and the bonding surface of the second dielectric layer 232. In some embodiments, the active surfaces AS1 and AS2 may be cleaned by, for example, wet cleaning. Not only will the particles be removed, but native oxides formed on the bonding surfaces of the first connector 136 and the bonding surfaces of the second connector 236 may also be removed. The native oxides formed on the bonding surfaces of the first connector 136 and the bonding surfaces of the second connector 236 may be removed by, for example, chemicals used in a wet cleaning process.

[0071] After cleaning the active surface AS1 of the semiconductor wafer W and the active surface AS2 of the semiconductor die 200, activation of the bonding surface of the first dielectric layer 132 and activation of the bonding surface of the second dielectric layer 232 may be performed to form a high bonding strength. In some embodiments, plasma activation may be performed to treat the bonding surface of the first dielectric layer 132 and the bonding surface of the second dielectric layer 232. When the activated bonding surface of the first dielectric layer 132 contacts the activated bonding surface of the second dielectric layer 232, the first dielectric layer 132 of the semiconductor wafer W and the second dielectric layer 232 of the semiconductor die 200 are pre-bonded.

[0072] After the semiconductor die 200 is pre-bonded onto the semiconductor wafer W, hybrid bonding of the semiconductor die 200 and the semiconductor wafer W is performed. The hybrid bonding of the semiconductor die 200 and the semiconductor wafer W may include a heat treatment for dielectric bonding and a thermal annealing for conductor bonding. In some embodiments, the thermal treatment for dielectric bonding is performed to strengthen the bonding between the first dielectric layer 132 and the second dielectric layer 232. For example, the thermal treatment for dielectric bonding may be performed at a temperature ranging from about 200° C. to about 400° C. After the thermal treatment for dielectric bonding is performed, thermal annealing for conductor bonding is performed to promote the bonding between the first connector 136 and the second connector 236. For example, the thermal annealing for conductor bonding may be performed at a temperature ranging from about 150° C. to about 400° C. After the thermal annealing for conductor bonding is performed, the first dielectric layer 132 is hybrid bonded to the second dielectric layer 232 and the first connector 136 is hybrid bonded to the second connector 236. For example, the first dielectric layer 132 directly contacts the second dielectric layer 232. Similarly, the first connector 136 directly contacts the second connector 236. Thus, the first bonding structure 130 is hybrid-bonded to the second bonding structure 230.

[0073] Reference Figure 1B and Figure 1C After hybrid bonding the semiconductor die 200 to the semiconductor wafer W, the height H of the semiconductor die 200 is reduced. 200’ For example, a portion of the semiconductor substrate 210 is removed so that Figure 1C The rear surface RS2′ of the semiconductor die 200 shown in FIG. Figure 1B In some embodiments, the semiconductor substrate 210 may be partially removed by a planarization process. In some embodiments, the planarization process includes a mechanical grinding process, a chemical mechanical polishing (CMP) process, etc. Figure 1C As shown in FIG. 1 , after the planarization process is performed, the TSV 212 is still not exposed. That is, at this stage, the thickness of the semiconductor substrate 210 is greater than the height of the TSV 212. In some embodiments, after the planarization process is performed, each semiconductor die 200 has a height H ranging from about 15 μm to about 30 μm. 200 .

[0074] Reference Figure 1D, a plurality of through insulating vias (TIVs) 300 are formed on the semiconductor wafer W. In some embodiments, the TIVs 300 are formed to surround the semiconductor die 200 and adhere to the auxiliary connector 138. For example, the TIVs 300 are plated on the groove portions 138b of the auxiliary connectors 138. In other words, the TIVs 300 directly contact the auxiliary connectors 138 and are physically and electrically connected to the first bonding structure 130. The method of forming the TIVs 300 will be described in detail below. First, a protective layer (not shown) may be formed to protect the semiconductor die 200. Subsequently, a seed material layer (not shown) is formed on the semiconductor wafer WS. In some embodiments, the seed material layer includes a titanium / copper composite layer and is formed by a sputtering process. Thereafter, a mask pattern (not shown) having an opening is formed on the seed material layer. The opening of the mask pattern exposes the intended position of the subsequently formed TIV 300. For example, the opening of the mask pattern may correspond to the position of the auxiliary connector 138. Afterwards, a plating process is performed to form a metal material layer (e.g., a copper layer) on the seed material layer exposed by the opening of the mask pattern. The mask pattern, the seed material layer not covered by the metal material layer, and the protective layer are then removed by a stripping process and an etching process, thereby forming the TIV 300. However, the present disclosure is not limited thereto. In some alternative embodiments, other suitable methods may be used to form the TIV 300. For example, the prefabricated TIV 300 may be picked up and placed on a semiconductor wafer W.

[0075] In some embodiments, TIV 300 is formed to have a width (critical dimension) W of about 20 μm to about 50 μm. 300 On the other hand, the height H of TIV 300 300 It may be in the range between about 25 μm and about 40 μm. Figure 1D As shown in FIG. 1 , the TIV 300 is formed to have substantially the same height as the semiconductor die 200 , and the rear surface RS2 ′ of the semiconductor die 200 is aligned with the top surface T of the TIV 300 . 300 300 are located at substantially the same level. However, the present disclosure is not limited thereto. In some alternative embodiments, TIV 300 may be shorter or taller than semiconductor die 200. For example, rear surface RS2′ of semiconductor die 200 may be located at a height higher than top surface TIV 300. 300 High or low level.

[0076] It should be noted that although Figure 1B to Figure 1DThe semiconductor die 200 is shown hybrid bonded to the semiconductor wafer W before forming the TIV 300 , however the present disclosure is not limited thereto. In some alternative embodiments, the TIV 300 may be plated on the semiconductor wafer W before the semiconductor die 200 is hybrid bonded to the semiconductor wafer W.

[0077] Reference Figure 1E , a first encapsulant material 400a' is formed on the semiconductor wafer W to encapsulate the semiconductor die 200 and the TIV 300. In some embodiments, the TIV 300 and the semiconductor substrate 210 of the semiconductor die 200 are not exposed and are well protected by the first encapsulant material 400a'. For example, the top surface T of the first encapsulant material 400a' is 400a’ Located at the top surface of TIV 300 300 and the rear surface RS2' of the semiconductor die 200. In some embodiments, the first encapsulant material 400a' includes a molding compound, a molding bottom filler, or the like. Alternatively, the first encapsulant material 400a' may be a polymeric material, such as polyimide, epoxy resin, acrylic resin, phenolic resin, BCB, PBO, or other suitable polymer-based dielectric materials. In some embodiments, the first encapsulant material 400a' may include a filler. Alternatively, the first encapsulant material 400a' may be free of fillers. In some embodiments, the first encapsulant material 400a' may be formed by a molding process (e.g., a compression molding process) or a spin coating process. In some embodiments, after the first encapsulant material 400a' is formed on the semiconductor wafer W, Figure 1E The structure shown in FIG. 1 is flipped, and the rear surface RS1 of the semiconductor wafer W may be thinned to reduce the total thickness of the package to be formed subsequently. In some embodiments, the rear surface RS1 of the semiconductor wafer W may be thinned by a mechanical grinding process, a CMP process, etc. It should be noted that the step of thinning the rear surface RS1 of the semiconductor wafer W may be optional, and therefore, this step is not included in the embodiment. Figure 1E Shown in.

[0078] Reference Figure 1E and Figure 1F , the first encapsulant material 400a', the TIV 300 and the semiconductor die 200 are thinned until both the TIV 300 and the TSV 212 are exposed. In some embodiments, the first encapsulant material 400a', the TIV 300 and the semiconductor die 200 can be thinned by a grinding process (such as a mechanical grinding process, a CMP process, etc.). After grinding the first encapsulant material 400a', a first encapsulant 400a is formed on the semiconductor wafer W to encapsulate the semiconductor die 200 and the TIV 300. Figure 1E and Figure 1F As shown in FIG. 2 , since TSV 212 is embedded in semiconductor substrate 210 of semiconductor die 200, a portion of semiconductor substrate 210 is removed to expose TSV 212. At the same time, a portion of TIV 300 is also removed. After grinding, semiconductor die 200 has a top surface T 300’ , the top surface T of the first encapsulation body 400a 400a and the top surface T of the TSV 212 212 The back surface RS2 is substantially coplanar. In some embodiments, the TSVs 212 penetrate at least a portion of each semiconductor die 200 . For example, the TSVs 212 may penetrate the semiconductor substrate 210 of the semiconductor die 200 .

[0079] like Figure 1F As shown in FIG. 1 , the first encapsulant 400a laterally encapsulates the semiconductor die 200 and the TIV 300. In some embodiments, the TIV 300 penetrates the first encapsulant 400a. In some embodiments, the first dielectric layer 132 of the first bonding structure 130 and the second dielectric layer 232 of the second bonding structure 230 are attached to the first encapsulant 400a. For example, the first dielectric layer 132 and the second dielectric layer 232 directly contact the first encapsulant 400a. In some embodiments, the first encapsulant 400a laterally covers the second dielectric layer 232.

[0080] Reference Figure 1G , a portion of each semiconductor die 200 is removed to form a plurality of recesses R. For example, a portion of the semiconductor substrate 210 is removed to form the recesses R. Figure 1G As shown in FIG. 1 , TSV 212 is partially located in recess R. In some embodiments, at least a portion of each TSV 212 protrudes from semiconductor substrate 210 of semiconductor die 200. That is, a top surface T of TSV 212 212 Located at a level higher than the rear surface RS2'' of the semiconductor die 200. In some embodiments, the semiconductor substrate 210 can be locally removed by an etching process. The etching process includes, for example, an isotropic etching process and / or an anisotropic etching process. For example, the semiconductor substrate 210 can be locally removed by a wet etching process, a dry etching process, or a combination thereof.

[0081] Reference Figure 1H, forming a second encapsulant 400b to fill the groove R. In some embodiments, the second encapsulant 400b includes a molding compound, a molding bottom filler, etc. Alternatively, the second encapsulant 400b may be a polymer material, such as polyimide, epoxy resin, acrylic resin, phenolic resin, BCB, PBO, or other suitable polymer-based dielectric materials. In some embodiments, the second encapsulant 400b may include a filler. Alternatively, the second encapsulant 400b may not contain a filler. In some embodiments, the material of the second encapsulant 400b may be the same as the material of the first encapsulant 400a. However, the present disclosure is not limited to this. In some alternative embodiments, the material of the second encapsulant 400b may be different from the material of the first encapsulant 400a. In some embodiments, the first encapsulant 400a and the second encapsulant 400b may be collectively referred to as an encapsulant 400. As Figure 1H As shown in , the second encapsulant 400b encapsulates the protruding portion of each TSV 212. That is, each TSV 212 is partially surrounded by the encapsulant 400. In some embodiments, the encapsulant 400 covers the sidewalls and the rear surface RS2'' of the semiconductor die 200. In some embodiments, the second encapsulant 400b can be formed by an over-molding process. For example, a second encapsulant material (not shown) can be formed on the first encapsulant 400a and the TIV 300. The second encapsulant material also fills the groove R. Thereafter, the second encapsulant material is thinned until the TIV 300 and the TSV 212 are exposed, thereby forming the second encapsulant 400b. In some embodiments, the second encapsulant material can be thinned by a mechanical grinding process, a CMP process, etc. As Figure 1H As shown in FIG. 4 , the top surface T of the first encapsulation body 400 a 400a 、The top surface T of TIV 300 300’ , the top surface T of the TSV 212 212 and the top surface T of the second encapsulation body 400b 400b Substantially coplanar.

[0082] Reference Fig. 1I , a dielectric layer 500 is formed on the encapsulant 400 and the TIV 300. In some embodiments, the material of the dielectric layer 500 includes polyimide, epoxy resin, acrylic resin, phenolic resin, BCB, PBO or any other suitable polymer dielectric material. The dielectric layer 500 can be formed by a suitable manufacturing technology (such as spin coating, CVD, PECVD, etc.).

[0083] Reference Figure 1J, a plurality of under-ball metallurgy (UBM) patterns 600 and a plurality of conductive terminals 700 are sequentially formed on the first encapsulation 400a, the second encapsulation 400b, the TSV 212 and the TIV 300. In some embodiments, the UBM pattern 600 can be formed by the following steps. First, a plurality of contact openings OP are formed in the dielectric layer 500. The contact openings OP at least expose each TSV 212 and each TIV 300. Then, a seed material layer (not shown) is formed on the dielectric layer 500 and in the contact openings OP. The seed material layer extends into the contact openings OP to directly contact the TSV 212 and the TIV 300. In some embodiments, the seed material layer includes a titanium / copper composite layer and is formed by a sputtering process. Then, a mask pattern (not shown) having an opening is formed on the seed material layer. The opening of the mask pattern exposes the intended position of the UBM pattern 600 to be formed subsequently. For example, the opening of the mask pattern may expose the seed material layer located inside the contact opening OP and the seed material layer located near the contact opening OP. Afterwards, a plating process is performed to form a conductive material layer on the seed material layer exposed by the opening of the mask pattern. In some embodiments, the material of the conductive material layer includes aluminum, titanium, copper, nickel, tungsten and / or alloys thereof. The mask pattern and the underlying seed material layer are then removed by a stripping process and an etching process. The remaining seed material layer and the conductive material layer then constitute the UBM pattern 600.

[0084] In some embodiments, the UBM pattern 600 is connected to the TSV 212 and the TIV 300. Therefore, the UBM pattern 600 can be electrically connected to the semiconductor wafer W through the TIV 300. At the same time, the UBM pattern 600 is also electrically connected to the semiconductor die 200 through the TSV 212. Figure 1J As shown in FIG. 1 , at least one of the TSVs 212 and at least one of the TIVs 300 are simultaneously connected to the same UBM pattern 600. In some embodiments, at least one UBM pattern 600 is connected to a plurality of TSVs 212. By making the UBM pattern 600 fall on a plurality of TSVs 212, the resistance can be substantially reduced, and the heat dissipation of the device during operation can be effectively enhanced. It should be noted that throughout the disclosure, the term “plurality” means “more than one”. In some embodiments, each UBM pattern 600 is formed to have a width W of about 40 μm to about 200 μm. 600 On the other hand, two adjacent UBM patterns 600 may have a pitch ranging between about 100 μm and about 1000 μm.

[0085] In some embodiments, a conductive terminal 700 is disposed on the UBM pattern 600. In some embodiments, the conductive terminal 700 is attached to the UBM pattern 600 by solder. In some embodiments, the conductive terminal 600 is, for example, a solder ball, a ball grid array (BGA) ball, or a controlled collapse chip connection (C4) bump. In some embodiments, the conductive terminal 700 is made of a conductive material having a low resistivity (e.g., Sn, Pb, Ag, Cu, Ni, Bi, or an alloy thereof).

[0086] Reference Figure 1K , a singulation process is performed to form a plurality of packages 10. In some embodiments, a dicing process or a singulation process generally involves dicing with a rotating blade or a laser beam. In other words, the dicing process or the singulation process is, for example, a laser cutting process, a mechanical cutting process, or other suitable process. In some embodiments, during the singulation process, the encapsulation body 400 is cut and the semiconductor wafer W is divided into a plurality of semiconductor dies 100. That is, each semiconductor die 100 includes a semiconductor substrate 110, a first interconnect structure 120 disposed on the semiconductor substrate 110, and a first bonding structure 130 disposed on the first interconnect structure 120. In some embodiments, the semiconductor die 100 may be referred to as a first die of the package 10, and the semiconductor die 200 may be referred to as a second die of the package 10.

[0087] In some embodiments, Figure 1A to Figure 1K The steps shown in the figure can be referred to as "chip on wafer (CoW) level packaging". Figure 1K As shown in FIG. 1 , semiconductor die 200 is stacked on semiconductor die 100. In other words, multiple semiconductor dies 100, 200 are integrated into a single package 10. Therefore, package 10 may be referred to as a "system on integrated circuit (SOIC) package". In some embodiments, by using Figure 1A to Figure 1KAccording to the steps shown in , heterogeneous semiconductor components or homogeneous semiconductor components can be effectively integrated into a single package at a lower cost. For example, a known-good-die (KDG) can be effectively integrated with a semiconductor wafer / semiconductor die at a low cost. In addition, the stacked chip / die size can be flexible. In addition, since the semiconductor die 100 and 200 are stacked on each other, the compactness of the package 10 can be enhanced. On the other hand, since the conductive terminal 700 is electrically connected to the semiconductor die 100 and the semiconductor die 200 through the TIV 300 and the TSV 212, respectively, a short circuit path can be adopted. In other words, the signal transmission performance of the package 10 can be effectively enhanced. In some embodiments, the package 10 can be used in a flip-chip application. That is, the package 10 can be further bonded to a substrate (such as a printed circuit board (PCB)) in a flip-chip manner.

[0088] Figure 2 is a schematic cross-sectional view of a package 20 according to some alternative embodiments of the present disclosure. Figure 2 , package 20 is similar to Figure 1K However, in the package 20, each TIV 300 falls on a plurality of auxiliary connectors 138. That is, the groove portions 138b of the plurality of auxiliary connectors 138 directly contact the same TIV 300.

[0089] In some embodiments, since the semiconductor dies 100 and 200 are stacked on each other, the compactness of the package 20 can be enhanced. In addition, since the conductive terminal 700 is electrically connected to the semiconductor die 100 and the semiconductor die 200 through the TIV 300 and the TSV 212, respectively, a short circuit path can be adopted. In other words, the signal transmission performance of the package 20 can be effectively enhanced. In some embodiments, the package 20 can be used in flip chip applications. In other words, the package 20 can be further bonded to a substrate (such as a PCB, etc.) in a flip chip manner.

[0090] Figure 3 is a schematic cross-sectional view of a package 30 according to some alternative embodiments of the present disclosure. Figure 3 , package 30 is similar to Figure 1K However, in the package 30, each UMB pattern 600 is attached to one TSV 212 and one TIV 300. That is, each UMB pattern 600 directly contacts one of the TSVs 212 and one of the TIVs 300.

[0091] In some embodiments, since the semiconductor dies 100 and 200 are stacked on each other, the compactness of the package 30 can be enhanced. In addition, since the conductive terminal 700 is electrically connected to the semiconductor die 100 and the semiconductor die 200 through the TIV 300 and the TSV 212, respectively, a short circuit path can be adopted. In other words, the signal transmission performance of the package 30 can be effectively enhanced. In some embodiments, the package 30 can be used in flip chip applications. In other words, the package 30 can be further bonded to a substrate (such as a PCB, etc.) in a flip chip manner.

[0092] Figure 4 is a schematic cross-sectional view of a package 40 according to some alternative embodiments of the present disclosure. Figure 4 , package 40 is similar to Figure 1K 10 in the package 40, and therefore, a detailed description thereof is omitted herein. However, in the package 40, each TIV 300 falls on a plurality of auxiliary connectors 138. That is, the groove portions 138b of the plurality of auxiliary connectors 138 directly contact the same TIV 300. In addition, in the package 40, each UBM pattern 600 is attached to one TSV 212 and one TIV 300. That is, each UBM pattern 600 directly contacts one of the TSVs 212 and one of the TIVs 300.

[0093] In some embodiments, since the semiconductor dies 100 and 200 are stacked on each other, the compactness of the package 40 can be enhanced. In addition, since the conductive terminal 700 is electrically connected to the semiconductor die 100 and the semiconductor die 200 through the TIV 300 and the TSV 212, respectively, a short circuit path can be adopted. In other words, the signal transmission performance of the package 40 can be effectively enhanced. In some embodiments, the package 40 can be used in flip chip applications. In other words, the package 40 can be further bonded to a substrate (such as a PCB, etc.) in a flip chip manner.

[0094] According to some embodiments of the present disclosure, a package includes a first tube core, a second tube core, an encapsulation body, and an insulating layer through-hole (TIV). The first tube core has a first bonding structure. The first bonding structure includes a first dielectric layer and a first connector embedded in the first dielectric layer. The second tube core has a second bonding structure. The second bonding structure includes a second dielectric layer and a second connector embedded in the second dielectric layer. The first dielectric layer is hybrid bonded with the second dielectric layer. The first connector is hybrid bonded with the second connector. The encapsulation body laterally encapsulates the second tube core. The insulating layer through-hole penetrates the encapsulation body and is connected to the first bonding structure.

[0095] According to some embodiments of the present disclosure, the first dielectric layer is adhered to the encapsulation body and the second dielectric layer is laterally covered by the encapsulation body.

[0096] According to some embodiments of the present disclosure, each of the first connectors has a through hole portion and a groove portion stacked on the through hole portion, each of the second connectors has a through hole portion and a groove portion stacked on the through hole portion, and the groove portion of the second connector is mixed with the groove portion of the first connector.

[0097] According to some embodiments of the present disclosure, the first bonding structure further includes an auxiliary connector embedded in the first dielectric layer, and the auxiliary connector is attached to the through-hole of the insulating layer.

[0098] According to some embodiments of the present disclosure, the second die further includes a semiconductor through via penetrating at least a portion of the second die.

[0099] According to some embodiments of the present disclosure, the package further comprises an under-ball metal pattern and a conductive terminal. The under-ball metal pattern is disposed on the encapsulation body. The under-ball metal pattern is connected to the insulating layer through-hole and the semiconductor through-hole. The conductive terminal is disposed on the under-ball metal pattern.

[0100] According to some embodiments of the present disclosure, at least one of the semiconductor through vias and at least one of the insulating layer through vias are connected to the same under ball metallization pattern.

[0101] According to some embodiments of the present disclosure, a plurality of the semiconductor through vias are connected to the same under ball metal pattern.

[0102] According to some alternative embodiments of the present disclosure, the package includes a first tube core, a second tube core and an encapsulant. The first tube core includes a first pad, a first connector and a first dielectric layer. The first connector is located on the first pad. The first dielectric layer encapsulates the first pad and the first connector. The second tube core includes a second pad, a second connector and a second dielectric layer. The second connector is located on the second pad and is in direct contact with the first connector. The second dielectric layer encapsulates the second pad and the second connector. The second dielectric layer is in direct contact with the first dielectric layer. The encapsulant laterally encapsulates the second tube core. The encapsulant is in direct contact with the first dielectric layer.

[0103] According to some alternative embodiments of the present disclosure, the first tube core further includes a first semiconductor substrate, a first interconnect structure and an auxiliary connector. The first interconnect structure is sandwiched between the first pad and the first semiconductor substrate. The auxiliary connector is embedded in the first dielectric layer. The auxiliary connector is electrically connected to the first interconnect structure.

[0104] According to some alternative embodiments of the present disclosure, the package further includes an insulating layer through-hole penetrating the encapsulation body, and the insulating layer through-hole is in direct contact with the auxiliary connector.

[0105] According to some alternative embodiments of the present disclosure, a plurality of the auxiliary connectors directly contact the same insulating layer through-hole.

[0106] According to some alternative embodiments of the present disclosure, the second die further includes a second semiconductor substrate, a second interconnect structure, and a semiconductor through-hole. The second interconnect structure is sandwiched between the second pad and the second semiconductor substrate. The semiconductor through-hole penetrates the second semiconductor substrate.

[0107] According to some alternative embodiments of the present disclosure, each of the semiconductor through-vias is partially surrounded by the encapsulation body.

[0108] According to some alternative embodiments of the present disclosure, the package further comprises an under-ball metal pattern and a conductive terminal. The under-ball metal pattern is disposed on the encapsulation body and is connected to the insulating layer through-hole and the semiconductor through-hole. The conductive terminal is disposed on the under-ball metal pattern.

[0109] According to some alternative embodiments of the present disclosure, a plurality of the semiconductor through vias are connected to the same under ball metal pattern.

[0110] According to some embodiments of the present disclosure, a method for manufacturing a package includes at least the following steps. A semiconductor wafer having a first bonding structure formed thereon is provided. A semiconductor die is bonded to the semiconductor wafer. Each of the semiconductor dies has a second bonding structure formed thereon and a semiconductor through-hole (TSV) formed therein. The first bonding structure is bonded to the second bonding structure. A through-insulation layer via (TIV) is formed to surround the semiconductor die. A first encapsulant is used to encapsulate the semiconductor die and the insulating layer through-hole. A portion of each of the semiconductor die is removed to form a groove. A second encapsulant is filled into the groove. An under-ball metal pattern and a conductive terminal are formed on the first encapsulant and the second encapsulant. The under-ball metal pattern is connected to the insulating layer through-hole and the semiconductor through-hole.

[0111] According to some embodiments of the present disclosure, the semiconductor die is bonded to the semiconductor wafer by a hybrid bonding process, and a temperature of the hybrid bonding process ranges from about 150°C to about 400°C.

[0112] According to some embodiments of the present disclosure, the portion of each of the semiconductor dies is removed such that at least a portion of each of the semiconductor through-vias protrudes from the semiconductor die.

[0113] According to some embodiments of the present disclosure, encapsulating the semiconductor die and the insulating layer through-holes comprises at least the following steps: forming a first encapsulant material on the semiconductor wafer to encapsulate the semiconductor die and the insulating layer through-holes; and thinning the first encapsulant material and the semiconductor die until the insulating layer through-holes and the semiconductor through-holes are exposed.

[0114] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A package comprising: A first tube core having a first bonding structure, wherein the first bonding structure includes a first dielectric layer and a first connector embedded in the first dielectric layer; A second tube core, having a semiconductor substrate and a second bonding structure located on the semiconductor substrate, wherein the second bonding structure includes a second dielectric layer and a second connector embedded in the second dielectric layer, a sidewall of the second dielectric layer is aligned with a sidewall of the semiconductor substrate, the first dielectric layer is hybrid bonded with the second dielectric layer, and the first connector is hybrid bonded with the second connector; An encapsulation body, laterally encapsulating the second tube core; as well as The insulating layer is perforated to penetrate the encapsulation body, wherein the insulating layer perforation is connected to the first bonding structure. 2 . The package of claim 1 , wherein the first dielectric layer is attached to the encapsulation and the second dielectric layer is laterally covered by the encapsulation.

3. The package according to claim 1, wherein each of the first connectors has a through-hole portion and a groove portion stacked on the through-hole portion, each of the second connectors has a through-hole portion and a groove portion stacked on the through-hole portion, and the groove portion of the second connector is mixedly joined with the groove portion of the first connector. 4 . The package according to claim 1 , wherein the first bonding structure further comprises an auxiliary connector embedded in the first dielectric layer, and the auxiliary connector is attached to the insulating layer through-hole. 5 . The package of claim 1 , wherein the second die further comprises a semiconductor through via penetrating at least a portion of the second die.

6. The package according to claim 5, further comprising: an under-ball metal pattern, disposed on the package, wherein the under-ball metal pattern is connected to the insulating layer through-hole and the semiconductor through-hole; as well as The conductive terminal is arranged on the under-ball metal pattern. 7 . The package of claim 6 , wherein at least one of the semiconductor through vias and at least one of the insulating layer through vias are connected to the same under ball metallization pattern. 8 . The package of claim 6 , wherein a plurality of the semiconductor through vias are connected to the same under ball metal pattern.

9. A package comprising: The first die comprises: a first semiconductor substrate; A first pad, located on the first semiconductor substrate; A first connecting member, located on the first pad; and A first dielectric layer encapsulating the first pad and the first connecting member; The second die comprises: a second semiconductor substrate; a second pad, located on the second semiconductor substrate; a second connecting member, located on the second pad, wherein the second connecting member is in direct contact with the first connecting member; and a second dielectric layer encapsulating the second pad and the second connector, wherein the second dielectric layer is in direct contact with the first dielectric layer, and a sidewall of the second dielectric layer is aligned with a sidewall of the second semiconductor substrate; and An encapsulant laterally encapsulates the second die, wherein the encapsulant is in direct contact with the first dielectric layer.

10. The package of claim 9, wherein the first die further comprises: A first interconnect structure, sandwiched between the first pad and the first semiconductor substrate; as well as An auxiliary connector is embedded in the first dielectric layer, wherein the auxiliary connector is electrically connected to the first interconnect structure. 11 . The package according to claim 10 , further comprising an insulation layer through-hole penetrating the encapsulation body, wherein the insulation layer through-hole is in direct contact with the auxiliary connector. 12 . The package of claim 11 , wherein a plurality of the auxiliary connectors directly contact the same insulating layer through-hole.

13. The package of claim 11 , wherein the second die further comprises: A second interconnect structure, sandwiched between the second pad and the second semiconductor substrate; as well as The semiconductor through hole penetrates the second semiconductor substrate. The package of claim 13 , wherein each of the semiconductor through-vias is partially surrounded by the encapsulation body.

15. The package of claim 13, further comprising: an under-ball metal pattern, disposed on the package, wherein the under-ball metal pattern is connected to the insulating layer through-hole and the semiconductor through-hole; as well as The conductive terminal is arranged on the under-ball metal pattern. 16 . The package of claim 15 , wherein a plurality of the semiconductor through vias are connected to the same under ball metal pattern.

17. A method for manufacturing a package, comprising: providing a semiconductor wafer having a first bonding structure formed thereon, wherein the first bonding structure comprises a first dielectric layer and a first connector embedded in the first dielectric layer; Bonding semiconductor dies to the semiconductor wafer, wherein each of the semiconductor dies has a semiconductor substrate and a second bonding structure formed on the semiconductor substrate and a semiconductor through via formed in the semiconductor substrate, the second bonding structure comprising a second dielectric layer and a second connector embedded in the second dielectric layer, a sidewall of the second dielectric layer is aligned with a sidewall of the semiconductor substrate, and the first bonding structure is bonded to the second bonding structure; forming an insulating layer through-hole to surround the semiconductor die; Encapsulating the semiconductor die and the insulating layer through-hole using a first encapsulation body; removing a portion of each of the semiconductor dies to form a recess; Filling the second encapsulation body into the groove; as well as An under ball metallization pattern and a conductive terminal are formed on the first encapsulation body and the second encapsulation body, wherein the under ball metallization pattern is connected to the insulating layer through hole and the semiconductor through hole.

18. The method for manufacturing a package according to claim 17, wherein the semiconductor die is bonded to the semiconductor wafer by a hybrid bonding process, and a temperature of the hybrid bonding process is in a range from 150°C to 400°C. 19 . The method of manufacturing a package according to claim 17 , wherein the portion of each of the semiconductor dies is removed such that at least a portion of each of the semiconductor through-vias protrudes from the semiconductor die.

20. The method for manufacturing a package according to claim 17, wherein encapsulating the semiconductor die and perforating the insulating layer comprises: forming a first encapsulant material on the semiconductor wafer to encapsulate the semiconductor die and the insulating layer through-hole; as well as The first encapsulant material and the semiconductor die are thinned until the insulating layer through-hole and the semiconductor through-hole are exposed.

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