A high-power IGBT drive control circuit and method

Abstract

The present invention discloses a high-power IGBT drive control circuit and method, wherein the circuit includes: a PWM input module for receiving a PWM input signal and an enable signal, and outputting a clamping voltage to a drive amplifier module; a power output module including a P-channel field effect transistor and an N-channel field effect transistor; a drive amplifier module including a PMOS drive circuit and an NMOS drive circuit for controlling the P-channel field effect transistor and the N-channel field effect transistor to switch working states in an orderly manner. The present invention controls two power tubes, the P-channel field effect transistor and the N-channel field effect transistor, through a timing control scheme, that is, it fully utilizes the strong drive output current capability of the field effect transistor MOSFET drain output amplifier, and at the same time solves the problem of current through-phenomenon generated by the MOS tube drain output complementary amplifier, and can be widely used in the field of semiconductor technology.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a high-power IGBT drive control circuit and method. Background Art

[0002] Existing patents (such as patent numbers CN202020318822.5, CN202020365413.0, etc.) describe IGBT drive application circuits and various protections, but these technologies can only drive small and medium-power IGBTs and intelligent power modules. They cannot normally drive ultra-high voltage and ultra-high current 6500V / 750A IGBTs (model FZ750R65KE3T) from Germany's Infineon (Cies can reach 205nF, gate charge Qg reaches 31uC).

[0003] Terminology explanation:

[0004] IGBT: Insulated Gate Bipolar Transistor, is a composite fully controlled voltage-driven power semiconductor device composed of BJT (bipolar junction transistor) and MOS (insulated gate field effect transistor). It has the advantages of both MOSFET's high input impedance and GTR's low on-state voltage drop. Summary of the invention

[0005] In order to solve one of the technical problems existing in the prior art to at least a certain extent, an object of the present invention is to provide a high-power IGBT drive control circuit and method.

[0006] The technical solution adopted by the present invention is:

[0007] A high-power IGBT drive control circuit, comprising:

[0008] A PWM input module is used to receive a PWM input signal and an enable signal, and output a clamping voltage to a drive amplifier module;

[0009] A power output module, including a P-channel field effect transistor and an N-channel field effect transistor;

[0010] A driving amplifier module, including a PMOS driving circuit and an NMOS driving circuit, for controlling the P-channel field effect transistor and the N-channel field effect transistor to switch working states in an orderly manner;

[0011] Among them, when the PWM input module receives a high level, the N-channel field effect tube is first turned off and then the P-channel field effect tube is turned on; when the PWM input module receives a low level, the P-channel field effect tube is first turned off and then the N-channel field effect tube is turned on.

[0012] Further, the PWM input module includes a first resistor, a second resistor, a sixth resistor, a seventh resistor, a first Darlington inverting amplifier, a second Darlington inverting amplifier, a third Darlington inverting amplifier, and a fourth Darlington inverting amplifier;

[0013] One end of the first resistor is connected to the PWM signal input end, the other end of the first resistor is respectively connected to the input end of the first Darlington inverting amplifier and one end of the seventh resistor, the output end of the first Darlington inverting amplifier is connected to one end of the sixth resistor, the other end of the sixth resistor is connected to the input end of the second Darlington inverting amplifier, the output end of the second Darlington inverting amplifier is connected to the input end of the fourth Darlington inverting amplifier, the output end of the fourth Darlington inverting amplifier is connected to one end of the second resistor, and the other end of the second resistor is connected to the NMOS driving circuit;

[0014] The other end of the seventh resistor is connected to the input end of the third Darlington inverting amplifier, and the output end of the third Darlington inverting amplifier is connected to the PMOS driving circuit.

[0015] Further, the PWM input module also includes a first diode and a second diode;

[0016] The first diode is connected in parallel with the sixth resistor, and the second diode is connected in parallel with the seventh resistor.

[0017] Further, the PMOS driving circuit includes a first bipolar transistor, a second bipolar transistor, a first zener diode and a sixth capacitor;

[0018] The base of the first bipolar transistor and the base of the second bipolar transistor are both connected to the output end of the third Darlington inverting amplifier, the collector of the first bipolar transistor is connected to a first voltage, the emitter of the first bipolar transistor is connected to the emitter of the second bipolar transistor, the collector of the second bipolar transistor is grounded, the emitter of the first bipolar transistor is connected to the anode of the first Zener diode, the cathode of the first Zener diode is connected to the gate of the P-channel field effect transistor, and the sixth capacitor is connected in parallel with the first Zener diode.

[0019] Further, the NMOS driving circuit includes a third bipolar transistor, a fourth bipolar transistor, a second zener diode, a third zener diode, a third diode and a seventh capacitor;

[0020] The base of the third bipolar transistor and the base of the fourth bipolar transistor are both connected to the other end of the second resistor, the collector of the third bipolar transistor is connected to the first voltage, the emitter of the third bipolar transistor is connected to the emitter of the fourth bipolar transistor, the collector of the fourth bipolar transistor is grounded, the emitter of the third bipolar transistor is connected to the cathode of the second Zener diode, the anode of the second Zener diode is respectively connected to the gate of the N-channel field effect transistor and the cathode of the third Zener diode, the anode of the third Zener diode is connected to the anode of the third diode, the cathode of the third diode is connected to the second voltage, and the seventh capacitor is connected in parallel with the second Zener diode.

[0021] Further, the drain of the P-channel field effect transistor is connected to a first voltage, the source of the P-channel field effect transistor is connected to the drain of the N-channel field effect transistor, and the source of the N-channel field effect transistor is connected to a second voltage.

[0022] Another technical solution adopted by the present invention is:

[0023] A control method, applied to a high-power IGBT drive control circuit as described above, comprises the following steps:

[0024] Obtaining a PWM input signal, and obtaining a clamping voltage according to the PWM input signal;

[0025] The driving amplifier module controls the P-channel field effect transistor and the N-channel field effect transistor to switch working states in an orderly manner according to the clamping voltage;

[0026] Among them, when the PWM input module receives a high level, the N-channel field effect tube is first turned off and then the P-channel field effect tube is turned on; when the PWM input module receives a low level, the P-channel field effect tube is first turned off and then the N-channel field effect tube is turned on.

[0027] The beneficial effect of the present invention is that the present invention controls two power tubes, a P-channel field effect tube and an N-channel field effect tube, through a timing control scheme, that is, the strong driving output current capability of the field effect tube MOSFET drain output amplifier is fully utilized, and at the same time, the problem of current through-phenomenon generated by the MOS tube drain output complementary amplifier is solved. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the embodiments of the present invention or the drawings of related technical solutions in the prior art are introduced below. It should be understood that the drawings introduced below are only for the convenience of clearly describing some embodiments of the technical solutions of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0029] Figure 1 It is an electronic circuit diagram of a high-power IGBT drive control circuit in an embodiment of the present invention;

[0030] Figure 2 It is a simulation circuit diagram of a high-power IGBT drive control circuit in an embodiment of the present invention;

[0031] Figure 3 It is a simulation result diagram of a high-power IGBT drive control circuit in an embodiment of the present invention. DETAILED DESCRIPTION

[0032] The embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and are not to be construed as limitations of the present invention. For the step numbers in the following embodiments, they are only provided for the convenience of explanation, and the order between the steps is not limited in any way, and the execution order of each step in the embodiment can be adaptively adjusted according to the understanding of those skilled in the art.

[0033] In the description of the present invention, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., and orientations or positional relationships indicated are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0034] In the description of the present invention, "several" means one or more, "more" means more than two, "greater than", "less than", "exceed" etc. are understood as not including the number itself, and "above", "below", "within" etc. are understood as including the number itself. If there is a description of "first" or "second", it is only used for the purpose of distinguishing the technical features, and cannot be understood as indicating or implying the relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0035] In the description of the present invention, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in the present invention based on the specific content of the technical solution.

[0036] like Figure 1 As shown, the present invention provides a high-power IGBT drive control circuit, including:

[0037] A PWM input module is used to receive a PWM input signal and an enable signal, and output a clamping voltage to a drive amplifier module;

[0038] A power output module, including a P-channel field effect transistor TP and an N-channel field effect transistor TN;

[0039] The driving amplifier module includes a PMOS driving circuit and an NMOS driving circuit, which are used to control the P-channel field effect transistor TP and the N-channel field effect transistor TN to switch working states in an orderly manner;

[0040] Among them, when the PWM input module receives a high level, the N-channel field effect transistor TN is first turned off and then the P-channel field effect transistor TP is turned on; when the PWM input module receives a low level, the P-channel field effect transistor TP is first turned off and then the N-channel field effect transistor TN is turned on.

[0041] See also Figure 1 , further as an optional implementation, the PWM input module includes a first resistor R1, a second resistor R2, a sixth resistor R6, a seventh resistor R7, a first Darlington inverting amplifier IC1_1, a second Darlington inverting amplifier IC1_2, a third Darlington inverting amplifier IC1_3, and a fourth Darlington inverting amplifier IC1_4;

[0042] One end of the first resistor R1 is connected to the PWM signal input end, the other end of the first resistor R1 is respectively connected to the input end of the first Darlington inverting amplifier IC1_1 and one end of the seventh resistor R7, the output end of the first Darlington inverting amplifier IC1_1 is connected to one end of the sixth resistor R6, the other end of the sixth resistor R6 is connected to the input end of the second Darlington inverting amplifier IC1_2, the output end of the second Darlington inverting amplifier IC1_2 is connected to the input end of the fourth Darlington inverting amplifier IC1_4, the output end of the fourth Darlington inverting amplifier IC1_4 is connected to one end of the second resistor R2, and the other end of the second resistor R2 is connected to the NMOS drive circuit;

[0043] The other end of the seventh resistor R7 is connected to the input end of the third Darlington inverting amplifier IC1_3 , and the output end of the third Darlington inverting amplifier IC1_3 is connected to the PMOS driving circuit.

[0044] Among them, the model of the Darlington inverting amplifier is ULN2003, and the working logic is simple, that is, the output and input are in opposite relationship, such as if the input is high level, the output is low level; if the input is low level, the output is high level.

[0045] See also Figure 1 , further as an optional implementation, the PWM input module further includes a first diode D1 and a second diode D2;

[0046] The first diode D1 is connected in parallel with the sixth resistor R6 , and the second diode D2 is connected in parallel with the seventh resistor R7 .

[0047] Further as an optional implementation, the PMOS driving circuit includes a first bipolar transistor T1, a second bipolar transistor T2, a first voltage zener diode D4 and a sixth capacitor C6;

[0048] The base of the first bipolar transistor T1 and the base of the second bipolar transistor T2 are both connected to the output end of the third Darlington inverting amplifier IC1_3, the collector of the first bipolar transistor T1 is connected to the first voltage, the emitter of the first bipolar transistor T1 is connected to the emitter of the second bipolar transistor T2, the collector of the second bipolar transistor T2 is grounded, the emitter of the first bipolar transistor T1 is connected to the anode of the first zener diode D4, the cathode of the first zener diode D4 is connected to the gate of the P-channel field effect transistor TP, and the sixth capacitor C6 is connected in parallel with the first zener diode D4.

[0049] See also Figure 1 , further as an optional implementation, the NMOS driving circuit includes a third bipolar transistor T3, a fourth bipolar transistor T4, a second zener diode D3, a third zener diode D6, a third diode D5 and a seventh capacitor C7;

[0050] The base of the third bipolar transistor T3 and the base of the fourth bipolar transistor T4 are both connected to the other end of the second resistor R2, the collector of the third bipolar transistor T3 is connected to the first voltage, the emitter of the third bipolar transistor T3 is connected to the emitter of the fourth bipolar transistor T4, the collector of the fourth bipolar transistor T4 is grounded, the emitter of the third bipolar transistor T3 is connected to the cathode of the second Zener diode D3, the anode of the second Zener diode D3 is respectively connected to the gate of the N-channel field effect transistor TN and the cathode of the third Zener diode D6, the anode of the third Zener diode D6 is connected to the anode of the third diode D5, the cathode of the third diode D5 is connected to the second voltage, and the seventh capacitor C7 is connected in parallel with the second Zener diode D3.

[0051] See also Figure 1, further as an optional implementation, the drain of the P-channel field effect transistor TP is connected to the first voltage, the source of the P-channel field effect transistor TP is connected to the drain of the N-channel field effect transistor TN, and the source of the N-channel field effect transistor TN is connected to the second voltage.

[0052] The above circuit is explained in detail below.

[0053] The high-performance ultra-high-power IGBT drive application circuit of this embodiment includes three parts: a PWM input part, a drive amplifier part and a power drive output part.

[0054] (1) Input part

[0055] The input part includes resistors R25, R6, R7, diodes D1, D2 and Darlington inverter amplifiers IC1_1, IC1_2, IC1_3, IC1_4. This part receives PWM signal input. EN is the enable terminal, and EN receives PWM signal transmission when it is at a high level. The input signals of R6 and R7 are connected in series with the resistors, and are matched with the input of IC1_1~IC1_4 logic CMOS inverters. D1 and D2 are accelerated discharge diodes, which can improve the shutdown response speed of the driver.

[0056] (2) Intermediate drive amplifier

[0057] This part is the core part, which adopts the power amplifier of N-channel and P-channel MOSFET complementary combination. In order to avoid the current direct-through phenomenon caused by the MOS tube drain output complementary amplifier, the shutdown and opening timing control scheme is adopted, that is, when the PWM signal input is high level, the lower tube (N-channel field effect transistor) is turned off first and then the upper tube (P-channel field effect transistor) is turned on; when the PWM signal input is low level, the upper tube is turned off first and then the lower tube is turned on.

[0058] When the input PWM signal turns to a high level, a low level (such as 0) is obtained at the output point P of IC1_4 through inverters IC1_1, IC1_2 and IC1_4. The potential of point A will be further pulled down to a negative level by resistor R23 at this time. This potential is set to Va. At the same time, when the PWM input signal is low, C7 has been charged to a high level at the previous moment. When the input PWM signal is high, the signal is inverted, so C7 is discharged at this moment. Therefore, the potential of point B continues to decrease until the potential of point B is lower than that of point C. At this time, the voltage regulator D3 switches from the original reverse breakdown state to the forward conduction state, so the potential of point B is Vee (negative voltage , you can choose -9V) to a negative level, that is, when the driving input PWM signal is at a high level, the potential at point B must be lower than the potential at point A, that is, Va>Vb, so at this time the transistor T3 is turned on and T4 is turned off, and at the same time the potential at point B is pulled to a certain negative level by Vee, diode D5 and voltage regulator D4, but it will be pulled higher by the potentials of D4 and D5 (that is, the potential is definitely higher than Vee). At this time, the potential at point C is higher than the potential at point B by the tube voltage drop of D3. At this time, the lower tube TN is turned on because Vgs>0, so when the upper tube TP is turned on, the lower tube TN will be turned off first.

[0059] When the driving input PWM signal is high level, the output of point F is low level 0, and the potential of point A will be further pulled down to negative level by resistor R23. At the same time, by comparing the potential of point H, we know that when the PWM input signal is low level, that is, C6 has been charged to high level at the previous moment. Therefore, at the moment when the input PWM signal switches to high level, the potential of point H is still higher than that of point F. Therefore, at this time, transistor T1 is cut off and T2 is turned on. At the same time, point H will be pulled up to a certain potential by T2 (but still in a low level state). At this time, C6 will continue to discharge until the anode potential of Zener tube D4 is lower than the cathode potential (that is, the potential of point H < the potential of point I). At this time, Zener tube D4 works in the reverse breakdown state, and the potential of point I will raise the potential of D4 by a voltage regulation value based on the potential of point H. Proper selection of the voltage regulation value of Zener tube D4 can still make TP tube Vgs < 0 (that is, TP tube gate potential Vi < Vo), and the corresponding upper tube TP-MOSFET is turned on.

[0060] Therefore, the PWM signal is driven and amplified at point F after being matched by R7 and IC1_3 Darlington inverting amplifier. At this time, transistor T1 is turned off and T2 is turned on. T2 pulls the H voltage to a low level. At this time, the voltage at point I is appropriately increased through the voltage regulator D4. At this time, since the lower tube TN is turned off and the upper tube TP has not yet been turned on, the Vo output is high at this time, which meets the turning-on condition of the upper tube TP. At this time, the upper tube TP is normally driven to the output Vcc positive level, so that the TP is turned on and the output is pulled to the Vcc level, thereby driving the IGBT output. When the driving input PWM signal is high, the output point I potential (i.e., the TP tube gate potential) is pulled down to a negative level by the negative level Vee and TN-MOSFET tube at the previous moment because the lower tube TN-MOSFET is turned on at the previous low level moment. When the input PWM signal is high, the lower tube TN is turned off and the upper tube TP is not turned on yet. Therefore, the upper tube TP tube is now in a floating state, and the floating level is blocked at this time because the pull-down path is blocked. Therefore, the TP tube source potential G point potential can only be charged to Vcc through Vcc pull-up. When the driving input PWM signal is high, the output point I potential (i.e., the TP tube gate potential) is only raised to a certain positive level (but definitely less than the positive power supply Vcc potential) by T2 and the voltage regulator tube D4 on the basis of 0 potential. Therefore, at this time, the TP tube gate potential I is lower than Source potential G, so at this time the TP tube is turned on, and the output Vo is pulled to the positive power supply Vcc. Therefore, it can be seen that there is timing control when the upper tube is turned on. The lower tube TN tube must be turned off first to block the path of the lower tube to prevent the TP tube source potential from being pulled low when the input signal is high. At this time, the upper tube TP-source potential point G can be pulled to a low level, so that when the input signal is high, the upper tube TP is turned on by controlling the transistors T1, T2, C2 and the voltage regulator D4. Similarly, the principle of turning on the lower tube TN is the same as the principle of turning on TP. It is necessary to turn off the upper tube TP first and cut off the upper tube TP path so that the TN source can only be pulled down, so that its TN source potential is pulled down to Vee. By controlling the transistors T4, T5, the voltage regulator D3, the capacitor C7, etc., the TN source potential is less than the lower tube TN-gate C potential, thereby turning on the lower tube TN.

[0061] Among them, resistor R8 is the pull-up resistor of the positive power supply of the upper tube, R10 is the pull-down resistor of the negative power supply of the lower tube TN, and C6 is an acceleration capacitor, which plays the role of adjusting the opening speed of the upper tube TP charging express and accelerating the charging.

[0062] Similarly, before turning off the output low level, the upper tube is turned off first and then the lower tube is turned on. For example, when the input PWM signal turns into a low level, the IC1_3 inverter is first turned into a high level through the PWM signal at a low level. At this time, the transistor T1 is turned on and T2 is turned off. T1 works in the amplification state and pulls the H voltage to a high level. To ensure that the upper tube is turned off reliably, the voltage at point H is raised to the point where the TP tube cannot be turned on through the voltage regulator D4. At this time, the upper tube PMOSFET is turned off first when the output is low level, and then the lower tube NMOSFET is turned on. The PWM signal is matched by R25, R6 and IC1_2 and IC1_4 Darlington inverting amplifiers and then driven and amplified at point A. At this time, the transistor T3 is turned on and T4 is turned off. T3 pulls the B voltage to a negative level. At this time, the voltage at point B is appropriately increased through the voltage regulator D3 to meet the opening conditions of the lower tube TN. The TN conduction output is pulled to the negative level of Vee. At this time, the drive output is normally turned off, thereby turning off the input PWM signal. Capacitor C7 is an accelerating capacitor, which plays the role of regulating the turn-off speed of the lower tube TN discharge and improving the dynamic performance of the driving circuit.

[0063] (3) Power drive output part

[0064] This part is mainly composed of the power drive output circuit composed of the upper tube TP and the lower tube TN. The power amplifier in the IGBT driver generally has an emitter follower composed of NPN and PNP tubes and a MOSFET field effect tube drain output amplifier. Although the former has a relatively simple circuit, it often has limited output capacity. This embodiment adopts the latter to achieve a greater output capacity.

[0065] Figure 2 Saber simulation application circuit for the above drive control circuit, Figure 3 1 and 2 are output voltage and current waveforms of the drive control circuit of this embodiment when simulating an IGBT load (simulating a load of CL=200nF and CL=500nF).

[0066] In summary, the drive control circuit of this embodiment has the following beneficial effects compared with the prior art:

[0067] (1) Provides an IGBT drive application circuit with ultra-high power and current currently on the market. The designed drive application circuit can drive an output current of up to 30A and an output total charge of up to 35uC, which can fully meet the driving requirements of the highest power IGBT currently on the market.

[0068] (2) A power amplifier using a complementary combination of N-channel and P-channel MOSFETs is used. To avoid the current direct-through phenomenon caused by the MOS tube drain output complementary amplifier, a shutdown and opening timing control scheme is adopted. That is, before turning on the high-level output, the lower tube is turned off first and then the upper tube is turned on; before turning off the negative-level output, the upper tube is turned off first and then the lower tube is turned on. Therefore, the performance is superior and the reliability is high.

[0069] This embodiment also provides a control method, which is applied to the high-power IGBT drive control circuit as described above, and includes the following steps:

[0070] S1, obtain PWM input signal, and obtain clamping voltage according to the PWM input signal;

[0071] S2, the driving amplifier module controls the P-channel field effect transistor and the N-channel field effect transistor to switch the working state in an orderly manner according to the clamping voltage;

[0072] Among them, when the PWM input module receives a high level, the N-channel field effect tube is first turned off and then the P-channel field effect tube is turned on; when the PWM input module receives a low level, the P-channel field effect tube is first turned off and then the N-channel field effect tube is turned on.

[0073] The control method of this embodiment has a corresponding relationship with the drive control circuit of the above-mentioned embodiment, and therefore has corresponding functions and beneficial effects.

[0074] In some selectable embodiments, the function / operation mentioned in the block diagram may not occur in the order mentioned in the operation diagram. For example, depending on the function / operation involved, the two boxes shown in succession can actually be executed substantially simultaneously or the boxes can sometimes be executed in reverse order. In addition, the embodiment presented and described in the flow chart of the present invention is provided by way of example, for the purpose of providing a more comprehensive understanding of technology. The disclosed method is not limited to the operation and logic flow presented herein. Selectable embodiments are expected, wherein the order of various operations is changed and the sub-operation of a part for which is described as a larger operation is performed independently.

[0075] In addition, although the present invention is described in the context of functional modules, it should be understood that, unless otherwise specified, one or more of the functions and / or features described may be integrated into a single physical device and / or software module, or one or more functions and / or features may be implemented in separate physical devices or software modules. It is also understood that a detailed discussion of the actual implementation of each module is unnecessary for understanding the present invention. More specifically, in view of the properties, functions, and internal relationships of the various functional modules in the device disclosed herein, the actual implementation of the module will be understood within the conventional skills of the engineer. Therefore, those skilled in the art can implement the present invention set forth in the claims without excessive experimentation using ordinary techniques. It is also understood that the specific concepts disclosed are merely illustrative and are not intended to limit the scope of the present invention, which is determined by the full scope of the appended claims and their equivalents.

[0076] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc., which can store program codes.

[0077] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in conjunction with such instruction execution systems, devices or apparatuses. For the purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in conjunction with such instruction execution systems, devices or apparatuses.

[0078] More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or more wires (electronic device), a portable computer disk case (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be a paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, deciphering or, if necessary, processing in another suitable manner, and then stored in a computer memory.

[0079] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0080] In the above description of this specification, the description with reference to the terms "one embodiment / example", "another embodiment / example" or "certain embodiments / examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0081] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

[0082] The above is a specific description of the preferred implementation of the present invention, but the present invention is not limited to the above embodiments. Those skilled in the art may make various equivalent modifications or substitutions without violating the spirit of the present invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of this application.

Claims

1. A high-power IGBT drive control circuit, characterized in that: include: A PWM input module is used to receive a PWM input signal and an enable signal, and output a clamping voltage to a drive amplifier module; A power output module, including a P-channel field effect transistor and an N-channel field effect transistor; A driving amplifier module, including a PMOS driving circuit and an NMOS driving circuit, for controlling the P-channel field effect transistor and the N-channel field effect transistor to switch working states in an orderly manner; When the PWM input module receives a high level, the N-channel field effect tube is first turned off, and then the P-channel field effect tube is turned on; when the PWM input module receives a low level, the P-channel field effect tube is first turned off, and then the N-channel field effect tube is turned on; The PWM input module includes a first resistor, a second resistor, a sixth resistor, a seventh resistor, a first Darlington inverting amplifier, a second Darlington inverting amplifier, a third Darlington inverting amplifier, and a fourth Darlington inverting amplifier; One end of the first resistor is connected to the PWM signal input end, the other end of the first resistor is respectively connected to the input end of the first Darlington inverting amplifier and one end of the seventh resistor, the output end of the first Darlington inverting amplifier is connected to one end of the sixth resistor, the other end of the sixth resistor is connected to the input end of the second Darlington inverting amplifier, the output end of the second Darlington inverting amplifier is connected to the input end of the fourth Darlington inverting amplifier, the output end of the fourth Darlington inverting amplifier is connected to one end of the second resistor, and the other end of the second resistor is connected to the NMOS driving circuit; The other end of the seventh resistor is connected to the input end of the third Darlington inverting amplifier, and the output end of the third Darlington inverting amplifier is connected to the PMOS driving circuit; Among them, the model of the Darlington inverting amplifier is ULN2003.

2. A high-power IGBT drive control circuit according to claim 1, characterized in that: The PWM input module also includes a first diode and a second diode; The first diode is connected in parallel with the sixth resistor, and the second diode is connected in parallel with the seventh resistor.

3. A high-power IGBT drive control circuit according to claim 1, characterized in that: The PMOS driving circuit includes a first bipolar transistor, a second bipolar transistor, a first voltage stabilizing diode and a sixth capacitor; The base of the first bipolar transistor and the base of the second bipolar transistor are both connected to the output end of the third Darlington inverting amplifier, the collector of the first bipolar transistor is connected to a first voltage, the emitter of the first bipolar transistor is connected to the emitter of the second bipolar transistor, the collector of the second bipolar transistor is grounded, the emitter of the first bipolar transistor is connected to the anode of the first Zener diode, the cathode of the first Zener diode is connected to the gate of the P-channel field effect transistor, and the sixth capacitor is connected in parallel with the first Zener diode.

4. A high-power IGBT drive control circuit according to claim 1, characterized in that: The NMOS driving circuit includes a third bipolar transistor, a fourth bipolar transistor, a second zener diode, a third zener diode, a third diode and a seventh capacitor; The base of the third bipolar transistor and the base of the fourth bipolar transistor are both connected to the other end of the second resistor, the collector of the third bipolar transistor is connected to the first voltage, the emitter of the third bipolar transistor is connected to the emitter of the fourth bipolar transistor, the collector of the fourth bipolar transistor is grounded, the emitter of the third bipolar transistor is connected to the cathode of the second Zener diode, the anode of the second Zener diode is respectively connected to the gate of the N-channel field effect transistor and the cathode of the third Zener diode, the anode of the third Zener diode is connected to the anode of the third diode, the cathode of the third diode is connected to the second voltage, and the seventh capacitor is connected in parallel with the second Zener diode.

5. A high-power IGBT drive control circuit according to claim 3, characterized in that: The drain of the P-channel field effect transistor is connected to a first voltage, the source of the P-channel field effect transistor is connected to the drain of the N-channel field effect transistor, and the source of the N-channel field effect transistor is connected to a second voltage.

6. A control method, applied to a high-power IGBT drive control circuit as claimed in any one of claims 1 to 5, characterized in that: The following steps are involved: Obtaining a PWM input signal, and obtaining a clamping voltage according to the PWM input signal; The driving amplifier module controls the P-channel field effect transistor and the N-channel field effect transistor to switch working states in an orderly manner according to the clamping voltage; Among them, when the PWM input module receives a high level, the N-channel field effect tube is first turned off and then the P-channel field effect tube is turned on; when the PWM input module receives a low level, the P-channel field effect tube is first turned off and then the N-channel field effect tube is turned on.

Images